Display substrate and display device

Abstract

A display substrate includes: at least one scan drive circuit. The scan drive circuit includes: a first voltage signal line, a second voltage signal line and a third voltage signal line; and a plurality of cascaded shift registers. The shift register includes: a first transistor and a second transistor arranged between the first voltage signal line and the second voltage signal line, the second electrode of the first transistor being electrically connected to the first output terminal, and the second electrode of the second transistor being electrically connected to the first output terminal; a third transistor and a fourth transistor arranged between the second voltage signal line and the third voltage signal line, the second electrode of the third transistor being electrically connected to the second output terminal, and the second electrode of the fourth transistor being electrically connected to the second output terminal; at least one first scan signal line electrically connected to the first output terminal; and at least one second scan signal line electrically connected to the second output terminal.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] The scanning drive circuit is an important component of the display device. The scanning drive circuit may include a multi-stage cascaded shift register, and the multi-stage shift register may be electrically connected to a plurality of wires in the display device, respectively. The scanning drive circuit may input scanning signals line by line into a plurality of wires (such as gate lines or enable signal lines, etc.) in the display device, so that the display device can display a picture.

[0003] Providing a scan driving circuit in a display device can effectively reduce costs and improve yield. Summary of the invention

[0004] In one aspect, a display substrate is provided. The display substrate comprises: a substrate; and at least one scan drive circuit disposed on the substrate. The scan drive circuit comprises: a first voltage signal line, a second voltage signal line, and a third voltage signal line extending along a first direction and sequentially arranged at intervals along a second direction; and a plurality of cascaded shift registers. The shift register includes: a first transistor and a second transistor arranged between the first voltage signal line and the second voltage signal line, the first electrode of the first transistor is electrically connected to the first voltage signal line, the second electrode of the first transistor is electrically connected to the first output terminal, the first electrode of the second transistor is electrically connected to the second voltage signal line, and the second electrode of the second transistor is electrically connected to the first output terminal; a third transistor and a fourth transistor arranged between the second voltage signal line and the third voltage signal line, the first electrode of the third transistor is electrically connected to the second voltage signal line, the second electrode of the third transistor is electrically connected to the second output terminal, the first electrode of the fourth transistor is electrically connected to the third voltage signal line, and the second electrode of the fourth transistor is electrically connected to the second output terminal; at least one first scanning signal line electrically connected to the first output terminal and extending along the second direction; and at least one second scanning signal line electrically connected to the second output terminal and extending along the second direction.

[0005] In some embodiments, an orthographic projection of the first scan signal line on the substrate and an orthographic projection of the second scan signal line on the substrate have no overlap.

[0006] In some embodiments, the number of the first scanning signal lines is plural, the number of the second scanning signal lines is plural, and along the first direction, the first scanning signal lines and the second scanning signal lines are alternately arranged in sequence.

[0007] In some embodiments, one of the first scanning signal lines and one of the second scanning signal lines constitute a group of output signal lines, and two adjacent groups of output signal lines are arranged at intervals.

[0008] In some embodiments, the first scan signal line and the second scan signal line are disposed in the same layer and located in the first gate conductive layer. And / or the first voltage signal line, the second voltage signal line and the third voltage signal line are disposed in the same layer and located in the source-drain conductive layer.

[0009] In some embodiments, the third transistor includes a third semiconductor portion, and the fourth transistor includes a fourth semiconductor portion; the third semiconductor portion and the fourth semiconductor portion are sequentially arranged at intervals along the first direction. Along the first direction, the first scan signal line and the second scan signal line are both located between the third semiconductor portion and the fourth semiconductor portion; and / or, along the first direction, the first scan signal line and the second scan signal line are both located between two adjacent shift registers.

[0010] In some embodiments, an orthographic projection of any one of the first scan signal line and the second scan signal line on the substrate has no overlap with an orthographic projection of any one of the third semiconductor portion and the fourth semiconductor portion on the substrate.

[0011] In some embodiments, the third semiconductor portion includes: a plurality of third channel portions arranged at intervals along the first direction, and a third input portion and a third output portion arranged on both sides of each third channel portion. The control electrode of the third transistor includes: a third gate conductive pattern arranged at a side of the third semiconductor portion away from the substrate and in a comb shape; the third gate conductive pattern includes a plurality of third sub-gates arranged at intervals along the first direction, and the orthographic projection of the third sub-gates on the substrate partially overlaps with the orthographic projection of the third channel portion on the substrate. The first electrode of the third transistor includes: a third input electrode pattern arranged at a side of the third gate conductive pattern away from the substrate and in a comb shape; the third input electrode pattern includes a plurality of third sub-input electrodes arranged at intervals along the first direction, and the orthographic projection of the third sub-input electrodes on the substrate partially overlaps with the orthographic projection of the third input portion on the substrate; the third input electrode pattern is electrically connected to the second voltage signal line. The second electrode of the third transistor includes: a third output electrode pattern arranged on the side of the third gate conductive pattern away from the substrate and in a comb shape; the third output electrode pattern includes a plurality of third sub-output electrodes arranged at intervals along the first direction, and the orthographic projection of the third sub-output electrode on the substrate partially overlaps with the orthographic projection of the third output portion on the substrate; the third output electrode pattern is electrically connected to the second scanning signal line. The third input electrode pattern and the third output electrode pattern are arranged in an interdigitated structure; and / or the third input electrode pattern and the third output electrode pattern are arranged in the same layer and are located in the source and drain conductive layer.

[0012] In some embodiments, the third input electrode pattern and the second voltage signal line are in an integrated structure.

[0013] In some embodiments, the fourth semiconductor portion includes: a plurality of fourth channel portions arranged at intervals along the first direction, and a fourth input portion and a fourth output portion arranged on both sides of each fourth channel portion. The control electrode of the fourth transistor includes: a fourth gate conductive pattern arranged at a side of the fourth semiconductor portion away from the substrate and in a comb shape; the fourth gate conductive pattern includes a plurality of fourth sub-gates arranged at intervals along the first direction, and the orthographic projection of the fourth sub-gates on the substrate partially overlaps with the orthographic projection of the fourth channel portion on the substrate; the fourth gate conductive pattern is electrically connected to the first scanning signal line. The first electrode of the fourth transistor includes: a fourth input electrode pattern arranged at a side of the fourth gate conductive pattern away from the substrate and in a comb shape; the fourth input electrode pattern includes a plurality of fourth sub-input electrodes arranged at intervals along the first direction, and the orthographic projection of the fourth sub-input electrodes on the substrate partially overlaps with the orthographic projection of the fourth input portion on the substrate; the fourth input electrode pattern is electrically connected to the third voltage signal line. The second electrode of the fourth transistor includes: a fourth output electrode pattern arranged on the side of the fourth gate conductive pattern away from the substrate and in a comb shape; the fourth output electrode pattern includes a plurality of fourth sub-output electrodes arranged at intervals along the first direction, and the orthographic projection of the fourth sub-output electrode on the substrate partially overlaps with the orthographic projection of the fourth output portion on the substrate; the fourth output electrode pattern is electrically connected to the second scanning signal line. The fourth input electrode pattern and the fourth output electrode pattern are arranged in an interdigitated structure; and / or the fourth input electrode pattern and the fourth output electrode pattern are arranged in the same layer and are located in the source and drain conductive layer.

[0014] In some embodiments, the fourth input electrode pattern and the third voltage signal line are in an integrated structure. And / or, the third output electrode pattern and the fourth output electrode pattern are in an integrated structure.

[0015] In some embodiments, the shift register further includes: a first connection portion extending along the first direction and disposed between the fourth gate conductive pattern and the first scan signal line. One end of the first connection portion is electrically connected to the fourth gate conductive pattern, and the other end of the first connection portion is electrically connected to the first scan signal line. The first connection portion is located in the source-drain conductive layer.

[0016] In some embodiments, the first transistor includes a first semiconductor portion, and the second transistor includes a second semiconductor portion. The first semiconductor portion and the second semiconductor portion are sequentially arranged along the first direction and are in an integrated structure.

[0017] In some embodiments, the first semiconductor portion includes: a plurality of first channel portions arranged at intervals along the first direction, and a first input portion and a first output portion arranged on both sides of each first channel portion. The control electrode of the first transistor includes: a first gate conductive pattern arranged at a side of the first semiconductor portion away from the substrate and in a comb shape; the first gate conductive pattern includes a plurality of first sub-gates arranged at intervals along the first direction, and the orthographic projection of the first sub-gate on the substrate partially overlaps with the orthographic projection of the first channel portion on the substrate. The first electrode of the first transistor includes: a first input electrode pattern arranged at a side of the first gate conductive pattern away from the substrate and in a comb shape; the first input electrode pattern includes a plurality of first sub-input electrodes arranged at intervals along the first direction, and the orthographic projection of the first sub-input electrode on the substrate partially overlaps with the orthographic projection of the first input portion on the substrate; the first input electrode pattern is also electrically connected to the first voltage signal line. The second electrode of the first transistor includes: a first output electrode pattern in a comb shape and arranged on the side of the first gate conductive pattern away from the substrate; the first output electrode pattern includes a plurality of first sub-output electrodes arranged at intervals along the first direction, and the orthographic projection of the first sub-output electrode on the substrate partially overlaps with the orthographic projection of the first output portion on the substrate; the first output electrode pattern is also electrically connected to the first scanning signal line. The second semiconductor portion includes: a plurality of second channel portions arranged at intervals along the first direction, and a second input portion and a second output portion arranged on both sides of each second channel portion. The control electrode of the second transistor includes: a second gate conductive pattern in a comb shape and arranged on the side of the second semiconductor portion away from the substrate; the second gate conductive pattern includes a plurality of second sub-gates arranged at intervals along the first direction, and the orthographic projection of the second sub-gates on the substrate partially overlaps with the orthographic projection of the second channel portion on the substrate. The first electrode of the second transistor includes: a second input electrode pattern in a comb shape and arranged at a side of the second gate conductive pattern away from the substrate; the second input electrode pattern includes a plurality of second sub-input electrodes arranged at intervals along the first direction, and the orthographic projection of the second sub-input electrode on the substrate partially overlaps with the orthographic projection of the second input part on the substrate; the second input electrode pattern is also electrically connected to the second voltage signal line. The second electrode of the second transistor includes: a second output electrode pattern in a comb shape and arranged at a side of the second gate conductive pattern away from the substrate; the second output electrode pattern includes a plurality of second sub-output electrodes arranged at intervals along the first direction, and the orthographic projection of the second sub-output electrode on the substrate partially overlaps with the orthographic projection of the second output part on the substrate; the second output electrode pattern is also electrically connected to the first scanning signal line.

[0018] In some embodiments, the shift register further includes: a fifth transistor disposed between the third transistor and the fourth transistor. The fifth transistor includes a fifth semiconductor portion; the fifth semiconductor portion includes: a fifth channel portion and a fifth input portion and a fifth output portion disposed on both sides of the fifth channel portion. The control electrode of the fifth transistor includes: a fifth gate conductive pattern disposed on the side of the fifth semiconductor portion away from the substrate; the orthographic projection of the fifth gate conductive pattern on the substrate partially overlaps with the orthographic projection of the fifth channel portion on the substrate; the fifth gate conductive pattern is electrically connected to the control electrode of the first transistor. The first electrode of the fifth transistor includes: a fifth input electrode pattern disposed on the side of the fifth gate conductive pattern away from the substrate; the orthographic projection of the fifth input electrode pattern on the substrate partially overlaps with the orthographic projection of the fifth input portion on the substrate; the fifth input electrode pattern is also electrically connected to the second voltage signal line. The second electrode of the fifth transistor includes: a fifth output electrode pattern disposed on the side of the fifth gate conductive pattern away from the substrate; the orthographic projection of the fifth output electrode pattern on the substrate partially overlaps with the orthographic projection of the fifth output portion on the substrate.

[0019] In some embodiments, the first sub-gate in the first gate conductive pattern extends toward the fifth transistor in a zigzag shape and is reused as the fifth gate conductive pattern.

[0020] In some embodiments, the length direction of the fifth channel portion is arranged along the second direction; the fifth input portion is located on a side of the fifth output portion close to the second voltage signal line. And / or, the fifth input electrode pattern is located in the source-drain conductive layer and is an integral structure with the second voltage signal line.

[0021] In some embodiments, a third sub-gate in the third gate conductive pattern close to the fifth transistor extends toward the fifth transistor in a corner shape and is electrically connected to the fifth output electrode pattern.

[0022] In some embodiments, when the first scan signal line and the second scan signal line are both located between the third semiconductor portion and the fourth semiconductor portion, the fifth transistor is disposed between the third transistor and the first scan signal line.

[0023] In some embodiments, the shift register further includes: a sixth transistor disposed between the third transistor and the fourth transistor. The sixth transistor includes a sixth semiconductor portion; the sixth semiconductor portion includes: a sixth channel portion and a sixth input portion and a sixth output portion disposed on both sides of the sixth channel portion. The control electrode of the sixth transistor includes: a sixth gate conductive pattern disposed on the side of the sixth semiconductor portion away from the substrate; the orthographic projection of the sixth gate conductive pattern on the substrate partially overlaps with the orthographic projection of the sixth channel portion on the substrate; the sixth gate conductive pattern is electrically connected to the control electrode of the fourth transistor. The first electrode of the sixth transistor includes: a sixth input electrode pattern disposed on the side of the sixth gate conductive pattern away from the substrate; the orthographic projection of the sixth input electrode pattern on the substrate partially overlaps with the orthographic projection of the sixth input portion on the substrate; the sixth input electrode pattern is also electrically connected to the third voltage signal line. The second electrode of the sixth transistor includes: a sixth output electrode pattern arranged on a side of the sixth gate conductive pattern away from the substrate; the orthographic projection of the sixth output electrode pattern on the substrate partially overlaps with the orthographic projection of the sixth output part on the substrate; when the shift register also includes a fifth transistor, the sixth output electrode pattern is electrically connected to the fifth output electrode pattern of the fifth transistor.

[0024] In some embodiments, a fourth sub-gate in the fourth gate conductive pattern close to the sixth transistor extends toward the sixth transistor in a corner shape and is reused as the sixth gate conductive pattern.

[0025] In some embodiments, the length direction of the sixth channel portion is arranged along the first direction; and the sixth input portion is located on a side of the sixth output portion close to the fourth transistor.

[0026] In some embodiments, the sixth semiconductor portion and the fourth semiconductor portion are in an integrated structure. The fourth input portion close to the sixth semiconductor portion is multiplexed as the sixth input portion. The fourth sub-input electrode close to the sixth semiconductor portion in the fourth input electrode pattern of the fourth transistor is multiplexed as the sixth input electrode pattern.

[0027] In some embodiments, when the first scan signal line and the second scan signal line are both located between the third semiconductor portion and the fourth semiconductor portion, the sixth transistor is disposed between the fourth transistor and the first scan signal line.

[0028] In some embodiments, the shift register further includes: a first capacitor disposed between the second transistor and the fourth transistor. The first capacitor includes: a first plate and a second plate disposed between the substrate and the second voltage signal line and stacked in sequence. The first plate of the first capacitor is electrically connected to the fifth output electrode pattern of the fifth transistor.

[0029] In some embodiments, the orthographic projection of any one of the first plate of the first capacitor and the second plate of the first capacitor on the substrate and the orthographic projection of the second voltage signal line on the substrate at least partially overlap. And / or, the size of any one of the first plate of the first capacitor and the second plate of the first capacitor in the second direction and the size of the second voltage signal line in the second direction are substantially equal.

[0030] In some embodiments, the first plate of the first capacitor and the fifth gate conductive pattern of the fifth transistor are disposed in the same layer and located in the second gate conductive layer. The second plate of the first capacitor is located in the first gate conductive layer.

[0031] In some embodiments, the scan drive circuit further includes: a first clock signal line arranged on a side of the first voltage signal line away from the second voltage signal line and extending along the first direction. The shift register further includes: a seventh transistor arranged between the first voltage signal line and the second voltage signal line. The seventh transistor includes a seventh semiconductor portion; the seventh semiconductor portion includes: a seventh channel portion and a seventh input portion and a seventh output portion arranged on both sides of the seventh channel portion. The control electrode of the seventh transistor includes: a seventh gate conductive pattern arranged on a side of the seventh semiconductor portion away from the substrate; the orthographic projection of the seventh gate conductive pattern on the substrate partially overlaps with the orthographic projection of the seventh channel portion on the substrate; the seventh gate conductive pattern is electrically connected to the first plate of the first capacitor. The first electrode of the seventh transistor includes: a seventh input electrode pattern arranged on a side of the seventh gate conductive pattern away from the substrate; the orthographic projection of the seventh input electrode pattern on the substrate partially overlaps with the orthographic projection of the seventh input portion on the substrate; the seventh input electrode pattern is also electrically connected to the first clock signal line. The second electrode of the seventh transistor includes: a seventh output electrode pattern arranged on a side of the seventh gate conductive pattern away from the substrate; an orthographic projection of the seventh output electrode pattern on the substrate partially overlaps with an orthographic projection of the seventh output portion on the substrate; and the seventh output electrode pattern is electrically connected to the second electrode plate of the first capacitor. The seventh semiconductor portion is arranged on a side of the second semiconductor portion away from the first semiconductor portion.

[0032] In some embodiments, the first plate of the first capacitor is close to one end of the seventh transistor, extends toward the seventh transistor, and is reused as the seventh gate conductive pattern.

[0033] In some embodiments, the length direction of the seventh channel portion is arranged along the second direction. The seventh input portion is located at a side of the seventh output portion away from the second voltage signal line.

[0034] In some embodiments, the shift register further includes: an eighth transistor disposed between the first voltage signal line and the seventh transistor. The eighth transistor includes an eighth semiconductor portion; the eighth semiconductor portion includes: an eighth channel portion. The control electrode of the eighth transistor includes: an eighth gate conductive pattern disposed on a side of the eighth semiconductor portion away from the substrate; the orthographic projection of the eighth gate conductive pattern on the substrate partially overlaps with the orthographic projection of the eighth channel portion on the substrate. The eighth gate conductive pattern extends along the second direction, one end of the eighth gate conductive pattern is electrically connected to the seventh input electrode pattern, and the other end of the eighth gate conductive pattern is electrically connected to the first clock signal line. The seventh input electrode pattern is electrically connected to the first clock signal line through the eighth gate conductive pattern.

[0035] In some embodiments, the scan drive circuit further includes: a second clock signal line arranged on a side of the first voltage signal line away from the second voltage signal line and extending along the first direction. The shift register further includes: a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor. The second electrode of the eighth transistor is electrically connected to the second electrode of the ninth transistor. The control electrode of the ninth transistor is electrically connected to the second clock signal line, and the first electrode of the ninth transistor is electrically connected to the second electrode of the tenth transistor. The control electrode of the tenth transistor is electrically connected to the control electrode of the eleventh transistor, and the first electrode of the tenth transistor is electrically connected to the first voltage signal line. The first electrode of the eleventh transistor is electrically connected to the second clock signal line, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the twelfth transistor. The control electrode of the twelfth transistor is electrically connected to the second clock signal line, and the second electrode of the twelfth transistor is electrically connected to the control electrode of the first transistor. Among them, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are arranged in sequence along the first direction.

[0036] In some embodiments, the ninth transistor includes a ninth semiconductor portion, the ninth semiconductor portion includes a ninth channel portion. The tenth transistor includes a tenth semiconductor portion, the tenth semiconductor portion includes a tenth channel portion; the eleventh transistor includes an eleventh semiconductor portion, the eleventh semiconductor portion includes an eleventh channel portion; the twelfth transistor includes a twelfth semiconductor portion, the twelfth semiconductor portion includes a twelfth channel portion. The length direction of the eighth channel portion, the length direction of the ninth channel portion, the length direction of the tenth channel portion, the length direction of the eleventh channel portion, and the length direction of the twelfth channel portion are all arranged along the first direction.

[0037] In some embodiments, the shift register further includes: a thirteenth transistor and a fourteenth transistor disposed between the eighth transistor and the seventh transistor and sequentially disposed along the first direction. The thirteenth transistor is a dual-gate transistor. The control electrode of the thirteenth transistor is electrically connected to the second electrode of the eighth transistor; the first electrode of the thirteenth transistor is electrically connected to the first clock signal line, and the second electrode of the thirteenth transistor is electrically connected to the first electrode of the fourteenth transistor. The control electrode of the fourteenth transistor is electrically connected to the second voltage signal line, and the second electrode of the fourteenth transistor is electrically connected to the control electrode of the eleventh transistor.

[0038] In some embodiments, the thirteenth transistor includes a thirteenth semiconductor portion, the thirteenth semiconductor portion includes a thirteenth channel portion; the fourteenth transistor includes a fourteenth semiconductor portion, the fourteenth semiconductor portion includes a fourteenth channel portion. The length direction of the thirteenth channel portion and the length direction of the fourteenth channel portion are both arranged along the first direction.

[0039] In some embodiments, the shift register also includes: a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor arranged between the thirteenth transistor and the seventh transistor and arranged in sequence along the first direction; a second capacitor arranged between the fifteenth transistor and the sixteenth transistor; a third capacitor arranged between the sixteenth transistor and the seventeenth transistor; and a fourth capacitor arranged on the side of the seventeenth transistor away from the sixteenth transistor. Among them, the control electrode of the fifteenth transistor is electrically connected to the first clock signal line, the first electrode of the fifteenth transistor is electrically connected to the second voltage signal line, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the fourteenth transistor; the control electrode of the sixteenth transistor is electrically connected to the second voltage signal line, the first electrode of the sixteenth transistor is electrically connected to the second electrode of the eighth transistor, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the second transistor; the control electrode of the seventeenth transistor is electrically connected to the second electrode of the eighth transistor, the first electrode of the seventeenth transistor is electrically connected to the first voltage signal line, and the second electrode of the seventeenth transistor is electrically connected to the control electrode of the first transistor; the first plate of the second capacitor is electrically connected to the second clock signal line, and the second plate of the second capacitor is electrically connected to the control electrode of the second transistor; the first plate of the third capacitor is electrically connected to the control electrode of the eleventh transistor, and the second plate of the third capacitor is electrically connected to the second electrode of the eleventh transistor; the first plate of the fourth capacitor is electrically connected to the control electrode of the first transistor, and the second plate of the fourth capacitor is electrically connected to the first voltage signal line.

[0040] In another aspect, a display device is provided, comprising: a display substrate as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0042] Figure 1 A structural diagram of a display substrate according to the related art;

[0043] Figure 2 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0044] Figure 3 is a structural diagram of a display substrate according to some embodiments of the present disclosure;

[0045] Figure 4 is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure;

[0046] Figure 5 is a circuit diagram of a shift register according to some embodiments of the present disclosure;

[0047] Figure 6 According to some embodiments of the present disclosure, Figure 5 The timing control diagram of the shift register shown;

[0048] Figure 7 is a layout diagram of a scan driving circuit according to some embodiments of the present disclosure;

[0049] Figure 8 is a layout diagram of another scan driving circuit according to some embodiments of the present disclosure;

[0050] Fig. 9 is a structural diagram of a semiconductor material layer according to some embodiments of the present disclosure;

[0051] Fig.10 is a structural diagram of a second gate conductive layer according to some embodiments of the present disclosure;

[0052] Fig.11 is a structural diagram of a first gate conductive layer according to some embodiments of the present disclosure;

[0053] Fig.12 is a structural diagram of a source-drain conductive layer according to some embodiments of the present disclosure;

[0054] Fig.13 for Figure 8 A cross-sectional view of the scan driving circuit shown along the EE' direction;

[0055] Fig.14 for Figure 8 A cross-sectional view of the scan driving circuit shown along the FF' direction;

[0056] Fig.15 for Figure 8 A cross-sectional view of the scan driving circuit shown along the HH' direction;

[0057] Fig.16 is a structural diagram of a scan driving circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0058] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0059] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0060] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0061] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0062] In some examples, the above-mentioned “connection” may refer to a direct connection or an indirect connection.

[0063] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0064] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0065] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0066] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0067] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0068] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0069] The transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are described by taking thin film transistors as an example.

[0070] In some embodiments, the control electrode of each transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be indistinguishable in structure. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0071] In the circuits provided in the embodiments of the present disclosure, "nodes" do not represent actual components, but rather represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram being equivalent.

[0072] In the following, in the circuits provided in the embodiments of the present disclosure, the transistors are all described as P-type transistors. It should be noted that the transistors in the circuits mentioned below use the same conduction type, which can simplify the process flow, reduce the process difficulty, and improve the yield of the product (such as the display substrate 100 and the display device 1000).

[0073] Some embodiments of the present disclosure provide a display substrate 100 and a display device 1000 . The display substrate 100 and the display device 1000 are respectively introduced below.

[0074] Some embodiments of the present disclosure provide a display device 1000, such as Figure 2 As shown. The display device 1000 can be any device that displays an image, whether in motion (e.g., video) or fixed (e.g., still image), and whether text or. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0075] In some examples, the display device 1000 includes a frame, a display substrate 100 disposed in the frame, a circuit board, a data driver IC (Integrated Circuit), and other electronic components.

[0076] The above-mentioned display substrate 100 can be, for example: an organic light emitting diode (OLED) display substrate, a quantum dot light emitting diode (QLED) display substrate, a micro light emitting diode (Micro LED) display substrate or a mini light emitting diode (Mini LED) display substrate, etc., and the present disclosure does not make any specific limitations on this.

[0077] In the following, some embodiments of the present disclosure are schematically described by taking the display substrate 100 as an OLED display substrate as an example.

[0078] In some embodiments, Figure 3 As shown, the display substrate 100 has a display area A and a frame area B arranged beside the display area A. The "side" refers to one side, two sides, three sides or surrounding sides of the display area A, that is, the frame area B can be located on one side, two sides or three sides of the display area A, or the frame area B can be arranged around the display area A.

[0079] In some examples, such as Figure 3 As shown, the display substrate 100 may include: a substrate 1, and a plurality of sub-pixels P, a plurality of gate lines, a plurality of data lines DL, a plurality of enable signal lines EL1, and a plurality of reset signal transmission lines RL1 arranged on one side of the substrate 1.

[0080] There are many types of the substrate 1, which can be selected according to actual needs.

[0081] Exemplarily, the substrate 1 may be a rigid substrate, such as a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0082] Exemplarily, the substrate 1 may be a flexible substrate, such as a PET (Polyethyleneterephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate.

[0083] Optional, such as Figure 3 As shown, the above-mentioned multiple sub-pixels P, multiple gate lines, multiple data lines DL, multiple enable signal lines EL1 and multiple reset signal transmission lines RL1 can be located in the display area A, and the multiple gate lines, multiple enable signal lines EL1 and multiple reset signal transmission lines RL1 can extend along the second direction X, and the multiple data lines DL can extend along the first direction Y.

[0084] Here, the second direction X and the first direction Y intersect each other. The angle between the second direction X and the first direction Y can be set according to actual needs. Exemplarily, the angle between the second direction X and the first direction Y can be 85°, 88°, 90°, 92° or 95°, etc.

[0085] For example, the plurality of sub-pixels P may be arranged in an array, that is, the plurality of sub-pixels P may be arranged in a plurality of rows along the second direction X, and may be arranged in a plurality of rows along the first direction Y. The sub-pixels P arranged in a row along the second direction X may be referred to as sub-pixels P in the same row, and the sub-pixels P arranged in a row along the first direction Y may be referred to as sub-pixels P in the same column. The sub-pixels P in the same row may be electrically connected to at least one gate line, one enable signal line EL1, and one reset signal transmission line RL1, and the sub-pixels P in the same column may be electrically connected to one data line DL.

[0086] In some examples, such as Figure 4 As shown, each of the plurality of sub-pixels P may include a pixel driving circuit P1 and a light emitting device P2 electrically connected to the pixel driving circuit P1. When the display substrate 100 is an OLED display substrate, the light emitting device P2 is an OLED.

[0087] The structure of the pixel driving circuit P1 includes multiple structures, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit P1 may include "4T1C", "6T1C", "7T1C", "6T2C", "7T2C" or "8T2C" structures. Among them, "T" represents a transistor, and the number in front of "T" represents the number of transistors, and "C" represents a storage capacitor, and the number in front of "C" represents the number of storage capacitors.

[0088] Exemplarily, the light-emitting device P2 may include an anode, a light-emitting layer, and a cathode stacked in sequence. In addition, the light-emitting device may also include, for example, a hole injection layer and / or a hole transport layer disposed between the anode and the light-emitting layer, and may also include, for example, an electron transport layer and / or an electron injection layer disposed between the light-emitting layer and the cathode. The pixel driving circuit is, for example, electrically connected to the anode of the light-emitting device.

[0089] Combine the following Figure 4 , taking the structure of the pixel driving circuit P1 as "7T1C" as an example, the structure of the sub-pixel P and the connection relationship between it and the gate line, the data line DL, and the enable signal line EL are schematically described. It should be noted that the seven transistors and one storage capacitor included in the pixel driving circuit P1 can also have other electrical connection relationships, and are not limited to the electrical connection relationships shown in this example.

[0090] For example, Figure 4 As shown, the pixel driving circuit P1 includes: a first reset transistor M1, a switch transistor M2, a driving transistor M3, a compensation transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, a second reset transistor M7 and a storage capacitor Cst.

[0091] For example, Figure 4 As shown, the control electrode of the first reset transistor M1 is electrically connected to the second gate signal terminal Gate2, the first electrode of the first reset transistor M1 is electrically connected to the initial signal terminal Init, and the second electrode of the first reset transistor M1 is electrically connected to the first pixel node Q1. The first reset transistor M1 is configured to be turned on under the control of the second gate signal transmitted by the second gate signal terminal Gate2, and transmit the initial signal received from the initial signal terminal Init to the first pixel node Q1, so as to reset the first pixel node Q1.

[0092] For example, Figure 4 As shown, the control electrode of the switch transistor M2 is electrically connected to the first gate signal terminal Gate1, the first electrode of the switch transistor M2 is electrically connected to the data signal terminal Data, and the second electrode of the switch transistor M2 is electrically connected to the third pixel node Q3. The switch transistor M2 is configured to be turned on under the control of the first gate signal transmitted by the first gate signal terminal Gate, and transmit the data signal transmitted by the data signal terminal Data to the third pixel node Q3.

[0093] For example, Figure 4As shown, the control electrode of the driving transistor M3 is electrically connected to the first pixel node Q1, the first electrode of the driving transistor M3 is electrically connected to the third pixel node Q3, and the second electrode of the driving transistor M3 is electrically connected to the second pixel node Q2. The driving transistor M3 is configured to be turned on under the control of the voltage of the first pixel node Q1, and transmit the signal (for example, a data signal) from the third pixel node Q3 to the second pixel node Q2.

[0094] For example, Figure 4 As shown, the control electrode of the compensation transistor M4 is electrically connected to the first gate signal terminal Gate1, the first electrode of the compensation transistor M4 is electrically connected to the second pixel node Q2, and the second electrode of the compensation transistor M4 is electrically connected to the first pixel node Q1. The compensation transistor M4 is configured to be turned on under the control of the first gate signal transmitted by the first gate signal terminal Gate1, transmit the signal (for example, the data signal) from the second pixel node Q2 to the first pixel node Q1, and perform threshold voltage compensation on the driving transistor T3.

[0095] Here, since the control electrode of the switching transistor M2 and the control electrode of the compensation transistor M4 are both electrically connected to the first gate signal terminal Gate1, the switching transistor M2 and the compensation transistor M4 can be turned on at the same time under the control of the first gate signal, and the data signal transmitted by the data signal terminal Data is transmitted to the first pixel node Q1 through the switching transistor M2, the driving transistor M3 and the compensation transistor M4 in sequence until the driving transistor M3 is in the cut-off state, thereby completing the compensation of the threshold voltage of the driving transistor T3.

[0096] For example, Figure 4 As shown, the control electrode of the first light-emitting control transistor M5 is electrically connected to the light-emitting control signal terminal EM, the first electrode of the first light-emitting control transistor M5 is electrically connected to the first power signal terminal VDD, and the second electrode of the first light-emitting control transistor M5 is electrically connected to the third pixel node Q3. The control electrode of the second light-emitting control transistor M6 is electrically connected to the light-emitting control signal terminal EM, the first electrode of the second light-emitting control transistor M6 is electrically connected to the second pixel node Q2, and the second electrode of the second light-emitting control transistor M6 is electrically connected to the anode of the light-emitting device. The first light-emitting control transistor M5 and the second light-emitting control transistor M6 are configured to be turned on at the same time under the control of the light-emitting control signal transmitted by the light-emitting control signal terminal EM, generate a driving signal according to the first power signal transmitted by the first power signal terminal VDD, and transmit the driving signal to the anode of the light-emitting device P2.

[0097] For example, Figure 4As shown, the control electrode of the second reset transistor M7 is electrically connected to the reset signal terminal Reset, the first electrode of the second reset transistor M7 is electrically connected to the initial signal terminal Init, and the second electrode of the second reset transistor M7 is electrically connected to the anode of the light emitting device P2. The second reset transistor M7 is configured to be turned on under the control of the reset signal transmitted by the reset signal terminal Reset, and transmit the initial signal received from the initial signal terminal Init to the anode of the light emitting device P2, so as to reset the anode of the light emitting device P2.

[0098] For example, Figure 4 As shown, the cathode of the light emitting device P2 is electrically connected to the second power signal terminal VSS. The light emitting device is configured to emit light under the control of the above driving signal.

[0099] For example, Figure 4 As shown, a first end of the storage capacitor Cst is electrically connected to the first power signal terminal VDD, and a second end of the storage capacitor Cst is electrically connected to the first pixel node Q1. The storage capacitor Cst is configured to store the signal transmitted to the first pixel node Q1 and maintain the voltage of the first pixel node Q1.

[0100] Exemplarily, the above-mentioned pixel driving circuit P1 is electrically connected to the corresponding gate line through the first gate signal terminal Gate1 to receive the first gate signal; is electrically connected to the corresponding gate line through the second gate signal terminal Gate2 to receive the second gate signal; is electrically connected to the corresponding data line DL through the data signal terminal Data to receive the data signal; is electrically connected to the corresponding enable signal line EL1 through the light emitting control signal terminal EM to receive the enable signal; and is electrically connected to the corresponding reset signal transmission line RL1 through the reset signal terminal Reset to receive the reset signal.

[0101] In related technologies, such as Figure 1 As shown, the first gate signal and the second gate signal received by each sub-pixel P' in the display substrate 100' are generated by the gate driving circuit, the received light control signal is generated by the light driving circuit ED', and the received reset signal is generated by the reset driving circuit RD'. Among them, the gate driving circuit, the light driving circuit ED' and the reset driving circuit RD' are all independent driving circuits, and are all arranged in the frame area of ​​the display substrate 100'. This will make the sum of the sizes of the gate driving circuit, the light driving circuit ED' and the reset driving circuit RD' larger, which will lead to a larger size occupied by the three in the display substrate 100', resulting in a larger frame size of the display substrate 100', which is not conducive to achieving a narrow frame design.

[0102] Based on this, Figure 3As shown, some embodiments of the present disclosure provide a display substrate 100, further comprising: at least one scan drive circuit 2 disposed on the substrate 1. The at least one scan drive circuit 2 may be disposed in the border region B, for example.

[0103] The present disclosure does not limit the number of the above-mentioned scan driving circuits 2, and the number can be selected according to actual needs.

[0104] Exemplarily, the number of the scan driving circuit 2 may be one. In this case, the scan driving circuit 2 may correspond to the multiple rows of sub-pixels P included in the display substrate 100 .

[0105] For example, the scan driving circuit 2 may be located at one side of the extending direction of the plurality of gate lines.

[0106] For example, Figure 3 As shown, the number of scanning driving circuits 2 can be two. In this case, one scanning driving circuit 2 can correspond to a part of the sub-pixels P in the above-mentioned multiple rows of sub-pixels P, and another scanning driving circuit 2 can correspond to another part of the sub-pixels P in the multiple rows of sub-pixels P.

[0107] For example, the two scan driving circuits 2 may be located at opposite sides of the extending direction of the plurality of gate lines.

[0108] In some examples, such as Fig.16 As shown, the scanning driving circuit 2 may include: a plurality of cascaded shift registers 2a. Figure 5 As shown, each shift register 2a may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4.

[0109] For example, Figure 5As shown, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the first voltage signal terminal VGH1 (corresponding to the first voltage signal line VGHL1), and the second electrode of the first transistor T1 is electrically connected to the first output terminal EM_OUT. The first transistor T1 is configured to be turned on under the control of the voltage of the first node N1 when the voltage of the first node N1 is at a low level, and transmit the first voltage signal received at the first voltage signal terminal VGH1 to the first output terminal EM_OUT, so that the first output terminal EM_OUT outputs the first voltage signal.

[0110] For example, the first voltage signal terminal VGH1 is configured to transmit a first DC high level signal (eg, higher than or equal to the high level portion of the clock signal). Here, the first DC high level signal is referred to as a first voltage signal.

[0111] For example, Figure 5 As shown, the first plate of the fourth capacitor C4 is electrically connected to the first node N1, and the second plate of the fourth capacitor C4 is electrically connected to the first voltage signal terminal VGH1. The fourth capacitor C4 is configured to maintain the voltage of the first node N1.

[0112] For example, Figure 5 As shown, the control electrode of the second transistor T2 is electrically connected to the second node N2, the first electrode of the second transistor T2 is electrically connected to the second voltage signal terminal VGL (corresponding to the second voltage signal line VGLL), and the second electrode of the second transistor T2 is electrically connected to the first output terminal EM_OUT. The second transistor T2 is configured to be turned on under the control of the voltage of the second node N2 when the voltage of the second node N2 is at a low level, and transmit the second voltage signal received at the second voltage signal terminal VGL to the first output terminal EM_OUT, so that the first output terminal EM_OUT outputs the second voltage signal.

[0113] For example, the second voltage signal terminal VGL is configured to transmit a DC low-level signal (eg, lower than or equal to the low-level portion of the clock signal). Here, the DC low-level signal is referred to as a second voltage signal.

[0114] It should be noted that the first transistor T1 and the second transistor T2 are turned on in different time periods. During the time period when the first transistor T1 is turned on, the first output terminal EM_OUT can output the first voltage signal as the first scanning signal, and during the time period when the second transistor T2 is turned on, the first output terminal EM_OUT can output the second voltage signal as the first scanning signal. The first voltage signal and the second voltage signal can be arranged in sequence according to the turn-on sequence of the first transistor T1 and the second transistor T2 to form a complete first scanning signal.

[0115] For example, Figure 5 As shown, the control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second voltage signal terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the second output terminal Reset_OUT. The third transistor T3 is configured to be turned on under the control of the voltage of the third node N3 when the voltage of the third node N3 is at a low level, and transmits the second voltage signal received at the second voltage signal terminal VGL to the second output terminal Reset_OUT, so that the second output terminal Reset_OUT outputs the second voltage signal.

[0116] For example, Figure 5 As shown, the control electrode of the fourth transistor T4 is electrically connected to the first output terminal EM_OUT, the first electrode of the fourth transistor T4 is electrically connected to the third voltage signal terminal VGH2 (corresponding to the third voltage signal terminal VGHL2), and the second electrode of the fourth transistor T4 is electrically connected to the second output terminal Reset_OUT. The fourth transistor T4 is configured to be turned on under the control of the first scanning signal when the level of the first scanning signal output by the first output terminal EM_OUT is low, and transmits the third voltage signal received at the third voltage signal terminal VGH2 to the second output terminal Reset_OUT, so that the second output terminal Reset_OUT outputs the third voltage signal.

[0117] For example, the third voltage signal terminal VGH2 is configured to transmit a second DC high level signal (e.g., higher than or equal to the high level portion of the clock signal). Here, the second DC high level signal is referred to as the third voltage signal. The "high level" and "low level" mentioned in this article are relative, and the voltage value of the "high level" and the voltage value of the "low level" are not limited.

[0118] It should be noted that the third transistor T3 and the fourth transistor T4 are turned on in different time periods. During the time period when the third transistor T3 is turned on, the second output terminal Reset_OUT can output the second voltage signal as the second scanning signal, and during the time period when the fourth transistor T4 is turned on, the second output terminal Reset_OUT can output the third voltage signal as the second scanning signal. The second voltage signal and the third voltage signal can be arranged in sequence according to the turn-on sequence of the third transistor T3 and the fourth transistor T4 to form a complete second scanning signal.

[0119] For example, Figure 5As shown, the control electrode of the fifth transistor T5 is electrically connected to the first node N1, the first electrode of the fifth transistor T5 is electrically connected to the second voltage signal terminal VGL, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3. The fifth transistor T5 is configured to be turned on under the control of the voltage of the first node N1 when the voltage of the first node N1 is at a low level, and transmits the second voltage signal received at the second voltage signal terminal VGL to the third node N3.

[0120] For example, Figure 5 As shown, the control electrode of the sixth transistor T6 is electrically connected to the first output terminal EM_OUT, the first electrode of the sixth transistor T6 is electrically connected to the third voltage signal terminal VGH2, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3. The sixth transistor T6 is configured to be turned on under the control of the first scanning signal when the level of the first scanning signal is low, and transmit the third voltage signal received at the third voltage signal terminal VGH2 to the third node N3.

[0121] For example, Figure 5 As shown, the control electrode of the seventh transistor T7 is electrically connected to the third node N3, the first electrode of the seventh transistor T7 is electrically connected to the first clock signal terminal CK (corresponding to the first clock signal line CKL), and the second electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1. The first plate of the first capacitor C1 is electrically connected to the third node N3. Among them, the seventh transistor T7 is configured to, when the voltage of the third node N3 is at a low level, be turned on under the control of the voltage of the third node N3, and transmit the first clock signal received at the first clock signal terminal CK to the second plate of the first capacitor C1. The first capacitor C1 is configured to maintain the voltage of the third node N3.

[0122] For example, Figure 5 As shown, the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CK, the first electrode of the eighth transistor T8 is electrically connected to the input signal terminal STV (corresponding to the third clock signal line STVL), and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 is configured to be turned on under the control of the first clock signal when the level of the first clock signal is low, and transmits the input signal received at the input signal terminal STV to the second node N2.

[0123] For example, Figure 5 As shown, the first plate of the second capacitor C2 is electrically connected to the second clock signal terminal CB (corresponding to the second clock signal line CBL), and the second plate of the second capacitor C2 is electrically connected to the second node N2. The second capacitor C2 is configured to maintain the voltage of the second node N2.

[0124] For example, Figure 5 As shown, the control electrode of the sixteenth transistor T16 is electrically connected to the second voltage signal terminal VGL, the first electrode of the sixteenth transistor T16 is electrically connected to the fourth node N4, and the second electrode of the sixteenth transistor T16 is electrically connected to the second node N2. Based on this, the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and is electrically connected to the second node N2 through the sixteenth transistor T16.

[0125] Here, since the second voltage signal is a DC low level signal, the sixteenth transistor T16 is in a normally open state and transmits the input signal from the fourth node N4 to the second node N2. In addition, the sixteenth transistor T16 can stabilize the voltage of the second node N2 to prevent the second node N2 from leaking through the eighth transistor T8.

[0126] For example, Figure 5 As shown, the control electrode of the seventeenth transistor T17 is electrically connected to the fourth node N4, the first electrode of the seventeenth transistor T17 is electrically connected to the first voltage signal terminal VGH1, and the second electrode of the seventeenth transistor T17 is electrically connected to the first node N1. The seventeenth transistor T17 is configured to be turned on under the control of the voltage of the fourth node N4 when the voltage of the fourth node N4 is at a low level, and the first voltage signal first node N1 is connected to charge the first node N1, and the voltage of the first node N1 is controlled to be a high level.

[0127] For example, Figure 5 As shown, the control electrode of the fifteenth transistor T15 is electrically connected to the first clock signal terminal CK, the first electrode of the fifteenth transistor T15 is electrically connected to the second voltage signal terminal VGL, and the second electrode of the fifteenth transistor T15 is electrically connected to the fifth node N5. The fifteenth transistor T15 is configured to be turned on under the control of the first clock signal when the level of the first clock signal is low, and transmit the first clock signal to the fifth node N5.

[0128] For example, Figure 5 As shown, the control electrode of the eleventh transistor T11 is electrically connected to the fifth node N5, the first electrode of the eleventh transistor T11 is electrically connected to the second clock signal terminal CB, and the second electrode of the eleventh transistor T11 is electrically connected to the sixth node N6. The eleventh transistor T11 is configured to be turned on under the control of the voltage of the fifth node N5 when the voltage of the fifth node N5 is at a low level, and transmit the second clock signal to the sixth node N6.

[0129] For example, Figure 5As shown, the first plate of the third capacitor C3 is electrically connected to the fifth node N5, and the second plate of the third capacitor C3 is electrically connected to the sixth node N6. The third capacitor C3 is configured to maintain the voltage of the fifth node C5.

[0130] For example, Figure 5 As shown, the control electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the sixth node N6, and the second electrode of the twelfth transistor T12 is electrically connected to the first node N1. The twelfth transistor T12 is configured to be turned on under the control of the second clock signal when the level of the second clock signal is low, and transmit the second clock signal from the sixth node N6 to the first node N1.

[0131] For example, Figure 5 As shown, the control electrode of the fourteenth transistor T14 is electrically connected to the second voltage signal terminal VGL, the first electrode of the fourteenth transistor T14 is electrically connected to the seventh node N7, and the second electrode of the fourteenth transistor T14 is electrically connected to the fifth node N5. Based on this, the second electrode of the fifteenth transistor T15 is electrically connected to the seventh node N7, and is electrically connected to the fifth node N5 through the fourteenth transistor T14.

[0132] Here, since the second voltage signal is a DC low level signal, the fourteenth transistor T14 is in a normally open state and transmits the signal from the seventh node N7 to the fifth node N5. In addition, the fourteenth transistor T14 can stabilize the voltage of the fifth node N5 to prevent the fifth node N5 from leaking through the fifteenth transistor T15.

[0133] For example, Figure 5 As shown, the control electrode of the ninth transistor T9 is electrically connected to the second clock signal terminal CB, the first electrode of the ninth transistor T9 is electrically connected to the second electrode of the tenth transistor T10, and the second electrode of the ninth transistor T9 is electrically connected to the fourth node N4. The control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, and the first electrode of the tenth transistor T10 is electrically connected to the first voltage signal terminal VGH1. Among them, the ninth transistor T9 is configured to be turned on under the control of the second clock signal when the level of the second clock signal is low. The tenth transistor T10 is configured to be turned on under the control of the fifth node N5 when the voltage of the fifth node N5 is low.

[0134] Here, when the level of the second clock signal is low and the voltage of the fifth node N5 is low, the ninth transistor T9 and the tenth transistor T10 can be turned on at the same time. The tenth transistor T10 can transmit the first voltage signal to the first electrode of the ninth transistor T9, and the ninth transistor T9 can transmit the first voltage signal to the fourth node N4, charge the fourth node N4, and control the voltage of the fourth node N4 to be high.

[0135] For example, Figure 5 As shown, the control electrode of the thirteenth transistor T13 is electrically connected to the fourth node N4, the first electrode of the thirteenth transistor T13 is electrically connected to the first clock signal terminal CK, and the second electrode of the thirteenth transistor T13 is electrically connected to the seventh node N7. The thirteenth transistor T13 is configured to be turned on under the control of the voltage of the fourth node N4 when the voltage of the fourth node N4 is at a low level, transmit the first clock signal to the seventh node N7, and control the voltage of the seventh node N7.

[0136] Exemplarily, the first voltage signal terminal VGH1 and the third voltage signal terminal VGH2 are the same signal terminal, and the first voltage signal transmitted by the first voltage signal terminal VGH1 and the third voltage signal transmitted by the third voltage signal terminal VGH2 are the same.

[0137] Combine the following Figure 6 ,right Figure 5 The working principle of the shift register 2a shown is schematically described. The working process of the shift register 2a includes: a first stage S1, a second stage S2, a third stage S3, a fourth stage S4, a fifth stage S5 and a sixth stage S6.

[0138] In the first stage S1, Figure 6 As shown, the level of the input signal is a high level, the level of the first clock signal is a low level, and the level of the second clock signal is a high level.

[0139] The eighth transistor T8 is turned on under the control of the first clock signal, and transmits the input signal to the fourth node N4, and transmits the input signal to the second node N2 through the sixteenth transistor T16. Since the level of the input signal is high, the second transistor T2, the thirteenth transistor T13 and the seventeenth transistor T17 are turned off under the control of the input signal. The fifteenth transistor T15 is turned on under the control of the first clock signal, and transmits the second voltage signal to the seventh node N7, and transmits the second voltage signal to the fifth node N5 through the fourteenth transistor T14, and charges the third capacitor C3. The twelfth transistor T12 is turned off under the control of the second clock signal. Due to the storage effect of the fourth capacitor C4, the voltage of the first node N1 remains at a high level, and the first transistor T1 is turned off under the control of the voltage of the first node N1. The first transistor T1 and the second transistor T2 are both turned off, and the level of the first scan signal output by the first output terminal EM_OUT remains at the previous low level.

[0140] The fifth transistor T5 is turned off under the control of the voltage of the first node N1. The fourth transistor T4 and the sixth transistor T6 are turned on under the control of the first scan signal, and the sixth transistor T6 transmits the third voltage signal to the third node N3, so that the third transistor T3 is turned off under the control of the voltage of the third node N3, and the fourth transistor T4 transmits the third voltage signal to the second output terminal Reset_OUT as the second scan signal output.

[0141] Therefore, in the first stage S1 , the level of the first scanning signal outputted by the first output terminal EM_OUT is a low level, and the level of the second scanning signal outputted by the second output terminal Reset_OUT is a high level.

[0142] In the second stage S2, if Figure 6 As shown, the level of the input signal is a high level, the level of the first clock signal is a high level, and the level of the second clock signal is a low level.

[0143] The eighth transistor T8 and the fifteenth transistor T15 are turned off under the control of the first clock signal, and the ninth transistor T9 and the twelfth transistor T12 are turned on under the control of the second clock signal. Due to the storage function of the third capacitor C3, the voltage of the fifth node N5 remains at a low level, and the tenth transistor T10 and the eleventh transistor T11 are turned on under the control of the voltage of the fifth node N5. The first voltage signal is transmitted to the second node N2 and the fourth node N4 through the tenth transistor T10 and the ninth transistor T9 in sequence, so that the second transistor T2 and the thirteenth transistor T13 are turned off. The second clock signal is transmitted to the first node N1 through the eleventh transistor T11 and the twelfth transistor T12 in sequence, so that the voltage of the first node N1 is a low level. The first transistor T1 is turned on under the control of the voltage of the first node N1, and the first voltage signal is output from the first output terminal EM_OUT as the first scan signal.

[0144] The fourth transistor T4 and the sixth transistor T6 are turned off under the control of the first scan signal. The fifth transistor T5 is turned on under the control of the voltage of the first node N1, and transmits the second voltage signal to the third node N3. The third transistor T3 is turned on under the control of the second voltage signal, and transmits the second voltage signal to the second output terminal Reset_OUT as the second scan signal output.

[0145] Therefore, in the second stage S2, the level of the first scanning signal outputted by the first output terminal EM_OUT is a high level, and the level of the second scanning signal outputted by the second output terminal Reset_OUT is a low level.

[0146] In the third stage S3, if Figure 6 As shown, the level of the input signal is a high level, the level of the first clock signal is a low level, and the level of the second clock signal is a high level.

[0147] The eighth transistor T8 is turned on under the control of the first clock signal, and transmits the input signal to the fourth node N4, and transmits the input signal to the second node N2 through the sixteenth transistor T16, and the second transistor T2, the thirteenth transistor T13 and the seventeenth transistor T17 are turned off under the control of the input signal. The fifteenth transistor T15 is turned on under the control of the first clock signal, and transmits the second voltage signal to the seventh node N7, and transmits the second voltage signal to the fifth node N5 through the fourteenth transistor T14, and charges the third capacitor C3. The twelfth transistor T12 is turned off under the control of the second clock signal. Due to the storage function of the fourth capacitor C4, the voltage of the first node N1 remains at a low level, and the first transistor T1 remains in a conducting state under the control of the voltage of the first node N1, and outputs the first voltage signal as the first scan signal from the first output terminal EM_OUT.

[0148] The fourth transistor T4 and the sixth transistor T6 are turned off under the control of the first scan signal. The fifth transistor T5 is turned on under the control of the voltage of the first node N1, and transmits the second voltage signal to the third node N3. The third transistor T3 is turned on under the control of the second voltage signal, and transmits the second voltage signal to the second output terminal Reset_OUT as the second scan signal output.

[0149] Therefore, in the third stage S3 , the level of the first scan signal outputted by the first output terminal EM_OUT is a high level, and the level of the second scan signal outputted by the second output terminal Reset_OUT is a low level.

[0150] In the fourth stage S4, if Figure 6 As shown, the level of the input signal is a low level, the level of the first clock signal is a high level, and the level of the second clock signal is a low level.

[0151] The eighth transistor T8 and the fifteenth transistor T15 are turned off under the control of the first clock signal, and the ninth transistor T9 and the twelfth transistor T12 are turned on under the control of the second clock signal. Due to the storage function of the third capacitor C3, the voltage of the fifth node N5 remains at a low level, and the tenth transistor T10 and the eleventh transistor T11 are turned on under the control of the voltage of the fifth node N5. The first voltage signal is transmitted to the second node N2 and the fourth node N4 through the tenth transistor T10 and the ninth transistor T9 in sequence, so that the second transistor T2 and the thirteenth transistor T13 are turned off. The second clock signal is transmitted to the first node N1 through the eleventh transistor T11 and the twelfth transistor T12 in sequence, so that the voltage of the first node N1 is a low level. The first transistor T1 is turned on under the control of the voltage of the first node N1, and the first voltage signal is output from the first output terminal EM_OUT as the first scan signal.

[0152] The fourth transistor T4 and the sixth transistor T6 are turned off under the control of the first scan signal. The fifth transistor T5 is turned on under the control of the voltage of the first node N1, and transmits the second voltage signal to the third node N3. The third transistor T3 is turned on under the control of the second voltage signal, and transmits the second voltage signal to the second output terminal Reset_OUT as the second scan signal output.

[0153] Therefore, in the fourth stage S4 , the level of the first scan signal outputted by the first output terminal EM_OUT is a high level, and the level of the second scan signal outputted by the second output terminal Reset_OUT is a low level.

[0154] In the fifth stage S5, if Figure 6 As shown, the level of the input signal is a low level, the level of the first clock signal is a low level, and the level of the second clock signal is a high level.

[0155] The ninth transistor T9 and the twelfth transistor T12 are turned off under the control of the second clock signal.

[0156] The eighth transistor T8 is turned on under the control of the first clock signal, and transmits the input signal to the fourth node N4, and transmits the input signal to the second node N2 through the sixteenth transistor T16, and the second transistor T2, the thirteenth transistor T13 and the seventeenth transistor T17 are turned on under the control of the input signal. The seventeenth transistor T17 transmits the first voltage signal to the first node N1, so that the first transistor T1 is turned off under the control of the voltage of the first node N1. The second transistor T2 is turned on under the control of the voltage of the second node N2, and transmits the second voltage signal to the first output terminal EM_OUT as the first scan signal output.

[0157] The fifth transistor T5 is turned off under the control of the voltage of the first node N1. The fourth transistor T4 and the sixth transistor T6 are turned on under the control of the first scan signal, and the sixth transistor T6 transmits the third voltage signal to the third node N3, so that the third transistor T3 is turned off under the control of the voltage of the third node N3, and the fourth transistor T4 transmits the third voltage signal to the second output terminal Reset_OUT as the second scan signal output.

[0158] Therefore, in the fifth stage S5 , the level of the first scan signal outputted by the first output terminal EM_OUT is a low level, and the level of the second scan signal outputted by the second output terminal Reset_OUT is a high level.

[0159] In the sixth stage S6, if Figure 6 As shown, the level of the input signal is a low level, the level of the first clock signal is a high level, and the level of the second clock signal is a low level.

[0160] The eighth transistor and the fifteenth transistor T15 are turned off under the control of the first clock signal. The fourth node N4 and the second node N2 are in a suspended state. Due to the bootstrap effect of the second capacitor C2, the voltages of the fourth node N4 and the second node N2 are at a low level, and the second transistor T2, the thirteenth transistor T13 and the seventeenth transistor T17 are turned on. The thirteenth transistor T13 is turned on under the control of the voltage of the fourth node N4, and transmits the first clock signal to the seventh node N7 and the fifth node N5. The eleventh transistor T11 is turned off under the control of the voltage of the fifth node N5. The seventeenth transistor T17 transmits the first voltage signal to the first node N1, so that the first transistor T1 is turned off under the control of the voltage of the first node N1. The second transistor T2 is turned on under the control of the voltage of the second node N2, and transmits the second voltage signal to the first output terminal EM_OUT as the first scan signal output.

[0161] The fifth transistor T5 is turned off under the control of the voltage of the first node N1. The fourth transistor T4 and the sixth transistor T6 are turned on under the control of the first scan signal, and the sixth transistor T6 transmits the third voltage signal to the third node N3, so that the third transistor T3 is turned off under the control of the voltage of the third node N3, and the fourth transistor T4 transmits the third voltage signal to the second output terminal Reset_OUT as the second scan signal output.

[0162] Therefore, in the sixth stage S6 , the level of the first scanning signal outputted by the first output terminal EM_OUT is a low level, and the level of the second scanning signal outputted by the second output terminal Reset_OUT is a high level.

[0163] After that, the fifth stage S5 and the sixth stage S6 are cycled in sequence. In this process, the second transistor T2 remains on, and the level of the first scanning signal output by the first output terminal EM_OUT remains at a low level; the third transistor T4 remains on, and the level of the second scanning signal output by the second output terminal Reset_OUT remains at a high level. After the level of the input signal becomes high, this process ends.

[0164] It is understandable that the present disclosure is explained by taking the multiple transistors included in the above-mentioned shift register 2a as P-type transistors as an example, of course, the multiple transistors can all be N-type transistors. Those skilled in the art can understand that when the types of the transistors are different, the corresponding timing diagrams may also be different, so the timing diagrams in this application are not limited thereto.

[0165] As can be seen from the above, in the display substrate 100 provided by the present disclosure, each shift register 2a in the scan drive circuit 2 has two signal output terminals (i.e., the first output terminal EM_OUT and the second output terminal Reset_OUT), and the two signal output terminals can output different signals respectively. In this way, the same drive circuit (i.e., the above-mentioned scan drive circuit 2) can be used to provide two different signals to the sub-pixel P. Compared with the related art, it is beneficial to improve the integration of the drive circuit, reduce the number of drive circuits required to be arranged, and facilitate the display substrate 100 to achieve a narrow frame design.

[0166] Exemplarily, the first scan signal outputted from the first output terminal EM_OUT may be transmitted to the sub-pixel P as a light emitting control signal, and the second scan signal outputted from the second output terminal Reset_OUT may be transmitted to the sub-pixel P as a reset signal.

[0167] It should be noted that in Figure 5In the shift register 2a shown, in order to illustrate the connection relationship between the transistors, signal terminals such as the first voltage signal terminal VGH1, the third voltage signal terminal VGH2, the second voltage signal terminal VGL, the first clock signal terminal CK, the second clock signal terminal CB, and the input signal terminal STV are defined, wherein each signal terminal, for example, does not represent an actual component, but rather represents the junction point of each transistor and the corresponding signal line.

[0168] For example, the first voltage signal terminal VGH1 is represented by the junction of the first electrode of the first transistor T1, the first electrode of the tenth transistor T10 and the first voltage signal line VGHL1. For other signal terminals, please refer to this description. In addition, for the first voltage signal line VGHL1, please refer to the description below, which will not be repeated here.

[0169] Combine the following Figure 7 and Figure 8 The layout of the scan driving circuit 2 is schematically described.

[0170] In some examples, such as Figure 7 and Figure 8 As shown, the scan driving circuit 2 further includes: a first voltage signal line VGHL1, a second voltage signal line VGLL and a third voltage signal line VGHL2 extending along the first direction Y and sequentially arranged in intervals along the second direction X. The first voltage signal line VGHL1 is configured to transmit a first voltage signal, the second voltage signal line VGLL is configured to transmit a second voltage signal, and the third voltage signal line VGHL2 is configured to transmit a third voltage signal.

[0171] Exemplarily, the first voltage signal line VGHL1 , the second voltage signal line VGLL and the third voltage signal line VGHL2 are disposed in the border area B, and the third voltage signal line VGHL2 is closer to the display area A than the first voltage signal line VGHL1 .

[0172] In some examples, such as Figure 7 and Figure 8 As shown, in the scan driving circuit 2, the first transistor T1 and the second transistor T2 included in each shift register 2a are arranged between the first voltage signal line VGHL1 and the second voltage signal line VGLL. The first electrode of the first transistor T1 is electrically connected to the first voltage signal line VGHL1, and the first electrode of the second transistor T2 is electrically connected to the second voltage signal line VGLL.

[0173] In some examples, such as Figure 7 and Figure 8As shown, in the scan driving circuit 2, the third transistor T3 and the fourth transistor T4 included in each shift register 2a are arranged between the second voltage signal line VGLL and the third voltage signal line VGHL2. The first electrode of the third transistor T3 is electrically connected to the second voltage signal line VGLL, and the first electrode of the fourth transistor T4 is electrically connected to the third voltage signal line VGHL2.

[0174] Since the first voltage signal and the third voltage signal are the same voltage signal, this means that the first voltage signal line VGHL1 and the third voltage signal line VGHL2 can be the same high voltage signal line.

[0175] By setting two identical high voltage signal lines, setting the two high voltage signal lines on opposite sides of the second voltage signal line VGLL, setting the first transistor T1 and the second transistor T2 between one of the high voltage signal lines (that is, the first voltage signal line VGHL1) and the second voltage signal line VGLL, and setting the third transistor T3 and the fourth transistor T4 between the other high voltage signal line (that is, the third voltage signal line VGHL2) and the second voltage signal line VGLL, the distance between the first transistor T1 and the first voltage signal line VGHL1 can be reduced, which is convenient for realizing the electrical connection between the first transistor T1 and the first voltage signal line VGHL1, the distance between the second transistor T2 and the second voltage signal line VGLL can be reduced, which is convenient for realizing the electrical connection between the second transistor T2 and the second voltage signal line VGLL, the distance between the third transistor T3 and the second voltage signal line VGLL can be reduced, which is convenient for realizing the electrical connection between the third transistor T3 and the second voltage signal line VGLL, and the distance between the fourth transistor T4 and the third voltage signal line VGHL2 can be reduced, which is convenient for realizing the electrical connection between the fourth transistor T4 and the third voltage signal line VGHL2. This is beneficial to simplifying the structure of the scan driving circuit 2 and improving the yield of the scan driving circuit 2 .

[0176] In some examples, such as Figure 7 and Figure 8 As shown, each shift register 2a further includes: at least one first scanning signal line EL2 electrically connected to the first output terminal EM_OUT; and at least one second scanning signal line RL2 electrically connected to the second output terminal Reset_OUT.

[0177] For example, Figure 3 As shown, when the first scan signal outputted from the first output terminal EM_OUT is used as the light emitting control signal, each first scan signal line EL2 can be electrically connected to an enable signal line EL1. In this way, the first scan signal outputted from the first output terminal EM_OUT can be sequentially transmitted to the corresponding sub-pixel P via the first scan signal line EL2 and the enable signal line EL1.

[0178] For example, Figure 3 As shown, when the second scan signal outputted by the second output terminal Reset_OUT is used as a reset signal, each second scan signal line RL2 can be electrically connected to a reset signal transmission line RL1. In this way, the second scan signal outputted by the second output terminal Reset_OUT can be sequentially transmitted to the corresponding sub-pixel P via the second scan signal line RL2 and the reset signal transmission line RL1.

[0179] For example, Figure 3 As shown, the first scan signal line EL2 and the second scan signal line RL2 both extend along the second direction X. That is, the extending directions of the first scan signal line EL2 and the second scan signal line RL2 are the same as the extending directions of the enable signal line EL1 and the reset signal transmission line RL1.

[0180] In this way, the first scanning signal line EL2 and the second scanning signal line RL2 can be basically straight-lined, and after extending to the display area A along the second direction X, they can be directly electrically connected to the corresponding enable signal line EL1 or the reset signal transmission line RL1, which can simplify the setting method of the first scanning signal line EL2 and the second scanning signal line RL2, and thus help to simplify the structure of the scanning driving circuit 2 and reduce the size of the scanning driving circuit 2.

[0181] Therefore, the display substrate 100 provided by some embodiments of the present disclosure can facilitate the electrical connection between the first transistor T1 and the first voltage signal line VGHL1, the electrical connection between the second transistor T2 and the second voltage signal line VGLL, the electrical connection between the third transistor T3 and the second voltage signal line VGLL, and the electrical connection between the fourth transistor T4 and the third voltage signal line VGHL2 by arranging the first voltage signal line VGHL1, the second voltage signal line VGLL and the third voltage signal line VGHL2 in the scan drive circuit 2 in sequence, and arranging the first transistor T1 and the second transistor T2 in the shift register 2a included therein between the first voltage signal line VGHL1 and the second voltage signal line VGLL, and arranging the third transistor T3 and the fourth transistor T4 between the second voltage signal line VGLL and the third voltage signal line VGHL2, thereby simplifying the structure of the scan drive circuit 2 and improving the yield of the scan drive circuit 2.

[0182] Moreover, by providing a first output terminal EM_OUT electrically connected to the second electrode of the first transistor T1 and the second electrode of the second transistor T2, providing a second output terminal Reset_OUT electrically connected to the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, and electrically connecting the control electrode of the third transistor T3 and the third node N3, and electrically connecting the control electrode of the fourth transistor T4 and the first output terminal EM_OUT, the third transistor T3 and the fourth transistor T4 can be used as inverters, so that the second scan signal output by the second output terminal Reset_OUT is an opposite signal to the first scan signal output by the first output terminal EM_OUT, that is, the second output terminal Reset_OUT and the first output terminal EM_OUT can output different signals respectively. In this way, different signals are transmitted to the display area through the first scan signal line EL2 electrically connected to the first output terminal EM_OUT and the second scan signal line RL2 electrically connected to the second output terminal Reset_OUT. Compared with the related art, it is beneficial to improve the integration of the scan drive circuit 2, reduce the number of drive circuits required to be arranged, and facilitate the display substrate 100 to achieve a narrow frame design.

[0183] In some examples, such as Figure 7 , Figure 8 and Fig.12 As shown, the first voltage signal line VGHL1, the second voltage signal line VGLL and the third voltage signal line VGHL2 are arranged on the same layer.

[0184] Here, the "same layer" mentioned in this article refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask template through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. In this way, the above-mentioned first voltage signal line VGHL1, the second voltage signal line VGLL and the third voltage signal line VGHL2 can be prepared and formed simultaneously in a single patterning process, which is conducive to simplifying the preparation process of the scan drive circuit 2 and the display substrate 100.

[0185] For example, Fig.12 As shown, the film layer where the first voltage signal line VGHL1 , the second voltage signal line VGLL and the third voltage signal line VGHL2 are located can be called a source-drain conductive layer 6 .

[0186] In some examples, the orthographic projection of the first scan signal line EL2 on the substrate 1 does not overlap with the orthographic projection of the second scan signal line RL2 on the substrate 1. That is, the first scan signal line EL2 and the second scan signal line RL2 are arranged at intervals. In the process of the first scan signal line EL2 and the second scan signal line RL2 extending along the second direction X, the two do not overlap.

[0187] In this way, a short circuit between the first scanning signal line EL2 and the second scanning signal line RL2 can be avoided, signal crosstalk can be avoided, and accuracy of signals transmitted by the first scanning signal line EL2 and the second scanning signal line RL2 can be ensured.

[0188] In some examples, such as Figure 7 , Figure 8 and Fig.11 As shown, the first scanning signal line EL2 and the second scanning signal line RL2 are arranged on the same layer.

[0189] In this way, the first scanning signal line EL2 and the second scanning signal line RL2 can be formed simultaneously in one patterning process, which is beneficial to simplifying the manufacturing process of the scanning driving circuit 2 and the display substrate 100 .

[0190] For example, Fig.11 As shown, the film layer where the first scanning signal line EL2 and the second scanning signal line RL2 are located can be called a first gate conductive layer 5. The first gate conductive layer 5 can be located between the source-drain conductive layer 6 and the substrate 1.

[0191] It should be noted that the present disclosure does not limit the number of the first scanning signal lines EL2 and the second scanning signal lines RL2 in the same shift register 2a, and the specific number can be selected and set according to actual needs.

[0192] In some examples, such as Figure 7 As shown, in the same shift register 2a, the number of the first scanning signal line EL2 is one, and the number of the second scanning signal line RL2 is one.

[0193] Exemplarily, the same shift register 2a can be electrically connected through a first scan signal line EL2 and an enable signal line EL1 to transmit a first scan signal to a corresponding row of sub-pixels P, and can be electrically connected through a second scan signal line RL2 and a reset signal transmission line RL1 to transmit a second scan signal to a corresponding row of sub-pixels P.

[0194] For example, the first scanning signal line EL2 and the second scanning signal line RL2 correspond to the same row of sub-pixels P. That is, one shift register 2 a corresponds to one row of sub-pixels P.

[0195] In other examples, such as Figure 8 As shown, the number of the first scanning signal lines EL2 and the second scanning signal lines RL2 included in the same shift register 2a is both multiple, wherein the number of the first scanning signal lines EL2 and the number of the second scanning signal lines RL2 may be equal, for example.

[0196] Exemplarily, the same shift register 2a can be electrically connected to multiple enable signal lines EL1 through multiple first scan signal lines EL2, respectively, to transmit first scan signals to corresponding multiple rows of sub-pixels P, and can be electrically connected to multiple reset signal transmission lines RL1 through multiple second scan signal lines RL2, respectively, to transmit second scan signals to corresponding multiple rows of sub-pixels P.

[0197] At this time, the same shift register 2 a can correspond to multiple rows of sub-pixels P. This is beneficial to reducing the number of shift registers 2 a and simplifying the structure of the scan drive circuit 2 .

[0198] Exemplarily, along the first direction Y, the first scanning signal lines EL2 and the second scanning signal lines RL2 are alternately arranged in sequence.

[0199] In this way, the regularity of the arrangement of the first scanning signal lines EL2 and the second scanning signal lines RL2 can be improved, which facilitates simplifying the layout difficulty of the shift register 2 a and the scanning driving circuit 2 .

[0200] For example, Figure 8 As shown, among the plurality of first scanning signal lines EL2 and the plurality of second scanning signal lines RL2, one first scanning signal line EL2 and one second scanning signal line RL2 form a group of output signal lines, and two adjacent groups of output signal lines are arranged at intervals.

[0201] For example, the adjacent first scanning signal line EL2 and the adjacent second scanning signal line RL2 can be divided into a group of output signal lines, wherein a group of output signal lines corresponds to a row of sub-pixels P.

[0202] By setting a gap between two adjacent groups of output signal lines, each first scanning signal line EL2 and each second scanning signal line RL2 can be basically straight, which not only facilitates the electrical connection with the corresponding enable signal line EL1 and the reset signal transmission line RL1, but also helps to optimize the layout structure of the scanning drive circuit 2 and reduce the impact of process fluctuations in the process of preparing the scanning drive circuit 2 on the scanning drive circuit 2.

[0203] In some embodiments, Figure 7 to Figure 9 As shown, the third transistor T3 includes a third semiconductor portion 31, and the fourth transistor T4 includes a fourth semiconductor portion 41. The third semiconductor portion 31 and the fourth semiconductor portion 41 are arranged in sequence along the first direction Y.

[0204] That is, the third transistor T3 and the fourth transistor T4 are sequentially arranged in an interval along the first direction Y. Figure 7 and Figure 8 In the embodiment, the third transistor T3 and the fourth transistor T4 are placed one above the other in space.

[0205] In this way, the third transistor T3 and the fourth transistor T4 can be reduced in the second direction X (eg Figure 7 and Figure 8 The area occupied by the second voltage signal line VGLL and the third voltage signal line VGHL2 can be reduced, thereby reducing the area occupied by the shift register 2a and the scan drive circuit 2 in the second direction X, which is beneficial to reducing the size of the frame area B and making it easier for the display substrate 100 to achieve a narrow frame design.

[0206] It should be noted that there are many locations where the first scanning signal line EL2 and the second scanning signal line RL2 can be set, and they can be selected according to actual needs.

[0207] In some examples, such as Figure 7 As shown, when the number of the first scanning signal line EL2 and the second scanning signal line RL2 included in the same shift register 2a is both one, along the first direction Y, the first scanning signal line EL2 and the second scanning signal line RL2 can be both located between the third semiconductor part 31 and the fourth semiconductor part 41, or, can be both located between two adjacent shift registers 2a.

[0208] In other examples, such as Figure 8 As shown, when the number of the first scanning signal lines EL2 and the second scanning signal lines RL2 included in the same shift register 2a is multiple, along the first direction Y, a portion of the first scanning signal lines EL2 and the second scanning signal lines RL2 (for example, a group of output signal lines) can be located between the third semiconductor part 31 and the fourth semiconductor part 41, and another portion of the first scanning signal lines EL2 and the second scanning signal lines RL2 (for example, at least one group of output signal lines) can be located between two adjacent shift registers 2a.

[0209] In this way, the gap in the shift register 2 a can be reasonably utilized, the area occupied by the scan driving circuit 2 in the first direction Y can be reduced, and the layout of other circuit structures in the display substrate 100 can be facilitated.

[0210] In some examples, such as Figure 7 and Figure 8 As shown, the orthographic projection of any one of the first scanning signal line EL2 and the second scanning signal line RL2 on the substrate 1 does not overlap with the orthographic projection of any one of the third semiconductor portion 31 and the fourth semiconductor portion 41 on the substrate 1 .

[0211] That is, there is a gap between the orthographic projection of any one of the first scanning signal line EL2 and the second scanning signal line RL2 on the substrate 1 and the orthographic projection of any one of the third semiconductor portion 31 and the fourth semiconductor portion 41 on the substrate 1 , and there is no overlap.

[0212] This can avoid forming a capacitor between any one of the first scanning signal line EL2 and the second scanning signal line RL2 and any one of the third transistor T3 and the fourth transistor T4, avoiding signal crosstalk, which is beneficial to ensuring the accuracy of the signals transmitted by the first scanning signal line EL2 and the second scanning signal line RL2.

[0213] In some examples, such as Fig. 9 As shown, the third semiconductor portion 31 of the third transistor T3 includes: a plurality of third channel portions 311 arranged at intervals along the first direction Y, and a third input portion 312 and a third output portion 313 disposed on both sides of each third channel portion 311 .

[0214] For example, the third channel portion 311 , the third input portion 312 , and the third output portion 313 may all extend along the second direction X.

[0215] For example, Fig. 9 As shown, the third input part 312 and the third output part 313 may be respectively arranged on opposite sides of each third channel part 311. For example, only the third input part 312 or the third output part 313 may be arranged between any two adjacent third channel parts 311. That is, the third input part 312 and the third output part 313 are arranged alternately in sequence.

[0216] For example, Fig. 9 As shown, the film layer where the third semiconductor portion 31 is located can be called a semiconductor material layer 3. The semiconductor material layer 3 can be located between the first gate conductive layer 5 and the substrate 1.

[0217] For example, the semiconductor material layer 3 may be formed by using materials such as amorphous silicon, polycrystalline silicon or oxide semiconductor.

[0218] In some examples, such as Figure 7 , Figure 8 and Fig.10 As shown, the control electrode of the third transistor T3 includes: a third gate conductive pattern G3 in a comb shape and arranged on a side of the third semiconductor portion 31 away from the substrate 1. The third gate conductive pattern G3 includes a plurality of third sub-gates G31 arranged at intervals along the first direction Y, and the orthographic projection of each third sub-gate G31 on the substrate 1 partially overlaps with the orthographic projection of the third channel portion 311 on the substrate 1.

[0219] For example, Fig.10 As shown, the third sub-gate G31 may extend along the second direction X. One third sub-gate G31 corresponds to one third channel portion 311 , and both ends of the third sub-gate G31 extend out of the range of the corresponding third channel portion 311 .

[0220] For example, Fig.10 As shown, the third gate conductive pattern G3 further includes: a third gate connection portion G32 extending along the first direction Y. The third gate connection portion G32 is connected to one end of each third sub-gate G31 so as to synchronously transmit a corresponding signal to each third sub-gate G31.

[0221] For example, the third gate connection portion G32 and each third sub-gate G31 are in an integrated structure. That is, the third gate connection portion G32 and each third sub-gate G31 are made of the same film layer and formed in the same patterning process, and there is no disconnection between the two. This is conducive to improving the structural stability of the third gate conductive pattern G3, and improving the structural stability of the scan drive circuit 2 and the display substrate 100.

[0222] For example, Fig.10 As shown, the film layer where the third gate conductive pattern G3 is located can be called the second gate conductive layer 4. The second gate conductive layer 4 can be located between the semiconductor material layer 3 and the first gate conductive layer 5.

[0223] For example, the display substrate 100 may further include: a first insulating layer disposed between the semiconductor material layer 3 and the second gate conductive layer 4, a second insulating layer disposed between the second gate conductive layer 4 and the first gate conductive layer 5, and a third insulating layer disposed between the first gate conductive layer 5 and the source-drain conductive layer 6. The first insulating layer may be used to protect the semiconductor material layer 3, the second insulating layer may be used to protect the second gate conductive layer 4, and the third insulating layer may be used to protect the first gate conductive layer 5.

[0224] It can be understood that, in the process of preparing and forming the third semiconductor portion 31, for example, a third semiconductor material layer can be first prepared and formed on the substrate 1, and then a third gate conductive pattern G3 can be sequentially formed on the third semiconductor material layer away from the substrate 1, and then the third gate conductive pattern G3 is used as a mask to dope the portion of the third semiconductor material layer not covered by the third gate conductive pattern G3, so that the portion of the third semiconductor material layer not covered by the third gate conductive pattern G3 is formed into a conductive portion (that is, a third input portion 312 and a third output portion 313), and the portion of the third semiconductor material layer covered by the third gate conductive pattern G3 is formed into a third channel portion 311, thereby obtaining the third semiconductor portion 31. The preparation process of the semiconductor portions of the remaining transistors is the same as that of the third semiconductor portion 31, and the third semiconductor portion 31 can be specifically referred to, and will not be described in detail herein.

[0225] In some examples, such as Fig.12 As shown, the first electrode of the third transistor T3 includes: a third input electrode pattern S3 in a comb shape, which is arranged on the side of the third gate conductive pattern G3 away from the substrate 1. The third input electrode pattern S3 includes a plurality of third sub-input electrodes S31 arranged at intervals along the first direction Y. The orthographic projection of each third sub-input electrode S31 on the substrate 1 partially overlaps with the orthographic projection of the corresponding third input portion 312 on the substrate 1.

[0226] For example, Fig.12 As shown, the third sub-input electrode S31 may extend along the second direction X. One third sub-input electrode S31 corresponds to one third input portion 312 , and both ends of the third sub-input electrode S31 extend out of the range of the corresponding third input portion 312 .

[0227] Furthermore, if Fig.12 As shown, a plurality of via holes K penetrating the first insulating layer, the second insulating layer and the third insulating layer are provided between each third sub-input electrode S31 and the corresponding third input portion 312, and each third sub-input electrode S31 can be electrically connected to the corresponding third input portion 312 through the plurality of via holes K. At this time, the third input portion 312 can also serve as a part of the first electrode of the third transistor T3.

[0228] For example, Fig.12 As shown, the third input electrode pattern S3 further includes: a third input connection portion S32 extending along the first direction Y. The third input connection portion S32 is connected to one end of each third sub-input electrode S31 so as to synchronously transmit a corresponding signal to each third sub-input electrode S31 .

[0229] For example, Fig.12 As shown, the first electrode of the third transistor T3 can be electrically connected to the second voltage signal terminal VGLL through the third input electrode pattern S3.

[0230] For example, Fig.12 As shown, in the third input electrode pattern S3, the third input connection portion S32 and each third sub-input electrode S31 are in an integrated structure. Further, the third input electrode pattern S3 can be in an integrated structure with the second voltage signal line VGLL, for example.

[0231] That is, the third input electrode pattern S3 and the second voltage signal line VGLL are formed by the same film layer and in the same patterning process, and there is no disconnection between the two. In addition, in the third input electrode pattern S3, there is no disconnection between the third input connection portion S32 and each third sub-input electrode S31. This is conducive to improving the structural stability of the third input electrode pattern S3 and the second voltage signal line VGLL, and improving the structural stability of the scan drive circuit 2 and the display substrate 100.

[0232] In some examples, such as Fig.12 As shown, the second electrode of the third transistor T3 includes: a third output electrode pattern D3 in a comb shape, which is arranged on the side of the third gate conductive pattern G3 away from the substrate 1. The third output electrode pattern D3 includes a plurality of third sub-output electrodes D31 arranged at intervals along the first direction Y. The orthographic projection of the third sub-output electrode D31 on the substrate 1 partially overlaps with the orthographic projection of the third output portion 313 on the substrate 1.

[0233] For example, Fig.12 As shown, the third sub-output electrode D31 may extend along the second direction X. One third sub-output electrode D31 corresponds to one third output portion 313 , and both ends of the third sub-output electrode D31 extend out of the range of the corresponding third output portion 313 .

[0234] Furthermore, if Fig.12 and Fig.13 As shown, a plurality of first via holes K1 penetrating the first insulating layer, the second insulating layer and the third insulating layer are provided between each third sub-output electrode D31 and the corresponding third output portion 313, and each third sub-output electrode D31 can be electrically connected to the corresponding third output portion 313 through the plurality of first via holes K1. At this time, the third output portion 313 can also serve as a part of the second electrode of the third transistor T3.

[0235] For example, Fig.12 As shown, the third output electrode pattern D3 further includes: a third output connection portion D32 extending along the first direction Y. The third output connection portion D32 is connected to one end of each third sub-output electrode D31 so as to synchronously transmit a corresponding signal to each third sub-output electrode D31 .

[0236] Optionally, in the third output electrode pattern D3, the third output connection portion D32 and each third sub-output electrode D31 are in an integrated structure, which is beneficial to improving the structural stability of the third output electrode pattern D3, and improving the structural stability of the scan driving circuit 2 and the display substrate 100.

[0237] For example, Fig.12 and Fig.13 As shown, the second electrode of the third transistor T3 may be electrically connected to the second scan signal line RL2 via the third output electrode pattern D3.

[0238] For example, a via hole K penetrating the third insulating layer is disposed between the third output electrode pattern D3 and the second scan signal line RL2 , and the third output electrode pattern D3 may be electrically connected to the second scan signal line RL2 through the via hole K.

[0239] For example, Fig.12 As shown, the third input electrode pattern S3 and the third output electrode pattern D3 are arranged in an interdigitated structure. That is, the third sub-input electrodes S31 and the third sub-output electrodes D31 are alternately arranged in sequence, and the third sub-input electrodes S31 and the third sub-output electrodes D31 are arranged between the third input connection portion S32 and the third output connection portion D32.

[0240] This is beneficial for rationally utilizing the space of the display substrate 100 and reducing the space occupied by the scan driving circuit 2 in the display substrate 100 .

[0241] For example, Fig.12 As shown, the third input electrode pattern S3 and the third output electrode pattern D3 are arranged in the same layer and are located in the source-drain conductive layer 6 .

[0242] In this way, the third input electrode pattern S3 and the third output electrode pattern D3 can be simultaneously formed in one patterning process, which is beneficial to simplifying the manufacturing process of the scan driving circuit 2 and the display substrate 100 .

[0243] In some examples, such as Figure 7 to Figure 9 As shown, the fourth semiconductor portion 41 of the fourth transistor T4 includes: a plurality of fourth channel portions 411 arranged at intervals along the first direction Y, and a fourth input portion 412 and a fourth output portion 413 disposed on both sides of each fourth channel portion 411 .

[0244] For example, the fourth channel portion 411 , the fourth input portion 412 , and the fourth output portion 413 may all extend along the second direction X.

[0245] For example, Fig. 9 As shown, the fourth input portion 412 and the fourth output portion 413 may be respectively disposed on opposite sides of each fourth channel portion 411. For example, only the fourth input portion 412 or the fourth output portion 413 may be disposed between any two adjacent fourth channel portions 411. That is, the fourth input portion 412 and the fourth output portion 413 are alternately disposed in sequence.

[0246] For example, Fig. 9 As shown, the film layer where the fourth semiconductor portion 41 is located may be the semiconductor material layer 3. That is, the fourth semiconductor portion 41 and the third semiconductor portion 31 may be disposed in the same layer.

[0247] In some examples, such as Figure 7 , Figure 8 and Fig.10As shown, the control electrode of the fourth transistor T4 includes: a fourth gate conductive pattern G4 in a comb shape and arranged on a side of the fourth semiconductor portion 41 away from the substrate 1. The fourth gate conductive pattern G4 includes a plurality of fourth sub-gates G41 arranged at intervals along the first direction Y, and the orthographic projection of each fourth sub-gate G41 on the substrate 1 partially overlaps with the orthographic projection of the fourth channel portion 411 on the substrate 1.

[0248] For example, Fig.10 As shown, the fourth sub-gate G41 may extend along the second direction X. One fourth sub-gate G41 corresponds to one fourth channel portion 411 , and both ends of the fourth sub-gate G41 extend out of the range of the corresponding fourth channel portion 411 .

[0249] For example, Fig.10 As shown, the fourth gate conductive pattern G4 further includes: a fourth gate connection portion G42 extending along the first direction Y. The fourth gate connection portion G42 is connected to one end of each fourth sub-gate G41 so as to synchronously transmit a corresponding signal to each fourth sub-gate G41.

[0250] For example, the fourth gate connection portion G42 and each fourth sub-gate G41 are in an integrated structure. That is, the fourth gate connection portion G42 and each fourth sub-gate G41 are made of the same film layer and formed in the same patterning process, and there is no disconnection between the two. This is conducive to improving the structural stability of the fourth gate conductive pattern G4, and improving the structural stability of the scan drive circuit 2 and the display substrate 100.

[0251] For example, Fig.10 As shown, the film layer where the fourth gate conductive pattern G4 is located may be the second gate conductive layer 4. That is, the fourth gate conductive pattern G4 and the third gate conductive pattern G3 may be disposed in the same layer.

[0252] For example, Figure 7 , Figure 8 and Fig.15 As shown, the control electrode of the fourth transistor T4 can be electrically connected to the first scanning signal line EL2 through the fourth gate conductive pattern G4. Therefore, the fourth gate conductive pattern G4 and the first scanning signal line EL2 are located in different film layers, so the two can be electrically connected by changing layers.

[0253] For example, Figure 7 , Figure 8 , 12 and Fig.15As shown, the shift register 2a further includes: a first connection portion CN1 extending along the first direction Y and disposed between the fourth gate conductive pattern G4 and the first scanning signal line EL2. One end of the first connection portion CN1 is electrically connected to the fourth gate conductive pattern G4, and the other end of the first connection portion CN1 is electrically connected to the first scanning signal line EL2.

[0254] Optional, such as Fig.15 As shown, a second via hole K2 penetrating the second insulating layer and the third insulating layer is provided between one end of the first connection portion CN1 and the overlapping portion of the fourth gate conductive pattern G4, and the two are electrically connected through the second via hole K2. A third via hole K3 penetrating the third insulating layer is provided between the other end of the first connection portion CN1 and the overlapping portion of the first scanning signal line EL2, and the two are electrically connected through the third via hole K3.

[0255] By setting a first connecting portion CN1 extending along the first direction Y and using the first connecting portion CN1 to connect the fourth gate conductive pattern G4 and the first scanning signal line EL2, it is possible to avoid forming a corner at the position where the first scanning signal line EL2 is electrically connected to the fourth gate conductive pattern G4, thereby ensuring that the position is straight, which is beneficial to improving the structural stability of the first scanning signal line EL2 and optimizing the layout of the scanning drive circuit 2.

[0256] In addition, if Figure 7 and Figure 8 As shown, a fourth sub-gate G41 in the fourth gate conductive pattern G4 closest to the first scanning signal line EL2 can extend to the position of the first connecting portion CN1 in a corner shape and form an electrical connection with the first connecting portion CN1. This can reduce the overlapping area between the conductive layers and avoid crosstalk.

[0257] It should be noted that, when the shift register 2a includes a plurality of first scanning signal lines EL2, the fourth gate conductive pattern G4 may be electrically connected to only one of the first scanning signal lines EL2.

[0258] In some examples, such as Fig.12 As shown, the first electrode of the fourth transistor T4 includes: a fourth input electrode pattern S4 in a comb shape, which is arranged on the side of the fourth gate conductive pattern G4 away from the substrate 1. The fourth input electrode pattern S4 includes a plurality of fourth sub-input electrodes S41 arranged at intervals along the first direction Y. The orthographic projection of each fourth sub-input electrode S41 on the substrate 1 partially overlaps with the orthographic projection of the corresponding fourth input portion 412 on the substrate 1.

[0259] For example, Fig.12As shown, the fourth sub-input electrode S41 may extend along the second direction X. One fourth sub-input electrode S41 corresponds to one fourth input portion 412 , and both ends of the fourth sub-input electrode S41 extend out of the range of the corresponding fourth input portion 412 .

[0260] Furthermore, if Fig.12 As shown, a plurality of first via holes K1 penetrating the first insulating layer, the second insulating layer and the third insulating layer are provided between each fourth sub-input electrode S41 and the corresponding fourth input portion 412, and each fourth sub-input electrode S41 can be electrically connected to the corresponding fourth input portion 412 through the plurality of first via holes K1. At this time, the fourth input portion 412 can also serve as a part of the first electrode of the fourth transistor T4.

[0261] For example, Fig.12 As shown, the fourth input electrode pattern S4 further includes: a fourth input connection portion S42 extending along the first direction Y. The fourth input connection portion S42 is connected to one end of each fourth sub-input electrode S41 so as to synchronously transmit a corresponding signal to each fourth sub-input electrode S41 .

[0262] Optionally, in the fourth input electrode pattern S4, the fourth input connection portion S42 and each fourth sub-input electrode S41 are in an integrated structure, which is beneficial to improving the structural stability of the fourth input electrode pattern S4, and improving the structural stability of the scan driving circuit 2 and the display substrate 100.

[0263] For example, Fig.12 As shown, the first electrode of the fourth transistor T4 can be electrically connected to the third voltage signal line VGHL2 through the fourth input electrode pattern S4.

[0264] In some examples, such as Fig.12 As shown, the second electrode of the fourth transistor T4 includes: a fourth output electrode pattern D4 in a comb shape, which is arranged on the side of the fourth gate conductive pattern G4 away from the substrate 1. The fourth output electrode pattern D4 includes a plurality of fourth sub-output electrodes D41 arranged at intervals along the first direction Y. The orthographic projection of the fourth sub-output electrode D41 on the substrate 1 partially overlaps with the orthographic projection of the fourth output portion 413 on the substrate 1.

[0265] For example, Fig.12 As shown, the fourth sub-output electrode D41 may extend along the second direction X. One fourth sub-output electrode D41 corresponds to one fourth output portion 413 , and both ends of the fourth sub-output electrode D41 extend out of the range of the corresponding fourth output portion 413 .

[0266] Furthermore, if Fig.12As shown, a plurality of first via holes K1 penetrating the first insulating layer, the second insulating layer and the third insulating layer are provided between each fourth sub-output electrode D41 and the corresponding fourth output portion 413, and each fourth sub-output electrode D41 can be electrically connected to the corresponding fourth output portion 413 through the plurality of first via holes K1. At this time, the fourth output portion 413 can also serve as a part of the second electrode of the fourth transistor T4.

[0267] For example, Fig.12 As shown, the fourth output electrode pattern D4 further includes: a fourth output connection portion D42 extending along the first direction Y. The fourth output connection portion D42 is connected to one end of each fourth sub-output electrode D41 so as to synchronously transmit a corresponding signal to each fourth sub-output electrode D41 .

[0268] Optionally, in the fourth input electrode pattern S4, the fourth output connection portion D42 and each fourth sub-output electrode D41 are in an integrated structure, which is beneficial to improving the structural stability of the fourth output electrode pattern D4, and improving the structural stability of the scan driving circuit 2 and the display substrate 100.

[0269] For example, Fig.12 and Fig.13 As shown, the second electrode of the fourth transistor T4 may be electrically connected to the second scan signal line RL2 through the fourth output electrode pattern D4.

[0270] For example, a third via hole K3 penetrating the third insulating layer is disposed between the fourth output electrode pattern D4 and the second scan signal line RL2 , and the fourth output electrode pattern D4 may be electrically connected to the second scan signal line RL2 through the third via hole K3 .

[0271] For example, Fig.12 As shown, the fourth input electrode pattern S4 and the fourth output electrode pattern D4 are disposed in the same layer and are located in the source-drain conductive layer 6. When the shift register 2a further includes the first connecting portion CN1, the first connecting portion CN1 may also be located in the source-drain conductive layer 6.

[0272] In this way, the fourth input electrode pattern S4 , the fourth output electrode pattern D4 and the source-drain conductive layer 6 can be simultaneously formed in one patterning process, which is beneficial to simplifying the manufacturing process of the scan driving circuit 2 and the display substrate 100 .

[0273] For example, Fig.12 As shown, the fourth input electrode pattern S4 and the fourth output electrode pattern D4 are arranged in an interdigitated structure. That is, the fourth sub-input electrodes S41 and the fourth sub-output electrodes D41 are alternately arranged in sequence, and the fourth sub-input electrodes S41 and the fourth sub-output electrodes D41 are arranged between the fourth input connection portion S42 and the fourth output connection portion D42.

[0274] This is beneficial for rationally utilizing the space of the display substrate 100 and reducing the space occupied by the scan driving circuit 2 in the display substrate 100 .

[0275] Optional, such as Fig.12 As shown, the third output electrode pattern D3 included in the third transistor T3 and the fourth output electrode pattern D4 are in an integrated structure. In this way, the third output electrode pattern D3 and the fourth output electrode pattern D4 can be simultaneously prepared in one patterning process, which is beneficial to improving the structural stability of the third output electrode pattern D3 and the fourth output electrode pattern D4, and improving the structural stability of the scan driving circuit 2 and the display substrate 100.

[0276] For example, Fig.12 As shown, the third output electrode pattern D3 and the fourth output electrode pattern D4 are electrically connected to each other through the third output connection portion D32 and the fourth output connection portion D42 to realize an integrated structure. The openings of the third output electrode pattern D3 and the fourth output electrode pattern D4 are both oriented toward the second voltage signal line VGLL, and the connection line between the third output connection portion D32 and the fourth output connection portion D42 is in a straight line.

[0277] This can not only optimize the layout of the scan drive circuit 2, but also reduce the impact of process fluctuations in the process of preparing the third output electrode pattern D3 and the fourth output electrode pattern D4, so that the patterns of the prepared third output electrode pattern D3 and the fourth output electrode pattern D4 are closer to the designed patterns, thereby improving the structural stability of the scan drive circuit 2 and the display substrate 100.

[0278] In this case, the electrical connection between the second electrode of the third transistor T3, the second electrode of the fourth transistor T4 and the second scanning signal line RL2 can be realized through the third output connection portion D32 and / or the fourth output connection portion D42. For example, the electrical connection with the second scanning signal line RL2 can be formed through the portion of the third output connection portion D32 and the fourth output connection portion D42 located between the third sub-output electrode D31 and the fourth sub-output electrode D41; and / or the electrical connection with the second scanning signal line RL2 can be formed through the end of the third output connection portion D32 away from the fourth output connection portion D42.

[0279] In addition, since the fourth input electrode pattern S4 and the fourth output electrode pattern D4 are arranged in an interdigitated structure, the fourth input electrode pattern S4 can be electrically connected to the third voltage signal line VGHL2 through the fourth sub-input electrode S41, and the fourth sub-input electrode S41 electrically connected to the third voltage signal line VGHL2 is the fourth sub-input electrode S41 farthest from the third transistor T3. In this way, overlap with the fourth output electrode pattern D4 can be avoided, thereby avoiding crosstalk.

[0280] Exemplarily, the fourth input electrode pattern S41 and the third voltage signal line VGHL2 are in an integrated structure, which is beneficial to improving the structural stability of the fourth input electrode pattern S41 and the third voltage signal line VGHL2, and improving the structural stability of the scan driving circuit 2 and the display substrate 100.

[0281] In some embodiments, Figure 7 to Figure 9 As shown, the first transistor T1 includes a first semiconductor portion 11, and the second transistor T2 includes a second semiconductor portion 21. The first semiconductor portion 11 and the second semiconductor portion 21 are sequentially arranged along a first direction Y and are in an integrated structure.

[0282] That is, the first transistor T1 and the second transistor T2 are sequentially arranged in a spaced relationship along the first direction Y. Figure 7 and Figure 8 In the embodiment, the first transistor T1 and the second transistor T2 are placed one above the other in space.

[0283] In this way, the first semiconductor portion 11 and the second semiconductor portion 21 can be simultaneously formed in one patterning process, thereby simplifying the manufacturing process of the scanning driving circuit 2 and the display substrate 100, and the first transistor T1 and the second transistor T2 in the second direction X (such as Figure 7 and Figure 8 The area occupied by the second voltage signal line VGLL and the first voltage signal line VGHL1 can be reduced, and the area occupied by the shift register 2a and the scan drive circuit 2 in the second direction X can be reduced, which is beneficial to reducing the size of the frame area B and making it easier for the display substrate 100 to achieve a narrow frame design.

[0284] Illustratively, the film layer where the first semiconductor portion 11 and the second semiconductor portion 21 are located may be a semiconductor material layer 3 .

[0285] The layout of the first transistor T1 and the second transistor T2 is schematically described below.

[0286] In some examples, such as Fig. 9As shown, the first semiconductor portion 11 includes: a plurality of first channel portions 111 arranged at intervals along a first direction Y, and a first input portion 112 and a first output portion 113 disposed on both sides of each first channel portion 111 .

[0287] For example, the first channel portion 111 , the first input portion 112 , and the first output portion 113 may all extend along the second direction X.

[0288] For example, Fig. 9 As shown, the first input portion 112 and the first output portion 113 may be respectively disposed on opposite sides of each first channel portion 111. For example, only the first input portion 112 or the first output portion 113 may be disposed between any two adjacent first channel portions 111. That is, the first input portion 112 and the first output portion 113 are alternately disposed in sequence.

[0289] In some examples, such as Fig.10 As shown, the control electrode of the first transistor T1 includes: a first gate conductive pattern G1 in a comb shape and arranged on a side of the first semiconductor portion 11 away from the substrate 1. The first gate conductive pattern G1 includes a plurality of first sub-gates G11 arranged at intervals along the first direction Y. The orthographic projection of the first sub-gate G11 on the substrate 1 partially overlaps with the orthographic projection of the first channel portion 111 on the substrate 1.

[0290] For example, Fig.10 As shown, the first sub-gate G11 may extend along the second direction X. One first sub-gate G11 corresponds to one first channel portion 111 , and two ends of the first sub-gate G11 extend out of the range of the corresponding first channel portion 111 .

[0291] For example, Fig.10 As shown, the first gate conductive pattern G1 further includes: a first gate connection portion G12 extending along the first direction Y. The first gate connection portion G12 is connected to one end of each first sub-gate G11 so as to synchronously transmit a corresponding signal to each first sub-gate G11.

[0292] For example, the first gate connection portion G12 and each first sub-gate G11 are in an integrated structure. That is, the first gate connection portion G12 and each first sub-gate G11 are made of the same film layer and formed in the same patterning process, and there is no disconnection between the two. This is conducive to improving the structural stability of the first gate conductive pattern G1, and improving the structural stability of the scan drive circuit 2 and the display substrate 100.

[0293] For example, Fig.10 As shown, the film layer where the first gate conductive pattern G1 is located may be the second gate conductive layer 4 .

[0294] In some examples, such as Fig.12As shown, the first electrode of the first transistor T1 includes: a first input electrode pattern S1 in a comb shape and arranged on a side of the first gate conductive pattern G1 away from the substrate 1. The first input electrode pattern S1 includes a plurality of first sub-input electrodes S11 arranged at intervals along the first direction Y. The orthographic projection of the first sub-input electrode S11 on the substrate 1 partially overlaps with the orthographic projection of the first input portion 112 on the substrate 1.

[0295] For example, Fig.12 As shown, the first sub-input electrode S11 may extend along the second direction X. One first sub-input electrode S11 corresponds to one first input portion 112 , and both ends of the first sub-input electrode S11 extend out of the range of the corresponding first input portion 112 .

[0296] Furthermore, if Fig.12 As shown, a plurality of via holes K penetrating the first insulating layer, the second insulating layer and the third insulating layer are provided between each first sub-input electrode S11 and the corresponding first input portion 112, and each first sub-input electrode S11 can be electrically connected to the corresponding first input portion 112 through the plurality of via holes K. At this time, the first input portion 112 can also serve as a part of the first electrode of the first transistor T1.

[0297] For example, Fig.12 As shown, the first input electrode pattern S1 further includes: a first input connection portion S12 extending along the first direction Y. The first input connection portion S12 is connected to one end of each first sub-input electrode S11 so as to synchronously transmit a corresponding signal to each first sub-input electrode S11.

[0298] For example, Fig.12 As shown, the first electrode of the first transistor T1 can be electrically connected to the first voltage signal line VGHL1 through the first input electrode pattern S1.

[0299] Optional, such as Fig.12 As shown, the shift register 2a further includes: a second connection portion CN2 disposed between the first input connection portion S12 in the first input electrode pattern S1 and the first voltage signal line VGHL1. The second connection portion CN2 extends in the second direction X, one end of which is electrically connected to the first input connection portion S12, and the other end of which is electrically connected to the first voltage signal line VGHL1. That is, the first input connection portion S12 is connected to the first voltage signal line VGHL1 through the second connection portion CN2.

[0300] By setting a second connecting portion CN2 extending along the second direction X, a certain gap can be formed between the first voltage signal line VGHL1 and the first transistor T1, so that multiple transistors or capacitors in the shift register 2a can be set in the gap, thereby optimizing the layout of the scan drive circuit 2 and reducing the size occupied by the scan drive circuit 2 in the border area B.

[0301] For example, Fig.12 As shown, in the first input electrode pattern S1, the first input connection portion S12 and each first sub-input electrode S11 are in an integrated structure. Further, the first input electrode pattern S1, the second connection portion CN2 and the first voltage signal line VGHL1 can be in an integrated structure. This is conducive to improving the structural stability of the first input electrode pattern S1 and the first voltage signal line VGHL1, and improving the structural stability of the scan drive circuit 2 and the display substrate 100.

[0302] It should be noted that if Figure 7 and Figure 8 As shown, the fourth capacitor C4 included in the shift register 2a can be arranged between the first transistor T1 and the first voltage signal line VGHL1, and is located on the side of the seventeenth transistor T17 away from the sixteenth transistor T16. The layout of the seventeenth transistor T17 and the sixteenth transistor T16 can be found below and will not be described here.

[0303] For example, Fig.10 As shown, the first plate C41 of the fourth capacitor C4 can be electrically connected to the first gate conductive pattern G1 included in the control electrode of the first transistor T1. For example, the first plate C41 of the fourth capacitor C4 can be electrically connected to the first gate connecting portion G12 in the first gate conductive pattern G1.

[0304] Here, the film layer where the first electrode plate C41 of the fourth capacitor C4 is located can be the second gate conductive layer 4. Further, the first electrode plate C41 of the fourth capacitor C4 can be an integral structure with the first gate connecting portion G12. This is conducive to improving the structural stability of the first electrode plate C41 of the fourth capacitor C4 and the first gate conductive pattern G1.

[0305] For example, Figure 8 and Fig.11 As shown, the second electrode plate C42 of the fourth capacitor C4 can be electrically connected to the first voltage signal line VGHL1. Fig.11As shown, the film layer where the second electrode plate C42 of the fourth capacitor C4 is located can be the first gate conductive layer 5. At this time, the fourth capacitor C4 can be located, for example, between the second connection portion CN2 and the substrate 1. The second electrode plate C42 of the fourth capacitor C4 can be electrically connected to the second connection portion CN2 through a via hole, and then electrically connected to the first voltage signal line VGHL1 through the second connection portion CN2.

[0306] In some examples, such as Fig.12 As shown, the second electrode of the first transistor T1 includes: a first output electrode pattern D1 in a comb shape and arranged on a side of the first gate conductive pattern G1 away from the substrate 1. The first output electrode pattern D1 includes a plurality of first sub-output electrodes D11 arranged at intervals along the first direction Y. The orthographic projection of the first sub-output electrode D11 on the substrate 1 partially overlaps with the orthographic projection of the first output portion 113 on the substrate 1.

[0307] For example, Fig.12 As shown, the first sub-output electrode D11 may extend along the second direction X. One first sub-output electrode D11 corresponds to one first output portion 113 , and both ends of the first sub-output electrode D11 extend out of the range of the corresponding first output portion 113 .

[0308] Furthermore, a plurality of first via holes K1 penetrating the first insulating layer, the second insulating layer and the third insulating layer are provided between each first sub-output electrode D11 and the corresponding first output portion 113, and each first sub-output electrode D11 can be electrically connected to the corresponding first output portion 113 through the plurality of first via holes K1. At this time, the first output portion 113 can also serve as a part of the second electrode of the first transistor T1.

[0309] For example, Fig.12 As shown, the first output electrode pattern D1 further includes: a first output connection portion D12 extending along the first direction Y. The first output connection portion D12 is connected to one end of each first sub-output electrode D11 so as to synchronously transmit a corresponding signal to each first sub-output electrode D11.

[0310] Optional, such as Fig.12 As shown, in the first output electrode pattern D1, the first output connection portion D12 and each first sub-output electrode D11 are in an integrated structure, which is beneficial to improving the structural stability of the first output electrode pattern D1, and improving the structural stability of the scan driving circuit 2 and the display substrate 100.

[0311] For example, Fig.12As shown, the first output electrode pattern D1 is also electrically connected to the first scanning signal line EL2. For example, the film layer where the first output electrode pattern D1 is located is the source-drain conductive layer 6. The first output electrode pattern D1 can be electrically connected to the first scanning signal line EL2 through a via hole, for example.

[0312] It should be noted that if Fig.12 As shown, in the scan driving circuit 2, for example, except for the last stage shift register 2a, the remaining stages shift registers 2a may include: a third connection portion CN3 electrically connected to the first output electrode pattern D1. One end of the third connection portion CN3 is also electrically connected to the input signal terminal STV of the next stage shift register 2a.

[0313] For example, Fig.12 As shown, one end of the third connection portion CN3 can be electrically connected to the first sub-output electrode D11 closest to the next-stage shift register 2a among the multiple first sub-output electrodes D11 included in the first output electrode pattern D1, and the other end of the third connection portion CN3 can be electrically connected to the first electrode of the eighth transistor T8 in the next-stage shift register 2a.

[0314] In some examples, such as Fig. 9 As shown, the second semiconductor portion 21 includes: a plurality of second channel portions 211 arranged at intervals along the first direction Y, and a second input portion 212 and a second output portion 213 disposed on both sides of each second channel portion 211 .

[0315] For example, the second channel portion 211 , the second input portion 212 , and the second output portion 213 may all extend along the second direction X.

[0316] For example, Fig. 9 As shown, the second input part 212 and the second output part 213 may be respectively disposed on opposite sides of each second channel part 211. For example, only the second input part 212 or the second output part 213 may be disposed between any two adjacent second channel parts 211. That is, the second input part 212 and the second output part 213 are alternately disposed in sequence.

[0317] In some examples, such as Fig.10 As shown, the control electrode of the second transistor T2 includes: a second gate conductive pattern G2 in a comb shape and arranged on a side of the second semiconductor portion 21 away from the substrate 1. The second gate conductive pattern G2 includes a plurality of second sub-gates G21 arranged at intervals along the first direction Y. The orthographic projection of the second sub-gate G21 on the substrate 1 partially overlaps with the orthographic projection of the second channel portion 211 on the substrate 1.

[0318] For example, Fig.10As shown, the second sub-gate G21 may extend along the second direction X. One second sub-gate G21 corresponds to one second channel portion 211 , and both ends of the second sub-gate G21 extend out of the range where the corresponding second channel portion 211 is located.

[0319] For example, Fig.10 As shown, the second gate conductive pattern G2 further includes: a second gate connection portion G22 extending along the first direction Y. The second gate connection portion G22 is connected to one end of each second sub-gate G21 so as to synchronously transmit a corresponding signal to each second sub-gate G21.

[0320] For example, the second gate connection portion G22 and each second sub-gate G21 are in an integrated structure. That is, the second gate connection portion G22 and each second sub-gate G21 are made of the same film layer and formed in the same patterning process, and there is no disconnection between the two. This is conducive to improving the structural stability of the second gate conductive pattern G2, and improving the structural stability of the scan drive circuit 2 and the display substrate 100.

[0321] For example, Fig.10 As shown, the film layer where the second gate conductive pattern G2 is located may be the second gate conductive layer 4 .

[0322] In some examples, such as Fig.12 As shown, the first electrode of the second transistor T2 includes: a comb-shaped second input electrode pattern S2 arranged on the side of the second gate conductive pattern G2 away from the substrate 1. The second input electrode pattern S2 includes a plurality of second sub-input electrodes S21 arranged at intervals along the first direction Y, and the orthographic projection of the second sub-input electrode S21 on the substrate 1 partially overlaps with the orthographic projection of the second input portion 212 on the substrate 1.

[0323] For example, Fig.12 As shown, the second sub-input electrode S21 may extend along the second direction X. One second sub-input electrode S21 corresponds to one second input portion 212 , and both ends of the second sub-input electrode S21 extend out of the range of the corresponding second input portion 212 .

[0324] Furthermore, if Fig.12 As shown, a plurality of via holes K penetrating the first insulating layer, the second insulating layer and the third insulating layer are provided between each second sub-input electrode S21 and the corresponding second input portion 212, and each second sub-input electrode S21 can be electrically connected to the corresponding second input portion 212 through the plurality of via holes K. At this time, the second input portion 212 can also serve as a part of the first electrode of the second transistor T2.

[0325] For example, Fig.12As shown, the second input electrode pattern S2 further includes: a second input connection portion S22 extending along the first direction Y. The second input connection portion S22 is connected to one end of each second sub-input electrode S21 so as to synchronously transmit a corresponding signal to each second sub-input electrode S21 .

[0326] Optionally, in the second input electrode pattern S2, the second input connection portion S22 and each second sub-input electrode S21 are in an integrated structure, which is beneficial to improving the structural stability of the second input electrode pattern S2, and improving the structural stability of the scan driving circuit 2 and the display substrate 100.

[0327] Exemplarily, the first electrode of the second transistor T2 may be electrically connected to the second voltage signal line VGLL via the second input electrode pattern S2 .

[0328] It should be noted that if Figure 7 and Figure 8 As shown, the second capacitor C2 included in the shift register 2a can be arranged between the second transistor T2 and the first voltage signal line VGHL1, and between the fifteenth transistor T15 and the sixteenth transistor T16. The layout of the fifteenth transistor T15 and the sixteenth transistor T16 can be found below and will not be described here.

[0329] For example, Fig.10 As shown, the second plate C22 of the second capacitor C2 can be electrically connected to the second gate conductive pattern G2 included in the control electrode of the second transistor T2. For example, the second plate C22 of the second capacitor C2 can be electrically connected to the second gate connection portion G22 in the second gate conductive pattern G2.

[0330] Here, the film layer where the second electrode plate C22 of the second capacitor C2 is located can be the second gate conductive layer 4. Further, the second electrode plate C22 of the second capacitor C2 can be an integral structure with the second gate connecting portion G22. This is conducive to improving the structural stability of the second electrode plate C22 of the second capacitor C2 and the second gate conductive pattern G2.

[0331] For example, Figure 7 , Figure 8 and Fig.11 As shown, the first plate C21 of the second capacitor C2 can be electrically connected to the second clock signal line CBL. Fig.11 As shown, the film layer where the first electrode plate C21 of the second capacitor C2 is located may be the first gate conductive layer 5. At this time, the first electrode plate C21 of the second capacitor C2 may be electrically connected to the second clock signal line CBL through a via.

[0332] In some examples, such as Fig.12As shown, the second electrode of the second transistor T2 includes: a second output electrode pattern D2 in a comb shape and arranged on a side of the second gate conductive pattern G2 away from the substrate 1. The second output electrode pattern D2 includes a plurality of second sub-output electrodes D21 arranged at intervals along the first direction Y. The orthographic projection of the second sub-output electrode D21 on the substrate 1 partially overlaps with the orthographic projection of the second output portion 213 on the substrate 1.

[0333] For example, Fig.12 As shown, the second sub-output electrode D21 may extend along the second direction X. One second sub-output electrode D21 corresponds to one second output portion 213 , and both ends of the second sub-output electrode D21 extend out of the range of the corresponding second output portion 213 .

[0334] Furthermore, a plurality of first via holes K1 penetrating the first insulating layer, the second insulating layer and the third insulating layer are provided between each second sub-output electrode D21 and the corresponding second output portion 213, and each second sub-output electrode D21 can be electrically connected to the corresponding second output portion 213 through the plurality of first via holes K1. At this time, the second output portion 213 can also serve as a part of the second electrode of the second transistor T2.

[0335] For example, Fig.12 As shown, the second output electrode pattern D2 further includes: a second output connection portion D22 extending along the first direction Y. The second output connection portion D22 is connected to one end of each second sub-output electrode D21 so as to synchronously transmit a corresponding signal to each second sub-output electrode D21.

[0336] Optionally, in the second input electrode pattern S2, the second output connection portion D22 and each second sub-output electrode D21 are in an integrated structure, which is beneficial to improving the structural stability of the second output electrode pattern D2, and improving the structural stability of the scan driving circuit 2 and the display substrate 100.

[0337] Exemplarily, the second electrode of the second transistor T2 can be electrically connected to the first scan signal line EL2 through the second output electrode pattern S2. For example, the film layer where the second output electrode pattern D2 is located is the source-drain conductive layer 6. The second output electrode pattern D2 can be electrically connected to the first scan signal line EL2 through a via, for example.

[0338] Optional, such as Fig.12As shown, the first input electrode pattern S1 and the first output electrode pattern D1 are arranged in an interdigitated structure, and the second input electrode pattern S2 and the second output electrode pattern D2 are arranged in an interdigitated structure. Among them, the openings of the first input electrode pattern S1 and the second input electrode pattern S2 are, for example, both facing the second voltage signal line VGLL, and the openings of the first output electrode pattern D1 and the second output electrode pattern D2 are, for example, both away from the second voltage signal line VGLL. Here, regarding "arranged in an interdigitated structure", please refer to the description in some of the above examples, which will not be repeated here.

[0339] This is conducive to optimizing the layout between the first scanning signal line EL2, the first transistor T1 and the second transistor T2, and is conducive to reducing the overlapping area between the first scanning signal line EL2 and the first transistor T1 and between the first scanning signal line EL2 and the second transistor T2, thereby avoiding crosstalk.

[0340] The layout of other transistors and capacitors included in the shift register 2a is schematically described below.

[0341] In some embodiments, Figure 7 and Figure 8 As shown, the fifth transistor T5 included in the shift register 2a is arranged between the third transistor T3 and the fourth transistor T4.

[0342] By setting the fifth transistor T5 in the gap between the third transistor T3 and the fourth transistor T4, it is possible to avoid increasing the distance between the second voltage signal line VGLL and the third voltage signal line VGHL2, which is beneficial for making the second voltage signal line VGLL and the third voltage signal line VGHL2 have a smaller distance, thereby facilitating the display substrate 100 to achieve a narrow frame design.

[0343] It should be noted that the fifth transistor T5 may be located at any position between the third transistor T3 and the fourth transistor T4, which is not limited in the present disclosure.

[0344] In some examples, such as Figure 7 and Figure 8 As shown, the fifth transistor T5 can be disposed between the second voltage signal line VGLL and the third voltage signal line VGHL2. That is, the fifth transistor T5 can be located in a region defined by the second voltage signal line VGLL, the third voltage signal line VGHL2, the third transistor T3 and the fourth transistor T4.

[0345] For example, Figure 7 and Figure 8As shown in FIG. 1 , when both the first scanning signal line EL2 and the second scanning signal line RL2 are located between the third semiconductor portion 31 and the fourth semiconductor portion 41, the fifth transistor T5 can be disposed between the third transistor T3 and the first scanning signal line EL2. That is, the fifth transistor T5 can be located in a region defined by the second voltage signal line VGLL, the third voltage signal line VGHL2, the third transistor T3 and the first scanning signal line EL2.

[0346] In this way, not only can the increase in the distance between the second voltage signal line VGLL and the third voltage signal line VGHL2 be avoided, but also the overlap between the third transistor T3 and the first scanning signal line EL2 can be avoided, thereby avoiding the formation of crosstalk.

[0347] In some examples, such as Figure 7 , Figure 8 and Fig. 9 As shown, the fifth transistor T5 may include a fifth semiconductor portion 51 . The fifth semiconductor portion 51 includes a fifth channel portion 511 and a fifth input portion 512 and a fifth output portion 513 disposed on both sides of the fifth channel portion 511 .

[0348] For example, Fig. 9 As shown, the film layer where the fifth semiconductor portion 51 is located may be the semiconductor material layer 3 .

[0349] In some examples, such as Fig.10 As shown, the control electrode of the fifth transistor T5 includes a fifth gate conductive pattern G5 disposed on the side of the fifth semiconductor portion 51 away from the substrate 1. The orthographic projection of the fifth gate conductive pattern G5 on the substrate 1 partially overlaps with the orthographic projection of the fifth channel portion 511 on the substrate 1.

[0350] Exemplarily, the extension direction of the fifth gate conductive pattern G5 is perpendicular to the length direction of the fifth channel portion 511. Both ends of the fifth gate conductive pattern G5 extend out of the range of the fifth channel portion 511. Here, the length direction of the fifth channel portion 511 refers to the direction from one of the fifth input portion 512 and the fifth output portion 513 to the other. The length directions of the channel portions of the remaining transistors can refer to the description here, and will not be repeated herein.

[0351] For example, Fig.10 As shown, the film layer where the fifth gate conductive pattern G5 is located may be the second gate conductive layer 4 .

[0352] For example, Fig.10As shown, the fifth gate conductive pattern G5 is electrically connected to the control electrode of the first transistor T1. When the control electrode of the first transistor T1 includes the first gate conductive pattern G1, the fifth gate conductive pattern G5 of the fifth transistor T5 can be electrically connected to the first gate conductive pattern G1.

[0353] Optional, such as Fig.10 As shown, the first gate conductive pattern G1 includes a plurality of first sub-gates G11. The fifth gate conductive pattern G5 can be electrically connected to a first sub-gate G11. This is beneficial to optimize the layout of the scan drive circuit 2 and reduce the overlap area between the conductive layers.

[0354] Since the film layer where the fifth gate conductive pattern G5 and the first gate conductive pattern G1 are located is the second gate conductive layer 4, the fifth gate conductive pattern G5 can be integrated with the first sub-gate G11 electrically connected thereto. Fig.10 In the structure shown, it can be considered that the first sub-gate G11 in the first gate conductive pattern G1 extends toward the fifth transistor T5 in a zigzag shape and is reused as the fifth gate conductive pattern G5.

[0355] This is beneficial to improving the structural stability of the fifth gate conductive pattern G5 and the first gate conductive pattern G1 , and improving the structural stability of the scan driving circuit 2 and the display substrate 100 .

[0356] In some examples, such as Fig.12 As shown, the first electrode of the fifth transistor T5 includes: a fifth input electrode pattern S5 arranged on the side of the fifth gate conductive pattern G5 away from the substrate 1. The orthographic projection of the fifth input electrode pattern S5 on the substrate 1 partially overlaps with the orthographic projection of the fifth input portion 512 on the substrate 1.

[0357] Exemplarily, a portion of the fifth input electrode pattern S5 covers the fifth input portion 512. A first via hole K1 penetrating the first insulating layer, the second insulating layer, and the third insulating layer is provided between the fifth input electrode pattern S5 and the fifth input portion 512, and the fifth input electrode pattern S5 can be electrically connected to the fifth input portion 512 through the first via hole K1. At this time, the fifth input portion 512 can also serve as a portion of the first electrode of the fifth transistor T5.

[0358] For example, Fig.12 As shown, the first electrode of the fifth transistor T5 can be electrically connected to the second voltage signal line VGLL through the fifth input electrode pattern S5.

[0359] Optional, such as Fig. 9 As shown, the length direction of the fifth channel portion 511 of the fifth transistor T5 is arranged along the second direction X, and the fifth input portion 512 is located at a side of the fifth output portion 513 close to the second voltage signal line VGLL.

[0360] By setting the fifth channel portion 511 in the above-mentioned manner, not only can the occupied size of the fifth channel portion 511 in the first direction Y be reduced, the distance between the third transistor and the first scanning signal line EL2 can be reduced, and the size of the scanning driving circuit 2 in the first direction Y can be reduced, but also the distance between the fifth input portion 512 and the second voltage signal line VGLL can be reduced, and the increase in the distance between the second voltage signal line VGLL and the third voltage signal line VGHL2 can be further avoided, so as to facilitate the display substrate 100 to achieve a narrow frame design.

[0361] For example, Fig.12 As shown, the fifth input electrode pattern S5 is located in the source-drain conductive layer 6 and is an integral structure with the second voltage signal line VGLL. At this time, for example, a part of the second voltage signal line VGLL can be used as the fifth input electrode pattern S5, and the position of the second voltage signal line VGLL corresponding to the fifth transistor T5 is still in a straight line.

[0362] This is not only conducive to further reducing the distance between the fifth input part 512 and the second voltage signal line VGLL, and further avoiding increasing the distance between the second voltage signal line VGLL and the third voltage signal line VGHL2, so as to facilitate the display substrate 100 to achieve a narrow frame design, but also conducive to improving the structural stability of the second voltage signal line VGLL, so that the layout structure of the scan drive circuit 2 is optimized, and the influence of process fluctuations in the process of preparing the scan drive circuit 2 on the scan drive circuit 2 is weakened.

[0363] In some examples, such as Fig.12 As shown, the second electrode of the fifth transistor T5 includes: a fifth output electrode pattern D5 arranged on the side of the fifth gate conductive pattern G5 away from the substrate 1. The orthographic projection of the fifth output electrode pattern D5 on the substrate 1 partially overlaps with the orthographic projection of the fifth output portion 513 on the substrate 1.

[0364] Exemplarily, a portion of the fifth output electrode pattern D5 covers the fifth output portion 513. A first via hole K1 penetrating the first insulating layer, the second insulating layer, and the third insulating layer is provided between the fifth output electrode pattern D5 and the fifth output portion 513, and the fifth output electrode pattern D5 can be electrically connected to the fifth output portion 513 through the first via hole K1. At this time, the fifth output portion 513 can also serve as a portion of the second electrode of the fifth transistor T5.

[0365] For example, Fig.12 As shown, the fifth output electrode pattern D5 and the fifth input electrode pattern S5 are arranged opposite to each other, and the film layer where the fifth output electrode pattern D5 is located may also be the source-drain conductive layer 6 .

[0366] Exemplarily, the second electrode of the fifth transistor T5 may be electrically connected to the control electrode of the third transistor T3 through the fifth output electrode pattern D5.

[0367] For example, when the control electrode of the third transistor T3 includes the third gate conductive pattern G3 , the fifth output electrode pattern D5 may be electrically connected to a third sub-gate G31 in the third gate conductive pattern G3 .

[0368] For example, Fig.10 As shown, the third sub-gate G31 in the third gate conductive pattern G3 close to the fifth transistor T3 extends toward the fifth transistor T5 in a corner shape. At this time, the third sub-gate G31 can be U-shaped, and one end of the third sub-gate G31 extending toward the fifth transistor T5 partially overlaps with the fifth output electrode pattern D5. The fifth output electrode pattern D5 can be electrically connected to the third sub-gate G31 through a corresponding via.

[0369] By selecting the third sub-gate G31 close to the fifth transistor T3 to be electrically connected to the fifth output electrode pattern D5 , overlapping between the conductive layers can be avoided, thereby avoiding crosstalk and optimizing the structure of the scan driving circuit 2 .

[0370] In some embodiments, Figure 7 and Figure 8 As shown, the sixth transistor T6 included in the shift register 2a is arranged between the third transistor T3 and the fourth transistor T4.

[0371] By setting the above-mentioned sixth transistor T6 in the gap between the third transistor T3 and the fourth transistor T4, it is possible to avoid increasing the distance between the second voltage signal line VGLL and the third voltage signal line VGHL2, which is beneficial for making the second voltage signal line VGLL and the third voltage signal line VGHL2 have a smaller distance, thereby facilitating the display substrate 100 to achieve a narrow frame design.

[0372] It should be noted that the sixth transistor T6 can be located at any position between the third transistor T3 and the fourth transistor T4, which is not limited in the present disclosure.

[0373] In some examples, such as Figure 7 and Figure 8 As shown, the sixth transistor T6 can be disposed between the second voltage signal line VGLL and the third voltage signal line VGHL2. That is, the sixth transistor T6 can be located in a region defined by the second voltage signal line VGLL, the third voltage signal line VGHL2, the third transistor T3 and the fourth transistor T4.

[0374] For example, Figure 7 and Figure 8As shown in FIG. 1 , when both the first scan signal line EL2 and the second scan signal line RL2 are located between the third semiconductor portion 31 and the fourth semiconductor portion 41, the sixth transistor T6 can be disposed between the fourth transistor T4 and the first scan signal line EL2. That is, the sixth transistor T6 can be located in a region defined by the second voltage signal line VGLL, the third voltage signal line VGHL2, the fourth transistor T4 and the first scan signal line EL2.

[0375] In this way, not only can the increase of the distance between the second voltage signal line VGLL and the third voltage signal line VGHL2 be avoided, but also the overlap between the fourth transistor T4 and the first scanning signal line EL2 can be avoided, thereby avoiding the formation of crosstalk.

[0376] In some examples, such as Figure 7 , Figure 8 and Fig. 9 As shown, the sixth transistor T6 may include a sixth semiconductor portion 61 . The sixth semiconductor portion 61 includes: a sixth channel portion 611 , and a sixth input portion 612 and a sixth output portion 613 disposed on both sides of the sixth channel portion 611 .

[0377] For example, Fig. 9 As shown, the film layer where the sixth semiconductor portion 61 is located may be the semiconductor material layer 3 .

[0378] In some examples, such as Fig.10 As shown, the control electrode of the sixth transistor T6 includes a sixth gate conductive pattern G6 disposed on the side of the sixth semiconductor portion 61 away from the substrate 1. The orthographic projection of the sixth gate conductive pattern G6 on the substrate 1 partially overlaps with the orthographic projection of the sixth channel portion 611 on the substrate 1.

[0379] Exemplarily, the extension direction of the sixth gate conductive pattern G6 is perpendicular to the length direction of the sixth channel portion 611. Both ends of the sixth gate conductive pattern G6 extend out of the range where the sixth channel portion 611 is located.

[0380] Illustratively, the film layer where the sixth gate conductive pattern G6 is located may be the second gate conductive layer 4 .

[0381] For example, Fig.10 As shown, the sixth gate conductive pattern G6 is electrically connected to the control electrode of the fourth transistor T4. When the control electrode of the fourth transistor T4 includes the fourth gate conductive pattern G4, the sixth gate conductive pattern G6 can be electrically connected to the fourth gate conductive pattern G4.

[0382] Optionally, the fourth gate conductive pattern G4 includes a plurality of fourth sub-gates G41. The sixth gate conductive pattern G6 may be electrically connected to a fourth sub-gate G41.

[0383] For example, Fig.10 As shown, the fourth sub-gate G41 near the sixth transistor T6 in the fourth gate conductive pattern G4 extends toward the sixth transistor T6 in a corner shape. At this time, the fourth sub-gate G41 can be U-shaped, and one end of the fourth sub-gate G41 extending toward the sixth transistor T6 is electrically connected to the sixth gate conductive pattern G6.

[0384] By selecting the fourth sub-gate G41 close to the sixth transistor T6 to be electrically connected to the sixth gate conductive pattern G6 , overlap between conductive layers can be avoided or reduced, thereby avoiding crosstalk and optimizing the structure of the scan driving circuit 2 .

[0385] Exemplarily, since the film layer where the sixth gate conductive pattern G6 and the fourth gate conductive pattern G4 are located is the second gate conductive layer 4, the sixth gate conductive pattern G6 and the fourth gate conductive pattern G4 can be an integrated structure. Fig.10 Based on the structure shown, it can be considered that the fourth sub-gate G41 is multiplexed as the sixth gate conductive pattern G6.

[0386] This is beneficial to improving the structural stability of the sixth gate conductive pattern G6 and the fourth gate conductive pattern G4 , and improving the structural stability of the scan driving circuit 2 and the display substrate 100 .

[0387] In some examples, such as Fig.12 As shown, the first electrode of the sixth transistor T6 includes: a sixth input electrode pattern S6 disposed on the side of the sixth gate conductive pattern G6 away from the substrate 1. The orthographic projection of the sixth input electrode pattern S6 on the substrate 1 partially overlaps with the orthographic projection of the sixth input portion 612 on the substrate 1.

[0388] Exemplarily, a portion of the sixth input electrode pattern S6 covers the sixth input portion 612. A first via hole K1 penetrating the first insulating layer, the second insulating layer, and the third insulating layer is provided between the sixth input electrode pattern S6 and the sixth input portion 612, and the sixth input electrode pattern S6 can be electrically connected to the sixth input portion 612 through the first via hole K1. At this time, the sixth input portion 612 can also serve as a portion of the first electrode of the sixth transistor T6.

[0389] For example, Fig.12 As shown, the first electrode of the sixth transistor T6 can be electrically connected to the third voltage signal line VGHL2 through the sixth input electrode pattern S6.

[0390] Optional, such as Fig.12As shown, since the fourth input electrode pattern S4 of the fourth transistor T4 and the third voltage signal line VGHL2 are integrated, the sixth input electrode pattern S6 of the sixth transistor T6 can be electrically connected to the fourth input electrode pattern S4, thereby achieving electrical connection between the sixth input electrode pattern S6 and the third voltage signal line VGHL2.

[0391] This helps to avoid overlap between conductive layers, thereby avoiding crosstalk.

[0392] For example, Fig. 9 As shown, in the sixth semiconductor portion 61 , the length direction of the sixth channel portion 611 is arranged along the first direction Y, and the sixth input portion 612 is located at a side of the sixth output portion 613 close to the fourth transistor T4 .

[0393] By setting the sixth channel portion 611 in the above-mentioned manner, not only can the distance between the sixth input portion 612 and the fourth input electrode pattern S4 be reduced, thereby avoiding increasing the size of the shift register 2a and the scan drive circuit 2 in the first direction Y, but also the number of bending times of the fourth sub-gate G41 electrically connected to the sixth transistor T6 in the fourth gate conductive pattern G4 can be reduced, thereby improving the structural stability of the sixth gate conductive pattern G6 and the fourth gate conductive pattern G4.

[0394] Optional, such as Fig. 9 As shown, the sixth semiconductor portion 61 can be, for example, an integral structure with the fourth semiconductor portion 41 of the fourth transistor T4. That is, the sixth semiconductor portion 61 and the fourth semiconductor portion 41 are formed by the same film layer and in the same patterning process, and there is no disconnection between the two. This is conducive to improving the structural stability of the sixth semiconductor portion 61 and the fourth semiconductor portion 41, and improving the structural stability of the scan drive circuit 2 and the display substrate 100.

[0395] It can be understood that, when the fourth semiconductor portion 41 includes a plurality of fourth channel portions 411 arranged at intervals along the second direction X, and a fourth input portion 412 and a fourth output portion 413 disposed on both sides of each fourth channel portion 411, the fourth input portion 412 close to the sixth semiconductor portion 61 can be reused as the sixth input portion 612. Based on this, the fourth sub-input electrode S41 close to the sixth semiconductor portion 61 in the fourth input electrode pattern S4 of the fourth transistor T4 can be reused as the sixth input electrode pattern S6.

[0396] That is, the fourth input portion 412 in the fourth semiconductor portion 41 close to the sixth semiconductor portion 61 may belong to the first electrode of the fourth transistor T4 or the first electrode of the sixth transistor T6. The fourth sub-input electrode S41 in the fourth input electrode pattern S4 close to the sixth semiconductor portion 61 may belong to the first electrode of the fourth transistor T4 or the first electrode of the sixth transistor T6.

[0397] This is beneficial to simplifying the structures of the fourth transistor T4 and the sixth transistor T6 , improving the integration of the two, and further reducing the size occupied by the shift register 2 a and the scan driving circuit 2 .

[0398] In some examples, such as Fig.12 As shown, the second electrode of the sixth transistor T6 includes: a sixth output electrode pattern D6 disposed on the side of the sixth gate conductive pattern G6 away from the substrate 1. The orthographic projection of the sixth output electrode pattern D6 on the substrate 2 partially overlaps with the orthographic projection of the sixth output portion 613 on the substrate 1.

[0399] Exemplarily, a portion of the sixth output electrode pattern D6 covers the sixth output portion 613. A first via hole K1 penetrating the first insulating layer, the second insulating layer, and the third insulating layer is provided between the sixth output electrode pattern D6 and the sixth output portion 613, and the sixth output electrode pattern D6 can be electrically connected to the sixth output portion 613 through the first via hole K1. At this time, the sixth output portion 613 can also serve as a portion of the second electrode of the sixth transistor T6.

[0400] For example, Fig.12 As shown, the sixth output electrode pattern D6 and the sixth input electrode pattern S6 are arranged opposite to each other, and the film layer where the sixth output electrode pattern D6 is located may also be the source-drain conductive layer 6 .

[0401] Exemplarily, the sixth transistor T6 may be electrically connected to the fifth output electrode pattern D5 of the fifth transistor T5 via the sixth output electrode pattern D6.

[0402] Optional, such as Fig.12 As shown, the sixth output electrode pattern D6 and the fifth output electrode pattern D5 both extend along the second direction X, and are respectively located on both sides of the first scanning signal line EL2. At this time, the shift register 2a may further include: a fourth connection portion CN4 disposed between the sixth output electrode pattern D6 and the fifth output electrode pattern D5 and extending along the first direction Y. One end of the fourth connection portion CN4 is electrically connected to the sixth output electrode pattern D6, and the other end is electrically connected to the fifth output electrode pattern D5.

[0403] The fourth connection portion CN4 is provided to reduce or even avoid the overlapping area between the sixth transistor T6 and the first scanning signal line EL2 and between the fifth transistor T5 and the first scanning signal line EL2, thereby reducing crosstalk.

[0404] For example, the sixth output electrode pattern D6, the fifth output electrode pattern D5 and the fourth connection portion CN4 are in an integrated structure, which is beneficial to improving the structural stability of the three.

[0405] In some embodiments, Figure 7 and Figure 8 As shown, the first capacitor C1 included in the shift register 2a can be arranged between the second transistor T2 and the fourth transistor T4. The first capacitor C1 can include: a first plate C11 and a second plate C12 which are arranged between the substrate 1 and the second voltage signal line VGLL and are stacked in sequence.

[0406] That is, the first capacitor C1 is located between the substrate 1 and the second voltage signal line VGLL.

[0407] By setting the first capacitor C1 in the space defined by the second transistor T2, the fourth transistor T4, the substrate 1 and the second voltage signal line VGLL, the space can be reasonably utilized to avoid increasing the size of the shift register 2a and the scan drive circuit 2 due to the setting of the first capacitor C1, so that the display substrate 100 can achieve a narrow frame design.

[0408] In addition, the second voltage signal transmitted by the second voltage signal line VGLL is a constant voltage signal. The first capacitor C1 is arranged between the substrate 1 and the second voltage signal line VGLL, which can avoid interference caused by signal fluctuation.

[0409] For example, Fig.10 As shown, the first plate C11 of the first capacitor C1 can be located in the second gate conductive layer 4 and arranged in the same layer as the fifth gate conductive pattern G5 of the fifth transistor T5. The second plate C12 of the first capacitor C1 can be located in the first gate conductive layer 5 and arranged in the same layer as the first scanning signal line EL2 and the second scanning signal line RL2.

[0410] In some examples, the first plate C11 of the first capacitor C1 and the fifth output electrode pattern D5 of the fifth transistor T5 are electrically connected.

[0411] For example, Fig.10As shown, the shift register 2a may further include: a fifth connection portion CN5 disposed between the first electrode plate C11 of the first capacitor C1 and the sixth output electrode pattern D6. One end of the fifth connection portion CN5 is electrically connected to the end of the first electrode plate C11 of the first capacitor C1 close to the fifth transistor T5, and the other end is electrically connected to the sixth output electrode pattern D6. At this time, the first electrode plate C11 of the first capacitor C1 can be electrically connected to the fifth output electrode pattern D5 of the fifth transistor T5 through the fifth connection portion CN5, the sixth output electrode pattern D6 and the fourth connection portion CN4 in sequence.

[0412] Since the first plate C11 of the first capacitor C1 and the fifth output electrode pattern D5 of the fifth transistor T5 are located in different layers, the first plate C11 of the first capacitor C1 and the fifth output electrode pattern D5 of the fifth transistor T5 need to be electrically connected through a via.

[0413] By setting the fifth connecting portion CN5 and realizing electrical connection through the sixth output electrode pattern D6 and the fifth output electrode pattern D5, it is possible to avoid setting the via between the second voltage signal line VGLL and the substrate 1 to ensure the flatness of the second voltage signal line VGLL, and it is also possible to avoid the first plate C11 of the first capacitor C1 and the first scanning signal line EL2 from overlapping, thereby avoiding interference caused by signal fluctuations.

[0414] For example, the first electrode plate C11 of the first capacitor C1 and the fifth connection portion CN5 are in an integrated structure, which is conducive to improving the structural stability of both.

[0415] In some examples, such as Fig.11 As shown, the second electrode plate C12 of the first capacitor C1 is electrically connected to the second electrode of the seventh transistor T7. The layout of the seventh transistor T7 can be referred to the following description, which will not be repeated here.

[0416] In some examples, such as Figure 7 and Figure 8 As shown, the orthographic projection of any one of the first plate C11 of the first capacitor C1 and the second plate C12 of the first capacitor C1 on the substrate 1 at least partially overlaps with the orthographic projection of the second voltage signal line VGLL on the substrate 1 .

[0417] Exemplarily, a portion of the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate 1 overlaps with a portion of the orthographic projection of the second voltage signal line VGLL on the substrate 1 , or is located within the orthographic projection range of the second voltage signal line VGLL on the substrate 1 .

[0418] Exemplarily, a portion of the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate 1 overlaps with a portion of the orthographic projection of the second voltage signal line VGLL on the substrate 1 , or is located within the orthographic projection range of the second voltage signal line VGLL on the substrate 1 .

[0419] In this way, the distance between the second transistor T2 and the fourth transistor T4 can be made smaller, thereby avoiding increasing the size of the shift register 2 a and the scan driving circuit 2 in the second direction X, thereby avoiding affecting the narrow frame design of the display substrate 100 .

[0420] In some examples, such as Figure 7 and Figure 8 As shown, the size of any one of the first plate C11 of the first capacitor C1 and the second plate C12 of the first capacitor C1 in the second direction X is substantially equal to the size of the second voltage signal line VGLL in the second direction X.

[0421] In this way, any one of the first plate C11 of the first capacitor C1 and the second plate C12 of the first capacitor C1 can be located between the substrate 1 and the second voltage signal line VGLL and overlap with the second voltage signal line VGLL, which is beneficial to further reduce the distance between the second transistor T2 and the fourth transistor T4, reduce the size of the shift register 2a and the scan drive circuit 2 in the second direction X, and avoid affecting the narrow frame design of the display substrate 100.

[0422] In some embodiments, Figure 7 and Figure 8 As shown, the scan driving circuit 2 further includes: a first clock signal line CKL, a second clock signal line CBL and a third clock signal line STVL which are arranged on a side of the first voltage signal line VGHL1 away from the second voltage signal line VGLL and extend along the first direction Y.

[0423] Here, the arrangement of the first clock signal line CKL, the second clock signal line CBL and the third clock signal line STVL can be selected and set according to actual needs, and the present disclosure does not limit this.

[0424] For example, Figure 7 and Figure 8 As shown, the first clock signal line CKL, the second clock signal line CBL and the third clock signal line STVL are arranged in sequence, and the first clock signal line CKL is closer to the first voltage signal line VGHL1 than the third clock signal line STVL.

[0425] For example, the first clock signal line CKL, the second clock signal line CBL, and the third clock signal line STVL may all be located in the source-drain conductive layer 6 .

[0426] In some embodiments, Figure 7 and Figure 8 As shown, the seventh transistor T7 included in the shift register 2a can be arranged between the first voltage signal line VGHL1 and the second voltage signal line VGLL. Wherein, when the first transistor T1 includes the first semiconductor portion 11, the second transistor T2 includes the second semiconductor portion 21, and the first semiconductor portion 11 and the second semiconductor portion 21 are arranged in sequence along the first direction Y, the seventh transistor T7 can be arranged on a side of the second semiconductor portion 21 away from the first semiconductor portion 11.

[0427] In some examples, such as Fig. 9 As shown, the seventh transistor T7 may include a seventh semiconductor portion 71. Since the seventh transistor T7 may be disposed on a side of the second semiconductor portion 21 away from the first semiconductor portion 11, the seventh semiconductor portion 71 may be disposed on a side of the second semiconductor portion 21 away from the first semiconductor portion 11.

[0428] The seventh semiconductor portion 71 includes a seventh channel portion 711 and a seventh input portion 712 and a seventh output portion 713 disposed on both sides of the seventh channel portion 711 .

[0429] For example, Fig. 9 As shown, the film layer where the seventh semiconductor portion 71 is located may be the semiconductor material layer 3 .

[0430] In some examples, such as Fig.10 As shown, the control electrode of the seventh transistor T7 includes a seventh gate conductive pattern G7 disposed on the side of the seventh semiconductor portion 71 away from the substrate 1. The orthographic projection of the seventh gate conductive pattern G7 on the substrate 2 partially overlaps with the orthographic projection of the seventh channel portion 711 on the substrate 1.

[0431] Exemplarily, the extending direction of the seventh gate conductive pattern G7 is perpendicular to the length direction of the seventh channel portion 711. Both ends of the seventh gate conductive pattern G7 extend out of the range where the seventh channel portion 711 is located.

[0432] For example, Fig.10 As shown, the film layer where the seventh gate conductive pattern G7 is located may be the second gate conductive layer 4 .

[0433] For example, Fig.10 As shown, the seventh gate conductive pattern G7 is electrically connected to the first electrode plate C11 of the first capacitor C1.

[0434] Optional, such as Fig.10As shown, the shift register 2a further includes: a sixth connection portion CN6 disposed between the seventh gate conductive pattern G7 and the first electrode plate C11 of the first capacitor C1 and extending along the second direction X. One end of the sixth connection portion CN6 is electrically connected to the seventh gate conductive pattern G7, and the other end is electrically connected to an end of the first electrode plate C11 of the first capacitor C1 close to the seventh transistor T7.

[0435] For example, the seventh gate conductive pattern G7, the first electrode plate C11 of the first capacitor C1 and the sixth connection portion CN6 are all arranged in the same layer and form an integrated structure. Fig.10 In the structure shown, it can be considered that the first electrode plate C11 of the first capacitor C1 is close to one end of the seventh transistor T7, extends toward the seventh transistor T7, and is reused as the seventh gate conductive pattern G7.

[0436] This is beneficial to improving the structural stability of the seventh gate conductive pattern G7 and the first electrode plate C11 of the first capacitor C1 , and improving the structural stability of the scan driving circuit 2 and the display substrate 100 .

[0437] In some examples, such as Fig.12 As shown, the first electrode of the seventh transistor T7 includes: a seventh input electrode pattern S7 arranged on the side of the seventh gate conductive pattern G7 away from the substrate 1. The orthographic projection of the seventh input electrode pattern S7 on the substrate 1 partially overlaps with the orthographic projection of the seventh input portion 712 on the substrate 1.

[0438] Exemplarily, a portion of the seventh input electrode pattern S7 covers the seventh input portion 712. A first via hole K1 penetrating the first insulating layer, the second insulating layer and the third insulating layer is provided between the seventh input electrode pattern S7 and the seventh input portion 712, and the seventh input electrode pattern S7 can be electrically connected to the seventh input portion 712 through the first via hole K1. At this time, the seventh input portion 712 can also serve as a portion of the first electrode of the seventh transistor T7.

[0439] For example, Figure 7 and Figure 8 As shown, the seventh input electrode pattern S7 is also electrically connected to the first clock signal line CKL.

[0440] Optional, such as Fig.10 As shown, the shift register 2a further includes: a seventh connection portion CN7 disposed between the seventh input electrode pattern S7 and the first clock signal line CKL and extending along the second direction X. One end of the seventh connection portion CN7 is electrically connected to the seventh input electrode pattern S7, and the other end is electrically connected to the first clock signal line CKL.

[0441] For example, the seventh connection portion CN7 may be located in the second gate conductive layer 4. At this time, the seventh connection portion CN7 may be electrically connected to the seventh input electrode pattern S7 and the first clock signal line CKL through different vias.

[0442] In some examples, such as Fig.12 As shown, the second electrode of the seventh transistor T7 includes: a seventh output electrode pattern D7 arranged on the side of the seventh gate conductive pattern G7 away from the substrate 1. The orthographic projection of the seventh output electrode pattern D7 on the substrate 1 partially overlaps with the orthographic projection of the seventh output portion 713 on the substrate 1.

[0443] Exemplarily, a portion of the seventh output electrode pattern D7 covers the seventh output portion 713. A first via hole K1 penetrating the first insulating layer, the second insulating layer and the third insulating layer is provided between the seventh output electrode pattern D7 and the seventh output portion 713, and the seventh output electrode pattern D7 can be electrically connected to the seventh output portion 713 through the first via hole K1. At this time, the seventh output portion 713 can also serve as a portion of the second electrode of the seventh transistor T7.

[0444] Exemplarily, the seventh output electrode pattern D7 and the seventh input electrode pattern S7 are arranged opposite to each other, and the film layer where the two are located may also be the source-drain conductive layer 6 .

[0445] For example, Fig.14 As shown, the seventh output electrode pattern D7 is electrically connected to the second plate C12 of the first capacitor C1.

[0446] Since the seventh output electrode pattern D7 and the second electrode plate C12 of the first capacitor C1 are located in different film layers, the two can be electrically connected by switching layers through vias.

[0447] Optional, such as Fig. 9 As shown, the length direction of the seventh channel portion 711 is arranged along the second direction X, and the seventh input portion 712 is located at a side of the seventh output portion 713 away from the second voltage signal line VGLL.

[0448] This can not only reduce the size of the seventh transistor T7 in the first direction Y, avoiding increasing the size of the shift register 2a and the scan drive circuit 2 in the first direction Y, but also reduce the distance between the seventh input part 712 and the first clock signal line CKL, and reduce the distance between the seventh output part 713 and the first capacitor C1, so that the structure of the shift register 2a and the scan drive circuit 2 is optimized.

[0449] In some embodiments, Figure 7 and Figure 8As shown, the eighth transistor T8 included in the shift register 2a can be arranged between the first voltage signal line VGHL1 and the seventh transistor T7. Fig. 9 and Fig.10 As shown, the eighth transistor T8 includes an eighth semiconductor portion 81 , and the control electrode of the eighth transistor T8 includes: an eighth gate conductive pattern G8 disposed on a side of the eighth semiconductor portion 81 away from the substrate 1 .

[0450] In some examples, such as Fig. 9 As shown, the eighth semiconductor portion 81 includes an eighth channel portion 811. The orthographic projection of the eighth gate conductive pattern G8 on the substrate 1 partially overlaps with the orthographic projection of the eighth channel portion 811 on the substrate 1.

[0451] Exemplarily, the extension direction of the eighth gate conductive pattern G8 is perpendicular to the length direction of the eighth channel portion 811. Both ends of the eighth gate conductive pattern G8 extend out of the range where the eighth channel portion 811 is located.

[0452] Exemplarily, the film layer where the eighth semiconductor portion 81 is located may be the semiconductor material layer 3 . The film layer where the eighth gate conductive pattern G8 is located may be the second gate conductive layer 4 .

[0453] In some examples, such as Fig.10 As shown, the eighth gate conductive pattern G8 extends along the second direction X, one end of the eighth gate conductive pattern G8 is electrically connected to the seventh input electrode pattern S7, and the other end of the eighth gate conductive pattern G8 is electrically connected to the first clock signal line CKL. The seventh input electrode pattern S7 is electrically connected to the first clock signal line CKL through the eighth gate conductive pattern G8.

[0454] Exemplarily, the connection direction of the eighth transistor T8 and the seventh transistor T7 may be substantially parallel to the second direction X.

[0455] In this way, the eighth gate conductive pattern G8 can be substantially in a straight line shape, which is beneficial to optimizing the layout structure of the scan driving circuit 2 and reducing the influence of process fluctuations in the process of preparing and forming the scan driving circuit 2 on the scan driving circuit 2 .

[0456] Optional, such as Fig.10 As shown, when the shift register 2a further includes the seventh connection portion CN7, a portion of the seventh connection portion CN7 and a portion of the eighth semiconductor portion 81 are arranged opposite to each other, and the orthographic projections of the two on the substrate 1 overlap. Part of the seventh connection portion CN7 can be used as the eighth gate conductive pattern G8, and a portion of the eighth semiconductor portion 81 can be used as the eighth channel portion 811.

[0457] Here, it can be understood that, in the scan drive circuit 2, when the first scan signal output by each stage shift register 2a is used as the input signal of the next stage shift register 2a, the first electrode of the eighth transistor T8 in the first stage shift register 2a can be electrically connected to the third clock signal line STVL, and the first electrode of the eighth transistor T8 in the remaining stages shift register 2a can be electrically connected to the third connection part CN3 of the previous stage shift register 2a.

[0458] In some embodiments, Figure 7 and Figure 8 As shown, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 included in the shift register 2a can be arranged in the gap between the second transistor T2 and the first voltage signal line VGHL1 and in the gap between the first transistor T1 and the first voltage signal line VGHL1.

[0459] In some examples, such as Figure 7 and Figure 8 As shown, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are sequentially arranged along the first direction Y. That is, the connection direction of the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 is substantially parallel to the first direction Y.

[0460] In this way, the space occupied by the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 in the second direction X can be reduced, which is beneficial to reducing the size between the first voltage signal line VGHL1 and the second voltage signal line VGLL, and further beneficial to reducing the size of the border area B, so as to facilitate the display substrate 100 to achieve a narrow border design.

[0461] In some examples, such as Fig. 9 As shown, the ninth transistor T9 includes a ninth semiconductor portion 91, and the ninth semiconductor portion 91 includes: a ninth channel portion 911. The tenth transistor T10 includes a tenth semiconductor portion 101, and the tenth semiconductor portion 101 includes: a tenth channel portion 1011. The eleventh transistor T11 includes an eleventh semiconductor portion 111, and the eleventh semiconductor portion 111 includes: an eleventh channel portion 1111. The twelfth transistor T12 includes a twelfth semiconductor portion 121, and the twelfth semiconductor 121 includes: a twelfth channel portion 1211. Among them, the length direction of the eighth channel portion 811, the length direction of the ninth channel portion 911, the length direction of the tenth channel portion 1011, the length direction of the eleventh channel portion 1111 and the length direction of the twelfth channel portion 1211 are all arranged along the first direction Y.

[0462] In this way, the space occupied by the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 in the second direction X can be further reduced, which is beneficial to further reduce the size between the first voltage signal line VGHL1 and the second voltage signal line VGLL, and further beneficial to reduce the size of the border area B, so as to facilitate the display substrate 100 to achieve a narrow border design.

[0463] In addition, the connection line between the ninth transistor T9 and the second clock signal line CBL, the connection line between the eleventh transistor T11 and the second clock signal line CBL, and the connection line between the twelfth transistor T12 and the second clock signal line CBL are all straight lines, which is convenient for inputting the second clock signal and is beneficial for optimizing the layout of the shift register 2a and the scan drive circuit 2.

[0464] For example, Fig. 9 As shown, the ninth semiconductor portion 91 further includes a ninth input portion 912 and a ninth output portion 913 disposed on both sides of the ninth channel portion 911. The tenth semiconductor portion 101 further includes a tenth input portion 1012 and a tenth output portion 1013 disposed on both sides of the tenth channel portion 1011.

[0465] For example, the ninth semiconductor portion 91 and the tenth semiconductor portion 101 are in an integrated structure and are both located in the semiconductor material layer 3. This is beneficial to improving the structural stability of the ninth semiconductor portion 91 and the tenth semiconductor portion 101.

[0466] Optional, such as Fig. 9 As shown, the ninth input portion 912 and the tenth output portion 1013 may be an integrated structure, and both may serve as the first electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10. This is not only conducive to simplifying the structure of the shift register 2a and the scan drive circuit 2 and optimizing the layout, but also conducive to reducing the size of the ninth semiconductor portion 91 and the tenth semiconductor portion 101 in the first direction Y, thereby facilitating reducing the size of the shift register 2a and the scan drive circuit 2 in the first direction Y.

[0467] For example, Fig. 9 As shown, compared with the ninth input portion 912, the ninth output portion 913 is closer to the eighth semiconductor portion 81. This is not only conducive to reducing the distance between the ninth output portion 913 and the eighth semiconductor portion 81, but also can make the connection line between the ninth output portion 913 and the eighth semiconductor portion 81 straight, which is conducive to optimizing the layout of the shift register 2a and the scan drive circuit 2.

[0468] For example, Fig. 9As shown, the eleventh semiconductor portion 111 further includes an eleventh input portion 1112 and an eleventh output portion 1113 disposed on both sides of the eleventh channel portion 1111. The twelfth semiconductor portion 121 further includes a twelfth input portion 1212 and a twelfth output portion 1213 disposed on both sides of the twelfth channel portion 1211.

[0469] For example, the eleventh semiconductor portion 111 and the twelfth semiconductor portion 121 are in an integrated structure and are both located in the semiconductor material layer 3 , which is beneficial to improving the structural stability of the eleventh semiconductor portion 111 and the twelfth semiconductor portion 121 .

[0470] Optionally, the eleventh output portion 1113 and the twelfth input portion 1212 may be an integrated structure, and both may serve as a part of the second electrode of the eleventh transistor T11, and may also serve as a part of the first electrode of the twelfth transistor T12. This is not only conducive to simplifying the structure of the shift register 2a and the scan drive circuit 2 and optimizing the layout, but also conducive to reducing the size of the eleventh semiconductor portion 111 and the twelfth semiconductor portion 121 in the first direction Y, and further conducive to reducing the size of the shift register 2a and the scan drive circuit 2 in the first direction Y.

[0471] In some embodiments, Figure 7 and Figure 8 As shown, the thirteenth transistor T13 and the fourteenth transistor T14 included in the shift register 2a can be arranged between the eighth transistor T8 and the seventh transistor T7, and arranged in sequence along the first direction Y. That is, the connection direction of the thirteenth transistor T13 and the fourteenth transistor T14 is substantially parallel to the first direction Y.

[0472] In this way, the space occupied by the thirteenth transistor T13 and the fourteenth transistor T14 in the second direction X can be reduced, which is beneficial to reducing the size between the first voltage signal line VGHL1 and the second voltage signal line VGLL, and further beneficial to reducing the size of the border area B, so as to realize a narrow border design for the display substrate 100.

[0473] In some examples, such as Fig. 9 As shown, the thirteenth transistor T13 includes a thirteenth semiconductor portion 131, and the thirteenth semiconductor portion 131 includes: a thirteenth channel portion 1311. The fourteenth transistor T14 includes a fourteenth semiconductor portion 141, and the fourteenth semiconductor portion 141 includes: a fourteenth channel portion 1411. The length direction of the thirteenth channel portion 1311 and the length direction of the fourteenth channel portion 1411 are both arranged along the first direction Y.

[0474] This can further reduce the space occupied by the thirteenth transistor T13 and the fourteenth transistor T14 in the second direction X, which is beneficial to further reduce the size between the first voltage signal line VGHL1 and the second voltage signal line VGLL, and further beneficial to reduce the size of the border area B, so as to facilitate the display substrate 100 to achieve a narrow border design.

[0475] Optional, such as Fig. 9 As shown, the thirteenth semiconductor portion 131 further includes a thirteenth input portion 1312 and a thirteenth output portion 1313 disposed on both sides of the thirteenth channel portion 1311 . The fourteenth semiconductor portion 141 further includes a fourteenth input portion 1412 and a fourteenth output portion 1413 disposed on both sides of the fourteenth channel portion 1411 .

[0476] The thirteenth output portion 1313 and the fourteenth input portion 1412 may be an integrated structure, and both may serve as a part of the second electrode of the thirteenth transistor T13, and may also serve as a part of the first electrode of the fourteenth transistor T14. This is not only conducive to simplifying the structure of the shift register 2a and the scan drive circuit 2, and optimizing the layout, but also conducive to reducing the size of the thirteenth semiconductor portion 131 and the fourteenth semiconductor portion 141 in the first direction Y, and further conducive to reducing the size of the shift register 2a and the scan drive circuit 2 in the first direction Y.

[0477] For example, Figure 7 and Figure 8 As shown, the thirteenth transistor T13 is a dual-gate transistor. The control electrode of the thirteenth transistor T13 includes a thirteenth gate conductive pattern G13. The thirteenth gate conductive pattern G13 includes: a first sub-gate conductive pattern G131 extending along the second direction X, a second sub-gate conductive pattern G132, and a third sub-gate conductive pattern G133 extending along the first direction Y, one end of the third sub-gate conductive pattern G133 is electrically connected to the first sub-gate conductive pattern G131, and the other end is electrically connected to the second sub-gate conductive pattern G132. The thirteenth gate conductive pattern G13 is U-shaped as a whole.

[0478] Optionally, the first sub-gate conductive pattern G131 , the second sub-gate conductive pattern G132 and the third sub-gate conductive pattern G133 are in an integrated structure and are located in the second gate conductive layer 4 .

[0479] For example, Figure 7 and Figure 8 As shown, the thirteenth transistor T13 is electrically connected to the second electrode of the eighth transistor T8 through the third sub-gate conductive pattern G133, and is electrically connected to the first electrode of the sixteenth transistor T16 through the second sub-gate conductive pattern G132.

[0480] In some embodiments, Figure 7 and Figure 8As shown, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 included in the shift register 2a can be arranged between the thirteenth transistor T13 and the seventh transistor T7, and are arranged in sequence along the first direction Y. Among them, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 can be arranged at intervals, the third capacitor C3 can be arranged between the sixteenth transistor T16 and the seventeenth transistor T17, and the second capacitor C2 can be arranged between the fifteenth transistor T15 and the sixteenth transistor T16.

[0481] In some examples, such as Fig. 9 As shown, the fifteenth transistor T15 includes a fifteenth semiconductor portion 151, and the fifteenth semiconductor portion 151 includes a fifteenth channel portion 1511. The sixteenth transistor T16 includes a sixteenth semiconductor portion 161, and the sixteenth semiconductor portion 161 includes a sixteenth channel portion 1611. The seventeenth transistor T17 includes a seventeenth semiconductor portion 171, and the seventeenth semiconductor portion 171 includes a seventeenth channel portion 1711. The length direction of the fifteenth channel portion 1511, the length direction of the sixteenth channel portion 1611, and the length direction of the seventeenth channel portion 1711 are all arranged along the second direction X.

[0482] In this way, the connection wiring between the fifteenth transistor T15 and the sixteenth transistor T16, and the connection wiring between the sixteenth transistor T16 and the seventeenth transistor T17, can be more regular, which is beneficial to improving the structural stability of the connection wiring.

[0483] In the scan driving circuit 2 provided in some embodiments of the present disclosure, the cascade relationship of the plurality of shift registers 2a may include various types, which may be selected and set according to actual needs.

[0484] In some embodiments, Fig.16 As shown, among the plurality of shift registers 2a, except for the last shift register 2a, the first scanning signal terminal EM_OUT of the Nth shift register 2a is electrically connected to the input signal terminal STV of the N+1th shift register 2a, where N is a positive integer.

[0485] That is, the first scanning signal output by the Nth shift register 2a can be used as the input signal of the N+1th shift register 2a.

[0486] In some examples, such as Fig.16As shown, the first clock signal line CKL can be electrically connected to the first clock signal terminal CK of the 2N-1th shift register 2a, and to the second clock signal terminal CB of the 2Nth shift register 2a. The second clock signal line CBL can be electrically connected to the second clock signal terminal CB of the 2N-1th shift register 2a, and to the first clock signal terminal CK of the 2Nth shift register 2a.

[0487] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: The display substrate comprises: A substrate; and at least one scan driving circuit disposed on the substrate; The scanning driving circuit comprises: A first voltage signal line, a second voltage signal line and a third voltage signal line extending along the first direction and sequentially spaced along the second direction; and a plurality of cascaded shift registers; The shift register consists of: A first transistor and a second transistor are arranged between the first voltage signal line and the second voltage signal line; a first electrode of the first transistor is electrically connected to the first voltage signal line, and a second electrode of the first transistor is electrically connected to a first output terminal; a first electrode of the second transistor is electrically connected to the second voltage signal line, and a second electrode of the second transistor is electrically connected to the first output terminal; a third transistor and a fourth transistor arranged between the second voltage signal line and the third voltage signal line; a first electrode of the third transistor being electrically connected to the second voltage signal line, and a second electrode of the third transistor being electrically connected to the second output terminal; a first electrode of the fourth transistor being electrically connected to the third voltage signal line, and a second electrode of the fourth transistor being electrically connected to the second output terminal; at least one first scanning signal line electrically connected to the first output terminal and extending along the second direction; and, At least one second scanning signal line is electrically connected to the second output terminal and extends along the second direction.

2. The display substrate according to claim 1, characterized in that: The orthographic projection of the first scanning signal line on the substrate has no overlap with the orthographic projection of the second scanning signal line on the substrate.

3. The display substrate according to claim 1, characterized in that: The number of the first scanning signal lines is plural, and the number of the second scanning signal lines is plural; Along the first direction, the first scanning signal lines and the second scanning signal lines are alternately arranged in sequence.

4. The display substrate according to claim 3, characterized in that: One of the first scanning signal lines and one of the second scanning signal lines form a group of output signal lines; Two adjacent groups of output signal lines are arranged at intervals.

5. The display substrate according to claim 1, characterized in that: The first scanning signal line and the second scanning signal line are arranged in the same layer and are located in the first gate conductive layer; and / or, The first voltage signal line, the second voltage signal line and the third voltage signal line are arranged in the same layer and are located in the source-drain conductive layer.

6. The display substrate according to claim 1, characterized in that: The third transistor includes a third semiconductor portion, and the fourth transistor includes a fourth semiconductor portion; the third semiconductor portion and the fourth semiconductor portion are sequentially arranged at intervals along the first direction; Along the first direction, the first scanning signal line and the second scanning signal line are both located between the third semiconductor portion and the fourth semiconductor portion; and / or, Along the first direction, the first scanning signal line and the second scanning signal line are both located between two adjacent shift registers.

7. The display substrate according to claim 6, characterized in that: An orthographic projection of any one of the first scanning signal line and the second scanning signal line on the substrate does not overlap with an orthographic projection of any one of the third semiconductor portion and the fourth semiconductor portion on the substrate.

8. The display substrate according to claim 6, characterized in that: The third semiconductor portion includes: a plurality of third channel portions arranged at intervals along the first direction, and a third input portion and a third output portion arranged on both sides of each third channel portion; The control electrode of the third transistor comprises: a third gate conductive pattern arranged on a side of the third semiconductor portion away from the substrate and in a comb shape; the third gate conductive pattern comprises a plurality of third sub-gates arranged at intervals along the first direction, and the orthographic projection of the third sub-gates on the substrate partially overlaps with the orthographic projection of the third channel portion on the substrate; The first electrode of the third transistor comprises: a third input electrode pattern in a comb shape, which is arranged on a side of the third gate conductive pattern away from the substrate; the third input electrode pattern comprises a plurality of third sub-input electrodes arranged at intervals along the first direction, and the orthographic projection of the third sub-input electrode on the substrate partially overlaps with the orthographic projection of the third input portion on the substrate; the third input electrode pattern is electrically connected to the second voltage signal line; The second electrode of the third transistor comprises: a third output electrode pattern in a comb shape, which is arranged on a side of the third gate conductive pattern away from the substrate; the third output electrode pattern comprises a plurality of third sub-output electrodes arranged at intervals along the first direction, and the orthographic projection of the third sub-output electrode on the substrate partially overlaps with the orthographic projection of the third output portion on the substrate; the third output electrode pattern is electrically connected to the second scanning signal line; Wherein, the plurality of third sub-input electrodes and the plurality of third sub-output electrodes are arranged alternately in sequence; and / or, The third input electrode pattern and the third output electrode pattern are arranged in the same layer and are located in the source-drain conductive layer.

9. The display substrate according to claim 8, characterized in that: The third input electrode pattern and the second voltage signal line are in an integrated structure.

10. The display substrate according to claim 8, characterized in that: The fourth semiconductor portion includes: a plurality of fourth channel portions arranged at intervals along the first direction, and a fourth input portion and a fourth output portion arranged on both sides of each fourth channel portion; The control electrode of the fourth transistor comprises: a fourth gate conductive pattern disposed on a side of the fourth semiconductor portion away from the substrate and in a comb shape; the fourth gate conductive pattern comprises a plurality of fourth sub-gates arranged at intervals along the first direction, and the orthographic projection of the fourth sub-gates on the substrate partially overlaps with the orthographic projection of the fourth channel portion on the substrate; the fourth gate conductive pattern is electrically connected to the first scanning signal line; The first electrode of the fourth transistor comprises: a fourth input electrode pattern in a comb shape, which is arranged on a side of the fourth gate conductive pattern away from the substrate; the fourth input electrode pattern comprises a plurality of fourth sub-input electrodes arranged at intervals along the first direction, and the orthographic projection of the fourth sub-input electrode on the substrate partially overlaps with the orthographic projection of the fourth input portion on the substrate; the fourth input electrode pattern is electrically connected to the third voltage signal line; The second electrode of the fourth transistor comprises: a fourth output electrode pattern in a comb shape, which is arranged on a side of the fourth gate conductive pattern away from the substrate; the fourth output electrode pattern comprises a plurality of fourth sub-output electrodes arranged at intervals along the first direction, and the orthographic projection of the fourth sub-output electrode on the substrate partially overlaps with the orthographic projection of the fourth output portion on the substrate; the fourth output electrode pattern is electrically connected to the second scanning signal line; Wherein, the plurality of fourth sub-input electrodes and the plurality of fourth sub-output electrodes are arranged alternately in sequence; and / or, The fourth input electrode pattern and the fourth output electrode pattern are arranged in the same layer and are located in the source-drain conductive layer.

11. The display substrate according to claim 10, characterized in that: The fourth input electrode pattern and the third voltage signal line are in an integrated structure; and / or, The third output electrode pattern and the fourth output electrode pattern are in an integrated structure.

12. The display substrate according to claim 10 or 11, characterized in that: The shift register further includes: a first connecting portion extending along the first direction and disposed between the fourth gate conductive pattern and the first scan signal line; One end of the first connection portion is electrically connected to the fourth gate conductive pattern, and the other end of the first connection portion is electrically connected to the first scan signal line; The first connecting portion is located in the source-drain conductive layer.

13. The display substrate according to claim 10, characterized in that: The first transistor includes a first semiconductor portion, and the second transistor includes a second semiconductor portion; The first semiconductor portion and the second semiconductor portion are sequentially arranged along the first direction and are in an integrated structure.

14. The display substrate according to claim 13, characterized in that: The first semiconductor portion includes: a plurality of first channel portions arranged at intervals along the first direction, and a first input portion and a first output portion arranged on both sides of each first channel portion; The control electrode of the first transistor comprises: a first gate conductive pattern in a comb shape and arranged on a side of the first semiconductor portion away from the substrate; the first gate conductive pattern comprises a plurality of first sub-gates arranged at intervals along the first direction, and the orthographic projection of the first sub-gates on the substrate partially overlaps with the orthographic projection of the first channel portion on the substrate; The first electrode of the first transistor comprises: a first input electrode pattern in a comb shape and arranged on a side of the first gate conductive pattern away from the substrate; the first input electrode pattern comprises a plurality of first sub-input electrodes arranged at intervals along the first direction, and the orthographic projection of the first sub-input electrode on the substrate partially overlaps with the orthographic projection of the first input portion on the substrate; the first input electrode pattern is also electrically connected to the first voltage signal line; The second electrode of the first transistor comprises: a first output electrode pattern in a comb shape and arranged on a side of the first gate conductive pattern away from the substrate; the first output electrode pattern comprises a plurality of first sub-output electrodes arranged at intervals along the first direction, and the orthographic projection of the first sub-output electrode on the substrate partially overlaps with the orthographic projection of the first output portion on the substrate; the first output electrode pattern is also electrically connected to the first scanning signal line; The second semiconductor portion includes: a plurality of second channel portions arranged at intervals along the first direction, and a second input portion and a second output portion arranged on both sides of each second channel portion; The control electrode of the second transistor comprises: a second gate conductive pattern in a comb shape and arranged on a side of the second semiconductor portion away from the substrate; the second gate conductive pattern comprises a plurality of second sub-gates arranged at intervals along the first direction, and the orthographic projection of the second sub-gates on the substrate partially overlaps with the orthographic projection of the second channel portion on the substrate; The first electrode of the second transistor comprises: a second input electrode pattern in a comb shape and arranged on a side of the second gate conductive pattern away from the substrate; the second input electrode pattern comprises a plurality of second sub-input electrodes arranged at intervals along the first direction, and the orthographic projection of the second sub-input electrode on the substrate partially overlaps with the orthographic projection of the second input portion on the substrate; the second input electrode pattern is also electrically connected to the second voltage signal line; The second electrode of the second transistor includes: a second output electrode pattern in a comb shape, which is arranged on the side of the second gate conductive pattern away from the substrate; the second output electrode pattern includes a plurality of second sub-output electrodes arranged at intervals along the first direction, and the orthographic projection of the second sub-output electrode on the substrate partially overlaps with the orthographic projection of the second output part on the substrate; the second output electrode pattern is also electrically connected to the first scanning signal line.

15. The display substrate according to claim 14, characterized in that: The shift register further includes: a fifth transistor disposed between the third transistor and the fourth transistor; The fifth transistor includes a fifth semiconductor portion; the fifth semiconductor portion includes: a fifth channel portion and a fifth input portion and a fifth output portion disposed on both sides of the fifth channel portion; The control electrode of the fifth transistor comprises: a fifth gate conductive pattern arranged on a side of the fifth semiconductor portion away from the substrate; an orthographic projection of the fifth gate conductive pattern on the substrate partially overlaps with an orthographic projection of the fifth channel portion on the substrate; and the fifth gate conductive pattern is electrically connected to the control electrode of the first transistor; The first electrode of the fifth transistor comprises: a fifth input electrode pattern arranged on a side of the fifth gate conductive pattern away from the substrate; the orthographic projection of the fifth input electrode pattern on the substrate partially overlaps with the orthographic projection of the fifth input portion on the substrate; the fifth input electrode pattern is also electrically connected to the second voltage signal line; The second electrode of the fifth transistor includes: a fifth output electrode pattern arranged on a side of the fifth gate conductive pattern away from the substrate; an orthographic projection of the fifth output electrode pattern on the substrate partially overlaps with an orthographic projection of the fifth output portion on the substrate.

16. The display substrate according to claim 15, characterized in that: The first sub-gate in the first gate conductive pattern extends toward the fifth transistor in a zigzag shape and is reused as the fifth gate conductive pattern.

17. The display substrate according to claim 15, characterized in that: The length direction of the fifth channel portion is arranged along the second direction; the fifth input portion is located at a side of the fifth output portion close to the second voltage signal line; and / or, The fifth input electrode pattern is located in the source-drain conductive layer and is an integral structure with the second voltage signal line.

18. The display substrate according to claim 15, characterized in that: A third sub-gate in the third gate conductive pattern close to the fifth transistor extends toward the fifth transistor in a corner shape and is electrically connected to the fifth output electrode pattern.

19. The display substrate according to any one of claims 15 to 18, characterized in that: In the case where both the first scanning signal line and the second scanning signal line are located between the third semiconductor portion and the fourth semiconductor portion, The fifth transistor is disposed between the third transistor and the first scan signal line.

20. The display substrate according to claim 15, characterized in that: The shift register further includes: a sixth transistor disposed between the third transistor and the fourth transistor; The sixth transistor includes a sixth semiconductor portion; the sixth semiconductor portion includes: a sixth channel portion and a sixth input portion and a sixth output portion disposed on both sides of the sixth channel portion; The control electrode of the sixth transistor comprises: a sixth gate conductive pattern arranged on a side of the sixth semiconductor portion away from the substrate; an orthographic projection of the sixth gate conductive pattern on the substrate partially overlaps with an orthographic projection of the sixth channel portion on the substrate; and the sixth gate conductive pattern is electrically connected to the control electrode of the fourth transistor; The first electrode of the sixth transistor comprises: a sixth input electrode pattern arranged on a side of the sixth gate conductive pattern away from the substrate; the orthographic projection of the sixth input electrode pattern on the substrate partially overlaps with the orthographic projection of the sixth input portion on the substrate; the sixth input electrode pattern is also electrically connected to the third voltage signal line; The second electrode of the sixth transistor includes: a sixth output electrode pattern arranged on a side of the sixth gate conductive pattern away from the substrate; the orthographic projection of the sixth output electrode pattern on the substrate partially overlaps with the orthographic projection of the sixth output part on the substrate; when the shift register also includes a fifth transistor, the sixth output electrode pattern is electrically connected to the fifth output electrode pattern of the fifth transistor.

21. The display substrate according to claim 20, characterized in that: A fourth sub-gate in the fourth gate conductive pattern close to the sixth transistor extends toward the sixth transistor in a corner shape and is reused as the sixth gate conductive pattern.

22. The display substrate according to claim 20, characterized in that: The length direction of the sixth channel portion is arranged along the first direction; the sixth input portion is located on a side of the sixth output portion close to the fourth transistor.

23. The display substrate according to claim 20, characterized in that: The sixth semiconductor portion and the fourth semiconductor portion are in an integrated structure; A fourth input portion close to the sixth semiconductor portion is multiplexed as the sixth input portion; A fourth sub-input electrode close to the sixth semiconductor portion in the fourth input electrode pattern of the fourth transistor is multiplexed as the sixth input electrode pattern.

24. The display substrate according to any one of claims 20 to 23, characterized in that: In the case where both the first scanning signal line and the second scanning signal line are located between the third semiconductor portion and the fourth semiconductor portion, The sixth transistor is disposed between the fourth transistor and the first scan signal line.

25. The display substrate according to claim 15, characterized in that: The shift register further includes: a first capacitor disposed between the second transistor and the fourth transistor; The first capacitor includes: a first plate and a second plate which are arranged between the substrate and the second voltage signal line and are stacked in sequence; The first plate of the first capacitor is electrically connected to the fifth output electrode pattern of the fifth transistor.

26. The display substrate according to claim 25, characterized in that: An orthographic projection of any one of the first plate of the first capacitor and the second plate of the first capacitor on the substrate at least partially overlaps with an orthographic projection of the second voltage signal line on the substrate; and / or, A size of any one of the first plate of the first capacitor and the second plate of the first capacitor in the second direction is substantially equal to a size of the second voltage signal line in the second direction.

27. The display substrate according to claim 25 or 26, characterized in that: The first electrode plate of the first capacitor and the fifth gate conductive pattern of the fifth transistor are arranged in the same layer and are located in the second gate conductive layer; The second plate of the first capacitor is located on the first gate conductive layer.

28. The display substrate according to claim 25, characterized in that: The scan driving circuit further includes: a first clock signal line which is arranged at a side of the first voltage signal line away from the second voltage signal line and extends along the first direction; The shift register further includes: a seventh transistor disposed between the first voltage signal line and the second voltage signal line; The seventh transistor includes a seventh semiconductor portion; the seventh semiconductor portion includes: a seventh channel portion and a seventh input portion and a seventh output portion disposed on both sides of the seventh channel portion; The control electrode of the seventh transistor comprises: a seventh gate conductive pattern arranged on a side of the seventh semiconductor portion away from the substrate; an orthographic projection of the seventh gate conductive pattern on the substrate partially overlaps with an orthographic projection of the seventh channel portion on the substrate; the seventh gate conductive pattern is electrically connected to the first plate of the first capacitor; The first electrode of the seventh transistor comprises: a seventh input electrode pattern arranged on a side of the seventh gate conductive pattern away from the substrate; an orthographic projection of the seventh input electrode pattern on the substrate partially overlaps with an orthographic projection of the seventh input portion on the substrate; and the seventh input electrode pattern is also electrically connected to the first clock signal line; The second electrode of the seventh transistor comprises: a seventh output electrode pattern arranged on a side of the seventh gate conductive pattern away from the substrate; an orthographic projection of the seventh output electrode pattern on the substrate partially overlaps with an orthographic projection of the seventh output portion on the substrate; the seventh output electrode pattern is electrically connected to the second electrode plate of the first capacitor; The seventh semiconductor portion is arranged on a side of the second semiconductor portion away from the first semiconductor portion.

29. The display substrate according to claim 28, characterized in that: The first plate of the first capacitor is close to one end of the seventh transistor, extends toward the seventh transistor, and is reused as the seventh gate conductive pattern.

30. The display substrate according to claim 28, characterized in that The length direction of the seventh channel portion is arranged along the second direction; The seventh input portion is located at a side of the seventh output portion away from the second voltage signal line.

31. The display substrate according to claim 28, characterized in that The shift register further includes: an eighth transistor disposed between the first voltage signal line and the seventh transistor; The eighth transistor includes an eighth semiconductor portion; the eighth semiconductor portion includes: an eighth channel portion; The control electrode of the eighth transistor comprises: an eighth gate conductive pattern arranged on a side of the eighth semiconductor portion away from the substrate; an orthographic projection of the eighth gate conductive pattern on the substrate partially overlaps with an orthographic projection of the eighth channel portion on the substrate; The eighth gate conductive pattern extends along the second direction, one end of the eighth gate conductive pattern is electrically connected to the seventh input electrode pattern, and the other end of the eighth gate conductive pattern is electrically connected to the first clock signal line; The seventh input electrode pattern is electrically connected to the first clock signal line through the eighth gate conductive pattern.

32. The display substrate according to claim 31, characterized in that: The scan driving circuit further includes: a second clock signal line arranged at a side of the first voltage signal line away from the second voltage signal line and extending along the first direction; The shift register further includes: a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor; The second electrode of the eighth transistor is electrically connected to the second electrode of the ninth transistor; The control electrode of the ninth transistor is electrically connected to the second clock signal line, and the first electrode of the ninth transistor is electrically connected to the second electrode of the tenth transistor; The control electrode of the tenth transistor is electrically connected to the control electrode of the eleventh transistor, and the first electrode of the tenth transistor is electrically connected to the first voltage signal line; A first electrode of the eleventh transistor is electrically connected to the second clock signal line, and a second electrode of the eleventh transistor is electrically connected to a first electrode of the twelfth transistor; The control electrode of the twelfth transistor is electrically connected to the second clock signal line, and the second electrode of the twelfth transistor is electrically connected to the control electrode of the first transistor; Among them, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are arranged in sequence along the first direction.

33. The display substrate according to claim 32, characterized in that: The ninth transistor includes a ninth semiconductor portion, the ninth semiconductor portion including: a ninth channel portion; The tenth transistor includes a tenth semiconductor portion, the tenth semiconductor portion including: a tenth channel portion; The eleventh transistor includes an eleventh semiconductor portion, and the eleventh semiconductor portion includes: an eleventh channel portion; The twelfth transistor includes a twelfth semiconductor portion, and the twelfth semiconductor portion includes: a twelfth channel portion; The length direction of the eighth channel portion, the length direction of the ninth channel portion, the length direction of the tenth channel portion, the length direction of the eleventh channel portion, and the length direction of the twelfth channel portion are all arranged along the first direction.

34. The display substrate according to claim 32, characterized in that: The shift register further includes: a thirteenth transistor and a fourteenth transistor which are arranged between the eighth transistor and the seventh transistor and are arranged in sequence along the first direction; The thirteenth transistor is a dual-gate transistor, the control electrode of the thirteenth transistor is electrically connected to the second electrode of the eighth transistor; the first electrode of the thirteenth transistor is electrically connected to the first clock signal line, and the second electrode of the thirteenth transistor is electrically connected to the first electrode of the fourteenth transistor; The control electrode of the fourteenth transistor is electrically connected to the second voltage signal line, and the second electrode of the fourteenth transistor is electrically connected to the control electrode of the eleventh transistor.

35. The display substrate according to claim 34, characterized in that: The thirteenth transistor includes a thirteenth semiconductor portion, and the thirteenth semiconductor portion includes: a thirteenth channel portion; The fourteenth transistor includes a fourteenth semiconductor portion, and the fourteenth semiconductor portion includes: a fourteenth channel portion; The length direction of the thirteenth channel portion and the length direction of the fourteenth channel portion are both arranged along the first direction.

36. The display substrate according to claim 34, characterized in that: The shift register further includes: a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor disposed between the thirteenth transistor and the seventh transistor and sequentially disposed along the first direction; a second capacitor disposed between the fifteenth transistor and the sixteenth transistor; A third capacitor is provided between the sixteenth transistor and the seventeenth transistor; and a fourth capacitor disposed on a side of the seventeenth transistor away from the sixteenth transistor; The control electrode of the fifteenth transistor is electrically connected to the first clock signal line, the first electrode of the fifteenth transistor is electrically connected to the second voltage signal line, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the fourteenth transistor; The control electrode of the sixteenth transistor is electrically connected to the second voltage signal line, the first electrode of the sixteenth transistor is electrically connected to the second electrode of the eighth transistor, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the second transistor; The control electrode of the seventeenth transistor is electrically connected to the second electrode of the eighth transistor, the first electrode of the seventeenth transistor is electrically connected to the first voltage signal line, and the second electrode of the seventeenth transistor is electrically connected to the control electrode of the first transistor; A first plate of the second capacitor is electrically connected to the second clock signal line, and a second plate of the second capacitor is electrically connected to a control electrode of the second transistor; The first plate of the third capacitor is electrically connected to the control electrode of the eleventh transistor, and the second plate of the third capacitor is electrically connected to the second electrode of the eleventh transistor; The first plate of the fourth capacitor is electrically connected to the control electrode of the first transistor, and the second plate of the fourth capacitor is electrically connected to the first voltage signal line.

37. A display device, characterized in that: The display device comprises: a display substrate according to any one of claims 1 to 36.

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