Display device

Abstract

A display device includes a substrate; a first drive transistor provided over or on the substrate and included in a first sub-pixel; a cover layer over or on the first drive transistor; a first anode provided over or on the first drive transistor and included in the first sub-pixel; a first light-emitting layer over the first anode; and a cathode over the first light-emitting layer. The first anode includes a first electrode portion in a first region of the first sub-pixel, a second electrode portion in a second region of the first sub-pixel different from the first region, and a first wire portion connecting the first electrode portion and the second electrode portion. The cover layer includes a first trench in a region overlapping with the first wire portion. The first wire portion includes a first bent portion provided over or on a protection layer and bent along first and second inner side surfaces and a bottom surface of the first trench.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0166127, filed on November 26, 2021, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display device. Background Technology

[0004] In the manufacturing of display panels, defects may occur due to various reasons, such as impurities existing in multiple locations of a sub-pixel, causing the sub-pixel to form bright or dark spots. For example, impurities may be present between the anode and cathode of the light-emitting device in each sub-pixel. In this case, the light-emitting device may not emit light, and therefore the corresponding sub-pixel may become a dark spot. Summary of the Invention

[0005] In the field of display technology, when an anode-cathode short circuit occurs between the anode and cathode of a light-emitting device due to impurities introduced during the manufacturing process, a repair method has been used to normalize the corresponding sub-pixels by irradiating the anode with a laser beam to cut a portion of the anode. However, this repair method requires a separate laser irradiation device, and the laser beam must reach the anode. Therefore, there is a problem that repair cannot be performed after panel manufacturing is complete. Furthermore, there is a problem that repair cannot be performed after the product has been shipped and the user has received the display device. Therefore, the inventors of this application have invented a repair method that can self-cut the anode without irradiating a laser beam, thereby normalizing the corresponding sub-pixels.

[0006] Embodiments of this disclosure provide a display device having a structure that enables a portion of the anode to self-cut.

[0007] A display device is also provided in which a repair process can be performed during panel manufacturing or after the product leaves the factory, thereby enabling a portion of the anode to self-cut and thus normalizing the corresponding sub-pixels through reverse bias processing.

[0008] According to an embodiment, a display device is provided, comprising: a substrate; a first driving transistor disposed on or above the substrate and included in a first sub-pixel; a cover layer located on or above the first driving transistor; a first anode disposed on or above the first driving transistor and included in the first sub-pixel; a first light-emitting layer located on the first anode; and a cathode located on the first light-emitting layer.

[0009] The first anode may include a first electrode portion disposed in a first region of the first sub-pixel, a second electrode portion disposed in a second region of the first sub-pixel that is different from the first region, and a first conductive portion connecting the first electrode portion and the second electrode portion.

[0010] The cover layer may include a first groove in the area overlapping with the first conductor portion. The first conductor portion may include a first curved portion disposed on or above the cover layer and curved along a first inner surface, a bottom surface, and a second inner surface of the first groove.

[0011] A display device is also provided, comprising: a first sub-pixel including a first driving transistor, a first anode and a first light-emitting layer; a second sub-pixel including a second driving transistor, a second anode and a second light-emitting layer; and a cover layer located between the first driving transistor and the second driving transistor and the first anode and the second anode, and including a first trench located in a region of the first anode and a second trench located in a region of the second anode.

[0012] The first anode may include a first electrode portion disposed in a first region of the first sub-pixel, a second electrode portion disposed in a second region of the first sub-pixel that is different from the first region, and a first conductive portion connecting the first electrode portion and the second electrode portion.

[0013] The second anode may include a third electrode portion disposed in a third region of the second sub-pixel, a fourth electrode portion disposed in a fourth region of the second sub-pixel that is different from the third region, and a second conductive portion connecting the third electrode portion and the fourth electrode portion.

[0014] When the first sub-pixel is a sub-pixel that has undergone self-partial anode repair (SPARP) and the second sub-pixel is a sub-pixel that has not undergone SPARP, the first conductor portion can be disconnected in the first trench of the cover layer, and the second conductor portion can remain connected in the second trench of the cover layer.

[0015] According to an embodiment, the display device may have a structure that enables a portion of the anode to self-cut.

[0016] According to the implementation, in the display device, during panel manufacturing or after the product leaves the factory, a repair process can be performed to enable a portion of the anode to self-cut through reverse biasing, thereby normalizing the corresponding sub-pixels. Attached Figure Description

[0017] The above and other objects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 This is a diagram illustrating the system structure of a display device according to an embodiment;

[0019] Figure 2 An example is illustrated of a cathode-anode short circuit in a sub-pixel containing impurities in a display device according to an embodiment;

[0020] Figure 3 An aging process for removing a cathode-anode short circuit in a display device according to an embodiment is illustrated.

[0021] Figure 4 An example is shown of the light emission state according to the sub-pixel type in a display device according to an embodiment;

[0022] Figure 5 and Figure 6 It is an equivalent circuit for conceptually describing the first sub-pixel of a display device according to an embodiment of the self-localized anodizing repair (SPARP);

[0023] Figures 7 to 9 An example of a self-cutting enabling structure for the first anode of a SPARP for a display device according to an embodiment is shown;

[0024] Figure 10 An example of a first trench in the cover layer of a SPARP for a display device according to an embodiment is shown;

[0025] Figure 11 An example is shown of an inclined structure on the inner surface of the first trench of a SPARP cover layer for a display device according to an embodiment;

[0026] Figure 12 An example of an organic material deposition structure in the first trench of a SPARP cover layer for a display device according to an embodiment is shown;

[0027] Figure 13 An example is illustrated of a first sub-pixel undergoing first anode self-cutting via SPARP processing in a display device according to an embodiment;

[0028] Figure 14 This example illustrates the change in the luminous state of the first sub-pixel before and after SPARP processing.

[0029] Figure 15 Examples of a first driving transistor in a first sub-pixel and an example of a second driving transistor in a second sub-pixel are shown in a display device according to an embodiment;

[0030] Figure 16 Examples of a first anode in a first sub-pixel and an example of a second anode in a second sub-pixel are shown in a display device according to an embodiment;

[0031] Figures 17 to 19 Examples of trench structures in a first sub-pixel and examples of trench structures in a second sub-pixel are illustrated in a display device according to an embodiment;

[0032] Figures 20 to 22 Examples illustrating the relationship between the connecting wire structure of the first sub-pixel and the connecting wire structure of the second sub-pixel, as well as the relationship between the trench structure of the first sub-pixel and the trench structure of the second sub-pixel;

[0033] Figure 23 This is a plan view illustrating an area with four sub-pixels when the display device according to the embodiment is a transparent display; and

[0034] Figure 24 This is an example Figure 23 A cross-sectional view of region AA′. Detailed Implementation

[0035] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and wherein the same reference numerals and symbols may be used to denote the same or similar parts, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and parts incorporated herein are omitted where it is determined that the description may make the subject matter of some embodiments of the invention less clear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional parts, unless these terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0036] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0037] When referring to the first element and the second element as "connected or coupled" or "in contact or overlapping", it should be understood that not only can the first element be "directly connected or coupled" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled", "in contact or overlapping" with each other through a fourth element, etc. Here, the second element can be included in at least one of two or more elements that are "connected or coupled", "in contact or overlapping" with each other, etc.

[0038] In the following text, various embodiments will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 This is a diagram illustrating the system configuration of the display device 100 according to an embodiment. (Refer to...) Figure 1 The display driving system of the display device 100 according to the embodiment may include a display panel 110 and a display driver circuit for driving the display panel 110.

[0040] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images. The display panel 110 may include multiple sub-pixels SP disposed on or above the substrate SUB to display images. The display panel 110 may include multiple signal lines disposed on or above the substrate SUB to drive the multiple sub-pixels SP. For example, the multiple signal lines may include data lines DL, gate lines GL, drive voltage lines, etc.

[0041] Each of the multiple data lines DL can be arranged to extend in a first direction (e.g., column direction or row direction). Each of the multiple gate lines GL can be arranged to extend in a direction intersecting the first direction.

[0042] The display driver circuit may include a data driver circuit 120 and a gate driver circuit 130, and also includes a controller 140 to control the data driver circuit 120 and the gate driver circuit 130.

[0043] The data driver circuit 120 can output a data signal (also called a data voltage) corresponding to the image signal to multiple data lines DL. The gate driver circuit 130 can generate a gate signal and output the gate signal to multiple gate lines GL. The controller 140 can convert the image data input from the external host 150 into image data with a data signal format that can be read by the data driver circuit 120, and provide the image data to the data driver circuit 120.

[0044] The data driver circuit 120 may include one or more source driver integrated circuits (SDICs). For example, each SDIC may be connected to the display panel 110 via a tape-on-brush (TAB) method, connected to bonding pads of the display panel 110 via a chip-on-glass (COG) method or a chip-on-panel (COP) method, or implemented as a chip-on-film (COF) structure connected to the display panel 110.

[0045] The gate driver circuit 130 can be connected to the display panel 110 via the TAB method, connected to the bonding pads of the display panel 110 via the COG or COP method, connected to the display panel 110 via the COF method, or formed in the non-display area NDA of the display panel 110 via the gate in panel (GIP) method.

[0046] Reference Figure 1 In the display device 100 according to the embodiment, each sub-pixel SP includes a light-emitting device ED and a pixel driver circuit SPC that drives the light-emitting device ED. The pixel driver circuit SPC may include a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0047] The driving transistor DRT drives the light-emitting device ED by controlling the current flowing through it. The scanning transistor SCT transmits the data voltage Vdata to the second node N2 of the driving transistor DRT, i.e., the gate node. The storage capacitor Cst can be configured to maintain the voltage for a predetermined time.

[0048] The light-emitting device (ED) may include an anode (AE), a cathode (CE), and a light-emitting layer (EL) located between the anode (AE) and the cathode (CE). The anode (AE) may be the pixel electrode of the ED that participates in forming each sub-pixel (SP), and may be electrically connected to the first node N1 of the driving transistor (DRT). The cathode (CE) may be the common electrode of the ED that participates in forming each sub-pixel (SP), and a reference voltage (EVSS) may be applied to the cathode (CE).

[0049] For example, a light-emitting device (ED) can be an organic light-emitting diode (OLED), a light-emitting diode based on inorganic materials (LED), or a quantum dot light-emitting device that is a self-emitting semiconductor crystal.

[0050] The driving transistor DRT can be a transistor used to drive a light-emitting device (ED), and may include a first node N1, a second node N2, and a third node N3. The first node N1 can be a source node or a drain node, and can be electrically connected to the anode AE ​​of the ED. The second node N2 can be a gate node, and can be electrically connected to the source node or the drain node of the scanning transistor SCT. The third node N3 can be a drain node or a source node, and can be electrically connected to the driving voltage line DVL, through which the driving voltage EVDD is provided. In the following text, for simplicity, the first node N2 will be described as a source node, and the third node N3 will be described as a drain node.

[0051] The scan transistor SCT can switch the connection between the data line DL and the second node N2 of the drive transistor DRT. The scan transistor SCT can control the connection between the second node N2 of the drive transistor DRT and the corresponding data line DL among multiple data lines DL in response to the scan signal SCAN provided through the scan line SCL (i.e., a type of gate line GL).

[0052] The storage capacitor Cst can be placed between the first node N1 and the second node N2 of the driving transistor DRT.

[0053] Figure 1 The structure of the subpixel SP shown is merely an example for illustration. Conversely, the subpixel structure may additionally include one or more transistors or one or more capacitors. Furthermore, multiple subpixels may all have the same structure, or some of the multiple subpixels may have different structures. Each of the driving transistor DRT and the scanning transistor SCT can be an N-type transistor or a P-type transistor.

[0054] Furthermore, the display device 100 according to the embodiment may have a top-emitting structure or a bottom-emitting structure. Hereinafter, as an example, the display device 100 will be described as having a top-emitting structure. For example, in the case of a top-emitting structure, the anode AE ​​may be formed of reflective metal, while the cathode CE may be formed of a transparent conductive film.

[0055] Figure 2 An example is illustrated of a cathode-anode short circuit in a sub-pixel SP containing impurities in a display device 100 according to an embodiment. (See also...) Figure 2 During or after the panel manufacturing process (e.g., after product shipment), impurities may be present in the region of one of the multiple sub-pixels SP disposed in the display panel 110. When an impurity present in the region of the sub-pixel SP is located on the anode AE ​​of the light-emitting device ED, the anode AE ​​and cathode CE may be electrically short-circuited by the impurity. This phenomenon is referred to as a cathode-anode short circuit (AC Short).

[0056] When a cathode-anode short circuit occurs, the drive current provided by the driving transistor DRT can flow directly from the anode AE, which is electrically connected to the first node N1 of the driving transistor DRT, to the cathode CE. Therefore, the light-emitting device ED in the sub-pixel SP where a cathode-anode short circuit has occurred may not produce light, and thus the corresponding sub-pixel SP will darken. A sub-pixel SP that darkens due to a cathode-anode short circuit with impurities can also be called a bad sub-pixel.

[0057] Figure 3 An aging process for removing a cathode-anode short circuit in a display device 100 according to an embodiment is illustrated.

[0058] Reference Figure 3 During panel manufacturing or post-production product repair, an aging process can be performed to eliminate cathode-anode short circuits. This aging process is a repair method for sub-pixels (SPs). The aging process may include a reverse bias process to apply a reverse bias voltage RBL between the cathode (CE) and the third node N3 of the driving transistor (DRT).

[0059] The reverse biasing process can be performed by a display driver circuit including a data driver circuit 120, a gate driver circuit 130, a controller 140, a power management circuit, etc. During the reverse biasing process, a turn-on voltage must be provided to the second node N2 of the driving transistor DRT to turn it on. Here, the turn-on voltage can be the turn-on data voltage Vdata provided to the second node N2 of the driving transistor DRT through the scan transistor SCT. During the reverse biasing process, the drive voltage EVDD must be converted to a low-level voltage, and the reference voltage EVSS must be converted to a high-level voltage.

[0060] In the reverse biasing process of the aging process, the cathode CE can have a higher voltage than the anode AE. When the reverse biasing process is performed, the aging current can flow from the cathode CE to the third node N3 of the driving transistor DRT. Here, the aging current can flow through the driving transistor DRT.

[0061] During aging treatment, heat may be generated in the portion where a cathode-anode short circuit forms. This generation of heat in the portion with the cathode-anode short circuit during aging treatment is known as Joule heating. The heat generated in the portion with the cathode-anode short circuit can melt the cathode CE and impurities, thereby eliminating the cathode-anode short circuit.

[0062] Figure 4 Examples of the luminescence states of a normal sub-pixel SP, a defective sub-pixel SP in which a cathode-anode short (AC Short) has been formed, a normalized sub-pixel SP from which the cathode-anode short (AC Short) has been eliminated, and a defective sub-pixel SP from which the cathode-anode short (AC Short) has not been eliminated.

[0063] When an impurity in a region of a sub-pixel SP that is in a normal luminous state (S1) forms a cathode-anode short circuit, the entire luminous region of the sub-pixel SP will darken (S2). The darkening state (S2) of the sub-pixel SP can be identified, and an aging process can be performed on the darkened sub-pixel SP.

[0064] When the cathode-anode short circuit is eliminated during the aging process, only the portion from which the cathode-anode short circuit is eliminated is in a non-light-emitting state, and the overall light-emitting state of the sub-pixel SP can be identified as generally normal (S3-1). When the cathode-anode short circuit is not eliminated during the aging process, the entire light-emitting area of ​​the sub-pixel SP remains in a darkened state (S3-2).

[0065] As described above, during aging processes, it is common for cathode-anode short circuits to persist and sub-pixels (SPs) to fail to normalize. Therefore, embodiments of this disclosure propose "Self-Local Anode Repair (SPARP)" as a repair method with a higher probability of normalizing defective sub-pixels containing impurities.

[0066] According to embodiments of this disclosure, SPARP is a repair process that cuts a portion of the anode AE ​​of a sub-pixel SP with impurities, thereby enabling a portion of the sub-pixel SP to emit light using the remaining portion of the anode AE, thereby normalizing the sub-pixel SP.

[0067] In the SPARP process according to the embodiment, the local cutting of the anode AE ​​is a method of self-cutting the anode AE ​​in response to the application of a reverse bias voltage, as in the aging process, rather than cutting the anode AE ​​by irradiating the anode AE ​​with a laser beam or by applying a physical force to the anode AE.

[0068] In the SPARP process according to the embodiment, the anode AE ​​may have a self-cutting enabling structure (also called a trench structure) for SPARP. Furthermore, the insulating layer beneath the anode AE ​​may have trenches, thereby forming a self-cutting enabling structure (also called a trench structure). Here, the insulating layer with trenches may also be referred to as a cover layer.

[0069] When SPARP, according to the embodiment, is a repair method that normalizes a sub-pixel SP with impurities by partially cutting the anode AE ​​of the sub-pixel SP and using half of the anode AE ​​to illuminate half of the sub-pixel SP, SPARP can be called self-half anode repair (SHARP). In the following, for the sake of brevity, the structure for SPARP and SPARP processing will be described in detail assuming that SPARP is SHARP.

[0070] The SPARP process according to the implementation method can be performed during the panel manufacturing process or during product repair processing after the product leaves the factory, or it can be performed after the product leaves the factory when the repair menu function in the user environment settings is executed.

[0071] Figure 5 and Figure 6This is an equivalent circuit for conceptually describing the first sub-pixel SP1 of the SPARP of the display device 100 according to an embodiment. Figure 5 The equivalent circuit of the first sub-pixel SP shown is the equivalent circuit of a normal sub-pixel. Since there are no impurities in it, it does not have a cathode-anode short circuit. Figure 6 The equivalent circuit of the first sub-pixel SP shown is the equivalent circuit of the sub-pixel with a cathode-anode short circuit eliminated by the SPARP process according to the embodiment.

[0072] Reference Figure 5 Each sub-pixel SP in the display device 100 according to the embodiment may include a first light-emitting device ED1, a first driving transistor DRT1, a first scanning transistor SCT1, and a first storage capacitor Cst1. Each sub-pixel SP may also include a first sensing transistor SENT1 that switches the connection between the first node N1 of the driving transistor DRT and the reference voltage line RVL. The first sensing transistor SENT1 may be controlled by a sensing signal SENSE to be turned on or off.

[0073] like Figure 5 As shown, the scan line SCL connected to the gate node of the first scan transistor SCT1 and the sensing line SENL of the first sensing transistor SENT1 can be different gate lines GL. Alternatively, the scan line SCL connected to the gate node of the first scan transistor SCT1 and the sensing line SENL of the first sensing transistor SENT1 can be the same gate line GL.

[0074] Reference Figure 5 For the SPARP according to the embodiment, the first light-emitting device ED1 may include a first light-emitting device portion PED1 and a second light-emitting device portion PED2. The first light-emitting device portion PED1 and the second light-emitting device portion PED2 may be connected in parallel to the first node N1 and the cathode CE of the first driving transistor DRT1.

[0075] Reference Figure 5 The first light-emitting device ED1 may include a first anode AE1, a first light-emitting layer EL1, and a cathode CE. For the SPARP according to the embodiment, the first anode AE1 may include a first electrode portion PAE1, a second electrode portion PAE2, and a first wire (or conductive line) portion CL1.

[0076] The first conductor CL1 can connect to the first electrode portion PAE1 and the second electrode portion PAE2, and is electrically connected to the first node N1 of the first driving transistor DRT1 through the contact hole CNT.

[0077] The first light-emitting device portion PED1 may include a first electrode portion PAE1, a first light-emitting layer EL1, and a cathode CE, while the second light-emitting device portion PED2 may include a second electrode portion PAE2, a first light-emitting layer EL1, and a cathode CE.

[0078] Reference Figure 5 In response to the current drive of the first driving transistor DRT1, a first portion of the driving current Iped1 can flow through the first light-emitting device portion PED1, while a second portion of the driving current Iped2 can flow through the second light-emitting device portion PED2. Therefore, light can be emitted from the entire light-emitting area corresponding to the first light-emitting device ED1.

[0079] When a cathode-anode short circuit is formed by impurities in the region of the first sub-pixel SP1, the SPARP process according to the embodiment can be performed. For example, it is assumed that a short circuit is formed between the first electrode portion PAE1 and the cathode CE due to impurities existing between the first electrode portion PAE1 and the cathode CE in the first electrode portion PAE1 and the second electrode portion PAE2.

[0080] In the SPARP process according to the embodiment, the first conductor portion CL1 may have predetermined cutting points CP1 and CP2.

[0081] The predetermined cutting points CP1 and CP2 in the first conductor portion CL1 may include one or more of a first cutting point CP1 located between the contact hole CNT and the first electrode portion PAE1 and a second cutting point CP2 located between the contact hole CNT and the second electrode portion PAE2. For the sake of brevity, it will be assumed hereinafter that both the first cutting point CP1 (i.e., the point forming the first trench TRC1 described later) and the second cutting point CP2 (i.e., the point forming the second trench TRC2 described later) exist. In the predetermined cutting points CP1 and CP2, the first conductor portion CL1 may have a structure that allows for easy cutting via reverse bias processing (i.e., a self-cutting enabled structure).

[0082] Reference Figure 6 In the SPARP process according to the embodiment, between the first cutting point CP1 and the second cutting point CP2, due to the characteristics of the self-cutting enabling structure, the first conductor portion CL1 can be self-cut by reverse biasing at the first cutting point CP1, which is closer to the impurity site PAE1 to CE (i.e., the position of the cathode-anode short circuit).

[0083] Reference Figure 6In the SPARP process according to the embodiment, in response to the current drive of the first driving transistor DRT1, no current is supplied to the first light-emitting device portion PED1, while the second driving current Iped2 can flow through the second light-emitting device portion PED2. Therefore, light can be emitted from the light-emitting area corresponding to the second light-emitting device portion PED2 within the entire light-emitting area corresponding to the first light-emitting device ED1. That is, light can only be emitted from half of the entire light-emitting area corresponding to the first light-emitting device ED1. However, since light can be emitted from a portion of the first sub-pixel SP, the first sub-pixel SP can be identified as a normal sub-pixel.

[0084] The self-cutting enabled structure of the first anode AE1, which can be easily cut by reverse biasing in the above-described SPARP process according to the embodiment, will be described in more detail below.

[0085] Figures 7 to 9 An example of a self-cutting enabling structure for the first anode AE1 of a SPARP for a display device 100 according to an embodiment is shown, and Figure 10 An example of a first trench TRC1 of a SPARP cover layer OC for a display device 100 according to an embodiment is shown.

[0086] Reference Figures 7 to 10 For the SPARP according to the embodiment, the first anode AE1 may have a self-cutting enabled structure (also known as a trench structure or SPARP structure). Here, as an example, the first anode AE1 may be included in the first sub-pixel SP and may be the pixel electrode of the first light-emitting device ED1 in the first sub-pixel SP.

[0087] The first sub-pixel SP may include a first driving transistor DRT1 disposed on or above the substrate SUB. The cover layer OC is an insulating layer that may be disposed on or above the first driving transistor DRT1.

[0088] The first anode AE1 can be disposed on or above the first driving transistor DRT1, and can be electrically connected to the first node N1 of the first driving transistor DRT1 through the contact hole CNT in the cover layer OC. The first light-emitting layer EL1 can be disposed on the first anode AE1. The cathode CE can be disposed on the first light-emitting layer EL1.

[0089] Reference Figures 7 to 10The first anode AE1 may include a first electrode portion PAE1, a second electrode portion PAE2, and a first conductive portion CL1. The first electrode portion PAE1 may be disposed in a first region A1 of the first sub-pixel SP. The second electrode portion PAE2 may be disposed in a second region A2 of the first sub-pixel SP, which is different from the first region A1. The first conductive portion CL1 may connect the first electrode portion PAE1 and the second electrode portion PAE2.

[0090] The first light-emitting layer EL1 can be disposed on all of the first electrode portion PAE1, the second electrode portion PAE2, and the first conductive portion CL1, or it can be disposed only on the first electrode portion PAE1 and the second electrode portion PAE2.

[0091] In the first light-emitting layer EL1, the portion located on the first electrode portion PAE1 and the portion located on the second electrode portion PAE2 can be integrated. Alternatively, the first light-emitting layer EL1 can be divided into a portion located on the first electrode portion PAE1 and a portion located on the second electrode portion PAE2.

[0092] Reference Figure 7 and Figure 8 The cover layer OC may include a first trench TRC1 in the area where the cover layer OC overlaps with the first conductor portion CL1. Here, the position of the first trench TRC1 may match the position of the first cutting point CP1 in the predetermined cutting point CP1 and CP2 in the first conductor portion CL1.

[0093] The first conductor portion CL1 may include a first bent portion BL1 disposed on or above the cover layer OC, and the first bent portion BL1 bends along the first inner surface SIDE1a, the bottom surface BOT1 and the second inner surface SIDE1b of the first groove TRC1.

[0094] The first conductor portion CL1 can pass through the contact hole CNT in the cover layer OC (see...). Figure 24 It is electrically connected to the first node N1 of the first driving transistor DRT1.

[0095] Reference Figure 7 and Figure 9 The cover layer OC may also include a second trench TRC2 in the area where the cover layer OC overlaps with the first conductor portion CL1. Here, the position of the second trench TRC2 may match the position of the second cutting point CP2 in the predetermined cutting point CP1 and CP2 in the first conductor portion CL1.

[0096] The first conductor portion CL1 may also include a second bending portion BL2, which is disposed on or above the cover layer OC and bends along the first inner surface SIDE2a, the bottom surface BOT2 and the second inner surface SIDE2b of the second groove TRC2.

[0097] The first trench TRC1 can be located between the contact hole CNT and the first electrode portion PAE1, while the second trench TRC2 can be located between the contact hole CNT and the second electrode portion PAE2.

[0098] The first trench TRC1 can have a structure such that when a cathode-anode short circuit is formed by impurities present between the first electrode portion PAE1 and the cathode CE, the first bent portion BL1 of the first conductor portion CL1 can self-cut through this structure. The second trench TRC2 can have a structure such that when a cathode-anode short circuit is formed by impurities present between the second electrode portion PAE2 and the cathode CE, the second bent portion BL2 of the first conductor portion CL1 can self-cut through this structure.

[0099] Reference Figure 7 and Figure 10 The first trench TRC1 of the cover layer OC can be formed in a direction that intersects the longitudinal direction of the first conductor portion CL1. Similarly, the second trench TRC2 of the cover layer OC can extend in a direction that intersects the longitudinal direction of the first conductor portion CL1.

[0100] Reference Figure 7 and Figure 8 The first organic material OM1 can be disposed inside and around the first trench TRC1. The first conductive part CL1 can be disposed on the first organic material OM1.

[0101] The first organic material OM1 may include a first side organic material OM1s located on the first inner surface SIDE1a and the second inner surface SIDE1b of the first trench TRC1. The first side organic material OM1s may extend to the outer surfaces TOP1a and TOP1b of the first trench TRC1. That is, the first side organic material OM1s may extend to the outer surfaces TOP1a and TOP1b of the first trench TRC1 to be disposed on the outer surfaces TOP1a and TOP1b of the first trench TRC1. The first organic material OM1 may also include a first bottom organic material OM1b located on the bottom surface BOT1 of the first trench TRC1.

[0102] Reference Figure 7 and Figure 8The first cutting point CP1 can be a point between the first side organic material OM1s and the first bottom organic material OM1b. In the SPARP process according to the embodiment, when the reverse bias process is performed, the first lead portion CL1 of the first anode AE1 can be easily broken (e.g., damaged) at the first cutting point CP1 between the first side organic material OM1s and the first bottom organic material OM1b.

[0103] As described above, since the first side organic material OM1s and the first bottom organic material OM1b are disposed on the bottom surface BOT1 and the inner surfaces SIDE1a and SIDE1b of the first trench TRC1 formed in the cover layer OC, and the first side organic material OM1s and the first bottom organic material OM1b are curved, the first conductor portion CL1 of the first anode AE1 can be configured to be easily broken at the first cutting point CP1 between the first side organic material OM1s and the first bottom organic material OM1b when the reverse biasing process is performed in the SPARP process according to the embodiment.

[0104] Reference Figure 7 and Figure 9 The second organic material OM2 can be disposed inside and surrounding the second trench TRC2. The first conductor portion CL1 can be disposed on the second organic material OM2. The second organic material OM2 can include second side organic materials OM2s located on the first inner surface SIDE2a and the second inner surface SIDE2b of the second trench TRC2. The second side organic materials OM2s can be configured to extend to the outer surfaces TOP2a and TOP2b of the second trench TRC2. That is, the second side organic materials OM2s can extend to the outer surfaces TOP2a and TOP2b of the second trench TRC2 and be disposed on the outer surfaces TOP2a and TOP2b of the second trench TRC2. The second organic material OM2 can also include a second bottom organic material OM2b located on the bottom surface BOT2 of the second trench TRC2.

[0105] Reference Figure 7 and Figure 9 The second cutting point CP2 can be a point between the second side organic material OM2s and the second bottom organic material OM2b. In the SPARP process according to the embodiment, when the reverse bias process is performed, the first lead portion CL1 of the first anode AE1 can be easily broken at the second cutting point CP2 between the second side organic material OM2s and the second bottom organic material OM2b.

[0106] As described above, since the second side organic material OM2s and the second bottom organic material OM2b are disposed on the inner surfaces SIDE2a and SIDE2b and the bottom surface BOT2 of the second trench TRC2 formed in the cover layer OC, and the second side organic material OM2s and the second bottom organic material OM2b are curved, the first lead portion CL1 of the first anode AE1 can be configured to be easily broken at the second cutting point CP2 between the second side organic material OM2s and the second bottom organic material OM2b when the reverse biasing process is performed in the SPARP process according to the embodiment.

[0107] The state of the first anode AE1 can vary depending on the presence or absence of the SPARP process according to the embodiment or the type of the first sub-pixel SP (e.g., a normal sub-pixel without impurities or a sub-pixel normalized by the SPARP process).

[0108] When the first sub-pixel SP is a normal sub-pixel, that is, when the first sub-pixel SP is a sub-pixel for which SPARP processing has not been performed, the first electrode portion PAE1, the second electrode portion PAE2, and the first conductor portion CL1 can all be considered to be electrically connected.

[0109] When the first sub-pixel SP is a sub-pixel normalized from a defective sub-pixel with a cathode-anode short circuit caused by impurities, that is, when the first sub-pixel SP is a sub-pixel normalized from a defective sub-pixel through SPARP processing, it can be considered that only one of the first electrode portion PAE1 and the second electrode portion PAE2 is electrically connected to the first conductor portion CL1.

[0110] In the SPARP process according to the embodiment, the ease with which the first conductor portion CL1 of the first anode AE1 with a cathode-anode short circuit is disconnected can vary depending on the trench structure of the cover layer OC (e.g., width Wt, depth Dt, or inner surface inclination angle θt) or the width WL of the first conductor portion CL1.

[0111] Reference Figure 8 and Figure 10 The first trench TRC1 of the capping layer OC is a groove and is the path through which the first conductor portion CL1 of the first anode AE1 extends. The first conductor portion CL1 of the first anode AE1 necessarily extends through the first trench TRC1 of the capping layer OC. The first conductor portion CL1 of the first anode AE1 can be provided along the first inner surface SIDE1a, the bottom surface BOT1, and the second inner surface SIDE1b of the first trench TRC1.

[0112] Reference Figure 8 and Figure 10The depth Dt of the first trench TRC1 can be the height from the outer surfaces TOP1a and TOP1b of the first trench TRC1 to the bottom surface BOT1 of the first trench TRC1. The width Wt of the first trench TRC1 can be the distance between the first inner surface SIDE1a and the second inner surface SIDE1b. The width Wt of the first trench TRC1 can be determined based on the bottom surface BOT1. The inclination angle θt of the inner surface of the first trench TRC1 can be the angle between the first inner surface SIDE1a or the second inner surface SIDE1b and the bottom surface BOT1.

[0113] Reference Figures 7 to 10 The first trench TRC1 and the second trench TRC2 through which the first conductor portion CL1 extends can have the same structure (e.g., the same width Wt, depth Dt, or inner surface inclination angle θt).

[0114] Reference Figures 7 to 10 The first conductive portion CL1 of the first anode AE1 may have a predetermined width WL. The width WL of the first conductive portion CL1 may correspond to the length Lt of the first trench TRC1. The length Lt of the first trench TRC1 may be equal to, greater than, or less than the width WL of the first conductive portion CL1.

[0115] Figure 11 An example is shown of the inclined structure of the inner surface of the first trench TRC1 of the SPARP cover layer OC for a display device 100 according to an embodiment.

[0116] The inclination angle θt of the inner surface of the first trench TRC1 is the angle between the inner surface SIDE1 of the first trench TRC1 and the bottom surface BOT1 of the first trench TRC1. Here, the inner surface SIDE1 of the first trench TRC1 can be either the first inner surface SIDE1a or the second inner surface SIDE1b.

[0117] In Case 1, the inclination angle θt of the inner surface of the first groove TRC1 can be greater than 90° and less than 180°. In Case 2, the inclination angle θt of the inner surface of the first groove TRC1 can be 90° (vertical). In Case 3, the inclination angle θt of the inner surface of the first groove TRC1 can be greater than 0° and less than 90°. The inclined inner surface structure in Case 1 can be called a conical structure, while the inclined inner surface structure in Case 3 can be called an inverted conical structure.

[0118] The self-cutting enabling structure of the first anode AE1 refers to a structure through which the first conductor portion CL1 of the first anode AE1 can be easily disconnected within the first trench TRC1.

[0119] As the self-cutting enabling structure for the first anode AE1, the inverted conical structure in case 3 is probably the most suitable, while the vertical structure in case 2 is probably the second most suitable. Therefore, for the self-cutting enabling structure of the first anode AE1, the angle between the first inner surface SIDE1a or the second inner surface SIDE1b of the first trench TRC1 and the bottom surface BOT1 of the first trench TRC1 can be equal to or less than 90° (cases 2 and 3).

[0120] Figure 12 An example of an organic material deposition structure in the first trench TRC1 of the SPARP cover layer OC for a display device 100 according to an embodiment is shown.

[0121] For the self-cutting enabled structure of the first anode AE1, the first organic material OM1 can be deposited inside and around the first trench TRC1.

[0122] The first organic material OM1 may include a first side organic material OM1s located on the first inner surface SIDE1a and the second inner surface SIDE1b of the first trench TRC1, and a first bottom organic material OM1b located on the bottom surface BOT1 of the first trench TRC1. The first side organic material OM1s may extend to the outer surfaces TOP1a and TOP1b of the first trench TRC1 to be disposed on the outer surfaces TOP1a and TOP1b of the first trench TRC1.

[0123] In case 4, the first side organic material OM1s and the first bottom organic material OM1b can be separated from each other. Alternatively, the first side organic material OM1s and the first bottom organic material OM1b can be connected to each other.

[0124] Figure 13 An example is illustrated of a first anode AE1 that is self-cut by performing SPARP processing on the first sub-pixel SP in the display device 100 according to an embodiment.

[0125] In the region of the first sub-pixel SP, where a cathode-anode short circuit is formed by impurities existing between the first electrode portion PAE1 of the first anode AE1 and the cathode CE, a reverse biasing process can be performed when the SPARP process according to the embodiment is performed on the first sub-pixel SP (see...). Figure 3 ).

[0126] When reverse biasing is performed, the first conductor portion CL1 can self-cut within the first trench TRC1 due to the characteristics of the self-cutting enabled structure (i.e., the trench structure). In particular, the first conductor portion CL1 can self-cut within the first trench TRC1, which is closer to the location where the cathode-anode short circuit is formed, in the first trench TRC1 and the second trench TRC2.

[0127] Here, the two predetermined cutting points CP1 and CP2 in the first conductor portion CL1 may include a first cutting point CP1 between the contact hole CNT and the first electrode portion PAE1, and a second cutting point CP2 between the contact hole CNT and the second electrode portion PAE2. The first cutting point CP1 may be located at the position where the first trench TRC1 is formed, and the second cutting point CP2 may be located at the position where the second trench TRC2 is formed.

[0128] Figure 14 The illustration shows the change in the luminous state of the first sub-pixel SP before and after SPARP processing for the first sub-pixel SP.

[0129] The state of the first anode AE1 can vary depending on the presence or absence of the SPARP process according to the embodiment or the type of the first sub-pixel SP (e.g., a normal sub-pixel without impurities or a sub-pixel normalized by the SPARP process).

[0130] When the first sub-pixel SP is a normal sub-pixel, that is, when the first sub-pixel SP is a sub-pixel for which SPARP processing has not been performed, the first electrode portion PAE1, the second electrode portion PAE2, and the first conductor portion CL1 can all be considered to be electrically connected.

[0131] Therefore, the driving current provided by the first driving transistor DRT1 can be supplied to the first electrode portion PAE1 and the second electrode portion PAE2 through the first conductor portion CL1. Thus, both the first region A1, where the first electrode portion PAE1 is located, and the second region A2, where the second electrode portion PAE2 is located, can generate light, and the first sub-pixel SP can be identified as normally generating light.

[0132] When a cathode-anode short circuit is formed by impurities present between the first electrode portion PAE1 of the first anode AE1 and the cathode CE, neither the first region A1, where the first electrode portion PAE1 is located, nor the second region A2, where the second electrode portion PAE2 is located, can generate light. Therefore, the first sub-pixel SP will be identified as a dark spot.

[0133] When the SPARP process according to the embodiment is performed, the first bend BL1 of the first conductor portion CL1 can be in an open state. That is, the first bend BL1 of the first conductor portion CL1 can self-cut within the first groove TRC1.

[0134] Therefore, the first electrode portion PAE1 in the first electrode portion PAE1 and the second electrode portion PAE2 is not electrically connected to the first driving transistor DRT1 through the first wire portion CL1.

[0135] Therefore, the drive current provided by the first driving transistor DRT1 can be supplied only to the second electrode portion PAE2 through the first conductor portion CL1. As a result, in the first region A1 where the first electrode portion PAE1 is provided and the second region A2 where the second electrode portion PAE2 is provided, the first region A1 does not generate light, while only the second region A2 can generate light. As described above, when the second region A2 (a part of the entire light-emitting area of ​​the first sub-pixel SP) generates light, the first sub-pixel SP can be identified as normally emitting light.

[0136] Figure 15 Examples of first driving transistor DRT1 in first sub-pixel SP1 and second driving transistor DRT2 in second sub-pixel SP2 in the display device 100 according to an embodiment are shown, and Figure 16 Examples of first anode AE1 in first sub-pixel SP1 and second anode AE2 in second sub-pixel SP2 are shown in the display device 100 according to the embodiment.

[0137] Reference Figure 15 The plurality of sub-pixels SP disposed in the display panel 110 may include a first sub-pixel SP and a second sub-pixel SP2. Each of the first sub-pixel SP and the second sub-pixel SP2 may have Figure 1 The sub-pixel structure shown or Figure 5 The sub-pixel structure is shown. In short, the first sub-pixel SP may include a first driving transistor DRT1 and a first light-emitting device ED1 disposed on or above the substrate SUB. The second sub-pixel SP2 may include a second driving transistor DRT2 and a second light-emitting device ED2 disposed on or above the substrate SUB.

[0138] The first light-emitting device ED1 may include a first anode AE1, a first light-emitting layer EL1, and a cathode CE. The second light-emitting device ED2 may include a second anode AE2, a second light-emitting layer EL2, and a cathode CE.

[0139] The first anode AE1 may be disposed on or above the first driving transistor DRT1 and included in the first sub-pixel SP. The first light-emitting layer EL1 may be disposed on the first anode AE1.

[0140] The second anode AE2 can be disposed on or above the second driving transistor DRT2 and included in the second sub-pixel SP2. The second light-emitting layer EL2 can be disposed on the second anode AE2. The cathode CE can be disposed on the first light-emitting layer EL1 and the second light-emitting layer EL2.

[0141] The buffer layer BUF can be disposed on or above the substrate SUB, and the first driving transistor DRT1 and the second driving transistor DRT2 can be disposed on or above the buffer layer BUF. The first light-shielding layer LS1 can be disposed below the first driving transistor DRT1, and the second light-shielding layer LS2 can be disposed below the second driving transistor DRT2.

[0142] The first driving transistor DRT1 may include a first active layer ACT1, a first source S1, a first drain D1, and a first gate G1. The first active layer ACT1 may be disposed on or above the buffer layer BUF, and may include a first channel region CH1, a first source conductive region SC1, and a first drain conductive region DC1. A gate insulating film GI may be disposed on the first active layer ACT1, and the first gate G1 may be disposed on the gate insulating film GI. An interlayer insulating film ILD may be disposed on the first active layer ACT1 and the first gate G1. The first source S1 and the first drain D1 may be disposed on the interlayer insulating film ILD, and may be electrically connected to the first source conductive region SC1 and the first drain conductive region DC1 respectively through holes in the interlayer insulating film ILD.

[0143] The second driving transistor DRT2 may include a second active layer ACT2, a second source S2, a second drain D2, and a second gate G2. The second active layer ACT2 may be disposed on or above the buffer layer BUF, and may include a second channel region CH2, a second source conductive region SC2, and a second drain conductive region DC2. A gate insulating film GI may be disposed on the second active layer ACT2, and the second gate G2 may be disposed on the gate insulating film GI. An interlayer insulating film ILD may be disposed on the second active layer ACT2 and the second gate G2. The second source S2 and the second drain D2 may be disposed on the interlayer insulating film ILD, and may be electrically connected to the second source conductive region SC2 and the second drain conductive region DC2 through contact holes in the interlayer insulating film ILD.

[0144] The channel size of the first driving transistor DRT1 can be obtained by dividing the width W1 of the first channel region CH1 by the length L1 of the first channel region CH1, which is the value W1 / L1. The channel size of the second driving transistor DRT2 can be obtained by dividing the width W2 of the second channel region CH2 by the length L2 of the second channel region CH2, which is the value W2 / L2.

[0145] For example, the channel size W1 / L1 of the first driving transistor DRT1 can be the same as the channel size W2 / L2 of the second driving transistor DRT2. As another example, the channel size W1 / L1 of the first driving transistor DRT1 can be different from the channel size W2 / L2 of the second driving transistor DRT2.

[0146] Reference Figure 16The first anode AE1 may include a first electrode portion PAE1 disposed in a first region A1 of the first sub-pixel SP1, a second electrode portion PAE2 disposed in a second region A2 of the first sub-pixel SP1 that is different from the first region A1, and a first wire portion CL1 connecting the first electrode portion PAE1 and the second electrode portion PAE2.

[0147] The first conductor CL1 can be electrically connected to the first node N1 of the first driving transistor DRT1 through the contact hole CNT.

[0148] The capping layer OC may include a first trench TRC1 in the region overlapping with the first conductor portion CL1. The capping layer OC may also include a second trench TRC2 in the region overlapping with the first conductor portion CL1. A first organic material OM1 may be disposed inside and around the first trench TRC1. A second organic material OM2 may be disposed inside and around the second trench TRC2.

[0149] The second anode AE2 may include a third electrode portion PAE3 disposed in a third region A3 of the second sub-pixel SP2, a fourth electrode portion PAE4 disposed in a fourth region A4 of the second sub-pixel SP2 that is different from the third region A3, and a second conductive portion CL2 connecting the third electrode portion PAE3 and the fourth electrode portion PAE4.

[0150] The second conductor CL2 can be electrically connected to the first node N1 of the second driving transistor DRT2 through the contact hole CNT.

[0151] The capping layer OC may include a third trench TRC3 in the region overlapping with the second conductor portion CL2. The capping layer OC may also include a fourth trench TRC4 in the region overlapping with the second conductor portion CL2. A third organic material OM3 may be disposed inside and around the third trench TRC3. A fourth organic material OM4 may be disposed inside and around the fourth trench TRC4.

[0152] In the region of the first sub-pixel SP1, the overlay layer OC may include a first trench TRC1 and a second trench TRC2. In the region of the second sub-pixel SP2, the overlay layer OC may include a third trench TRC3 and a fourth trench TRC4.

[0153] When the channel size W1 / L1 of the first driving transistor DRT1 of the first sub-pixel SP1 is the same as or similar to the channel size W2 / L2 of the second driving transistor DRT2 of the second sub-pixel SP2, the current driving capability of the first driving transistor DRT1 can be the same as or similar to the current driving capability of the second driving transistor DRT2. In this case, the trench structure and anode structure in the region of the first sub-pixel SP1 can be the same as or similar to the trench structure and anode structure in the region of the second sub-pixel SP2.

[0154] When the channel size W1 / L1 of the first driving transistor DRT1 of the first sub-pixel SP1 is different from the channel size W2 / L2 of the second driving transistor DRT2 of the second sub-pixel SP2, the current driving capability of the first driving transistor DRT1 may differ from that of the second driving transistor DRT2. In this case, the trench structure and anode structure in the region of the first sub-pixel SP1 may differ from those in the region of the second sub-pixel SP2.

[0155] Hereinafter, for example, we will describe the trench structure and anode structure in the region of the first sub-pixel SP1 and the trench structure and anode structure in the region of the second sub-pixel SP2 when the channel size W1 / L1 of the first driving transistor DRT1 of the first sub-pixel SP1 is smaller than the channel size W2 / L2 of the second driving transistor DRT2 of the second sub-pixel SP2.

[0156] The first trench TRC1 and the second trench TRC2 can have the same structure, and the third trench TRC3 and the fourth trench TRC4 can have the same structure. Therefore, the first trench TRC1 will be used to describe the trench structure and anode structure of the capping layer OC in the region of the first sub-pixel SP1, and the third trench TRC3 will be used to describe the trench structure and anode structure of the capping layer OC in the region of the second sub-pixel SP2.

[0157] Reference Figure 15 and Figure 16 When the first sub-pixel SP1 is a sub-pixel to which SPARP processing has been performed and the second sub-pixel SP2 is a sub-pixel to which SPARP processing has not been performed, the first conductor portion CL1 can be disconnected inside the first trench TRC1 of the cover layer OC, and the second conductor portion CL2 can remain connected inside the third trench TRC3 of the cover layer OC.

[0158] Figures 17 to 19 Examples of trench structures in the first sub-pixel SP1 and the second sub-pixel SP2 in the display device 100 according to an embodiment are shown.

[0159] Reference Figure 17 and Figure 18 The first conductor portion CL1 of the first anode AE1 may be disposed on or above the capping layer OC, and may include a first bent portion BL1 that bends along the first inner surface SIDE1a, the bottom surface BOT1, and the second inner surface SIDE1b of the first trench TRC1. The second conductor portion CL2 of the second anode AE2 may include a third bent portion BL3 disposed on or above the capping layer OC, and the third bent portion BL3 bends along the first inner surface SIDE1a, the bottom surface BOT1, and the second inner surface SIDE1b of the third trench TRC3.

[0160] Reference Figures 17 to 19 The channel size W1 / L1 of the first driving transistor DRT1 in the first sub-pixel SP1 can be smaller than the channel size W2 / L2 of the second driving transistor DRT2 in the second sub-pixel SP2. Therefore, the second driving transistor DRT2 can have a greater current driving capability than the first driving transistor DRT1, and drive a larger current through the second anode AE2. Conversely, the first driving transistor DRT1 can have a smaller current driving capability than the second driving transistor DRT2, and drive a smaller current through the first anode AE1.

[0161] Reference Figure 17 Since the channel size W1 / L1 of the first driving transistor DRT1 is smaller than the channel size W2 / L2 of the second driving transistor DRT2, the width Wt1 of the first trench TRC1 can be narrower than the width Wt2 of the third trench TRC3.

[0162] Because the channel size W1 / L1 of the first driving transistor DRT1 is relatively small, the amount of normal driving current flowing through the first driving transistor DRT1 may be relatively small. Therefore, the width Wt1 of the first trench TRC1 can be designed to be relatively narrow, so that the first trench TRC1 can be easily disconnected by the small aging current caused by the reverse bias process in the SHARP process.

[0163] Reference Figure 18 Since the channel size W1 / L1 of the first driving transistor DRT1 is smaller than the channel size W2 / L2 of the second driving transistor DRT2, the depth Dt1 of the first trench TRC1 can be deeper than the depth Dt2 of the third trench TRC3.

[0164] Because the channel size W1 / L1 of the first driving transistor DRT1 is relatively small, the amount of normal drive current flowing through the first driving transistor DRT1 may be relatively small. Therefore, the depth Dt1 of the first trench TRC1 can be designed to be relatively deep so that the first trench TRC1 can be easily disconnected by the small aging current caused by the reverse bias process in the SHARP process.

[0165] Reference Figure 19 Since the channel size W1 / L1 of the first driving transistor DRT1 is smaller than the channel size W2 / L2 of the second driving transistor DRT2, the width WL1 of the first conductor portion CL1 can be narrower than the width WL2 of the second conductor portion CL2.

[0166] Because the channel size W1 / L1 of the first driving transistor DRT1 is relatively small, the amount of normal driving current flowing through the first driving transistor DRT1 may be relatively small. Therefore, the width Wt1 of the first conductor portion CL1 can be designed to be relatively narrow so that the first conductor portion CL1 can be easily disconnected by the small aging current caused by the reverse bias process in the SHARP process.

[0167] Figures 20 to 22 Examples are given regarding the relationship between the connecting wire structure of the first sub-pixel SP1 and the connecting wire structure of the second sub-pixel SP2, as well as the relationship between the trench structure of the first sub-pixel SP1 and the trench structure of the second sub-pixel SP2.

[0168] Reference Figure 20 When the width Wt1 of the first trench TRC1 is narrower than the width Wt2 of the third trench TRC3 or the depth Dt1 of the first trench TRC1 is deeper than the depth Dt2 of the third trench TRC3, the width WL1 of the first conductor portion CL1 of the first anode AE1 can be wider than the width WL2 of the second conductor portion CL2 of the second anode AE2.

[0169] Reference Figure 20 When the width Wt2 of the third trench TRC3 is wider than the width Wt1 of the first trench TRC1 or the depth Dt2 of the third trench TRC3 is shallower than the depth Dt1 of the first trench TRC1, the width WL2 of the second conductor portion CL2 of the second anode AE2 can be narrower than the width WL1 of the first conductor portion CL1 of the first anode AE1.

[0170] Reference Figure 20In this structure, the width Wt1 of the first trench TRC1 can be narrower than the width Wt2 of the third trench TRC3, or the depth Dt1 of the first trench TRC1 can be deeper than the depth Dt2 of the third trench TRC3. Therefore, the amount of drive current flowing through the first conductor portion CL1 of the first anode AE1 may decrease. However, since the width WL1 of the first conductor portion CL1 of the first anode AE1 is designed to be wider than the width WL2 of the second conductor portion CL2 of the second anode AE2, the amount of drive current flowing through the first conductor portion CL1 of the first anode AE1 can increase, thereby compensating for the decrease in drive current.

[0171] Reference Figure 21 The channel size W1 / L1 of the first driving transistor DRT1 can be different from the channel size W2 / L2 of the second driving transistor DRT2. Even in this case, the width WL1 of the first conductor portion CL1 can be the same as the width WL2 of the second conductor portion CL2.

[0172] However, the width Wt1 of the first trench TRC1 can be different from the width Wt2 of the third trench TRC3, or the depth Dt1 of the first trench TRC1 can be different from the depth Dt2 of the third trench TRC3. For example, the width Wt1 of the first trench TRC1 can be narrower than the width Wt2 of the third trench TRC3, or the depth Dt1 of the first trench TRC1 can be deeper than the depth Dt2 of the third trench TRC3.

[0173] according to Figure 21 Even when the width WL1 of the first conductor portion CL1 and the width WL2 of the second conductor portion CL2 are the same, the structure allows the first conductor portion CL1 to be easily disconnected within the first trench TRC1 by setting the width Wt1 of the first trench TRC1 to be narrower than the width Wt2 of the third trench TRC3 or setting the depth Dt1 of the first trench TRC1 to be deeper than the depth Dt2 of the third trench TRC3.

[0174] Reference Figure 22 The channel size W1 / L1 of the first driving transistor DRT1 can be different from the channel size W2 / L2 of the second driving transistor DRT2. In this case, the width WL1 of the first conductive portion CL1 can be different from the width WL2 of the second conductive portion CL2. For example, the width WL1 of the first conductive portion CL1 can be narrower than the width WL2 of the second conductive portion CL2.

[0175] However, the width Wt1 of the first trench TRC1 can be the same as the width Wt2 of the third trench TRC3, or the depth Dt1 of the first trench TRC1 can be the same as the depth Dt2 of the third trench TRC3.

[0176] according to Figure 22 Even when the width Wt1 of the first trench TRC1 is the same as the width Wt2 of the third trench TRC3, or the depth Dt1 of the first trench TRC1 is the same as the depth Dt2 of the third trench TRC3, the first conductor CL1 can be easily disconnected in the first trench TRC1 by designing the width WL1 of the first conductor portion CL1 to be narrower than the width WL2 of the second conductor portion CL2.

[0177] Figure 23 This is a plan view showing the area where four sub-pixels SP1, SP2, SP3, and SP4 are provided when the display device 100 according to the embodiment is a transparent display, and Figure 24 This is an example Figure 23 A cross-sectional view of region AA′, in which the location is Figure 23 The self-cutting enabling structure (i.e., trench structure) of the first anode AE1 in the middle.

[0178] Reference Figure 23 The display device 100 according to the embodiment can be a transparent display. The display device 100 according to the embodiment can include a transmissive region TA and a non-transmissive region. The non-transmissive region can be a region where sub-pixels SP1, SP2, SP3, and SP4 are disposed, a light-emitting region of sub-pixels SP1, SP2, SP3, and SP4, or a region where pixel driver circuits SPC are disposed of for sub-pixels SP1, SP2, SP3, and SP4. The transmittance of the transmissive region can be equal to or higher than a predetermined threshold transmittance.

[0179] Reference Figure 23 For example, four sub-pixels SP1, SP2, SP3 and SP4 can be set in two columns, and the transmission area TA can be set on both sides of the four sub-pixels SP1, SP2, SP3 and SP4.

[0180] Reference Figure 23 Each of the four sub-pixels SP1, SP2, SP3 and SP4 can have the same self-cutting enable structure as described above.

[0181] The first anode AE1 of the first sub-pixel SP1 may include a first electrode portion PAE1, a second electrode portion PAE2, and a first conductive portion CL1. The second anode AE2 of the second sub-pixel SP2 may include a third electrode portion PAE3, a fourth electrode portion PAE4, and a second conductive portion CL2. The third anode AE3 of the third sub-pixel SP3 may include a fifth electrode portion PAE5, a sixth electrode portion PAE6, and a third conductive portion CL3. The fourth anode AE4 of the fourth sub-pixel SP4 may include a seventh electrode portion PAE7, an eighth electrode portion PAE8, and a fourth conductive portion CL4.

[0182] The transmissive region TA can be located on one side of the first sub-pixel SP1, and the first conductive portion CL1 can be configured to enter the transmissive region TA. The first conductive portion CL1 can extend across at least one trench TRC of the capping layer OC. Organic material OM can be disposed inside or around at least one trench TRC, and the first conductive portion CL1 can be disposed on the organic material OM. The first conductive portion CL1 can be connected to the driving transistor DRT of the first sub-pixel SP1 through the contact hole CNT.

[0183] The transmissive region TA can be located on one side of the second sub-pixel SP2, and the second conductive portion CL2 can be configured to enter the transmissive region TA. The second conductive portion CL2 can extend across at least one trench TRC of the capping layer OC. Organic material OM can be disposed inside or around at least one trench TRC, and the second conductive portion CL2 can be disposed on the organic material OM. The second conductive portion CL2 can be connected to the driving transistor DRT of the second sub-pixel SP2 through the contact hole CNT.

[0184] The transmissive region TA can be located on one side of the third sub-pixel SP3, and the third conductive portion CL3 can be configured to enter the transmissive region TA. The third conductive portion CL3 can extend across at least one trench TRC of the capping layer OC. The organic material OM can be disposed inside or around at least one trench TRC, and the third conductive portion CL3 can be disposed on the organic material OM. The third conductive portion CL3 can be connected to the driving transistor DRT of the third sub-pixel SP3 through the contact hole CNT.

[0185] The transmissive region TA can be located on one side of the fourth sub-pixel SP4, and the fourth conductive portion CL4 can be configured to enter the transmissive region TA. The fourth conductive portion CL4 can extend across at least one trench TRC of the capping layer OC. Organic material OM can be disposed inside or around at least one trench TRC, and the fourth conductive portion CL4 can be disposed on the organic material OM. The fourth conductive portion CL4 can be connected to the driving transistor DRT of the fourth sub-pixel SP4 through the contact hole CNT.

[0186] Reference Figure 24 The AA′ region can be a part of the region in which the first conductive portion CL1 of the first anode AE1, which is included in the first sub-pixel SP1, is disposed. The AA′ region can be the region where the self-cutting enabling structure (i.e., the trench structure) of the first anode AE1 is located.

[0187] Reference Figure 24A passivation film PAS can be applied to cover the first drain D1 and first source S1 of the first driving transistor DRT1 in the first sub-pixel SP1. The cross-sectional structure from the substrate SUB to the first driving transistor DRT1 is as described above. Figure 15 The described cross-sectional structures are the same.

[0188] Reference Figures 23 to 24 The capping layer OC can be disposed on or above the passivation film PAS. The capping layer OC may include a first trench TRC1 formed at a position corresponding to the first cut point CP1 and a second trench TRC2 formed at a position corresponding to the second cut point CP2. The second organic material OM2 may be disposed inside and outside the second trench TRC2.

[0189] The first anode AE1 may include a first electrode portion PAE1, a second electrode portion PAE2, and a first lead portion CL1. The first lead portion CL1 of the first anode AE1 may include a first connection portion connected to the first electrode portion PAE1, a second connection portion connected to the second electrode portion PAE2, and a connection portion between the first connection portion and the second connection portion. The connection portion of the first lead portion CL1 may be via a first trench TRC1 and a second trench TRC2.

[0190] The portion of the connecting part of the first conductor CL1 that passes through the second trench TRC2 can be provided along the inner and bottom surfaces of the second trench TRC2. Furthermore, the portion of the connecting part of the first conductor CL1 that passes through the second trench TRC2 can be provided on a second organic material OM2 disposed on the inner and outer sides of the trench TRC2.

[0191] The connection portion of the first conductor CL1 can be electrically connected to the first node N1 corresponding to the first source S1 of the first driving transistor DRT1 through the contact hole CNT in the cover layer OC.

[0192] A dam BK can be disposed on the first anode AE1. The dam BK can have an opening region corresponding to the light-emitting area of ​​the first sub-pixel SP1. Here, the light-emitting area of ​​the first sub-pixel SP1 can match the position of the first electrode portion PAE1 and the position of the second electrode portion PAE2. The position of the opening region in the dam BK can match the position of the first electrode portion PAE1 and the second electrode portion PAE2 of the first anode AE1.

[0193] The first light-emitting layer EL1 can be disposed on the dam BK. In each opening region of the dam BK, the first light-emitting layer EL1 can be disposed on the first electrode portion PAE1 and the second electrode portion PAE2. The cathode CE can be disposed on the first light-emitting layer EL1, the sealing layer ENCAP can be disposed on or above the cathode CE, the black matrix BM and the color filter CF can be disposed on a portion of the sealing layer ENCAP, and the top substrate TOP SUB can be disposed on or above the black matrix BM, the color filter CF, and the remaining portion of the sealing layer ENCAP not covered by the black matrix BM or the color filter CF.

[0194] The insulating layers BUF, ILD, and PAS can be disposed in the transmission region TA, but the metal layer cannot be disposed in the transmission region TA. Here, since the cathode CE is a transparent cathode formed from a transparent conductive film, the cathode CE can be disposed in the transmission region TA. The light-emitting layer EL can be disposed in the transmission region TA.

[0195] The above description is intended to enable any person skilled in the art to make and use the technical ideas of the present invention, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings are provided for illustrative purposes only, illustrating the technical ideas of the invention. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the invention. Therefore, the scope of the invention is not limited to the illustrated embodiments, but should be accorded the widest scope consistent with the claims. The scope of protection of the invention should be determined by the appended claims, and any technical ideas falling within their equivalent scope should be understood to be included within the scope of the invention.

Claims

1. A display device, comprising: substrate; A first driving transistor is disposed on or above the substrate and included in a first sub-pixel; A cover layer located on or above the first driving transistor; The first anode is disposed on or above the first driving transistor and included in the first sub-pixel; The first light-emitting layer is located on the first anode; as well as The cathode located on the first light-emitting layer, The first anode includes a first electrode portion disposed in a first region of the first sub-pixel, a second electrode portion disposed in a second region of the first sub-pixel different from the first region, and a first conductive wire portion connecting the first electrode portion and the second electrode portion. The cover layer includes a first groove in the area overlapping with the first conductor portion, and the first conductor portion includes a first bend portion disposed on or above the cover layer and bends along a first inner surface, a bottom surface and a second inner surface of the first groove.

2. The display device according to claim 1, wherein the first conductive portion is electrically connected to the first node of the first driving transistor through a contact hole in the cover layer.

3. The display device according to claim 2, wherein the cover layer further includes a second groove in the region overlapping with the first conductive portion, and the first conductive portion further includes a second bent portion, the second bent portion being disposed on or above the cover layer and bent along a first inner surface, a bottom surface, and a second inner surface of the second groove, and The first groove is located between the contact hole and the first electrode portion, and the second groove is located between the contact hole and the second electrode portion.

4. The display device according to claim 1, wherein the first groove extends in a direction intersecting the longitudinal direction of the first conductive portion.

5. The display device of claim 1, further comprising a first side organic material located on the first inner surface and the second inner surface of the first trench, wherein the first side organic material extends to the outside of the first trench.

6. The display device according to claim 5, further comprising a first bottom organic material located on the bottom surface of the first trench.

7. The display device according to claim 6, wherein the first side organic material and the first bottom organic material are separated from each other.

8. The display device according to claim 1, wherein the angle between the first inner surface or the second inner surface of the first trench and the bottom surface of the first trench is equal to or less than 90°.

9. The display device of claim 1, wherein the second electrode portion is connected to the first driving transistor, and the first electrode portion is not connected to the first driving transistor.

10. The display device according to claim 1, wherein the first bent portion of the first conductor portion is disconnected.

11. The display device according to claim 1, wherein the first region where the first electrode portion is provided does not emit light, and the second region where the second electrode portion is provided emits light.

12. The display device according to claim 1, further comprising: A second driving transistor is disposed on or above the substrate and included in the second sub-pixel; The second anode is disposed on or above the second driving transistor and included in the second sub-pixel; as well as The second light-emitting layer is located on the second anode. The second anode includes a third electrode portion disposed in a third region of the second sub-pixel, a fourth electrode portion disposed in a fourth region of the second sub-pixel different from the third region, and a second conductive portion connecting the third electrode portion and the fourth electrode portion. The cover layer includes a third groove in the area overlapping with the second conductor portion, and the second conductor portion includes a third bend portion disposed on or above the cover layer and bends along the first inner surface, bottom surface and second inner surface of the third groove.

13. The display device of claim 12, wherein the channel size of the first driving transistor is smaller than the channel size of the second driving transistor, and the width of the first trench is narrower than the width of the third trench.

14. The display device of claim 12, wherein the channel size of the first driving transistor is smaller than the channel size of the second driving transistor, and the depth of the first trench is deeper than the depth of the third trench.

15. The display device according to claim 12, wherein the channel size of the first driving transistor is smaller than the channel size of the second driving transistor, and the width of the first conductive portion is narrower than the width of the second conductive portion.

16. The display device according to claim 12, wherein, When the width of the first groove is narrower than the width of the third groove, or the depth of the first groove is deeper than the depth of the third groove, the width of the first conductor portion is wider than the width of the second conductor portion.

17. The display device according to claim 12, wherein the width of the first conductive portion is the same as the width of the second conductive portion, and The width of the first trench is different from the width of the third trench, or the depth of the first trench is different from the depth of the third trench.

18. The display device according to claim 12, wherein the width of the first conductive portion is different from the width of the second conductive portion, and The width of the first trench is the same as the width of the third trench, or the depth of the first trench is the same as the depth of the third trench.

19. The display device according to claim 1, wherein the transmissive region is located on one side of the first sub-pixel, and the first conductive portion is configured to enter the transmissive region.

20. A display device, comprising: The first sub-pixel includes a first driving transistor, a first anode, and a first light-emitting layer; The second sub-pixel includes a second driving transistor, a second anode, and a second light-emitting layer; as well as A capping layer is located between the first driving transistor and the second driving transistor and the first anode and the second anode, and includes a first trench located in the region of the first anode and a second trench located in the region of the second anode. The first anode includes a first electrode portion disposed in a first region of the first sub-pixel, a second electrode portion disposed in a second region of the first sub-pixel that is different from the first region, and a first conductive wire portion connecting the first electrode portion and the second electrode portion. The second anode includes a third electrode portion disposed in a third region of the second sub-pixel, a fourth electrode portion disposed in a fourth region of the second sub-pixel different from the third region, and a second conductive portion connecting the third electrode portion and the fourth electrode portion. The first conductor is disconnected within the first groove of the cover layer, while the second conductor is not disconnected within the second groove of the cover layer.

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