Display panel and its testing method, display device

Abstract

This invention provides a display panel and its detection method and device, relating to the field of display technology, for screening display panels with abnormalities such as cracks. The display panel's driving modes include a detection mode and a display mode; the display panel includes: multiple sub-pixels, multiple data lines, and multiple scan lines, with the sub-pixels electrically connected to the data lines and scan lines respectively; a scan driving circuit electrically connected to the scan lines to provide scan signals to the scan lines; a data driving circuit electrically connected to the data lines to provide data signals to the data lines; and a timing controller electrically connected to both the scan driving circuit and the data driving circuit, the timing controller controlling the scan driving circuit according to the display panel's driving mode so that scan signals are provided to the scan lines at different timings in different driving modes.

Description

[Technical Field]

[0001] This invention relates to the field of display technology, and in particular to a display panel, its testing method, and a display device. [Background Technology]

[0002] With the continuous development of display technology, display panels are being used more and more widely in various fields. To ensure product quality, display panels need to be inspected after manufacturing to prevent defective products, such as those with cracks or other defects, from entering the next process. How to inspect display panels and ensure the accuracy of the inspection has become a key research focus for relevant personnel. [Summary of the Invention]

[0003] In view of this, embodiments of the present invention provide a display panel and a detection method and display device thereof, for screening display panels with abnormalities such as cracks.

[0004] On one hand, embodiments of the present invention provide a display panel, the driving modes of which include a detection mode and a display mode; the display panel includes:

[0005] Multiple sub-pixels, multiple data lines, and multiple scan lines; the sub-pixels are electrically connected to the data lines and scan lines respectively.

[0006] The scan drive circuit is electrically connected to the scan line to provide a scan signal to the scan line;

[0007] A data drive circuit, electrically connected to the data line, provides data signals to the data line;

[0008] The timing controller is electrically connected to the scan drive circuit and the data drive circuit respectively. The timing controller is used to control the scan drive circuit according to the drive mode of the display panel so that the scan signal is provided to the scan line in different timing sequences under different drive modes.

[0009] On the other hand, embodiments of the present invention provide a detection method for a display panel, wherein the driving mode of the display panel includes a detection mode and a display mode; the display panel includes:

[0010] Multiple sub-pixels, multiple data lines, and multiple scan lines; the sub-pixels are electrically connected to the data lines and scan lines respectively.

[0011] The scan drive circuit is electrically connected to the scan line to provide a scan signal to the scan line;

[0012] A data drive circuit, electrically connected to the data line, provides data signals to the data line;

[0013] The detection methods include:

[0014] In detection mode, the control scan drive circuit is used to provide scan signals to the scan lines according to the detection timing; the detection timing is different from the timing of the scan drive circuit in display mode.

[0015] Determine if the display panel is malfunctioning based on the screen displayed in detection mode.

[0016] The display panel, detection method, and display device provided in this invention include a detection mode and a display mode in the driving mode of the display panel. According to the driving mode of the display panel, the timing controller in the display panel controls the scanning driving circuit to output scanning signals with different timing sequences in different driving modes. This allows the scanning signals to be provided to the scan lines with different timing sequences in different driving modes. With this setting, the timing of the display panel can be matched to the application scenario according to different application scenarios, so that the display effect in each application scenario can be more in line with the needs of that application scenario.

[0017] When cracks in the display panel are minor, meaning the delay caused by cracks on the data line is weak, the degree of undercharging of sub-pixels is also weak when the detection timing and display timing are set to the same. The difference between the actual displayed image and the standard test image is also small, making the anomaly difficult to observe and prone to missed detection. This invention addresses this issue by providing a different detection timing than the display timing in the detection mode. When defects such as cracks exist in the display panel, compared to setting the detection timing and display timing to the same, this increases the degree of incomplete charging of sub-pixels in the detection mode. In other words, it amplifies the difference between the actual test image and the standard test image, making the anomaly easier for the human eye to observe. This facilitates timely screening of abnormal panels and reduces the possibility of missed detection. [Attached Image Description]

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0020] Figure 2 An equivalent circuit diagram of a sub-pixel is provided for an embodiment of the present invention;

[0021] Figure 3 A signal comparison diagram of a data cable with and without cracks, provided as an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of a detection screen provided in an embodiment of the present invention;

[0023] Figure 5 A timing diagram of a data line and a scan line provided in an embodiment of the present invention;

[0024] Figure 6 A timing diagram of data lines and scan lines in display mode provided for an embodiment of the present invention;

[0025] Figure 7 This is a schematic flowchart of a method for detecting a display panel according to an embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram of a display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0027] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0029] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0030] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0031] This invention provides a display panel, whose driving modes include a detection mode and a display mode. For example... Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel 100 includes a plurality of sub-pixels 1, a plurality of data lines 2 and a plurality of scan lines 3, wherein the sub-pixels 1 are electrically connected to the data lines 2 and the scan lines 3 respectively.

[0032] For example, the display panel includes an organic light-emitting display panel. Sub-pixel 1 includes an electrically connected pixel driving circuit and a light-emitting element. Optionally, such as... Figure 2 As shown, Figure 2 An equivalent circuit diagram of a sub-pixel is provided in an embodiment of the present invention. The sub-pixel 1 includes a pixel driving circuit 11 and a light-emitting element 12 electrically connected. The pixel driving circuit 11 includes a switching transistor T1, a driving transistor T2, and a storage capacitor C. The gate of the switching transistor T1 is electrically connected to a scan line 3, and the first terminal of the switching transistor T1 is electrically connected to a data line 2. The second terminal of the switching transistor T1 is electrically connected to the gate of the driving transistor T2. The first terminal of the driving transistor T2 is electrically connected to a first power line PVDD. The second terminal of the driving transistor T2 is electrically connected to the light-emitting element 12. The light-emitting element 12 is also electrically connected to a second power line PVEE. The two plates of the storage capacitor C are respectively electrically connected to the first power line PVDD and the gate of the driving transistor T2.

[0033] It should be understood that Figure 2 The pixel driving circuit 11 shown is only an illustration. In this embodiment of the invention, a greater number of transistors can be incorporated into the pixel driving circuit 11 according to different design requirements. This embodiment of the invention does not impose any limitations on this. Of course, the display panel may also include a liquid crystal display panel. This embodiment of the invention does not limit the type of display panel.

[0034] like Figure 1 As shown, the display panel also includes a scan drive circuit 4, a data drive circuit 5, and a timing controller 6. The scan drive circuit 4 is electrically connected to the scan line 3. The data drive circuit 5 is electrically connected to the data line 2. The timing controller 6 is electrically connected to both the scan drive circuit 4 and the data drive circuit 5.

[0035] For example, the timing controller 6 can generate a data control signal and a scan control signal in response to an external synchronization signal. The data control signal controls the driving timing of the data driving circuit 5. The scan control signal controls the driving timing of the scan driving circuit 4. When the display panel is lit, the scan driving circuit 4 applies scan pulses with gate on-state voltages to the corresponding scan lines 3 line by line. The data driving circuit 5 receives image signals and, in response to the data control signal from the timing controller 6, provides data voltages to multiple data lines 2 of the display panel to charge the corresponding sub-pixels 1. For example, the image signals include a detection image signal in detection mode and a display image signal in display mode.

[0036] In this embodiment of the invention, the timing controller 6 controls the scanning drive circuit 4 according to the driving mode of the display panel, so that the scanning signal is provided to the scan line 3 with different timings in different driving modes. Hereinafter, the timing of the scanning signal in the detection mode is defined as the detection timing, and the timing in the display mode is defined as the display timing. In this embodiment of the invention, the detection timing and the display timing are different.

[0037] During the display panel illumination test, the display panel receives the detection image signal from the motherboard. The scan drive circuit 4 generates the detection timing sequence under the control of the timing controller 6. Sub-pixels 1 have, for example... Figure 2 Taking the structure shown as an example, under the action of the scanning signal received by the scanning line 3, the corresponding switching transistor T1 is turned on. For at least the time that the switching transistor T1 is turned on, the data driving circuit 5 provides the corresponding data line 2 with a data voltage corresponding to the detected image signal to charge the corresponding sub-pixel 1. If the actual test image and the target test image are consistent, the display panel is judged to be normal. If the actual test image and the target test image are inconsistent, the display panel is judged to have defects such as cracks.

[0038] When the display panel has defects such as cracks, the transmission of data voltage will be affected, and the delay in data voltage will increase compared to when there are no cracks. For example Figure 3 As shown, Figure 3 The following is a comparison diagram of the signals transmitted by a data line 2 under the conditions of having a crack and not having a crack, provided for an embodiment of the present invention. It can be seen that when there is a crack, the time A1 required for the data voltage to switch to the target voltage V is greater than the time A2 when there is no crack.

[0039] The display panel 100 provided in this embodiment of the invention includes a detection mode and a display mode in its driving mode. According to the driving mode of the display panel 100, the timing controller 6 controls the scan driving circuit 4 to output scan signals with different timing sequences, so that the scan signals are provided to the scan line 3 with different timing sequences in different driving modes. With this setting, the display panel 100 can be driven with a timing sequence that matches the application scenario according to different application scenarios, so that the display effect in each application scenario can be more in line with the needs of the application scenario.

[0040] When the cracks in the display panel 100 are minor, meaning the delay caused by the cracks on the data line 2 is weak, the degree of undercharging of sub-pixel 1 is also weak when the detection timing and display timing are set to the same. The difference between the actual test image and the target test image is also small, making the anomaly difficult to observe and thus failing to filter out defective display panels, resulting in missed detections. This embodiment of the invention drives the display panel 100 with a detection timing different from the display timing in the detection mode. When the display panel 100 has defects such as cracks, compared to making the detection timing and display timing the same, the degree of incomplete charging of sub-pixel 1 in the detection mode can be increased. That is, the difference between the actual test image and the target test image can be aggravated, making the anomaly easier for the human eye to observe. This facilitates timely screening of defective panels and reduces the possibility of missed detections.

[0041] When the display panel is displaying normally, it receives the display image signal. The scan drive circuit 4 generates the display timing sequence under the control of the timing controller 6. Under the action of the scan signal received by the scan line 3, the corresponding switching transistor T1 is turned on. During the time that the switching transistor T1 is on, the data drive circuit 5 provides the corresponding data voltage to the corresponding data line 2, corresponding to the display image signal, to charge the corresponding sub-pixel 1. This embodiment of the invention, by making the display timing sequence different from the detection timing sequence, ensures normal display in the display mode while guaranteeing timely screening of defective display panels, thus improving the display effect.

[0042] For example, in this embodiment of the invention, the data driving circuit 5 is used to provide different data signals to the data line 2 according to the driving mode of the display panel. The load of the data line 2 in the detection mode is greater than or equal to the load in the display mode. For example, the detection screen includes a heavy load screen. When there are defects such as cracks in the display panel, the difference between the actual test screen and the above-mentioned heavy load screen is more obvious, so it is easier to detect defects in the display panel and facilitate timely screening of abnormal display panels. Optionally, the heavy load screen includes a blue screen or such as Figure 4 The black-and-white interlaced display shown, etc. Figure 4 This is a schematic diagram of a detection screen provided in an embodiment of the present invention.

[0043] When the display panel includes an organic light-emitting display panel, the luminous efficiency of blue light-emitting diodes is lower than that of red and green light-emitting diodes. Therefore, the required blue data voltage is larger for the same brightness, resulting in a larger load on the data line.

[0044] When the detection screen includes a blue screen, for example, the blue screen includes a blue screen illuminated at the highest gray level. Taking a display panel that supports 256 gray levels from 0 to 255 as an example, the blue screen includes a blue screen illuminated at gray level 255.

[0045] Optionally, the data driving circuit 5 includes a register that stores multiple brightness levels. At different brightness levels, the brightness corresponding to the same grayscale on the display panel is different. For example, the test image illuminated at the highest grayscale includes the test image illuminated at the highest grayscale under the maximum brightness level (High Brightness Mode, HBM). At the maximum brightness level, the load on data line 2 is large, and the problem of insufficient charging of sub-pixels 1 caused by data signal delay becomes more pronounced. When the display panel 100 has defects such as cracks, the difference between the actual test image and the target test image is more obvious, thus facilitating the screening of defective display panels.

[0046] Optionally, in the display as Figure 4 When displaying a black-and-white interlaced image, the voltage on data line 2 needs to frequently switch between the data voltage corresponding to the white state and the data voltage corresponding to the black state. The voltage difference between the two is relatively large, resulting in a high load on data line 2. When there are defects such as cracks in the display panel, the load on data line 2 will increase further. Therefore, the delay of the data signal will be greater, and the difference between the actual test image and the target test image will be more obvious, making it easier for the human eye to perceive.

[0047] It should be noted that, in addition to the blue screen and the black and white interlaced display screen, the detection screen may also include other overloaded screens, which will not be described in detail here.

[0048] For example, in combination Figure 5 As shown, Figure 5 This is a timing diagram of data lines and scan lines provided in an embodiment of the present invention. Figure 5 The diagram illustrates the scan signals transmitted by three scan lines: the (i-1)th scan line 3_i-1, the ith scan line 3_i, and the (i+1)th scan line 3_i+1. During the sub-pixel's charging time, the interval between the time when data line 2 begins switching to the target voltage V required by the corresponding sub-pixel and the start time of the corresponding scan signal reaching the enable level is called the lead time. Here, lead time refers to the time during the sub-pixel's charging time when the data signal begins switching is earlier than the time when the corresponding scan signal transitions to the enable level. The target voltage V is the voltage required by the corresponding sub-pixel in the current frame. Figure 5 Let V1 and V2 be the target voltages of two adjacent sub-pixels electrically connected to the same data line 2, where V1 ≠ V2, as an illustration. When the display panel 100 is lit, the scan signal is transmitted line by line. Multiple sub-pixels connected to one data line 2 are charged sequentially according to the scan order. When the previous sub-pixel is fully charged, that is, when the scan signal transmitted on the scan line 3 electrically connected to the previous sub-pixel reaches the enable level ( Figure 5(Using a low enable level as an illustration) After switching to a non-enable level, the voltage on data line 2 changes from the target voltage required by the previous sub-pixel to the target voltage required by the current sub-pixel, and maintains the target voltage required by the current sub-pixel for a period of time. In this embodiment, the target voltage required by the previous sub-pixel is defined as the non-target voltage relative to the current sub-pixel. The previous sub-pixel emits light under the action of the target voltage stored in the storage capacitor C. After the scan signal is turned on, the target voltage transmitted by data line 2 is written to the corresponding sub-pixel, that is, the current sub-pixel begins to charge with its required target voltage. This process continues to complete the display of one frame. During the charging time of the sub-pixel, the length of the pre-charge time can affect the voltage on data line 2 when the corresponding switching transistor is turned on, that is, affect the voltage written to the sub-pixel, thereby affecting the charging status of the sub-pixel.

[0049] For example, the timing controller 6 described above is used to provide the scan signal to the scan line 3 with different timing sequences in different driving modes, including: the timing controller 6 is used to make the lead time in the detection mode different from the lead time in the display mode. Figure 5 As shown, the lead time in detection mode is g1, and the lead time in display mode is g, where g1 ≠ g.

[0050] The load on the cracked data line 2 differs from that on the non-cracked data line 2. Therefore, the switching time of the signal transmitted by the cracked data line 2 when changes occur differs from that of the non-cracked data line 2. In this embodiment of the invention, the lead time g1 in the detection mode is different from the lead time g in the display mode. For example, in a display panel with defects such as cracks, the load on the data line is greater, and the switching time of the signal transmitted by the data line in a display panel with defects such as cracks is longer when changes occur. In this embodiment of the invention, g1 < g2, that is, the lead time in the detection mode is compressed compared to the display mode. With this setting, when the display panel has defects such as cracks, |ΔV1| > |ΔV2| can be set, where ΔV1 is the difference between the actual voltage transmitted by the data line 2 when the corresponding switching transistor is turned on and the target voltage required for detection in the detection mode at a lead time of g1, and ΔV2 is the difference between the actual voltage transmitted by the data line 2 when the corresponding switching transistor is turned on and the target voltage required for detection in the detection mode at a lead time of g. That is, by setting the lead time in the detection mode to g1, when there are defects such as cracks in the display panel, the difference between the actual voltage written to sub-pixel 1 and the target voltage can be made larger, thereby aggravating the degree of incomplete charging of sub-pixel 1, making the abnormal picture more obvious, thereby enabling timely screening of abnormal panels and reducing the possibility of missed detection.

[0051] For example, in combination Figure 6 As shown, Figure 6 This is a timing diagram of data lines and scan lines in display mode, provided as an embodiment of the present invention. In display mode, the pre-display time threshold value is G. Optionally, as... Figure 6 As shown, during the charging time of a sub-pixel, from the moment the voltage on data line 2 begins to switch to the target voltage required by the corresponding sub-pixel, after a time period G, the voltage on data line 2 reaches the target voltage. Simultaneously, the voltage on scan line 3 also reaches the enable level. In other words, in display mode, when the aforementioned lead time is greater than G, the display panel will not experience display abnormalities caused by insufficient charging of the sub-pixels. When the lead time is less than or equal to G, the display panel will experience display abnormalities caused by insufficient charging of the sub-pixels. For example, the lead time threshold G can be determined based on factors such as the material and cross-sectional area of ​​the data line.

[0052] In this embodiment of the invention, G < g. With this setting, in display mode, during the charging time H of the sub-pixel, when the corresponding switching transistor controlled by scan line 3 is turned on, this embodiment of the invention can ensure that the voltage on data line 2 has switched to the required target voltage, thereby ensuring that the sub-pixel can be fully charged to guarantee the display effect. For example, the difference between G and g can be set according to various factors including the material and cross-sectional area of ​​the data line. For example, in this embodiment of the invention, g = G + 0.1 μs can be set. This setting, while ensuring that the sub-pixel can be fully charged in display mode, also avoids setting the lead time in display mode too long, ensuring that the time for the sub-pixel to be constantly written to the target voltage is not compressed.

[0053] For example, the timing controller 6 provided in this embodiment of the invention is further configured to control the pulse width of the scanning signal in detection mode to be equal to the pulse width of the scanning signal in display mode. Combined with Figure 5 As shown, the pulse width of the scan signal in detection mode is e1, and the pulse width of the scan signal in display mode is e; where e1 = e. The pulse width of the scan signal is the conduction time of the switching transistor used to control the charging duration of the sub-pixel. By setting e1 = e, this embodiment of the invention ensures that the conduction time of the switching transistor used to control the charging of sub-pixel 1 is consistent in both detection and display modes. This reduces the complexity of timing design and facilitates implementation. Furthermore, when detecting and screening defective display panels, it avoids introducing other factors that might cause abnormalities in the detection image, thus ensuring the accuracy of the detection. For example, the pulse width of the scan signal can be determined based on the resolution and refresh rate of the display panel.

[0054] For example, in this embodiment of the invention, the interval between the end time of the scan signal being at the enable level and the start time of the data signal on the corresponding data line switching from the target voltage required by the sub-pixel to the non-target voltage during the sub-pixel's charging time is called the "later time." Here, "later time" means that during the sub-pixel's charging time, the data signal transition occurs later than the scan signal transition. By ensuring that the data signal transition occurs later than the scan signal transition, this embodiment of the invention guarantees that the voltage on the data line remains at the target voltage for the specified duration in display mode, thus ensuring that the sub-pixel is fully charged in display mode.

[0055] For example, the timing controller 6 described above is also used to control the duration of the back time in the detection mode to be greater than the duration of the back time in the display mode. Combined with... Figure 5 As shown, the post-time in detection mode is f1, and the post-time in display mode is f. Where f1 > f.

[0056] For example, during the charging time of a sub-pixel, the interval between the start time of the data line 2 switching to the target voltage required by the sub-pixel and the start time of the data line 2 switching from the target voltage required by the sub-pixel to a non-target voltage is a unit time. Optionally, the timing controller 6 is further configured to control the duration of the unit time in detection mode to be equal to the duration of the unit time in display mode. Combined with... Figure 5 As shown, the duration of each unit of time in detection mode and display mode is both H. For example, as... Figure 5 As shown, H = g1 + e1 + f1 = g + e + f.

[0057] For example, the display panel provided in this embodiment of the invention further includes a clock signal line electrically connected to the scan driving circuit, wherein the clock signal line is used to transmit a clock signal. When the display panel is working, the scan driving circuit responds to the clock signal to provide a scan signal to the scan line 3. Optionally, this embodiment of the invention can achieve the difference in scan signal timing by adjusting the timing of the clock signal in the detection mode and the display mode.

[0058] This invention also provides a method for detecting a display panel, wherein the driving mode of the display panel includes a detection mode and a display mode; combined with Figure 1 As shown, the display panel includes multiple sub-pixels 1, multiple data lines 2, and multiple scan lines 3. The sub-pixels 1 are electrically connected to the data lines 2 and scan lines 3, respectively. Combined with... Figure 2 As shown, sub-pixel 1 includes a pixel driving circuit 11 and a light-emitting element 12 that are electrically connected. (As...) Figure 1As shown, the display panel 100 also includes a scan drive circuit 4 and a data drive circuit 5. The scan drive circuit 4 is electrically connected to the scan line 3 and is used to provide scan signals to the scan line 3. The data drive circuit 5 is electrically connected to the data line 2 and is used to provide data signals to the data line 2.

[0059] Combination Figure 7 As shown, Figure 7 This is a schematic flowchart of a display panel detection method provided in an embodiment of the present invention. The display panel detection method provided in this embodiment of the present invention includes:

[0060] Step S1: Control the display panel 100 to enter the detection mode; in the detection mode, control the scan drive circuit 4 to provide scan signals to the scan lines 3 according to the detection timing; wherein, the detection timing is different from the display timing in the display mode. For example, in the detection mode, in response to the scan pulses of the sequentially driven multiple scan lines, multiple sub-pixels 1 connected to the same data line 2 are sequentially charged with the target voltage corresponding to the detection image signal, so that the display panel displays the detection image; wherein, the scan pulses have a detection timing. In the display mode, control the scan drive circuit 4 to provide scan signals to the scan lines 3 according to the display timing; the detection timing is different from the display timing; for example, in the display mode, in response to the scan pulses of the sequentially driven multiple scan lines, multiple sub-pixels 1 connected to the same data line 2 are sequentially charged with the target voltage corresponding to the display image signal, so that the display panel displays the display image; wherein, the scan pulses have a display timing.

[0061] Step S2: Based on the display screen 100 shows in detection mode, determine whether the display panel has any abnormalities. For example, abnormalities include defects such as cracks. When the display panel 100 has cracks or other defects, the load on the data line 2 or other signal lines will increase, resulting in a difference between the actual test screen and the target test screen. For example, in this embodiment of the invention, the determination can be made visually, or it can be made using optical instruments.

[0062] The display panel detection method provided in this embodiment of the invention includes a detection mode and a display mode in the driving mode of the display panel 100. When detecting the display panel 100, the scanning driving circuit 4 is controlled to output a scanning signal with a detection timing sequence. The detection timing sequence is different from the display timing sequence in the display mode. With this setting, the display panel can be driven with a detection timing sequence that matches the detection mode, so that the display effect of the display panel in the detection mode can better meet the requirements of the detection mode.

[0063] When the cracks in the display panel 100 are minor, meaning the delay caused by the cracks on the data line 2 is relatively weak, the degree of undercharging of sub-pixel 1 is also relatively weak when the detection timing and display timing are set to the same. The difference between the actual test image and the target test image is also small, making the anomaly difficult to observe and prone to missed detection. This embodiment of the invention drives the display panel 100 with a detection timing different from the display timing in the detection mode. When the display panel has defects such as cracks, compared to the case where the detection timing and display timing are the same, the degree of incomplete charging of the sub-pixels in the detection mode can be increased. That is, the difference between the actual test image and the target test image can be aggravated, making the anomaly easier for the human eye to observe. This facilitates timely screening of abnormal panels and reduces the possibility of missed detection.

[0064] For example, the display panel detection method provided in this embodiment of the invention further includes: providing a detection image signal to the display panel 100 in detection mode; and providing a data voltage to the data line 2 according to the detection image signal; wherein the load of the data line 2 corresponding to the detection image signal is greater than or equal to the load corresponding to the display image signal in the display mode. For example, the image corresponding to the detection image signal is a heavy-load image. By making the load of the data line 2 corresponding to the detection image signal greater than or equal to the load corresponding to the display image signal in the display mode, this embodiment of the invention makes the difference between the actual test image and the above-mentioned heavy-load image more obvious when the display panel has defects such as cracks, thus making it easier to detect defects in the display panel and facilitating the timely screening of abnormal display panels.

[0065] In this embodiment of the invention, during the charging time of the sub-pixel, the interval between the start time of the data line 2 switching to the target voltage and the start time of the corresponding scan signal being at the enable level is the pre-time. For example, combined with... Figure 5 As shown, in the detection mode, the control of the scan drive circuit 4 ensures that the scan signal is provided to the scan line 3 according to the detection timing. Furthermore, the method for ensuring that the detection timing differs from the timing of the scan signal in the display mode includes: setting the pre-set time in the detection mode to g1; setting the pre-set time in the display mode to g; where g1 ≠ g. For example, in this embodiment of the invention, g1 < g. With this setting, when the display panel has defects such as cracks, the difference between the actual voltage written to sub-pixel 1 and the target voltage can be made larger, thereby aggravating the incomplete charging of sub-pixel 1, making abnormal images more obvious, and thus enabling timely screening of abnormal panels and reducing the possibility of missed detections.

[0066] Optional, combined Figure 6 As shown, in display mode, the critical time before an abnormal display occurs is G. Combined with... Figure 5 and Figure 6As shown, G < g. With this setting, in display mode, during the charging time of sub-pixel 1, when scan line 3 controls the corresponding switching transistor to turn on, this embodiment of the invention can ensure that the voltage on data line 2 has switched to the required target voltage, thereby ensuring that sub-pixel 1 can be fully charged to guarantee the display effect. For example, the difference between G and g can be set according to various factors including the material and cross-sectional area of ​​data line 2. For example, this embodiment of the invention can set g = G + 0.1 μs. This setting, while ensuring that the sub-pixel can be fully charged in display mode, also avoids setting the lead time in display mode too long, ensuring that the duration of constant writing to the target voltage for the sub-pixel is not compressed.

[0067] Optional, combined Figure 5 As shown, the display panel detection method provided in this embodiment of the invention further includes: controlling the pulse width e1 of the scanning signal in detection mode to be equal to the pulse width e in display mode. This setting ensures that the conduction time of the switching transistor used to control the charging of sub-pixel 1 is consistent in both detection and display modes. This reduces the complexity of timing design and facilitates implementation; furthermore, when detecting and screening defective display panels, it avoids introducing other factors that might cause abnormalities in the detection image, thus ensuring detection accuracy. For example, the pulse width of the scanning signal can be determined based on the resolution and refresh rate of the display panel.

[0068] For example, during the charging time of a sub-pixel, the interval between the end time of the scan signal being at the enable level and the start time of the corresponding data line 2 switching from the target voltage to the non-target voltage is called the lag time. Combined with... Figure 5 As shown, the detection method for the display panel provided in this embodiment of the invention further includes: controlling the duration f1 of the back time in the detection mode to be greater than the duration f of the back time in the display mode.

[0069] For example, in an embodiment of the present invention, during the charging time of a sub-pixel, the interval between the start time of the data line 2 switching to the target voltage required by the sub-pixel and the start time of the data line 2 switching from the target voltage required by the sub-pixel to a non-target voltage is a unit time. The detection method for the display panel provided in this embodiment of the present invention further includes: controlling the duration of the unit time in the detection mode to be equal to the duration of the unit time in the display mode. For example... Figure 5 As shown, both are H.

[0070] This invention also provides a display device, such as... Figure 8 As shown, Figure 8This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Of course, Figure 8 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0071] The display device provided in this embodiment of the invention includes a detection mode and a display mode in the driving mode of the display panel 100. According to the driving mode of the display panel 100, the timing controller 6 in the display panel 100 controls the scanning driving circuit 4 to output scanning signals with different timing sequences. This allows the scanning signals to be provided to the scanning line 3 with different timing sequences in different driving modes. With this configuration, the display panel 100 can be driven with a timing sequence that matches the application scenario, so that the display effect in each application scenario can be more in line with the needs of that application scenario.

[0072] When the cracks in the display panel 100 are minor, meaning the delay caused by the cracks on the data line 2 is relatively weak, the degree of undercharging of sub-pixel 1 is also relatively weak when the detection timing and display timing are set to the same. The difference between the actual displayed image and the standard test image is also small, making the anomaly difficult to observe and prone to missed detection. This embodiment of the invention drives the display panel 100 with a detection timing different from the display timing in the detection mode. When the display panel 100 has defects such as cracks, compared to making the detection timing and display timing the same, the degree of incomplete charging of sub-pixel 1 in the detection mode can be increased. That is, the difference between the actual test image and the standard test image can be aggravated, making the anomaly easier for the human eye to observe. This facilitates timely screening of abnormal panels and reduces the possibility of missed detection.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that, The driving modes of the display panel include a detection mode and a display mode; the display panel includes: Multiple sub-pixels, multiple data lines, and multiple scan lines, wherein the sub-pixels are electrically connected to the data lines and the scan lines respectively; A scan drive circuit, electrically connected to the scan line, provides a scan signal to the scan line; A data driving circuit is electrically connected to the data line to provide data signals to the data line; A timing controller is electrically connected to the scan driving circuit and the data driving circuit respectively. The timing controller is used to control the scan driving circuit according to the driving mode of the display panel so that the scan signal is provided to the scan line in different timing sequences under different driving modes. The interval between the start time of the data line switching to the target voltage and the start time of the corresponding scan signal being at the enable level is the lead time. The timing controller is used to provide the scan signal to the scan line at different timings under different driving modes, including: The timing controller is configured to set the pre-time to g1 in the detection mode and to set the pre-time to g in the display mode; wherein g1 < g.

2. The display panel according to claim 1, characterized in that, The data driving circuit is used to provide different data signals to the data line according to the driving mode of the display panel; the load of the data line in the detection mode is greater than or equal to the load in the display mode.

3. The display panel according to claim 1, characterized in that, In the display mode, the critical time before an abnormal display occurs is G, where G < g.

4. The display panel according to claim 1, characterized in that, The timing controller is further configured to control the pulse width of the scanning signal to be e1 in the detection mode; and to control the pulse width of the scanning signal to be e in the display mode; wherein e1=e.

5. The display panel according to claim 1, characterized in that, The interval between the end time of the scan signal being at the enable level and the start time of the corresponding data line switching from the target voltage to the non-target voltage is the post-time. The timing controller is further configured to control the post-time to f1 in the detection mode; and to control the post-time to f in the display mode; wherein f1 > f.

6. The display panel according to claim 1, characterized in that, The interval between the start time of the data line switching to the target voltage and the start time of the data line switching from the target voltage to a non-target voltage is a unit time. The timing controller is further configured to control the unit time to be H in the detection mode; and to control the unit time to be H in the display mode.

7. A method for detecting a display panel, characterized in that, The driving modes of the display panel include a detection mode and a display mode; the display panel includes: Multiple sub-pixels, multiple data lines, and multiple scan lines, wherein the sub-pixels are electrically connected to the data lines and the scan lines respectively; A scan drive circuit, electrically connected to the scan line, provides a scan signal to the scan line; A data driving circuit is electrically connected to the data line to provide data signals to the data line; The detection method includes: In the detection mode, the scan driving circuit is controlled to provide the scan signal to the scan line according to the detection timing; the detection timing is different from the timing of the scan driving circuit in the display mode; Based on the display screen in the detection mode, determine whether the display panel is abnormal; The interval between the start time of the data line switching to the target voltage and the start time of the corresponding scan signal being at the enable level is the lead time. In the detection mode, controlling the scan drive circuit to provide the scan signal to the scan line according to the detection timing; the method for the detection timing to differ from the timing of the scan signal in the display mode includes: The lead time in the detection mode is different from the lead time in the display mode; The lead time in the detection mode is g1, and the lead time in the display mode is g, where g1 < g.

8. The detection method according to claim 7, characterized in that, The detection method further includes: In the detection mode, a detection image signal is provided to the display panel; the data driving circuit is used to provide a data voltage to the data line according to the detection image signal; The load of the data line corresponding to the detected image signal is greater than or equal to the load corresponding to the displayed image signal in the display mode.

9. The detection method according to claim 7, characterized in that, In the display mode, the critical time before an abnormal display occurs is G, where G < g.

10. The detection method according to claim 7, characterized in that, Also includes: The pulse width of the scanning signal in the detection mode is controlled to be equal to the pulse width in the display mode.

11. The detection method according to claim 7, characterized in that, The interval between the end time of the scan signal being at the enable level and the start time of the corresponding data line switching from the target voltage to the non-target voltage is the post-time. The detection method further includes: The duration of the post-time in the detection mode is greater than the duration of the post-time in the display mode.

12. The detection method according to claim 7, characterized in that, The interval between the start time of the data line switching to the target voltage and the start time of the data line switching from the target voltage to a non-target voltage is a unit time. The detection method further includes: The duration of the unit time in the detection mode is controlled to be equal to the duration of the unit time in the display mode.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-6.

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