Electro-optical devices and electronic equipment

Abstract

Ensure a large area for incoming light from the outside. [Solution] In one pixel cluster 60 and adjacent pixel cluster 60 in the X direction, the power supply line 16, the scan line, and the control line are shared. The power supply line 16 supplies the power supply voltage of the light-emitting elements included in the pixel cluster 60, and the control line is supplied with a control signal that specifies the light emission period of the light-emitting elements. Between one pixel cluster 60 and adjacent pixel cluster 60 in the X direction, the power supply line 16, the scan line 12b which is a relay wiring for the scan line, and the control line 15c which is a relay wiring for the control line are superimposed in a plan view.

Description

Technical Field

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[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] As a light-emitting element used for display, for example, an electro-optical device using an OLED (Organic Light Emitting Diode) is known. Such a light-emitting element has a configuration in which a light-emitting functional layer is sandwiched between a pixel electrode and a common electrode. In an electro-optical device using such a light-emitting element, as a technique for making a see-through type in which an image (virtual image) can be visually recognized while allowing the outside world to be visible, a technique in which a light-transmitting region is provided around a region to be visually recognized as a pixel of the image is known (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the above technology does not mention how to process the wiring connecting the portions that function as pixels. Therefore, in the above technology, depending on the processing of the wiring, there is a problem that the light-transmitting region for making the outside world visible becomes narrow, making it difficult to visually recognize the outside world.

Means for Solving the Problems

[0005] An electro-optical apparatus according to one aspect of the present disclosure includes: a power supply line provided along a first direction; a scanning line provided along the power supply line; a first data line provided along a second direction intersecting the first direction; a second data line provided along the second direction; a first pixel circuit provided corresponding to the intersection of the scanning line and the first data line; a second pixel circuit provided corresponding to the intersection of the scanning line and the second data line; and a light-transmitting power supply line wiring section provided in a region between the first pixel circuit and the second pixel circuit in the first direction in a plan view, wherein the power supply line and the scanning line are provided in the power supply line wiring section; the first pixel circuit includes a first transistor, a second transistor and a first light-emitting element; and the second pixel circuit includes a third transistor The device includes a scanner, a fourth transistor, and a second light-emitting element, wherein the second transistor is turned on or off in accordance with the voltage of the scan line between the first data line and the first gate node of the first transistor, the fourth transistor is turned on or off in accordance with the voltage of the scan line between the second data line and the second gate node of the third transistor, the first transistor controls the current flowing from the power supply line to the first light-emitting element in accordance with the voltage of the first gate node, the third transistor controls the current flowing from the power supply line to the second light-emitting element in accordance with the voltage of the second gate node, and in the power supply line wiring section, the power supply line and the scan line overlap in a plan view.

[0006] Furthermore, an electro-optical apparatus according to another aspect of the present disclosure includes a power supply line provided along a first direction, a first scan line provided along the power supply line, a second scan line provided along the power supply line, a first data line provided along a second direction intersecting the first direction, a second data line provided along the second direction, a first pixel circuit provided corresponding to the intersection of the first scan line and the first data line, a second pixel circuit provided corresponding to the intersection of the first scan line and the second data line, and a third pixel provided corresponding to the intersection of the second scan line and the first data line. The circuit includes a fourth pixel circuit provided corresponding to the intersection of the second scan line and the second data line, and a data line wiring section that transmits light and is provided in a region between the first pixel circuit and the second pixel circuit and the third pixel circuit and the fourth pixel circuit in a plan view in the second direction, wherein the first pixel circuit includes a first transistor, a second transistor and a first light-emitting element, the second pixel circuit includes a third transistor, a fourth transistor and a second light-emitting element, and the third pixel circuit includes a fifth transistor, a sixth transistor and a third The 3 light-emitting elements are included, and the 4th pixel circuit includes a 7th transistor, an 8th transistor and a 4th light-emitting element, the 2nd transistor is turned on or off in accordance with the voltage of the 1st scan line between the 1st data line and the 1st gate node of the 1st transistor, the 4th transistor is turned on or off in accordance with the voltage of the 1st scan line between the 2nd data line and the 2nd gate node of the 3rd transistor, the 6th transistor is turned on or off in accordance with the voltage of the 2nd scan line between the 1st data line and the 3rd gate node of the 5th transistor, the 8th transistor is turned on or off in accordance with the voltage of the 2nd scan line between the 2nd data line and the 4th gate node of the 7th transistor, the 1st transistor controls the current flowing from the power supply line to the 1st light-emitting element in accordance with the voltage of the 1st gate node, the 3rd transistor controls the current flowing from the power supply line to the 2nd light-emitting element in accordance with the voltage of the 2nd gate node, the 5th transistor,The current flowing from the power supply line to the third light-emitting element is controlled according to the voltage of the third gate node, and the seventh transistor controls the current flowing from the power supply line to the fourth light-emitting element according to the voltage of the fourth gate node, and in the data line wiring section, the first data line and the second data line overlap in a plan view. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view showing the configuration of the electro-optical device according to the embodiment. [Figure 2] This is a diagram showing the electrical configuration of an electro-optical device. [Figure 3] This diagram shows the arrangement of pixel circuits in the pixel cluster section within the display area. [Figure 4] This diagram shows the division of the display area in an electro-optical device. [Figure 5] This is a plan view showing the equivalent circuit of a pixel circuit. [Figure 6] This is a timing chart used to explain the operation of an electro-optical device. [Figure 7] This is a plan view showing the configuration of the pixel cluster section. [Figure 8] This is a plan view showing the configuration of the horizontal wiring section. [Figure 9] This is a plan view showing the configuration of the vertical wiring section. [Figure 10] This is a plan view showing the configuration of the transparent section. [Figure 11] This is a partial cross-sectional view showing the configuration of the lateral wiring section. [Figure 12] This is a partial cross-sectional view showing the configuration of the vertical wiring section. [Figure 13] This is a perspective view showing a head-mounted display using an electro-optical device. [Figure 14] This figure shows the optical configuration of a head-mounted display. [Modes for carrying out the invention]

[0008] Hereinafter, an electro-optical apparatus according to an embodiment will be described with reference to the drawings. Note that the dimensions and scale of each part in each drawing have been appropriately changed from those of the actual parts. Furthermore, the embodiments described below are preferred examples and are subject to various technically preferred limitations, but the scope of this disclosure is not limited to these forms unless otherwise stated in the following description to specifically limit this disclosure.

[0009] Figure 1 is a perspective view showing an electro-optical device 10 according to an embodiment, and Figure 2 is a block diagram showing the schematic electrical configuration of the electro-optical device 10. This electro-optical device 10 is a microdisplay panel that displays color images transmissively, for example, in a head-mounted display. The electro-optical device 10 drives the OLED by transistors formed on a transparent insulating substrate. Examples of insulating substrates include quartz and sapphire, and the transistors are typically thin-film transistors, but are not limited to these.

[0010] The electro-optical device 10 is housed in a frame-shaped case 192 that opens in the display area 100. One end of an FPC (Flexible Printed Circuits) board 194 is connected to the electro-optical device 10. The other end of the FPC board 194 is provided with a plurality of terminals 196 for connecting a host device (not shown). When the plurality of terminals 196 are connected to the host device, the electro-optical device 10 is supplied with video data, synchronization signals, etc., from the host device via the FPC board 194.

[0011] In the diagram, the X direction refers to the horizontal direction of the display screen. The Y direction refers to the direction in which the data lines extend, which in terms of the display screen refers to the vertical direction. The two-dimensional plane defined by the X and Y directions is the substrate surface of the insulating substrate. The Z direction is perpendicular to the substrate surface of the insulating substrate and is the direction in which light is emitted from the OLED. In this explanation, a plan view refers to viewing the insulating substrate from the opposite direction of the Z direction, and a cross-sectional view refers to viewing the insulating substrate after it has been cut perpendicular to the substrate surface.

[0012] As shown in FIG. 2, the electro-optical device 10 is roughly divided into a control circuit 30, a data signal output circuit 50, a display region 100, and a scanning line driving circuit 120. In the display region 100, m power supply lines 16 are provided along the X direction. The power supply line 16 supplies the voltage Vel, which is the power supply for the OLED. In the display region 100, a pair of scanning lines 12 and control lines 15 are provided along the X direction so as to correspond one-to-one to the power supply line 16. Although a part of the scanning line 12 and the control line 15 is provided to bend along the Y direction, electrically speaking, it can be said that they are provided along the X direction. Here, m is an integer of 2 or more.

[0013] In the display region 100, data lines 14R, 14G, and 14B are provided. Among these, the data line 14G is provided along the Y direction. Also, although a part of the data lines 14R and 14B is provided to bend along the X direction, electrically speaking, it can be said that they are provided along the Y direction. The data lines 14R, 14G, and 14B are kept electrically insulated from the power supply line 16, the scanning line 12, and the control line 15.

[0014] In the present embodiment, the data lines are grouped for every three data lines 14R, 14G, and 14B. If the total number of groups is n, the total number of data lines in the present embodiment is three times n (3n). Here, n is an integer of 2 or more. Also, in the present embodiment, for convenience, m < (3n) is set.

[0015] In order to generally describe the rows of the scanning line 12, an integer i from 1 to m is used. For example, regarding the scanning line 12, in the figure, it may be called the 1st, 2nd, 3rd,..., (i - 1)th, ith,..., (m - 1)th, and mth rows in order from the top. Similarly, in order to generally describe the columns of the data lines, an integer j from 1 to n is used. For example, for distinguishing the data lines, in the figure, it may be called the 1st, 2nd, 3rd,..., (3j - 2)th, (3j - 1)th, (3j)th,..., (3n - 2)th, (3n - 1)th, and (3n)th columns in order from the left.

[0016] Furthermore, regarding data lines 14R, 14G, and 14B, in the case of the j-th group, the (3j-2)th column is sometimes described as the first series, the (3j-1)th column as the second series, and the (3j)th column as the third series. In other words, in the j-th group, data line 14R of the first series is the (3j-2)th column, data line 14G of the second series is the (3j-1)th column, and data line 14B of the third series is the (3j)th column.

[0017] The pixel cluster section 60 is provided in accordance with the intersections of m scan lines 12 and n groups of data lines 14R, 14G, and 14B.

[0018] Figure 3 is a plan view showing the configuration of the pixel cluster section 60. The pixel cluster section 60 has a configuration in which rectangular pixel circuits 600R, 600G, and 600B are arranged in order along the X direction. In the rectangular shape of the pixel circuits 600R, 600G, and 600B, the X direction is the shorter side and the Y direction is the longer side. Pixel circuit 600R is provided corresponding to the intersection of scan line 12 and data line 14R, pixel circuit 600G is provided corresponding to the intersection of scan line 12 and data line 14G, and pixel circuit 600B is provided corresponding to the intersection of scan line 12 and data line 14B.

[0019] Pixel circuit 600R includes an OLED that emits red wavelength light and is a circuit that controls the light emission of the red OLED. Similarly, pixel circuit 600G includes an OLED that emits green wavelength light and is a circuit that controls the light emission of the green OLED, and pixel circuit 600B includes an OLED that emits blue wavelength light and is a circuit that controls the light emission of the blue OLED.

[0020] In this embodiment, one color dot is represented by one pixel cluster 60. More specifically, one color dot is represented by additive color mixing, where a red OLED in pixel circuit 600R emits light, a green OLED in pixel circuit 600G emits light, and a blue OLED in pixel circuit 600B emits light. Therefore, in this embodiment, a color image with a vertical dimension of m dots and a horizontal dimension of n dots can be displayed.

[0021] Returning to Figure 2, the control circuit 30 receives video data Vin and synchronization signal Sync from the host device and controls the data signal output circuit 50 and the scan line drive circuit 120. The video data Vin is data that defines a color image with dimensions of m vertical dots x n horizontal dots, specifying, for example, the RGB color level for each dot using 8 bits. The Sync synchronization signal includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of supplying one dot of video data.

[0022] In the electro-optical device 10, there is a one-to-one correspondence between one color dot of the image to be displayed and one color dot represented by the pixel cluster 60. On the other hand, the brightness characteristics specified by the gradation level in the video data Vin do not necessarily match the brightness characteristics of the red, green, and blue OLEDs included in the pixel cluster 60. Therefore, the control circuit 30 upconverts the 8 bits of the gradation level specified in the video data Vid to, for example, 10 bits in order to make the OLED emit light at the brightness corresponding to that gradation level, and outputs it as video data Vdata that specifies the brightness of the OLED.

[0023] The scan line driving circuit 120 is a circuit for driving the pixel cluster section 600, which is arranged in m rows and n columns, row by row, according to the control of the control circuit 30. Specifically, the scan line driving circuit 120 outputs scan signals / Gwr(1), / Gwr(2), / Gwr(3), ..., / Gwr(m-1), and / Gwr(m) in order to the scan lines 12 of the 1st, 2nd, 3rd, ..., (m-1), and mth rows. Generally, the scan signal output to the scan line 12 of the ith row is denoted as / Gwr(i). Furthermore, the scan line drive circuit 120 outputs control signals / Gel(1), / Gel(2), / Gel(3), ..., / Gel(m-1), and / Gel(m) in sequence to the control lines 15 of the 1st, 2nd, 3rd, ..., (m-1), and mth lines, in synchronization with the output of the scan signals / Gwr(1) to / Gwr(m). Generally, the control signal output to the control line 15 of the ith line is denoted as / Gel(i).

[0024] The data signal output circuit 50 is a circuit that outputs R, G, and B data signals corresponding to one dot color represented by the pixel cluster 60 to the pixel cluster 60 located in the row selected by the scan line drive circuit 120, in the order of data lines 14R, 14G, and 14B. In detail, the data signal output circuit 50 is supplied with video data Vdata for a given row by the scan line drive circuit 120 before that row is selected. The data signal output circuit 50 latches the video data Vdata for that row, and when that row is selected, converts the latched video data Vdata into an analog data signal and outputs it to the data line.

[0025] Although not specifically shown in the diagram, a power supply circuit is provided outside the display area 100, and this power supply circuit generates the voltages Vel and Vct for the control circuit 30, the scan line drive circuit 120, the data signal output circuit 50, and the OLED power supply. Furthermore, in the diagram, the data signals output to data line 14 in columns 1, 2, 3, ..., (3n-2), (3n-1), and (3n) are denoted as Vd(1), Vd(2), Vd(3), ..., Vd(3n-2), Vd(3n-1), and Vd(3n), respectively. Generally, for example, the data signal output to data line 14G in column (3j-1) is denoted as Vd(3j-1).

[0026] In this embodiment, the pixel cluster units 60 are arranged at a distance from each other.

[0027] Figure 4 is a plan view showing the arrangement of pixel cluster sections 60 and the like in the display area 100. In the figure, the pixel cluster sections 60 are arranged with horizontal wiring sections 162 in between to the left and right, and vertical wiring sections 164 in between to the top and bottom. Furthermore, the transparent section 170 is positioned above and below the horizontal wiring section 162. In other words, the transparent section 170 is positioned to the left and right of the vertical wiring section 164.

[0028] The lateral wiring section 162 is a region through which the wiring constituting the power supply line 16, scan line 12, and control line 15 passes, and transmits light incident from the opposite side in the Z direction in regions other than the region where the wiring is formed. In other words, the lateral wiring section 162 is provided in the region between the pixel cluster sections 60 that are spaced apart from each other in the X direction, and the wiring constituting the power supply line 16, scan line 12, and control line 15 is provided in the lateral wiring section 162. The lateral wiring section 162 corresponds to the "power supply line wiring section" as referred to in the claims. The vertical wiring section 164 is the region through which the wiring constituting the data lines 14R, 14G, and 14B pass, and in the region other than the area where the wiring is formed, it transmits light in the same way as the horizontal wiring section 162. The transparent portion 170 is a region where no transistors or wiring are formed, and it transmits light incident from the opposite side in the Z direction.

[0029] Pixel circuits 600R, 600G, and 600G differ only in the color of light emitted from the OLED; electrically, they have the same configuration. Therefore, for the explanation of pixel circuits 600R, 600G, and 600G, we will use pixel circuit 600G, which is in row i and column (3j-1), as an example. Note that the pixel circuit 600G in row i (3j-1) is included in the pixel cluster section 60 in row i and column j.

[0030] Figure 5 shows the electrical configuration of the pixel circuit 600G. The pixel circuit 600G includes transistors 121, 122, and 124, an OLED 130, and a capacitive element 140. In this embodiment, transistors 121, 122, and 124 are all P-channel thin-film transistors.

[0031] In the i-row (3j-1) column pixel circuit 600G, transistor 121 has its gate node g electrically connected to the drain node of transistor 122, its source node electrically connected to the power supply line 16, and its drain node electrically connected to the drain node of transistor 124. In this explanation, "electrically connected" or simply "connected" means a state in which two or more elements are directly or indirectly connected or coupled.

[0032] In transistor 122, the gate node is connected to scan line 12 in the i-th row, and the source node is connected to data line 14G in the (3j-1)th column. In transistor 124, the gate node is connected to the i-th row control line 15, and the drain node is connected to the pixel electrode 131, which is the anode of the OLED 130. The cathode of the OLED130 is a common electrode 118 common to all pixel circuits 600R, 600G, and 600B. A voltage Vct is applied to the common electrode 118.

[0033] In the OLED 130, the light-emitting functional layer 132 is sandwiched between the pixel electrode 131 and the common electrode 133. In this embodiment, white light is emitted from the light-emitting functional layer 132. Specifically, in the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, and white light including the wavelength ranges of R, G, and B is generated. A color filter corresponding to green light is provided on the output side of the OLED130 included in the pixel circuit 600G. Therefore, the white light emitted from the OLED130 is perceived by the observer as green light after being colored by the color filter.

[0034] Here, we have described the OLED130 included in the pixel circuit 600G. For OLED130 that corresponds to red light, a color filter corresponding to red light is provided on the output side, and for OLED130 that corresponds to blue light, a color filter corresponding to blue light is provided on the output side. Therefore, a single color dot is represented by the additive color mixing of the red, green, and blue OLEDs 130 contained in the pixel cluster 60.

[0035] In this configuration, the OLED130 emits white light, and the colored light, after being colored by a color filter, is visible to the observer. However, for example, the OLED130 may emit the corresponding colored light, or a configuration that uses color filtering in combination may also be used. When the electro-optical device 10 simply displays a monochrome image consisting only of light and dark areas, the above-mentioned color filter is omitted.

[0036] One end of the capacitive element 140 is electrically connected to the gate node g of the transistor 121, and the other end of the capacitive element 140 is electrically connected to the power supply line 16. The role of the capacitive element 140 is to maintain the voltage at the gate node g. For this reason, parasitic capacitance may be used instead of actively adding a capacitive element 140.

[0037] Figure 6 is a timing chart illustrating the operation of the electro-optical device 10. In the electro-optical device 10, the m-row scan lines 12 are scanned one line at a time in the order of 1st, 2nd, 3rd, ..., mth line during a frame (V) period. More specifically, as shown in the figure, the scan signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), and / Gwr(m) are sequentially and exclusively set to L level by the scan line drive circuit 120 for each horizontal scanning period (H). In this embodiment, among the scan signals / Gwr(1) to / Gwr(m), the periods during which adjacent scan signals are at an L level are temporally separated. Specifically, after the scan signal / Gwr(i-1) changes from an L level to an H level, the next scan signal / Gwr(i) becomes L level after a period of time. This period corresponds to the horizontal retrace period.

[0038] In this explanation, the duration of one frame (V) refers to the period required to display one frame of the image specified by the video data Vid. The length of one frame (V) is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal if the vertical synchronization signal included in the synchronization signal Sync has a frequency of 60 Hz. The horizontal scanning period (H) is the time interval between the scan signals / Gwr(1) to / Gwr(m) becoming L levels in sequence. For convenience, in the diagram, the start timing of the horizontal scanning period (H) is set to approximately the center of the horizontal retrace period.

[0039] If one of the scan signals / Gwr(1) to / Gwr(m) is a scan signal / Gwr(i) supplied to the i-th row scan line 12, and that scan signal / Gwr(i) is at a low level, then, for example, in the (3j-1)th column, the transistor 122 in the i-th row (3j-1) column pixel circuit 600G will be turned on. As a result, the gate node g of the transistor 121 in the pixel circuit 600G will be electrically connected to the (3j-1)th column data line 14G.

[0040] In this explanation, the "on state" of a transistor refers to a state where the source node and drain node are electrically closed, resulting in a low impedance state. Conversely, the "off state" of a transistor refers to a state where the source node and drain node are electrically open, resulting in a high impedance state.

[0041] During the horizontal scanning period (H) when the scanning signal / Gwr(i) is at an L level, the data signal output circuit 50 converts the video data Vdata, which has been decomposed into R, G, and B components, into analog data signals Vd(1) to Vd(3n) and supplies them to the data lines of the 1st to (3n)th columns. The video data Vdata, which has been decomposed into R, G, and B components, is the three primary color components of the gradation level of a single color dot indicated by the video data Vid.

[0042] In the case of the (3j-1) column, the data signal output circuit 50 converts the grayscale level G(i,j) of the color dot component of row i and column j, indicated by the video data Vid, into an analog data signal Vd(3j-1) and supplies it to the data line 14G of the (3j-1) column. Furthermore, during the horizontal scanning period (H) when the scan signal / Gwr(i-1) one row prior to the scan signal / Gwr(i) is at a low level, the data signal output circuit 50 converts the grayscale level G(i-1,j) of the color dot component in row (i-1) and column j into an analog data signal Vd(3j-1) and supplies it to the data line 14G in column (3j-1).

[0043] The voltage of the data signal Vd(3j-1) is applied to the gate node g of transistor 121 in the i-th row (3j-1)-th column pixel circuit 600G via the (3j-1)-th column data line 14G. When the scan signal / Gwr(i) reaches a high level, transistor 122 turns off, but the voltage of the data signal Vd(3j-1) applied to the gate node g of transistor 121 is held by the capacitive element 140.

[0044] In this embodiment, the control signal / Gel(i) is at an L level during the following period: that is, the control signal / Gel(i) is at an L level from the time one horizontal scanning period (H) has elapsed since the scan signal / Gwr(i) became L level until the scan signal / Gwr(i) becomes H level again after one frame (V) has elapsed. When the control signal / Gel(i) reaches a low level, transistor 124 turns on. As a result, transistor 121 supplies a current to OLED 130 corresponding to the voltage between gate node g and source node s. Even when the scanning signal Gwr(i) goes to a high level and transistor 122 turns off, the voltage of the data signal Vd(3j-2) is maintained by the capacitive element 140, so current continues to flow through the OLED130G. Therefore, in the i-row (3j-1)-column pixel circuit 600G, the OLED 130 continues to emit light at a brightness corresponding to the voltage held by the capacitive element 140, i.e., the grayscale level, until the period of one frame (V) has elapsed and the control signal / Gel(i) reaches the H level.

[0045] Although the pixel circuit 600G in row i and column (3j-1) has been described here, the pixel circuits 600R, 600G, and 600B in row i, other than column (3j-1), also emit light at the brightness indicated by the video data Vin. Furthermore, for OLED130 in rows other than row i, the scanning signals / Gwr(1) to / Gwr(m) sequentially become L levels, causing them to emit light at the brightness indicated by the video data Vdata. Therefore, in the electro-optical device 10, during a frame (V) period, all OLEDs 130 from row 1 to row m (3n) emit light at a brightness indicated by the video data Vdata, thereby displaying one frame of image.

[0046] The period during which the control signals / Gel(1)~ / Gel(m) are at a low level is the period during which the OLED emits light. In other words, if the period during which the control signals / Gel(1)~ / Gel(m) are at a low level is longer, the displayed image will become brighter, and conversely, if the period during which they are at a low level is shorter, the displayed image will become darker. Furthermore, the period during which the control signals / Gel(1)~ / Gel(m) are at a low level may be intermittent.

[0047] Next, the configuration of the pixel cluster section 60, the horizontal wiring section 162, the vertical wiring section 164, and the transparent section 170 will be described.

[0048] Figure 7 is a plan view showing the configuration of the pixel cluster section 60. In the electro-optical device 10, the electrically contributing semiconductor or conductive layers are formed in the following order from the insulating substrate: semiconductor layer, gate electrode layer, first wiring layer, second wiring layer, and third wiring layer. An insulating layer, as shown in the figure, is provided between each layer. In practice, the pixel electrode layer, light-emitting functional layer, and common electrode are formed in a process after the third wiring layer, but this will not be explained here.

[0049] In the pixel cluster section 60, pixel circuits 600R, 600G, and 600B are arranged sequentially along the X direction in the figure. Since the pixel circuits 600R, 600G, and 600B in the pixel cluster section 60 have almost identical configurations, the explanation will mainly focus on pixel circuit 600G as a representative example.

[0050] In the pixel cluster section 60, island-shaped semiconductor regions Sm1 and Sm2 are provided along the Y direction by patterning the semiconductor layer. Semiconductor region Sm1 corresponds to transistors 121 and 124, and semiconductor region Sm2 corresponds to transistor 122. Note that semiconductor region Sm2 is hidden by the data line 14G of the second wiring layer in the pixel circuit 600G, and is therefore shown with a dashed line.

[0051] Rectangular gate electrodes Gt1, Gt2, and Gt4 are provided by patterning the gate electrode layer. The gate electrode Gt1 is positioned so as to overlap with the semiconductor region Sm1 in a plan view, and becomes the gate node of transistor 121. In other words, the region of the semiconductor region Sm1 that overlaps with the gate electrode Gt1 in a plan view becomes the channel region of transistor 121. The gate electrode Gt2 is positioned so as to overlap the semiconductor region Sm2 in a plan view, and becomes the gate node of transistor 122. In other words, the region of the semiconductor region Sm2 that overlaps with the gate electrode Gt2 in a plan view becomes the channel region of transistor 122. The gate electrode Gt4 is positioned so as to overlap the semiconductor region Sm1 in a plan view, and becomes the gate node of transistor 124. In other words, the region of the semiconductor region Sm1 that overlaps with the gate electrode Gt4 in a plan view becomes the channel region of transistor 124.

[0052] The portion of the semiconductor region Sm1 that extends above the gate electrode Gt1 in the diagram becomes the source node of transistor 121. The portion of the semiconductor region Sm1 that extends below the gate electrode Gt1 and extends above the gate electrode Gt4 becomes the drain node of transistor 121 and the source node of transistor 122. The portion of the semiconductor region Sm1 that extends below the gate electrode Gt4 becomes the drain node of transistor 124. The upper portion of the semiconductor region Sm2 that extends above the gate electrode Gt2 becomes the source node of transistor 122. The lower portion of the semiconductor region Sm2 that extends below the gate electrode Gt2 becomes the drain node of transistor 122.

[0053] In the pixel cluster section 60, the first wiring layer patterning provides the power supply line 16, scan line 12a, control line 15a, and relay wiring P1. Of these, the power supply line 16 is common to the pixel cluster section 60 included in one row and is provided in a straight line along the X direction by patterning only the first wiring layer. The power supply line 16 is electrically connected to the source node of the transistor 121 via a contact hole provided at a point where it overlaps with the semiconductor region Sm1. The contact holes are indicated by rectangular frames in the diagram.

[0054] The scan lines 12a and control lines 15a are provided along the X direction, similar to the power supply lines 16. However, unlike the power supply lines 16, the scan lines 12a and control lines 15a are provided for each pixel cluster 60. The scan line 12a is positioned so as to overlap the gate electrode Gt2 in a plan view. The scan line 12a is electrically connected to the gate electrode Gt2 via a contact hole provided at the point where it overlaps with the gate electrode Gt2. The control line 15a is provided so as to overlap the gate electrode Gt4 in a plan view. The control line 15a is electrically connected to the gate electrode Gt4 via a contact hole provided at the point where it overlaps with the gate electrode Gt4.

[0055] The relay wiring P1 is positioned so as to overlap the gate electrode Gt1 and the drain node of transistor 122 in a plan view. The relay wiring P1 is electrically connected to the gate electrode Gt1 via a contact hole located at a point where it overlaps with the gate electrode Gt1 in a plan view, and is electrically connected to the drain node of transistor 122 via a contact hole located at a point where it overlaps with the drain node of transistor 122 in a plan view.

[0056] In the pixel cluster section 60, data lines 14Ra, 14G, 14Ba and relay wiring P2 are provided by patterning the second wiring layer. Of these, the data line 14G is common to the pixel cluster portion 60 included in one row and is provided in a straight line along the Y direction by patterning only the second wiring layer. The data line 14G is electrically connected to the source node of the transistor 122 via a contact hole provided at a point where it overlaps with the semiconductor region Sm2.

[0057] Data lines 14Ra and 14Ba are provided along the Y direction, similar to data line 14G. However, unlike data line 14G, data lines 14Ra and 14Ba are provided for each pixel cluster 60. Except for the fact that data lines 14Ra and 14Ba are provided for each pixel cluster 60, the configuration is the same as that of data line 14G. Specifically, in the case of data line 14Ra, it is electrically connected to the source node of transistor 122 via a contact hole provided at a point overlapping with the semiconductor region Sm2.

[0058] The relay wiring P2 is positioned so as to overlap the drain node of transistor 124 in a plan view. The relay wiring P2 is electrically connected to the drain node by contact hole Ch1. The relay wiring P2 is also electrically connected to the upper layer pixel electrode 131, which functions as an anode in the OLED 130, via contact hole Cnt.

[0059] In the pixel cluster section 60, no wiring is provided by patterning of the third wiring layer. Also, although omitted in Figure 7, in reality, relay wiring and the like are provided to lead to the pixel electrodes 113 of the fourth wiring layer and beyond.

[0060] Figure 8 is a plan view showing the configuration of the lateral wiring section 162. In the horizontal wiring section 162, the power supply line 16 is provided by the patterning of the first wiring layer. As described above, the power supply line 16 is common to all pixel cluster sections 60 included in one row and is in a straight line along the X direction. Therefore, the power supply line 16 is provided as an extension line from adjacent pixel cluster sections 600 in the X direction.

[0061] In the pixel cluster section 60, a portion of the scan lines 12a and control lines 15a provided by the patterning of the first wiring layer are extended to the lateral wiring section 162.

[0062] In the lateral wiring section 162, the scan line 12b and relay wiring P3 and P4 are provided by the patterning of the second wiring layer. Scan line 12b is a wiring in the horizontal wiring section 162 that relays scan line 12a in the left adjacent pixel cluster section 60 and scan line 12a in the right adjacent pixel cluster section 60. The scan line 12b has a shape in which the portion along the boundary separating it from the pixel cluster 60 to its left, the portion overlapping the power supply line 16 in a plan view, and the portion along the boundary separating it from the pixel cluster 60 to its right are patterned together as a single unit. One end of scan line 12b is connected via a contact hole H2a to scan line 12a, which extends from the pixel cluster 60 to the left. The other end of scan line 12b is connected via a contact hole H2b to scan line 12b, which extends from the pixel cluster 60 to the right. Therefore, the scan line 12 is shared in one row of the pixel cluster section 60 in the X direction in the figure by a repeating pattern of scan line 12a and scan line 12b.

[0063] The relay wiring P3 is provided so as to overlap the control line 15a, which extends from the left adjacent pixel cluster 60, in a plan view. The relay wiring P3 is connected to the control line 15a via a contact hole H5a. The relay wiring P4 is provided so as to overlap the control line 15a, which extends from the pixel cluster section 60 to the right, in a plan view. The relay wiring P4 is connected to the control line 15a via the contact hole H5b.

[0064] In the lateral wiring section 162, control lines 15c are provided by the patterning of the third wiring layer. In a plan view, the control line 15c has a shape in which the portion overlapping the relay wiring P3 along the boundary separating it from the left adjacent pixel cluster 60, the portion overlapping the power supply line 16 and the scan line 12b, and the portion overlapping the relay wiring P4 along the boundary separating it from the right adjacent pixel cluster 60 are patterned together as a single unit. One end of control line 15c is connected to relay wiring P3 via contact hole H5c, and the other end of control line 15c is connected to relay wiring P4 via contact hole H5d. Therefore, the control line 15 is shared across one row of pixel cluster section 60 in the X direction in the figure by a repeating pattern of control line 15a, relay wiring P3, control line 15c, and relay wiring P4.

[0065] In the horizontal wiring section 162, a portion of the scan lines 12b and control lines 15c overlap with the straight power supply line 16 in a plan view. Therefore, in this embodiment, a larger area of ​​light transmission can be secured in the horizontal wiring section 162 compared to a configuration in which the scan lines 12b and control lines 15c do not overlap with the power supply line 16 in a plan view. In addition, a configuration in which the scan line 12b and control line 15c do not overlap with the power supply line 16 in a plan view specifically refers to a configuration in which the scan line 12 and control line 15 extend in a straight line in the X direction, similar to the power supply line 16.

[0066] Figure 11 is a partial cross-sectional view of the electro-optical device 10 broken along line Aa in Figure 8, and, like Figure 8, shows the wiring layers from the first to the third. As shown in the figure, the first insulating layer 181, the first wiring layer Ly1, the second insulating layer 182, the second wiring layer Ly2, the third insulating layer 183, the third wiring layer Ly3, and the fourth insulating layer 184 are laminated on the insulating substrate in that order. As described above, control lines 15a, scan lines 12a, and power supply lines 16 are provided by patterning the first wiring layer Ly1, relay wiring P3, scan lines 12b, and relay wiring P4 are provided by patterning the second wiring layer Ly2, and control lines 15c are provided by patterning the third wiring layer Ly3.

[0067] Scan line 12a is connected to one end of scan line 12b via a contact hole H2a that opens in the second insulating layer 182, and the other end of scan line 12b is connected to scan line 12b in the pixel cluster 60 to the right in Figure 7 via a contact hole H2b that opens in the second insulating layer 182.

[0068] The control line 15a is connected to the relay wiring P3 via a contact hole H5a that opens in the second insulating layer 182, and the relay wiring P3 is connected to one end of the control line 15c via a contact hole H5c that opens in the third insulating layer 183. The other end of the control line 15c is connected to the relay wiring P4 via a contact hole H5d that opens in the third insulating layer 183, and the relay wiring P4 is connected to the control line 15a in the pixel cluster 60 to the right in Figure 7 via a contact hole H5b that opens in the second insulating layer 182. Furthermore, in a plan view, parts of the scan lines 12b and control lines 15c overlap with the power supply line 16.

[0069] Figure 9 is a plan view showing the configuration of the vertical wiring section 164. In the vertical wiring section 164, data lines 14Rb are provided by the patterning of the first wiring layer. Data line 14Rb is a connection in the vertical wiring section 164 that relays data line 14Ra in the upper adjacent pixel cluster section 60 and data line 14Ra in the lower adjacent pixel cluster section 60.

[0070] In the pixel cluster section 60, a portion of the data lines 14Ra provided by the patterning of the second wiring layer is extended to the vertical wiring section 164. The data line 14Rb has a shape in which the portion along the boundary separating it from the upper adjacent pixel cluster 60, the portion that overlaps with the data line 14G in a plan view, and the portion along the boundary separating it from the lower adjacent pixel cluster 60 are patterned together as a single unit. One end of data line 14Rb is connected to data line 14Ra, which extends from the adjacent pixel cluster 60 above, via a contact hole Hra. The other end of data line 14Rb is connected to data line 14Ra, which extends from the adjacent pixel cluster 60 below, via a contact hole Hrb. Therefore, in the diagram, data line 14R is shared in one row of pixel cluster 60 by a repeating pattern of data lines 14Ra and 14Rb in the Y direction.

[0071] In the vertical wiring section 164, data lines 14G are provided by the patterning of the second wiring layer. As described above, the data lines 14G are common to all pixel cluster sections 60 included in one row and are provided in a straight line along the Y direction by the patterning of only the second wiring layer. Therefore, the data lines 14G are provided as extensions from adjacent pixel cluster sections 600 in the Y direction.

[0072] In the vertical wiring section 164, data lines 14Bb are provided by the patterning of the third wiring layer. Data line 14Bb is a connection in the vertical wiring section 164 that relays data line 14Ba in the upper adjacent pixel cluster section 60 and data line 14Ba in the lower adjacent pixel cluster section 60.

[0073] In the pixel cluster section 60, a portion of the data lines 14Ba provided by the patterning of the second wiring layer is extended to the vertical wiring section 164. The data line 14Bb has a shape in which the portion along the boundary separating it from the upper adjacent pixel cluster 60, the portion that overlaps with the data line 14G in a plan view, and the portion along the boundary separating it from the lower adjacent pixel cluster 60 are patterned together as a single unit. One end of data line 14Bb is connected to data line 14Ba, which extends from the adjacent pixel cluster 60 above, via contact hole Hba. The other end of data line 14Bb is connected to data line 14Ba, which extends from the adjacent pixel cluster 60 below, via contact hole Hbb. Therefore, in the diagram, data line 14B is shared in one row of pixel cluster 60 by a repeating pattern of data lines 14Ba and 14Bb in the Y direction.

[0074] Thus, in the vertical wiring section 164, a portion of the data lines 14Rb and 14Bb overlap with the straight data line 14G in a plan view. Therefore, in this embodiment, a larger area of ​​light transmission can be secured in the vertical wiring section 164 compared to a configuration in which the data lines 14Rb and 14Bb do not overlap with the data line 14G in a plan view. The configuration in which data lines 14Rb and 14Bb do not overlap with data line 14G in a plan view refers, for example, to a configuration in which data lines 14R and 14B extend in a straight line in the Y direction, similar to data line 14G. The vertical wiring section 164 is provided in the region between pixel cluster sections 60 that are spaced apart from each other in the Y direction, and the wiring constituting data line 14G, data line 14R and 14B is provided in the vertical wiring section 164. The vertical wiring section 164 corresponds to the "data line wiring section" as referred to in the claims.

[0075] Figure 12 is a partial cross-sectional view of the electro-optical device 10 broken along line Bb in Figure 9, and, like Figure 9, shows the wiring layers from the first to the third. As described above, data line 14Rb is provided by patterning the first wiring layer Ly1, data lines 14Ra, 14G, and 14Ba are provided by patterning the second wiring layer Ly2, and data line 14Bb is provided by patterning the third wiring layer Ly3.

[0076] Data line 14Ra is connected to data line 14Rb located in the lower layer via a contact hole Hrb that opens in the first insulating layer 181. A portion of data line 14Rb overlaps with data line 14G in a plan view. On the other hand, data line 14Ba is connected to data line 14Bb located in the upper layer via a contact hole Hba that opens in the second insulating layer 182. A portion of data line 14Bb overlaps with data line 14G in a plan view.

[0077] Figure 10 is a plan view showing the configuration of the transparent section 170. As shown in the figure, the transparent section 170 does not have a semiconductor layer or wiring layer. Therefore, the transparent section 170 can secure a larger area for light transmission compared to the horizontal wiring section 162 or the vertical wiring section 164 where wiring exists.

[0078] Therefore, in this embodiment, a large area for light transmission is secured not only in the transparent section 170 but also in the horizontal wiring section 162 and the vertical wiring section 164, making it possible to superimpose the real world in a bright, see-through state onto the image displayed by the electro-optical device 10.

[0079] In this embodiment, the scan lines 12 are shared in one row of pixel cluster 60 by a repeating pattern of scan lines 12a and scan lines 12b connected via contact holes in the X direction. Similarly, the control lines 15 are shared in one row of pixel cluster 60 by a repeating pattern of control line 15a, relay wiring P3, control line 15c and relay wiring P4 connected via contact holes in the X direction. In contrast, the power supply line 16 is formed in a straight line without passing through contact holes and is shared by one row of pixel clusters 60, thus enabling low resistance for the power supply line 16 that supplies the voltage Vel, which is the power supply for the OLED 130. Therefore, the voltage drop due to the resistance component of the power supply line 16 is suppressed, making it possible to prevent a decrease in display quality due to voltage Vel fluctuations within the display area 100.

[0080] Generally, if the loads such as resistance and parasitic capacitance on data lines 14R, 14G, and 14B are not uniform, the brightness of one row will differ in the displayed image, specifically appearing as vertical lines, thus degrading the display quality. In this embodiment, data line 14R is shared in one row of pixel circuits 600R, data line 14G is shared in one row of pixel circuits 600G, and data line 14B is shared in one row of pixel circuits 600B. In addition, in this embodiment, in the vertical wiring section 164, data lines 14R, 14G, and 14B of the same series overlap in a plan view. Therefore, in this embodiment, the load on each color of data lines 14R, 14G, and 14B is more easily aligned, thus preventing a decrease in display quality caused by different loads.

[0081] In this embodiment, transistor 124 is located between transistor 121 and OLED 130, but it can be located at any point along the path from the power supply line 16 through OLED 130 to the common electrode 118.

[0082] In this embodiment, three transistors, 121, 122, and 124, are provided in the pixel circuit 600R, 600G, or 600B, but transistor 124 can be omitted. Even in a configuration in which transistor 124 is omitted in the pixel circuit 600R, 600G, or 600B, the power supply line 16 and the scan line 12 are provided, so in the lateral wiring section 162, the area through which light is transmitted can be secured by overlapping the power supply line 16 and the scan line 12b in a plan view, compared to a configuration in which they do not overlap.

[0083] The number of transistors constituting the pixel circuits 600R, 600G, and 600B may be four or more. For example, a compensation transistor may be provided to connect / disconnect the source node and drain node of transistor 121 in order to compensate for the threshold value of transistor 121, or a reset transistor may be provided to reset the anode potential of OLED 130. Whether it is a compensation transistor or a reset transistor, a separate control line can be provided in the lateral wiring section 162 in the same way as the scan line 12 or control line 15, so as to overlap with the power supply line 16 in a plan view.

[0084] Next, an electronic device to which the electro-optical device 10 according to the embodiment is applied will be described. The electro-optical device 10 has small pixels, high resolution, and is suitable for transmissive display. Therefore, a head-mounted display will be used as an example of an electronic device in the description.

[0085] Figure 13 shows the external appearance of the head-mounted display, and Figure 14 shows its optical configuration.

[0086] First, as shown in Figure 13, the head-mounted display 300 has, externally, the same features as ordinary eyeglasses, including temples 310, a bridge 320, and lenses 301L and 301R. Furthermore, as shown in Figure 14, the head-mounted display 300 is equipped with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the bridge 320, behind (below in the figure) the lenses 301L and 301R.

[0087] The display surfaces of the electro-optical device 10L and the electro-optical device 10R are perpendicular to the direction in which the wearer of the head-mounted display 300 faces directly. In this configuration, the wearer can observe the images displayed by the electro-optical devices 10L and 10R in a see-through state, superimposed on the outside view. Furthermore, in this head-mounted display 300, if the left-eye image is displayed by the electro-optical device 10L and the right-eye image is displayed by the electro-optical device 10R, the wearer can perceive the displayed images as if they had depth and three-dimensionality. In reality, optical systems such as lenses are provided to efficiently allow viewing of the displays from the electro-optical device 10L and the electro-optical device 10R, but the illustration of the optical system is omitted to avoid complicating the drawing.

[0088] Furthermore, the electronic device including the electro-optical device 10 can be applied not only to the head-mounted display 300, but also to electronic viewfinders in video cameras and interchangeable-lens digital cameras, and to transmissive display units such as smartwatches and wearable devices.

[0089] From the forms exemplified above, the following aspects can be understood, for example.

[0090] An electro-optical apparatus according to one embodiment 1 includes a power supply line provided along a first direction, a scanning line provided along the power supply line, a first data line provided along a second direction intersecting the first direction, a second data line provided along the second direction, a first pixel circuit provided corresponding to the intersection of the scanning line and the first data line, a second pixel circuit provided corresponding to the intersection of the scanning line and the second data line, and a light-transmitting power supply line wiring section provided in a region between the first pixel circuit and the second pixel circuit in the first direction in a plan view, wherein the power supply line and the scanning line are provided in the power supply line wiring section, the first pixel circuit includes a first transistor, a second transistor and a first light-emitting element, and the second pixel circuit includes a third transistor The device includes a scanner, a fourth transistor, and a second light-emitting element, wherein the second transistor is turned on or off in accordance with the voltage of the scan line between the first data line and the first gate node of the first transistor, the fourth transistor is turned on or off in accordance with the voltage of the scan line between the second data line and the second gate node of the third transistor, the first transistor controls the current flowing from the power supply line to the first light-emitting element in accordance with the voltage of the first gate node, the third transistor controls the current flowing from the power supply line to the second light-emitting element in accordance with the voltage of the second gate node, and in the power supply line wiring section, the power supply line and the scan line overlap in a plan view.

[0091] In the electro-optical apparatus according to Embodiment 1, the power supply line and the scanning line along the first direction overlap in a plan view between the first pixel circuit and the second pixel circuit. Compared to a configuration in which they do not overlap, a larger area can be secured for light to pass through from the outside.

[0092] In Embodiment 1, the X direction is an example of a "first direction," and the Y direction is an example of a "second direction." "B provided along A" means that the entirety of B does not need to be provided along A, but that a part of B is provided along A. A data line 14G corresponding to a certain pixel cluster 60 is an example of a "first data line," and a data line 14G corresponding to a pixel cluster 60 located to the right of that pixel cluster 60 is an example of a "second data line." A pixel circuit 600G included in a certain pixel cluster 60 is an example of a "first pixel circuit," and a pixel circuit 600G included in a pixel cluster 60 located to the right of that pixel cluster 60 is an example of a "second pixel circuit." Transistor 121 is an example of the "first transistor" and "third transistor," and transistor 122 is an example of the "second transistor" and "fourth transistor." OLED 130 is an example of a "light-emitting element."

[0093] An electro-optical apparatus according to a specific embodiment 2 of embodiment 1 further includes a control line provided along the power supply line, the control line provided in the power supply line wiring section, the first pixel circuit having a fifth transistor between the power supply line and the first light-emitting element, the second pixel circuit having a sixth transistor between the power supply line and the second light-emitting element, the fifth transistor and the sixth transistor being on or off depending on the voltage of the control line, the first transistor controlling the current flowing to the first light-emitting element when the fifth transistor is on, the third transistor controlling the current flowing to the second light-emitting element when the sixth transistor is on, and in the power supply line wiring section, the power supply line and the control line overlap in a plan view.

[0094] According to the electro-optical device of embodiment 2, between the first pixel circuit and the second pixel circuit, the power supply line and the scanning line are aligned in the same direction, and the power supply line also overlaps with them in a plan view. Therefore, even in a configuration in which the fifth transistor and the sixth transistor control the light emission period of the light-emitting element, a large area can be secured through which light from the outside world is transmitted. Transistor 124 is an example of the "fifth transistor" and the "sixth transistor".

[0095] In an electro-optical apparatus according to another specific embodiment 3 of embodiment 1, the power supply line is formed in a single wiring layer in a straight line along the first direction from the first pixel circuit to the second pixel circuit. According to the electro-optical device of embodiment 3, the resistance of the power supply line is reduced, so the deterioration of display quality caused by voltage drop in the power supply line can be suppressed. Furthermore, "formed with a single wiring layer" means that the wiring, which consists of multiple wiring layers, is formed by the patterning of a single wiring layer, without connecting them with contact holes.

[0096] An electro-optical apparatus according to one embodiment 4 includes a power supply line provided along a first direction, a first scan line provided along the power supply line, a second scan line provided along the power supply line, a first data line provided along a second direction intersecting the first direction, a second data line provided along the second direction, a first pixel circuit provided corresponding to the intersection of the first scan line and the first data line, a second pixel circuit provided corresponding to the intersection of the first scan line and the second data line, and a third pixel circuit provided corresponding to the intersection of the second scan line and the first data line. The device includes, a fourth pixel circuit provided corresponding to the intersection of the second scan line and the second data line, and a data line wiring section that transmits light, provided in a plan view in the region between the first pixel circuit and the second pixel circuit and the third pixel circuit and the fourth pixel circuit in the second direction, wherein the first pixel circuit includes a first transistor, a second transistor and a first light-emitting element, the second pixel circuit includes a third transistor, a fourth transistor and a second light-emitting element, and the third pixel circuit includes a fifth transistor, a sixth transistor and a third light-emitting element. The optical element is included, and the fourth pixel circuit includes a seventh transistor, an eighth transistor and a fourth light-emitting element, the second transistor is turned on or off in accordance with the voltage of the first scan line between the first data line and the first gate node of the first transistor, the fourth transistor is turned on or off in accordance with the voltage of the first scan line between the second data line and the second gate node of the third transistor, the sixth transistor is turned on or off in accordance with the voltage of the second scan line between the first data line and the third gate node of the fifth transistor, the eighth transistor is turned on or off in accordance with the voltage of the second scan line between the second data line and the fourth gate node of the seventh transistor, the first transistor controls the current flowing from the power supply line to the first light-emitting element in accordance with the voltage of the first gate node, the third transistor controls the current flowing from the power supply line to the second light-emitting element in accordance with the voltage of the second gate node, and the fifth transistor,The current flowing from the power supply line to the third light-emitting element is controlled according to the voltage of the third gate node, and the seventh transistor controls the current flowing from the power supply line to the fourth light-emitting element according to the voltage of the fourth gate node, and in the data line wiring section, the first data line and the second data line overlap in a plan view.

[0097] In the electro-optical apparatus according to Embodiment 4, the first data line and the second data line along the Y direction overlap in a plan view between the first and second pixel circuits and the third and fourth pixel circuits. Therefore, compared to a configuration in which they do not overlap, a larger area can be secured for light to pass through from the outside.

[0098] In embodiment 4, a data line 14R corresponding to a certain pixel cluster 60 is an example of a "first data line," and a data line 14B corresponding to the same pixel cluster 60 is an example of a "second data line." Furthermore, a scan line 12 corresponding to a certain pixel cluster 60 is an example of a "first scan line," and a scan line 12 corresponding to a pixel cluster 60 located immediately below the said pixel cluster 60 is an example of a "second scan line." Pixel circuits 600R and 600B included in a certain pixel cluster 60 are examples of the "first pixel circuit" and "second pixel circuit," respectively, and pixel circuits 600R and 600B included in the pixel cluster 60 located immediately below the said pixel cluster 60 are examples of the "third pixel circuit" and "fourth pixel circuit," respectively. Transistor 121 is an example of the "first transistor," "third transistor," "fifth transistor," and "seventh transistor," and transistor 122 is an example of the "second transistor," "fourth transistor," "sixth transistor," and "eighth transistor."

[0099] In the electro-optical apparatus according to a specific embodiment 5 of embodiment 4, the first light-emitting element and the third light-emitting element correspond to the first color light, and the second light-emitting element and the fourth light-emitting element correspond to the second color light. According to the electro-optical apparatus of embodiment 5, since the data lines correspond to the same color light, the loads such as resistance and parasitic capacitance in the data lines can be matched for each color. Furthermore, the statement that a light-emitting element corresponds to the first color of light includes cases where the light-emitting element emits white light, which is then filtered through a color filter to emit the first color of light, or cases where the light-emitting element emits the first color of light.

[0100] The electronic device according to embodiment 6 has an electro-optical device according to any of embodiments 1 to 4. [Explanation of symbols]

[0101] 10... Electro-optical device, 12... Scanning line, 14R, 14G, 14B... Data line, 15... Control line, 16... Power supply line, 60... Pixel cluster section, 121, 122, 124... Transistor, 162... Horizontal wiring section, 164... Vertical wiring section, 170... Transmissive section, 300... Head-mounted display, 600R, 600G, 600B... Pixel circuit.

Claims

1. A power supply line provided along the first direction, A scanning line provided along the aforementioned power supply line, A first data line is provided along a second direction intersecting the first direction, A second data line provided along the second direction, A first pixel circuit is provided corresponding to the intersection of the scan line and the first data line, A second pixel circuit is provided corresponding to the intersection of the scan line and the second data line, In a plan view, a power supply line wiring section is provided in the region between the first pixel circuit and the second pixel circuit in the first direction, and which transmits light. Includes, The power supply line and the scanning line are provided in the power supply line wiring section. The first pixel circuit is, It includes a first transistor, a second transistor, and a first light-emitting element, The second pixel circuit is, It includes a third transistor, a fourth transistor, and a second light-emitting element, The second transistor is switched on or off between the first data line and the first gate node of the first transistor, depending on the voltage of the scan line. The fourth transistor is switched on or off between the second data line and the second gate node of the third transistor, depending on the voltage of the scan line. The first transistor controls the current flowing from the power supply line to the first light-emitting element according to the voltage at the first gate node. The third transistor controls the current flowing from the power supply line to the second light-emitting element according to the voltage at the second gate node. In the aforementioned power supply line wiring section, the power supply line and the scanning line overlap in a plan view. Electro-optical device.

2. The control lines provided along the aforementioned power supply lines further include, The control line is provided in the power supply line wiring section, The first pixel circuit has a fifth transistor between the power supply line and the first light-emitting element, The second pixel circuit has a sixth transistor between the power supply line and the second light-emitting element, The fifth transistor and the sixth transistor turn on or off depending on the voltage of the control line. The first transistor controls the current flowing to the first light-emitting element when the fifth transistor is in the ON state. The third transistor controls the current flowing to the second light-emitting element when the sixth transistor is in the ON state. In the aforementioned power supply line wiring section, In a plan view, the power supply line and the control line overlap. The electro-optical apparatus according to claim 1.

3. The power supply line is formed in a single wiring layer in a straight line along the first direction from the first pixel circuit to the second pixel circuit. The electro-optical apparatus according to claim 1.

4. A power supply line provided along the first direction, A first scanning line provided along the aforementioned power supply line, A second scanning line provided along the aforementioned power supply line, A first data line is provided along a second direction intersecting the first direction, A second data line provided along the second direction, A first pixel circuit is provided corresponding to the intersection of the first scan line and the first data line, A second pixel circuit is provided corresponding to the intersection of the first scan line and the second data line, A third pixel circuit is provided corresponding to the intersection of the second scan line and the first data line, A fourth pixel circuit is provided corresponding to the intersection of the second scan line and the second data line, In a plan view, a data line wiring section that transmits light is provided in the region between the first pixel circuit and the second pixel circuit and the third pixel circuit and the fourth pixel circuit in the second direction, Includes, The first pixel circuit is, It includes a first transistor, a second transistor, and a first light-emitting element, The second pixel circuit is, It includes a third transistor, a fourth transistor, and a second light-emitting element, The aforementioned third pixel circuit is It includes a fifth transistor, a sixth transistor, and a third light-emitting element, The aforementioned fourth pixel circuit is It includes a seventh transistor, an eighth transistor, and a fourth light-emitting element, The second transistor is turned on or off in response to the voltage of the first scan line between the first data line and the first gate node of the first transistor. The fourth transistor is turned on or off in response to the voltage of the first scan line between the second data line and the second gate node of the third transistor. The sixth transistor is turned on or off in response to the voltage of the second scan line between the first data line and the third gate node of the fifth transistor. The eighth transistor is switched on or off between the second data line and the fourth gate node of the seventh transistor, depending on the voltage of the second scan line. The first transistor controls the current flowing from the power supply line to the first light-emitting element according to the voltage at the first gate node. The third transistor controls the current flowing from the power supply line to the second light-emitting element according to the voltage at the second gate node. The fifth transistor controls the current flowing from the power supply line to the third light-emitting element according to the voltage of the third gate node. The seventh transistor controls the current flowing from the power supply line to the fourth light-emitting element according to the voltage of the fourth gate node. In the data line wiring section, the first data line and the second data line overlap in a plan view. Electro-optical device.

5. The first light-emitting element and the third light-emitting element correspond to the first color light, The second light-emitting element and the fourth light-emitting element correspond to the second color light, The electro-optical apparatus according to claim 4.

6. An electronic device having an electro-optical device according to any one of claims 1 to 5.

Images