Display panel dual drive architecture and switching method thereof

Abstract

The application discloses a display panel double-driving architecture and a switching method thereof. The display panel double-driving architecture comprises a plurality of pixel units arranged in an array, a plurality of scan lines arranged in a row direction, the scan lines comprising even-numbered row scan lines and odd-numbered row scan lines, and being used for outputting scan signals to the pixel units in each row, and a plurality of data lines arranged in a column direction, the data lines comprising even-numbered column data lines and odd-numbered column data lines, and being used for outputting data signals to the pixel units in each column. The display panel double-driving architecture comprises a driving switching module, and the driving switching module is used for realizing the switching between a first driving architecture and a second driving architecture of the display panel double-driving architecture. Through the above structure, the driving switching in the display panel is realized, and the shortcomings of a single driving architecture are made up.

Description

Technical Field

[0001] This invention relates to the field of display panels, and in particular to a dual-drive architecture for display panels and a switching method thereof. Background Technology

[0002] In liquid crystal displays (LCDs), the driving voltage applied to the liquid crystal molecules must be reversed periodically to prevent polarization of the liquid crystal material and permanent damage, as well as to avoid image retention effects. Therefore, various polarity reversal methods have been proposed, including frame reversal, row reversal, column reversal, and dot reversal. Frame reversal, row reversal, and column reversal, due to their large areas of uniform polarity, can cause asymmetry in polarity when the VCOM voltage shifts, resulting in noticeable screen flicker. Dot reversal effectively solves screen flicker, but it drastically increases the screen size.

[0003] Currently, LCD monitor architectures are mainly divided into Strip architecture and FLIP architecture. In Strip architecture, sub-pixels of the same color in the same column transmit pixel information via a single data line. In this architecture, column flipping causes severe strain on the VCOM of that column, leading to flickering and noticeable crosstalk. FLIP architecture, on the other hand, can achieve pixel flipping using column flipping, simultaneously solving both flickering and power consumption issues. However, with current large-size, high-refresh-rate monitors, insufficient charging can cause bright and dark lines on the screen.

[0004] Therefore, both Strip and FLIP drive architectures have their own advantages and disadvantages, and combining these two drive mechanisms can achieve complementarity. Summary of the Invention

[0005] The main technical problem addressed by this application is to provide a dual-drive architecture for a display panel and a switching method thereof, so as to realize the mutual switching between the two drive architectures and make up for the shortcomings of a single drive architecture.

[0006] To address the aforementioned problems, this application provides a dual-drive architecture for a display panel, comprising multiple pixel units arranged in an array; multiple scan lines arranged along the row direction, including even-numbered row scan lines and odd-numbered row scan lines, for outputting scan signals to the pixel units in each row; and multiple data lines arranged along the column direction, including even-numbered column data lines and odd-numbered column data lines, for outputting data signals to the pixel units in each column; wherein the dual-drive architecture includes a drive switching module, which is used to switch between a first drive architecture and a second drive architecture of the dual-drive architecture; wherein, in the first drive architecture, the odd-numbered row scan lines are used to output scan signals to the pixel units in the odd-numbered rows. In the first driving architecture, the even-numbered row scan lines are used to output scan signals to the even-numbered pixel units, the odd-numbered column data lines are used to output data signals to the odd-numbered pixel units, and the even-numbered column data lines are used to output data signals to the even-numbered pixel units.

[0007] The drive switching module includes adding multiple first scan lines corresponding to the even-numbered row scan lines or the odd-numbered row scan lines in the first drive architecture. The first scan lines connect the pixel units in the even-numbered or odd-numbered rows to the data lines in the next column of the current column, and are used to control the data lines to transmit data voltage to the pixel units in the previous column, so as to realize the switching between the first drive architecture and the second drive architecture.

[0008] The drive switching module includes multiple first switching units. Each first switching unit is connected to the even-numbered scan line and the first scan line corresponding to the even-numbered scan line, and is used to control the transmission of scan signals to the first scan line or the even-numbered scan line; or it is connected to the odd-numbered scan line and the first scan line corresponding to the odd-numbered scan line, and is used to control the transmission of scan signals to the first scan line or the odd-numbered scan line.

[0009] Each of the first switching units includes a first transistor and a second transistor. The first terminals of the first transistor and the second transistor are connected to the same scan signal line. The second terminal of the first transistor is connected to the even-numbered scan line or the odd-numbered scan line. The second terminal of the second transistor is connected to the first scan line. The switching of the scan signal line from transmitting a scan signal to the even-numbered scan line or the odd-numbered scan line to transmitting a scan signal to the first scan line is achieved by controlling the on / off state of the first transistor and the second transistor.

[0010] The drive switching module includes adding a first data line corresponding to each data line in the first drive architecture; the first data line corresponding to the odd-numbered column data line is connected to the pixel units of the odd-numbered rows of the odd-numbered column and the pixel units of the even-numbered rows of the even-numbered column, and the first data line corresponding to the even-numbered column data line is connected to the pixel units of the odd-numbered rows of the even-numbered column and the pixel units of the even-numbered rows of the odd-numbered column, and the switching between the first drive architecture and the second drive architecture is realized by switching the data line and the first data line.

[0011] The drive switching module includes multiple second switching units, each of which is connected to the data line and a first data line corresponding to the data line, so as to realize the switching between the data line and the first data line.

[0012] The second switching unit includes a third transistor and a fourth transistor. The first ends of the third transistor and the fourth transistor are connected to the data signal line, the second end of the third transistor is connected to the data line, and the second end of the fourth transistor is connected to the first data line. The switching between transmitting data signals from the data signal line to the data line and transmitting data signals to the first data line is achieved by controlling the on / off state of the third transistor and the fourth transistor.

[0013] This application also provides a method for switching a dual-drive architecture for a display panel, the dual-drive architecture including a first display panel drive architecture and a second display panel drive architecture, wherein the switching method includes: obtaining a drive mode of the dual-drive architecture; wherein the drive mode includes a first drive mode using the first drive architecture and a second drive mode using the second drive architecture; transmitting scan signals sequentially through the odd-numbered row scan lines to the pixel units in the odd-numbered rows according to the first drive mode, and transmitting scan signals through the even-numbered row scan lines to the pixel units in the even-numbered rows, and transmitting scan signals through the odd-numbered column data lines. Data signals are transmitted to the pixel units in the odd-numbered columns, and data signals are transmitted to the pixel units in the even-numbered columns via the data lines in the even-numbered columns; or, according to the second driving mode, scan signals are transmitted sequentially through the odd-numbered row scan lines to the pixel units in the odd-numbered rows, the even-numbered row scan lines to the pixel units in the even-numbered rows, the odd-numbered column data lines to the pixel units in the odd-numbered columns and to the pixel units in the even-numbered columns, and the even-numbered column data lines to the pixel units in the odd-numbered columns and to the pixel units in the even-numbered columns.

[0014] The step of obtaining the driving mode of the dual-drive architecture of the display panel includes: detecting whether the display screen of the display panel is flickering or has bright and dark lines; if the display panel is flickering, then obtaining the second driving mode; if the display panel has bright and dark lines, then obtaining the first driving mode.

[0015] The dual-drive architecture of the display panel includes a first switching unit, which includes a first transistor and a second transistor. The switching method includes selecting to turn on the first transistor or the second transistor according to the driving mode, so as to achieve mutual switching between driving the display panel according to the first driving mode and driving the display panel according to the second driving mode.

[0016] The dual-drive architecture of the display panel includes a second switching unit, which includes a third transistor and a fourth transistor. The switching method includes selecting to turn on the third transistor or the fourth transistor according to the driving mode, so as to achieve mutual switching between driving the display panel according to the first driving mode and driving the display panel according to the second driving mode.

[0017] The beneficial effects of this application are: the dual-drive architecture of the display panel includes a first drive architecture formed by scan lines, data lines and pixel units, and the dual-drive architecture of the display panel also includes a drive switching module that forms a second drive architecture with some scan lines, data lines and pixel units, and the switching unit in the drive switching module realizes the switching between the first drive architecture and the second drive architecture, thereby making up for the deficiencies of a single drive architecture and improving the display effect. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of an embodiment of the first driving architecture of this application;

[0020] Figure 2 This is a schematic diagram of a specific embodiment of the pixel circuit in the pixel unit of this application;

[0021] Figure 3 This is a schematic diagram of the structure of an embodiment of the second driving architecture of this application;

[0022] Figure 4 This is a schematic diagram of another embodiment of the second drive architecture of this application;

[0023] Figure 5 This is a schematic diagram of the structure of the first embodiment of the dual-drive architecture for the display panel in this application;

[0024] Figure 6 This is a schematic diagram of the structure of the first specific embodiment of the drive switching module of this application;

[0025] Figure 7 This is a schematic diagram of the structure of the second embodiment of the dual-drive architecture for the display panel in this application;

[0026] Figure 8 This is a schematic diagram of the structure of the third embodiment of the dual-drive architecture for the display panel in this application;

[0027] Figure 9 This is a schematic diagram of the structure of the second specific embodiment of the drive switching module of this application;

[0028] Figure 10 This is a schematic diagram of the structure of the fourth embodiment of the dual-drive architecture for the display panel in this application;

[0029] Figure 11This is a flowchart illustrating an embodiment of the switching method for the dual-drive architecture of the display panel in this application;

[0030] Figure 12 For this application Figure 11 A flowchart illustrating a further embodiment of step S101.

[0031] 10 pixel unit; 11 sub-pixels; G scan line; G' first scan line; D data line; D' first data line; 101 first switching unit; 102 second switching unit; T1 first transistor; T2 second transistor; T3 third transistor; T4 fourth transistor. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0034] It should be understood that the term "and / or" used herein is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0035] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0036] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0037] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0038] This application provides a dual-drive architecture for a display panel, wherein the dual-drive architecture includes at least a plurality of pixel units 10 arranged in an array. Multiple scan lines G arranged along the row direction, including G1-Gn (where n is a positive integer), include odd-numbered row scan lines (G1, G3, G5, ...) and even-numbered row scan lines (G2, G4, G6, ...), wherein the scan lines G are used to output scan signals to the pixel units 10 in each row. And multiple data lines D arranged along the column direction, including D1-Dm (where m is a positive integer), include odd-numbered row data lines (D1, D3, D5, ...) and even-numbered row data lines (D2, D4, D6, ...), wherein the data lines D are used to output data signals to the pixel units 10 in each column.

[0039] In this embodiment, the scan line G, the data line D, and the pixel unit 10 can selectively form a first driving architecture and a second driving architecture. The dual driving architecture of the display panel includes a driving switching module, which is used to switch between the first driving architecture and the second driving architecture in the dual driving architecture of the display panel.

[0040] Please refer to the details. Figure 1 , Figure 1 This is a schematic diagram of a first driving architecture embodiment of the present application. The first driving architecture includes a plurality of pixel units 10 arranged in an array, scan lines G arranged along the row direction, and data lines D arranged along the column direction. Figure 1As shown, odd-numbered row scan lines G are connected to pixel units 10 in odd-numbered rows, even-numbered row scan lines G are connected to pixel units 10 in even-numbered rows, odd-numbered column data lines D are connected to pixel units 10 in odd-numbered columns, and even-numbered column data lines D are connected to pixel units 10 in even-numbered columns, thus forming a first driving architecture. In this first driving architecture, odd-numbered row scan lines G transmit scan signals to pixel units 10 in odd-numbered rows, even-numbered row scan lines G transmit scan signals to pixel units 10 in even-numbered rows, odd-numbered column data lines D transmit data signals to pixel units 10 in odd-numbered columns, and even-numbered column data lines D transmit data signals to pixel units 10 in even-numbered columns. Furthermore, in this first driving architecture, the data signals transmitted by adjacent columns of data lines have opposite polarities; that is, the data signals transmitted by odd-numbered column data lines and even-numbered column data lines have opposite polarities.

[0041] Specifically, each pixel unit 10 includes a sub-pixel and pixel circuits connected to the sub-pixel. See [link to details]. Figure 2 , Figure 2 This is a schematic diagram of a specific embodiment of the pixel circuit in the pixel unit of this application. Figure 2 As shown, each pixel unit includes at least one pixel transistor T0 and a sub-pixel 11. The gate of the pixel transistor T0 is connected to the scan line G, the source is connected to the data line D, and the drain is connected to the sub-pixel 11. The scan line G is used to control the pixel transistor T0 to turn on, so that the data voltage on the data line D charges the sub-pixel 11, thereby realizing light emission. In this specific pixel circuit, a storage capacitor Cst and a pixel capacitor Clc may also be included. Figure 1 (The details are omitted here). The storage capacitor Cst can be used to store the data voltage to power the sub-pixel 11 for emission. In other embodiments, the pixel circuit may also include other complex circuit structures, which are not limited here. The three primary color sub-pixels in pixel unit 10 can be arranged along the row direction or along the column direction; that is, R, G, and B can be arranged along the row direction or along the column direction, which is not limited here. Each sub-pixel is connected to a separate scan line and data line to receive different data voltages, achieving color (grayscale) display.

[0042] In the first driving architecture, each row of sub-pixels is activated by the same scan line G, and each column of sub-pixels is driven by the same data line D. This architecture uses a column-flipping method, meaning that within the current frame, the data of sub-pixels in the same column are of the same polarity, changing to a different polarity in the next frame. In this first driving architecture, when the common electrode voltage shifts, the positive and negative voltages of this column of sub-pixels become asymmetrical, resulting in uneven brightness and flickering.

[0043] Figure 3This is a schematic diagram of a second driving architecture embodiment of the present application. The second driving architecture includes a plurality of pixel units 10 arranged in an array, scan lines G arranged along the row direction, and data lines D arranged along the column direction. Figure 3 As shown, odd-numbered row scan lines G are connected to odd-numbered row pixel units 10, even-numbered row scan lines G are connected to even-numbered row pixel units 10, odd-numbered column data lines D are connected to the pixel units 10 of the current odd-numbered column and the pixel units 10 of the previous even-numbered column, and even-numbered column data lines D are connected to the pixel units 10 of the current even-numbered column and the pixel units 10 of the previous even-numbered column, thus forming a second driving architecture. In this second driving architecture, odd-numbered row scan lines G transmit scan signals to the pixel units 10 of odd-numbered rows, even-numbered row scan lines G transmit scan signals to the pixel units 10 of even-numbered rows, odd-numbered column data lines D transmit data signals to the pixel units 10 of the current odd-numbered column and the previous even-numbered column, and even-numbered column data lines D transmit data signals to the pixel units 10 of the current even-numbered column and the previous even-numbered column, thus forming a Z-shaped second driving architecture. In another specific embodiment, the odd-numbered column data lines can be connected to the even-numbered row pixel units 10 of the odd-numbered columns and the odd-numbered row pixel units 10 of the even-numbered columns. Similarly, the even-numbered column data lines can be connected to the even-numbered row pixel units 10 of the even-numbered columns and the odd-numbered row pixel units 10 of the odd-numbered columns. In other words, pixel units in the same column are alternately connected to the data lines D of adjacent columns (even-numbered and odd-numbered columns). For specific connection methods, please refer to further details. Figure 4 , Figure 4 This is a schematic diagram of another embodiment of the second drive architecture of this application.

[0044] In the second driving architecture, taking the second column data line D2 as an example, the first row, second column data line D2 charges the sub-pixels of the second column, and the second row, second column data line D2 then charges the sub-pixels of the first column. Under the column-flip driving method, a single data line in the current frame delivers a voltage of the same polarity, while adjacent sub-pixels in the same column exhibit opposite polarities, thus achieving sub-pixel flipping through column flipping. In this driving architecture, there is a charging difference between pixels charging from bright to bright and from black to bright, resulting in brightness differences and consequently, the appearance of horizontal bright and dark lines.

[0045] Therefore, the first and second drive architectures each have their own advantages and disadvantages.

[0046] This application adds a drive switching module to the first or second drive architecture to add another drive architecture to the display panel, and realizes the mutual switching between the first and second drive architectures through the switching module.

[0047] In a first specific embodiment, the drive switching module includes adding multiple first scan lines G' corresponding to even-numbered scan lines G in the first drive architecture. See details below. Figure 5 , Figure 5 This is a schematic diagram of the structure of the first embodiment of the dual-drive architecture for the display panel in this application. Figure 5 As shown, multiple first scan lines G' corresponding to even-numbered row scan lines G are added to the first driving architecture. The first scan lines G' connect even-numbered row pixel units 10 to even-numbered column data lines D, controlling the even-numbered column data lines D to transmit data voltage to even-numbered row pixel units 10. This, together with the odd-numbered row scan lines G in the first driving architecture connecting odd-numbered column pixel units 10 to odd-numbered column data lines D, forms the second driving architecture. Switching between the first and second driving architectures is achieved by controlling the conduction of even-numbered row scan lines G and first scan lines G'. In this embodiment, odd-numbered row scan lines G connect odd-numbered column data lines D to odd-numbered row and odd-numbered column sub-pixels 11, and even-numbered column data lines D to even-numbered row and even-numbered column sub-pixels 11; even-numbered row scan lines G connect even-numbered column data lines D to even-numbered row and even-numbered column sub-pixels 11, and odd-numbered column data lines D to odd-numbered row and odd-numbered column sub-pixels 11, forming the first driving architecture. Odd-numbered row scan lines G connect odd-numbered column data lines D to sub-pixels 11 in odd-numbered columns and rows, and even-numbered column data lines D to sub-pixels 11 in even-numbered columns and odd-numbered rows; the first scan line G' corresponding to the even-numbered row scan line G connects even-numbered column data lines D to sub-pixels 11 in even-numbered columns and even-numbered rows, and odd-numbered column data lines D to sub-pixels 11 in odd-numbered columns and even-numbered rows, thus forming the second driving architecture. Specifically, in this embodiment, in the second driving architecture, the Mth column sub-pixel of the even-numbered row is connected to the (M+1)th column data line, while the Mth column sub-pixel of the odd-numbered row is connected to the Mth column data line. In other embodiments, the Mth column sub-pixel of the even-numbered row can also be connected to the (M-1)th column data line. That is, in the second driving architecture, the sub-pixels of the even-numbered rows and the sub-pixels of the odd-numbered rows are connected in a staggered manner, that is, adjacent rows of sub-pixels are connected to adjacent even-numbered column data lines and odd-numbered column data lines, respectively. In this embodiment, the subpixels of even-numbered rows are misaligned with those of odd-numbered rows. In other embodiments, the odd-numbered rows can also be misaligned with the even-numbered rows, meaning the connection relationships of the even-numbered rows remain unchanged while the connections of the odd-numbered rows are modified. Please refer to the second embodiment for details.

[0048] In this specific embodiment, the drive switching module includes multiple first switching units 101, for details please refer to [link / reference needed]. Figure 6 , Figure 6This is a schematic diagram of the structure of the first specific embodiment of the drive switching module of this application. Each switching unit 101 is connected to an even-numbered row scan line G and a first scan line G' corresponding to the even-numbered row scan line G, and is used to control the transmission of scan signals to the first scan line G' or the even-numbered row scan line G. The output terminal of each first switching unit 101 is connected to the even-numbered row scan line G (e.g., G2, G4, etc.) and the first scan line G' (e.g., G2' and G4', etc.), and the input terminal is connected to the same scan signal line Gate. The scan signal line Gate is located on one side of the display panel and sequentially inputs clock signals to each row of sub-pixels 11. Each scan signal line CLK and each scan line G in the display panel are also provided with a GOA circuit; other circuits can also be used, and are not limited here. The first switching unit 101 includes a first transistor T1 and a second transistor T2. Both transistors T1 and T2 include a first terminal, a second terminal, and a control terminal. The first terminals of both transistors T1 and T2 are connected to the same scan signal line CLK. The second terminal of the first transistor T1 is connected to an even-numbered scan line G, and the second terminal of the second transistor T2 is connected to a first scan line G'. The control terminals of both transistors T1 and T2 are connected to a control signal line with the opposite scan level signal. That is, when the first transistor T1 is on, the second transistor T2 is off; when the second transistor T2 is on, the first transistor T1 is off, thereby achieving the switching between the first driving architecture and the second driving architecture. In another specific embodiment, the control signals for the first transistor T1 and the second transistor T2 are opposite-type transistors, i.e., one is a P-type transistor and the other is an N-type transistor. The control terminals of the first transistor T1 and the second transistor T2 are connected to the same control signal line. When the control signal line outputs a high-level signal, one transistor is on and the other is off. This step is defined in this case. In other embodiments, the first transistor T1 and the second transistor T2 can also be replaced by a single-pole double-throw switch controlled by a logic signal, which is not limited here. In one specific embodiment, the first switching unit 101 may also be located at the output end of the GOA circuit, and the location is not limited here.

[0049] In another embodiment, multiple first scan lines corresponding to odd-numbered scan lines can be added to the first driving architecture. See details below. Figure 7 , Figure 7 This is a schematic diagram of the structure of the second embodiment of the dual-drive architecture for the display panel in this application. Figure 7As shown, multiple first scan lines G' corresponding to odd-numbered row scan lines G are added to the first driving architecture. The first scan lines G' connect the pixel units 10 of odd-numbered rows to the data lines D of even-numbered columns, controlling the transmission of data voltage from the even-numbered column data lines D to the pixel units 10 of odd-numbered rows. This, together with the even-numbered row scan lines G in the first driving architecture connecting the pixel units 10 of even-numbered columns to the data lines D of odd-numbered columns, forms the second driving architecture. Switching between the first and second driving architectures is achieved by controlling the conduction of the odd-numbered row scan lines G and the first scan lines G'. The driving switching module includes multiple first switching units, each connected to the odd-numbered row scan line G and the corresponding first scan line G', controlling the transmission of scan signals to either the first scan line G' or the odd-numbered row scan line G. The first switching unit includes a first transistor and a second transistor. The first terminals of the first transistor T1 and the second transistor T2 are connected to the same scan signal line G'. The second terminal of the first transistor T1 is connected to the odd-numbered scan line G. The second terminal of the second transistor T2 is connected to the odd-numbered scan line G. The second terminal of the second transistor T2 is connected to the first scan line G'. The switching of the scan signal line from transmitting a scan signal to the odd-numbered scan line G to transmitting a scan signal to the first scan line G' is achieved by controlling the on / off state of the first transistor T1 and the second transistor T2.

[0050] In this embodiment, by adding a first scan line at a position parallel to the scan line corresponding to the first driving architecture, the data lines connecting the sub-pixels in even-numbered rows to columns N+1 are staggered with the data lines connecting the sub-pixels in odd-numbered rows to columns N, forming a second driving architecture. The first switching unit of the driving switching module is then used to switch between the first driving architecture and the second driving architecture.

[0051] In another embodiment, multiple first scan lines can be set in the second driving architecture at positions corresponding to even-numbered or odd-numbered scan lines. That is, the positions of the first scan lines are interchanged with those of even-numbered or odd-numbered scan lines, which will not be described in detail here.

[0052] In another embodiment, the drive switching module includes adding a first data line D' corresponding to each data line D in the first drive architecture. See details below. Figure 8 , Figure 8 This is a schematic diagram of the structure of the third embodiment of the dual-drive architecture for the display panel in this application. Figure 8As shown, the first data line D' corresponding to the odd-numbered data line D is the odd-numbered first data line D', and the first data line D' corresponding to the even-numbered data line D is the even-numbered first data line D'. The first data line D' of the odd-numbered column is connected to the pixel unit 10 of the odd-numbered row of the odd-numbered column and to the pixel unit 10 of the even-numbered row of the even-numbered column; the first data line D' of the even-numbered column is connected to the pixel unit 10 of the even-numbered row of the odd-numbered column and to the pixel unit 10 of the odd-numbered row of the even-numbered column. The scan line G and the data line D form a first driving architecture, and the scan line G and the first data line D' form a second driving architecture; the switching between the first driving architecture and the second driving architecture is achieved by switching the data line D and the first data line D'. Specifically, taking the first data line D3' of the third column and the fourth data line D4' of the fourth column as examples, the first data line D3' of the third column is connected to the pixel unit of the odd row and odd column (the third column), and to the pixel unit of the even row and even column (the second column). The first data line D4' of the fourth column is connected to the pixel unit of the odd row and even column (the fourth column), and to the pixel unit of the even row and odd column (the third column). In other words, the first data line D' of the odd column is connected to the pixel unit 10 of the odd row of the current column, and also to the pixel unit 10 of the even row of the previous column. The first data line D' of the even column is connected to the pixel unit 10 of the even row of the current column, and also to the pixel unit 10 of the odd row of the previous column.

[0053] In this embodiment, the drive switching module includes multiple second switching units 102, each second switching unit 102 being connected to data line D and first data line D' respectively, and the switching between data line D and first data line D' is achieved through the second switching unit 102. For details of the drive switching module, please refer to [link to relevant documentation]. Figure 9 , Figure 9 This is a structural diagram of a second specific embodiment of the drive switching module of this application. (See diagram below.) Figure 9 As shown, the second switching unit 102 includes a third transistor T3 and a fourth transistor T4. The first terminals (input terminals) of the third transistor T3 and the fourth transistor T4 are connected to the data signal line DATE. The second terminal of the third transistor T3 is connected to the data line D. The second terminal of the fourth transistor T4 is connected to the first data line D'. By controlling the on / off state of the third transistor T3 and the fourth transistor T4, the data signal line D transmits data signals to the data line D or the first data line D'. This enables the switching of the data signal line DATE from transmitting data signals to the data line D to transmitting data signals to the first data line D', and from transmitting data signals to the first data line D' to transmitting data signals to the data line D.

[0054] In another embodiment, the drive switching module further includes adding a first data line D' corresponding to each data line in the second drive architecture, as detailed in the following example. Figure 10 , Figure 10This is a schematic diagram of the fourth embodiment of the dual-drive architecture for the display panel in this application. Figure 10 As shown, the newly added first data line D' of the current column is connected to the sub-pixel 11 of the current column. That is, the first data line D' of the odd column is connected to the pixel unit of the odd column (including odd rows and even rows), and the first data line D' of the even column is connected to the pixel unit of the even column (including odd rows and even rows).

[0055] It should be noted that in the third and fourth embodiments, the pixel units 10 in the same column are respectively connected to a data line D and a first data line D'. Each pixel unit 10 may contain a pixel circuit, the input terminals of which are respectively connected to the data line D and the first data line D'. Data signals are not simultaneously input to the data line D and the first data line D', thereby realizing the first driving architecture and the second driving architecture respectively. Alternatively, two pixel circuits may be provided, with their input terminals connected to the data line D and the first data line D' respectively, and their output terminals connected together to the pixel electrode of the pixel unit 10. The pixel circuits in the pixel unit are not limited here.

[0056] The beneficial effects of this embodiment are: by adding a first data line in the column direction, and connecting the original data lines according to the first driving architecture through the scan lines, connecting the first data lines according to the second driving architecture, or connecting the original data lines according to the second driving architecture and connecting the first data lines according to the first driving architecture, a first driving architecture and a second driving architecture are formed in the display panel, and the switching between the first driving architecture and the second driving architecture is realized through the control of the second switching unit.

[0057] This application also provides a method for switching between dual-drive architectures of a display panel, wherein the dual-drive architecture includes the structure of the dual-drive architecture described in any of the above embodiments. Please refer to the following for details. Figure 11 , Figure 11 This is a flowchart illustrating an embodiment of the switching method for the dual-drive architecture of the display panel in this application. Figure 11 As shown, the switching method for the dual-drive architecture of this display panel includes:

[0058] Step S101: Obtain the driving mode of the dual-drive architecture of the display panel.

[0059] The scan lines and data lines in the display panel form a first driving architecture and a second driving architecture. The driving modes include a first driving mode using the first driving architecture and a second driving mode using the second driving architecture.

[0060] The driving mode of the dual-drive architecture of the display panel can be obtained by detecting the display surface. Please refer to further details. Figure 12 , Figure 12 For this application Figure 11 A flowchart illustrating a further embodiment of step S101. (See attached diagram.) Figure 12 As shown, step S101 includes:

[0061] Step S111: Detect whether the display panel shows a flickering screen or a screen with bright and dark lines.

[0062] If a flickering screen appears, proceed to step S112; if a screen with bright and dark lines appears, proceed to step S113.

[0063] Specifically, this can be detected through the screen capture function of the timing controller in the display panel.

[0064] Step S112: Obtain the second driving mode.

[0065] Specifically, the second driving mode is used to drive the display panel.

[0066] Step S113: Obtain the first driving mode.

[0067] Specifically, the first driving mode is used to drive the display panel.

[0068] When the display panel is driven in the first driving mode, a voltage shift can easily cause flickering. If flickering occurs, switching to the second driving mode eliminates the display defects inherent in the first driving mode. Conversely, when the display panel is driven in the second driving mode, bright and dark lines can easily appear. Again, switching back to the first driving mode eliminates these defects.

[0069] Step S102: According to the first driving mode, scan signals are transmitted sequentially to pixel units in odd-numbered rows via odd-numbered scan lines, to pixel units in even-numbered rows via even-numbered scan lines, to pixel units in odd-numbered columns via odd-numbered data lines, and to pixel units in even-numbered columns via even-numbered data lines.

[0070] Specifically, odd-numbered row scan lines drive odd-numbered column data lines to transmit data voltage to odd-numbered row and odd-numbered column pixel units, and drive even-numbered column data lines to transmit data voltage to odd-numbered row and even-numbered column pixel units; conversely, even-numbered row scan lines drive odd-numbered column data lines to transmit data voltage to even-numbered row and odd-numbered column pixel units, and conversely, even-numbered column data lines to transmit data voltage to even-numbered row and even-numbered column pixel units. More specifically, odd-numbered row scan lines drive each column data line (including both odd-numbered and even-numbered row data lines) to transmit data voltage to the pixel unit of the current column in the current row; even-numbered row scan lines drive each column data line (including both odd-numbered and even-numbered row data lines) to transmit data voltage to the pixel unit of the current column in the current row.

[0071] Step S103: According to the second driving mode, scan signals are transmitted sequentially through odd-numbered scan lines to pixel units in odd-numbered rows, even-numbered scan lines to pixel units in even-numbered rows, odd-numbered column data lines to pixel units in odd-numbered columns and even-numbered columns, and even-numbered column data lines to pixel units in odd-numbered columns and even-numbered columns.

[0072] Odd-numbered row scan lines drive odd-numbered column data lines to transmit data signals to odd-numbered row and odd-numbered column pixel units, and drive even-numbered column data lines to transmit data signals to odd-numbered row and even-numbered column pixel units. Even-numbered row scan lines drive odd-numbered column data lines to transmit data voltages to even-numbered row and even-numbered column pixel units, and drive even-numbered column data lines to transmit data voltages to even-numbered row and odd-numbered column pixel units. Specifically, odd-numbered row scan lines drive each column data line (including odd-numbered row data lines and even-numbered row data lines) to transmit data voltages to the pixel units of the previous column in the current row; even-numbered row scan lines drive each column data line (including odd-numbered row data lines and even-numbered row data lines) to transmit data voltages to the pixel units of the previous column in the current row.

[0073] In the first and second embodiments, the dual-drive architecture of the display panel includes a first switching unit, each of which includes a first transistor and a second transistor. The switching method includes: selecting to turn on either the first transistor or the second transistor according to a driving mode, thereby achieving mutual switching between driving the display panel according to the first driving mode and driving the display panel according to the second driving mode. Specifically, the first transistor is controlled to turn on via a control signal line, thereby driving the display panel according to the first driving mode; the second transistor is controlled to turn on via a control signal line, thereby driving the display panel according to the second driving mode. Switching from turning on the first transistor to turning on the second transistor via a control signal line achieves a drive switch from the first driving mode to the second driving mode; switching from turning on the second transistor to turning on the first transistor achieves a drive switch from the second driving mode to the first driving mode.

[0074] In the third and fourth embodiments, the dual-drive architecture of the display panel includes a second switching unit, and each first switching unit includes a third transistor and a fourth transistor. The switching method includes selecting to turn on either the third transistor or the fourth transistor according to the driving mode, thereby achieving mutual switching between driving the display panel according to the first driving mode and driving the display panel according to the second driving mode. Specifically, when the third transistor is turned on by a control signal line, the display panel is driven according to the first driving mode; when the fourth transistor is turned on by a control signal line, the display panel is driven according to the second driving mode. Further, the control signal line controls the third and fourth transistors to control whether the display panel is driven according to the first or second driving mode. Switching from turning on the third transistor to turning on the fourth transistor achieves a drive switch from the first driving mode to the second driving mode; switching from turning on the fourth transistor to turning on the third transistor achieves a drive switch from the second driving mode to the first driving mode.

[0075] The beneficial effects of this embodiment are: the dual-drive architecture of the display panel includes a first drive architecture formed by scan lines, data lines and pixel units, and the dual-drive architecture of the display panel also includes a drive switching module that forms a second drive architecture with some scan lines, data lines and pixel units, and the switching unit in the drive switching module realizes the switching between the first drive architecture and the second drive architecture, thereby making up for the deficiencies of a single drive architecture and improving the display effect.

[0076] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A dual-drive architecture for a display panel, comprising a plurality of pixel units arranged in an array; a plurality of scan lines arranged along a row direction, the scan lines including even-numbered row scan lines and odd-numbered row scan lines, for outputting scan signals to the pixel units in each row; and a plurality of data lines arranged along a column direction, the data lines including even-numbered column data lines and odd-numbered column data lines, for outputting data signals to the pixel units in each column; characterized in that, The dual-drive architecture of the display panel includes a drive switching module, which is used to switch between the first drive architecture and the second drive architecture of the dual-drive architecture of the display panel. In the first driving architecture, the odd-numbered row scan lines are used to output scan signals to the pixel units in the odd-numbered rows, the even-numbered row scan lines are used to output scan signals to the pixel units in the even-numbered rows, the odd-numbered column data lines are used to output data signals to the pixel units in the odd-numbered columns, and the even-numbered column data lines are used to output data signals to the pixel units in the even-numbered columns. In the second driving architecture, the odd-numbered row scan lines are used to output scan signals to the pixel units in the odd-numbered rows, the even-numbered row scan lines are used to output scan signals to the pixel units in the even-numbered rows, the odd-numbered column data lines are used to output data signals to the pixel units in the odd-numbered columns and the pixel units in the even-numbered columns, and the even-numbered column data lines are used to output data signals to the pixel units in the odd-numbered columns and the pixel units in the even-numbered columns. The drive switching module includes adding multiple first scan lines corresponding to the even-numbered row scan lines or the odd-numbered row scan lines in the first drive architecture. The first scan lines connect the pixel units in the even-numbered or odd-numbered rows to the data lines in the next column of the current column, and are used to control the data lines to transmit data voltage to the pixel units in the previous column, so as to realize the switching between the first drive architecture and the second drive architecture.

2. The dual-drive architecture of the display panel according to claim 1, characterized in that, The drive switching module includes multiple first switching units. Each first switching unit is connected to the even-numbered scan line and the first scan line corresponding to the even-numbered scan line, and is used to control the transmission of scan signals to the first scan line or the even-numbered scan line; or it is connected to the odd-numbered scan line and the first scan line corresponding to the odd-numbered scan line, and is used to control the transmission of scan signals to the first scan line or the odd-numbered scan line.

3. The dual-drive architecture of the display panel according to claim 2, characterized in that, Each of the first switching units includes a first transistor and a second transistor. The first terminals of the first transistor and the second transistor are connected to the same scan signal line. The second terminal of the first transistor is connected to the even-numbered scan line or the odd-numbered scan line. The second terminal of the second transistor is connected to the first scan line. The switching of the scan signal line from transmitting a scan signal to the even-numbered scan line or the odd-numbered scan line to transmitting a scan signal to the first scan line is achieved by controlling the on / off state of the first transistor and the second transistor.

4. The dual-drive architecture of the display panel according to claim 1, characterized in that, The drive switching module includes adding a first data line corresponding to each of the data lines in the first drive architecture; The first data line corresponding to the odd-numbered column data line is connected to the pixel units of the odd-numbered rows of the odd-numbered column and the pixel units of the even-numbered rows of the even-numbered column. The first data line corresponding to the even-numbered column data line is connected to the pixel units of the odd-numbered rows of the even-numbered column and the pixel units of the even-numbered rows of the odd-numbered column. The switching between the first driving architecture and the second driving architecture is achieved by switching the data line and the first data line.

5. The dual-drive architecture of the display panel according to claim 4, characterized in that, The drive switching module includes multiple second switching units, each of which is connected to the data line and a first data line corresponding to the data line, so as to realize the switching between the data line and the first data line.

6. The dual-drive architecture of the display panel according to claim 5, characterized in that, The second switching unit includes a third transistor and a fourth transistor. The first ends of the third transistor and the fourth transistor are connected to the data signal line, the second end of the third transistor is connected to the data line, and the second end of the fourth transistor is connected to the first data line. The switching between transmitting data signals from the data signal line to the data line and transmitting data signals to the first data line is achieved by controlling the on / off state of the third transistor and the fourth transistor.

7. A method for switching a dual-drive architecture for a display panel, wherein the dual-drive architecture comprises the dual-drive architecture for a display panel as described in any one of claims 1 to 6, characterized in that, The switching method includes: Obtain the driving mode of the dual-drive architecture of the display panel; wherein, the driving mode includes a first driving mode that uses the first driving architecture and a second driving mode that uses the second driving architecture. According to the first driving mode, scan signals are transmitted sequentially through the odd-numbered scan lines to the pixel units in the odd-numbered rows, the even-numbered scan lines to the pixel units in the even-numbered rows, the odd-numbered data lines to the pixel units in the odd-numbered columns, and the even-numbered data lines to the pixel units in the even-numbered columns; or, According to the second driving mode, scan signals are transmitted sequentially through the odd-numbered scan lines to the pixel units in the odd-numbered rows, the even-numbered scan lines to the pixel units in the even-numbered rows, the odd-numbered column data lines to the pixel units in the odd-numbered columns and the even-numbered columns, and the even-numbered column data lines to the pixel units in the odd-numbered columns and the even-numbered columns.

8. The switching method for the dual-drive architecture of the display panel according to claim 7, characterized in that, The step of obtaining the driving mode of the dual-drive architecture of the display panel includes: Detect whether the display panel shows a flickering image or a bright / dark line image; If the display panel is showing a flickering image, then the second driving mode is obtained; If the display panel shows bright and dark lines, then the first driving mode is obtained.

9. The switching method for the dual-drive architecture of the display panel according to claim 7, characterized in that, The dual-drive architecture of the display panel includes a first switching unit, which includes a first transistor and a second transistor; the switching method includes: The first transistor or the second transistor is turned on according to the driving mode to achieve the switching between driving the display panel according to the first driving mode and driving the display panel according to the second driving mode.

10. The switching method for the dual-drive architecture of the display panel according to claim 7, characterized in that, The dual-drive architecture of the display panel includes a second switching unit, which includes a third transistor and a fourth transistor; the switching method includes: The third or fourth transistor is selected to be turned on according to the driving mode, so as to switch between driving the display panel according to the first driving mode and driving the display panel according to the second driving mode.

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