Pixel driving circuit, method and display panel

Abstract

The present application relates to a pixel driving circuit, a pixel driving method, and a display panel. The pixel driving circuit includes: a current driving circuit, configured to receive a display data signal and a display control signal, and output a driving current corresponding to the intensity of the display data signal when the display control signal is received; a gray scale control circuit, configured to receive the driving current, a pulse width selection signal, and a pulse width modulation signal, and drive a light emitting element for a preset duration according to the pulse width modulation signal; wherein the preset duration is a first duration, a second duration, or a third duration corresponding to the pulse width selection signal. Thus, the light emitting element can also not be in a low current state when displaying a gray scale, avoiding the phenomenon of screen flicker during low gray scale display, and improving the display effect of the display panel at high and low gray scales. In addition, since the pixel driving circuit can drive the light emitting element with three durations, the voltage gradient between gray scales is increased, and the display effect is better.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a pixel driving circuit, a pixel driving method, and a display panel. Background Art

[0002] With the development of display technologies, people have higher and higher requirements for display products. Glass substrate-driven MiniLED (sub-millimeter light-emitting diode) / MicroLED (micro light-emitting diode) can achieve seamless splicing and uniform pictures due to its characteristics of micro-pitch display, and is becoming more and more popular.

[0003] In traditional glass substrate driving technologies, the brightness of light-emitting elements is regulated by the amplitude of current pulses. However, when driving light-emitting elements with this driving architecture, low current density corresponds to low gray levels, and MiniLED / MicroLED will have uneven brightness under low current conditions, which affects the display effect of the display panel and cannot meet people's requirements for high-quality display products. Summary of the Invention

[0004] Based on this, in view of the problem of uneven brightness of light-emitting elements when displaying low gray levels, it is necessary to provide a pixel driving circuit, a pixel driving method, and a display panel.

[0005] A pixel driving circuit for driving a light-emitting element, the circuit comprising:

[0006] A current driving circuit for receiving a display data signal and a display control signal, and outputting a driving current corresponding to the intensity of the display data signal when receiving the display control signal;

[0007] A gray level control circuit for receiving the driving current, a pulse width selection signal, and a pulse width modulation signal, and driving the light-emitting element to reach a preset duration according to the pulse width modulation signal; wherein the preset duration is a first duration, a second duration, or a third duration corresponding to the pulse width selection signal.

[0008] In one embodiment, the gray level control circuit includes a first pulse width selection circuit and a second pulse width selection circuit, and both the first pulse width selection circuit and the second pulse width selection circuit receive the driving current, the pulse width selection signal, and the pulse width modulation signal;

[0009] Under the control of the pulse width selection signal, the first pulse width selection circuit and the second pulse width selection circuit alternately drive the light-emitting element to reach a first duration according to the pulse width modulation signal; or the first pulse width selection circuit drives the light-emitting element to reach a second duration according to the pulse width modulation signal under the control of the pulse width selection signal; or the second pulse width selection circuit drives the light-emitting element to reach a third duration according to the pulse width modulation signal under the control of the pulse width selection signal, where the first duration is the sum of the second duration and the third duration.

[0010] In one embodiment, the first pulse width selection circuit includes a first transistor and a first pulse width selection sub-circuit; the first transistor is respectively connected to the current drive circuit, the light-emitting element and the first pulse width selection sub-circuit; the first pulse width selection sub-circuit is configured to receive the pulse width selection signal and the pulse width modulation signal, and under the control of the pulse width selection signal, control the first transistor to turn on / off the current drive circuit and the light-emitting element according to the pulse width modulation signal;

[0011] The second pulse width selection circuit includes a second transistor and a second pulse width selection sub-circuit; the second transistor is respectively connected to the current drive circuit, the light-emitting element and the second pulse width selection sub-circuit, and the second pulse width selection sub-circuit is configured to receive the pulse width selection signal and the pulse width modulation signal, and under the control of the pulse width selection signal, control the second transistor to turn on / off the current drive circuit and the light-emitting element according to the pulse width modulation signal;

[0012] The first transistor is a first-type transistor, and the second transistor is a second-type transistor.

[0013] In one embodiment, the first pulse width selection sub-circuit includes a third transistor, a fourth transistor and a first capacitor. The input end of the third transistor is used to access the pulse width selection signal, the controlled end of the third transistor is used to receive the first scan signal, the output end of the third transistor is respectively connected to the controlled end of the fourth transistor and the first end of the first capacitor, the input end of the fourth transistor is used to receive the pulse width modulation signal, the output end of the fourth transistor is connected to the first transistor, and the second end of the first capacitor receives the regulated voltage signal.

[0014] In one embodiment, the second pulse width selection sub-circuit includes a fifth transistor, a sixth transistor, and a second capacitor. The input end of the fifth transistor is used to access a pulse width selection signal. The controlled end of the fifth transistor is used to receive a second scan signal. The output end of the fifth transistor is respectively connected to the controlled end of the sixth transistor and the first end of the second capacitor. The input end of the sixth transistor is used to receive a pulse width modulation signal. The output end of the sixth transistor is connected to the second transistor. The second end of the second capacitor receives a regulated voltage signal.

[0015] In one embodiment, the current driving circuit includes a reset circuit, a writing compensation circuit, and a driving circuit. The writing compensation circuit is respectively connected to the reset circuit, the driving circuit, and the grayscale control circuit.

[0016] The reset circuit is used to receive a reset signal and a first scan signal, and reset the writing compensation circuit according to the first scan signal.

[0017] The writing compensation circuit is further used to receive a display data signal, and write the display data signal according to the second scan signal.

[0018] The driving circuit is used to access a first voltage and a display control signal, and control the writing compensation circuit to output a driving current corresponding to the intensity of the display data signal according to the first voltage and the display control signal.

[0019] In one embodiment, the writing compensation circuit includes a data writing transistor and a compensation sub-circuit. The controlled end of the data writing transistor is used to access a second scan signal. The input end of the data writing transistor is used to access a display data signal. The output end of the data writing transistor is connected to the compensation sub-circuit.

[0020] The compensation sub-circuit is connected to the driving circuit and receives the first voltage output by the driving circuit. The compensation sub-circuit is further used to receive the second scan signal, and perform voltage compensation according to the first voltage and the display data signal under the control of the second scan signal.

[0021] In one embodiment, the compensation sub-circuit includes a seventh transistor, an eighth transistor, and a third capacitor. The controlled end of the seventh transistor is used to access a second scan signal. The input end of the seventh transistor is connected to the output end of the eighth transistor. The output end of the seventh transistor, the first end of the third capacitor, and the controlled end of the eighth transistor are respectively connected to the reset circuit. The second end of the third capacitor is used to access a regulated voltage signal. The input end of the eighth transistor is connected to the output end of the writing transistor.

[0022] A pixel driving method for a pixel driving circuit as described above, the method comprising:

[0023] A current driving circuit receives a display data signal and a display control signal, and outputs a driving current corresponding to the intensity of the display data signal when receiving the display control signal;

[0024] A grayscale control circuit receives the driving current, a pulse width selection signal, and a pulse width modulation signal, and drives the light-emitting element to reach a preset duration according to the pulse width modulation signal; wherein the preset duration is a first duration, a second duration, or a third duration corresponding to the pulse width selection signal.

[0025] A display panel includes a plurality of light-emitting elements and a plurality of pixel circuits for driving the light-emitting elements, and the pixel circuits are the pixel driving circuits as described above.

[0026] The above-mentioned pixel driving circuit, pixel driving method, and display panel can drive the light-emitting element for different durations according to the pulse width selection signal corresponding to different grayscales to achieve the display of different grayscales. Thus, the light-emitting element does not need to be at a low current when displaying grayscales, avoiding the screen flickering phenomenon that occurs during low grayscale display, and improving the display effect of the display panel at high and low grayscales. In addition, since the pixel driving circuit can drive the light-emitting element for three durations, the voltage gradient between grayscales is increased, and the display effect is better. Description of the Drawings

[0027] Figure 1 It is a module schematic diagram of a pixel driving circuit in an embodiment;

[0028] Figure 2 It is a module schematic diagram of a pixel driving circuit in another embodiment;

[0029] Figure 3 It is a circuit structure schematic diagram of a pixel driving circuit in an embodiment;

[0030] Figure 4 It is a module schematic diagram of a pixel driving circuit in yet another embodiment;

[0031] Figure 5 It is a timing schematic diagram of a frame period of a pixel driving circuit in an embodiment;

[0032] Figure 6 It is a timing schematic diagram of a pulse width selection signal in an embodiment;

[0033] Figure 7 For Figure 6 A schematic diagram of the on states of the first transistor and the second transistor in the pixel driving circuit in the embodiment;

[0034] Figure 8 Schematic diagram of the pixel driving method in an embodiment. Detailed implementation

[0035] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] In one embodiment, as Figure 1 shown, a pixel driving circuit is provided, including a current driving circuit 100 and a grayscale control circuit 200. The current driving circuit 100 is configured to receive a display data signal D1 and a display control signal EM, and output a driving current corresponding to the intensity of the display data signal D1 when receiving the display control signal EM. The grayscale control circuit 200 is configured to receive the driving current, a pulse width selection signal D2, and a pulse width modulation signal PWM, and drive the light-emitting element 300 for a preset duration according to the pulse width modulation signal PWM; wherein, the preset duration is a first duration, a second duration, or a third duration corresponding to the pulse width selection signal D2.

[0037] The light-emitting element 300 may be a mini light-emitting diode (MiniLED) or a micro light-emitting diode (MicroLED), or may be other types of light-emitting diodes such as an organic light-emitting diode (OLED). In practical applications, the structure of the light-emitting element 300 needs to be designed and determined according to the actual application environment, which is not limited herein. For the convenience of description, hereinafter, it is assumed that the light-emitting element 300 includes a mini light-emitting diode D. The anode of the mini light-emitting diode D is connected to the grayscale control circuit 200, and the cathode is connected to the low voltage terminal VSS.

[0038] Specifically, the current driving circuit 100 is respectively connected to a first voltage terminal VDD, a display data signal input terminal, and a display control signal input terminal, receives the display data signal D1 at the display data signal input terminal, receives the display control signal EM at the display control signal input terminal, and generates a driving current according to the control of the display control signal EM and outputs it to the grayscale control circuit 200, and generates the intensity of the driving current according to the control of the display data signal D1.

[0039] The grayscale control circuit 200 is connected to the current driving circuit 100, the light-emitting element 300, the pulse width selection signal input terminal, and the pulse width modulation signal input terminal; receives the driving current, and drives the light-emitting element 300 or stops driving the light-emitting element 300 according to the received pulse width modulation signal PWM. In one frame period, the total duration of driving the light-emitting element 300 may be the first duration, the second duration, or the third duration, and the specific duration is controlled by the received pulse width selection signal D2. When the pulse width selection signal D2 corresponds to a high grayscale, the total duration of driving the light-emitting element 300 is the first duration; when the pulse width selection signal D2 corresponds to a medium grayscale, the total duration of driving the light-emitting element 300 is the second duration; when the pulse width selection signal D2 corresponds to a low grayscale, the total duration of driving the light-emitting element 300 is the third duration. Correspondingly, the first duration is greater than the second duration, and the second duration is greater than the third duration. Among them, the division of high grayscale, medium grayscale, and low grayscale needs to be combined with the situation.

[0040] It should be noted that when driving the light-emitting element 300 with one duration, such as driving the light-emitting element 300 with the first duration, if you want to achieve low grayscale display, you need to reduce the intensity of the driving current, and the voltage gradient between grayscales is small. When adjusting in two gears, that is, driving the light-emitting element 300 with two durations, the intensity of the driving current can be increased, the voltage gradient between grayscales can be increased, and the display effect can be improved. In this embodiment, three-gear grayscale adjustment can be achieved, that is, driving the light-emitting element 300 with three durations, so that the voltage value of the display data signal D1 is relatively higher, the driving current is larger, the voltage gradient between grayscales is larger, the brightness difference between grayscales is larger, the display effect is better and the display is more stable.

[0041] This pixel driving circuit still has the function of current pulse amplitude dimming, can output driving currents of different intensities, and drives the light-emitting element 300 for different durations to achieve displays of different grayscales. Therefore, the light-emitting element 300 does not need to be in a low current state when displaying grayscales, avoiding the phenomenon of screen flicker that occurs during low grayscale display. Especially when the light-emitting element 300 is a sub-millimeter light-emitting diode (MiniLED) or a micro light-emitting diode (MicroLED), the display effect of the display panel at low grayscales can be significantly improved. In addition, since this pixel driving circuit can drive the light-emitting element 300 for three durations and achieve multi-grayscale display through three-gear pulse width modulation, the display effect is better.

[0042] In one embodiment, such as Figure 2As shown, the grayscale control circuit 200 includes a first pulse width selection circuit 21 and a second pulse width selection circuit 22. Both the first pulse width selection circuit 21 and the second pulse width selection circuit 22 receive a drive current, a pulse width selection signal D2, and a pulse width modulation signal PWM. Under the control of the pulse width selection signal D2, the first pulse width selection circuit 21 and the second pulse width selection circuit 22 alternately drive the light-emitting element 300 according to the pulse width modulation signal PWM to reach a first duration; or the first pulse width selection circuit 21 drives the light-emitting element 300 to reach a second duration according to the pulse width modulation signal PWM under the control of the pulse width selection signal D2; or the second pulse width selection circuit 22 drives the light-emitting element 300 to reach a third duration according to the pulse width modulation signal PWM under the control of the pulse width selection signal D2.

[0043] In this embodiment, both the first pulse width selection circuit 21 and the second pulse width selection circuit 22 are connected to the current drive circuit 100, the light-emitting element 300, a pulse width selection signal input terminal, and a pulse width modulation signal input terminal; to drive the light-emitting element 300 according to the pulse width modulation signal PWM under the control of the pulse width selection signal D2 or not.

[0044] In one embodiment, the second duration and the third duration are related to the duty cycle of the pulse width modulation signal PWM. The magnitudes of the second duration and the third duration need to be specifically determined according to the grayscale range to be displayed. The first duration is the sum of the third duration and the second duration. For example, when it is necessary to display three grayscales of high, medium, and low, the second duration can be set to be greater than the third duration. The second pulse width selection circuit 22 controls the total conduction duration of the current drive circuit 100 and the light-emitting element 300 to be the third duration to achieve low grayscale display; the first pulse width selection circuit 21 controls the total conduction duration of the current drive circuit 100 and the light-emitting element 300 to be the second duration to achieve medium grayscale display; the first pulse width selection circuit 21 and the second pulse width selection circuit 22 alternately control the total conduction duration of the current drive circuit 100 and the light-emitting element 300 to be the first duration to achieve high grayscale display; thus, three-level grayscale adjustment is achieved according to the pulse width modulation signal PWM.

[0045] It can be understood that according to actual control requirements, the duty cycle of the pulse width modulation signal PWM can also be adjusted to make the second duration equal to the third duration, and the first duration is the sum of the third duration and the second duration, thereby achieving two-level grayscale adjustment.

[0046] In one embodiment, the first pulse width selection circuit 21 includes a first transistor T6 and a first pulse width selection sub-circuit 201; the first transistor T6 is respectively connected to the current driving circuit 100, the light emitting element 300 and the first pulse width selection sub-circuit 201. The first pulse width selection sub-circuit 201 is configured to receive a pulse width selection signal D2 and a pulse width modulation signal PWM, and under the control of the pulse width selection signal D2, control the first transistor T6 to conduct / turn off the current driving circuit 100 and the light emitting element 300 according to the pulse width modulation signal PWM. The second pulse width selection circuit 22 includes a second transistor T11 and a second pulse width selection sub-circuit 202; the second transistor T11 is respectively connected to the current driving circuit 100, the light emitting element 300 and the second pulse width selection sub-circuit 202. The second pulse width selection sub-circuit 202 is configured to receive a pulse width selection signal D2 and a pulse width modulation signal PWM, and under the control of the pulse width selection signal D2, control the second transistor T11 to conduct / turn off the current driving circuit 100 and the light emitting element 300. The first transistor T6 is a first type transistor, and the second transistor T11 is a second type transistor.

[0047] The first type transistor includes an N-type transistor or a P-type transistor, and the second type transistor includes a P-type transistor or an N-type transistor, and the transistor type of the second type transistor is different from that of the first type transistor. That is, when the first type transistor is an N-type transistor, the second type transistor is a P-type transistor; when the first type transistor is a P-type transistor, the second type transistor is an N-type transistor. For the convenience of description, in this embodiment, the first transistor T6 is a P-type transistor and the second transistor T11 is an N-type transistor as an example. The type of the transistor does not need to be limited and can be a TFT (Thin Film Transistor). The thin film transistor can be a bottom gate structure thin film transistor or a top gate structure thin film transistor, as long as the above functions can be realized.

[0048] The input terminal of the first transistor T6 is connected to the current driving circuit 100, the output terminal is connected to the light emitting element 300, and the controlled terminal is connected to the first pulse width selection sub-circuit 201. The first pulse width selection sub-circuit 201 is respectively connected to the pulse width selection signal input terminal and the pulse width modulation signal input terminal, and receives the pulse width selection signal D2 and the pulse width modulation signal PWM. The first pulse width selection sub-circuit 201 also outputs the pulse width modulation signal PWM to the controlled terminal of the first transistor T6 under the control of the pulse width selection signal D2. When the first transistor T6 receives the pulse width modulation signal PWM, it turns on / off the current driving circuit 100 and the light emitting element 300 according to the pulse width modulation signal PWM, so that the light emitting element 300 displays the corresponding gray level according to the driving current. Since the first transistor T6 is a P-type transistor, it turns on when the pulse width modulation signal PWM is at a low level, and the first pulse width selection sub-circuit 201 controls the light emitting duration of the light emitting element 300 to be the total duration when the pulse width modulation signal PWM is at a low level.

[0049] The input terminal of the second transistor T11 is connected to the current driving circuit 100, the output terminal is connected to the light emitting element 300, and the controlled terminal is connected to the second pulse width selection sub-circuit 202. The second pulse width selection sub-circuit 202 is respectively connected to the pulse width selection signal input terminal and the pulse width modulation signal input terminal, and receives the pulse width selection signal D2 and the pulse width modulation signal PWM. The second pulse width selection sub-circuit 202 also outputs the pulse width modulation signal PWM to the controlled terminal of the second transistor T11 under the control of the pulse width selection signal D2. When the second transistor T11 receives the pulse width modulation signal PWM, it turns on / off the current driving circuit 100 and the light emitting element 300 according to the pulse width modulation signal PWM, so that the light emitting element 300 displays the corresponding gray level according to the driving current. The second transistor T11 is an N-type transistor and turns on when the pulse width modulation signal PWM is at a high level, and the second pulse width selection sub-circuit 202 controls the light emitting duration of the light emitting element 300 to be the total duration when the pulse width modulation signal PWM is at a high level.

[0050] Further, the first pulse width selection sub-circuit 201 is connected to the first scan signal input terminal to receive the first scan signal G1; the second pulse width selection sub-circuit 202 is connected to the second scan signal input terminal to receive the second scan signal G2. The first pulse width selection sub-circuit 201 receives the pulse width selection signal D2 under the control of the first scan signal G1, and then receives the pulse width modulation signal PWM. When the first scan signal G1 is not received, the pulse width selection signal D2 is not received. The second pulse width selection sub-circuit 202 receives the pulse width selection signal D2 under the control of the second scan signal G2, and then receives the pulse width modulation signal PWM. When the second scan signal G2 is not received, the pulse width selection signal D2 is not received. Thus, by controlling the timing of the first scan signal G1 and the second scan signal G2, the level of the pulse width control signal D2 received by the first pulse width selection sub-circuit 201 and the second pulse width selection sub-circuit 202 can be controlled, realizing three-level control.

[0051] In one embodiment, as Figure 3 shown, the first pulse width selection sub-circuit 201 includes a third transistor T10, a fourth transistor T8, and a first capacitor C1. The input terminal of the third transistor T10 is used to connect to the pulse width selection signal input terminal to receive the pulse width selection signal D2. The controlled terminal of the third transistor T10 is used to connect to the first scan signal input terminal to receive the first scan signal G1. The output terminal of the third transistor T10 is respectively connected to the controlled terminal of the fourth transistor T8 and the first end of the first capacitor C1. The input terminal of the fourth transistor T8 is used to connect to the pulse width modulation signal input terminal to receive the pulse width modulation signal PWM. The output terminal of the fourth transistor T8 is connected to the controlled terminal of the first transistor T6. The second end of the first capacitor C1 is connected to the regulated voltage signal Vcom input terminal to receive the regulated voltage signal Vcom.

[0052] The first scan signal G1, the second scan signal G2, the pulse width selection signal D2, the display data signal D1, the display control signal EM, and the regulated voltage signal Vcom can be generated by a driving IC (Integrated Circuit Chip). The regulated voltage signal Vcom can also be the first voltage of the first voltage terminal VDD or the second voltage of the low voltage terminal VSS.

[0053] In one embodiment, the second pulse width selection sub-circuit includes a fifth transistor T9, a sixth transistor T7, and a second capacitor C2. The input terminal of the fifth transistor T9 is used to connect to the pulse width selection signal input terminal to receive the pulse width selection signal. The control terminal of the fifth transistor T9 is used to connect to the second scan signal input terminal to receive the second scan signal G2. The output terminal of the fifth transistor T9 is respectively connected to the control terminal of the sixth transistor T7 and the first end of the second capacitor C2. The input terminal of the sixth transistor T7 is used to connect to the pulse width modulation signal input terminal to receive the pulse width modulation signal PWM. The output terminal of the sixth transistor T7 is connected to the second transistor T11. The second end of the second capacitor C2 is connected to the regulated voltage signal Vcom input terminal to receive the regulated voltage signal Vcom.

[0054] The above-mentioned third transistor T10 and fifth transistor T9 are of the same type, both being N-type transistors, which conduct when receiving a high level. They are turned on in sequence according to the first scan signal G1 and the second scan signal G2, so that the potential of the pulse width selection signal D2 when the first scan signal G1 arrives is stored in the first capacitor C1, and the potential when the second scan signal G2 arrives is stored in the second capacitor C2. The fourth transistor T8 and the sixth transistor T7 are of the same type, which can both be N-type transistors or both be P-type transistors, and need to be set in combination with the timing of the pulse width selection signal D2.

[0055] In one embodiment, as Figure 4 shown, the current driving circuit 100 includes a reset circuit 11, a write compensation circuit 12, and a driving circuit 13. The write compensation circuit 12 is respectively connected to the reset circuit 11, the driving circuit 13, and the grayscale selection circuit 200. The write compensation circuit 12 is also used to connect to the display data signal input terminal and the second scan signal input terminal to receive the display data signal D1 and the second scan signal G2. The reset circuit 11 is connected to the reset signal input terminal and the first scan signal input terminal to receive the reset signal Vini and the first scan signal G1. The driving circuit 13 is connected to the first voltage terminal VDD and the display control signal input terminal to access the first voltage VDD and the display control signal EM. The reset circuit 11 is used to reset the write compensation circuit 12 according to the first scan signal G1. The write compensation circuit 12 is used to write the display data signal D1 according to the second scan signal G2. The driving circuit 13 controls the write compensation circuit 12 to output a driving current corresponding to the intensity of the display data signal D1 according to the first voltage VDD and the display control signal EM.

[0056] Specifically, the reset circuit 11 is turned on when receiving the first scan signal G1, causing the potential of the write compensation circuit 12 at the end of a cycle to be pulled down to the potential of the reset signal Vini. The write compensation circuit 12 writes the display data signal D1 according to the second scan signal G2 and performs voltage compensation according to the written display data signal D1. The driving circuit 13 is turned on to connect the first voltage terminal VDD and the write compensation circuit 12 when receiving the display control signal EM, so that the write compensation circuit 12 outputs a driving current corresponding to the intensity of the display data signal D1 to the light-emitting element 300.

[0057] In one embodiment, the write compensation circuit 12 includes a data write transistor T4 and a compensation sub-circuit 102. The controlled terminal of the data write transistor T4 is used to connect to the second scan signal input terminal to access the second scan signal G2; the input terminal of the data write transistor T4 is used to connect to the display data signal input terminal to access the display data signal D1; the output terminal of the data write transistor T4 is connected to the compensation sub-circuit 102. The compensation sub-circuit is connected to the driving circuit 13 to receive the first voltage output by the driving circuit 13; the compensation sub-circuit 102 is further used to connect to the second scan signal input terminal to receive the second scan signal G2, and under the control of the second scan signal G2, perform compensation according to the first voltage VDD and the display data signal D1.

[0058] In one embodiment, referring again to Figure 3 , the compensation sub-circuit 102 includes a seventh transistor T3, an eighth transistor T2, and a third capacitor C3; the controlled terminal of the seventh transistor T3 is used to connect to the second scan signal input terminal to access the second scan signal G2; the input terminal of the seventh transistor T3 is connected to the output terminal of the eighth transistor T2, and the output terminal of the seventh transistor T3, the first end of the third capacitor C3, and the controlled terminal of the eighth transistor T2 are respectively connected to the reset circuit 11; the second end of the third capacitor C3 is used to access the regulated signal Vcom, and the input terminal of the eighth transistor T2 is connected to the output terminal of the write transistor T4.

[0059] Wherein, the output terminal of the seventh transistor T3, the first end of the third capacitor C3, and the controlled terminal of the eighth transistor T2 are respectively connected to the output terminal of the reset transistor T1, and the input terminal of the eighth transistor T2 is further connected to the driving circuit 13.

[0060] The structures of the reset circuit 11, the write compensation circuit 12, and the driving circuit 13 can be set according to actual needs. In one embodiment, the reset circuit 11 includes a reset transistor T1. The input terminal of the reset transistor T1 is connected to the input terminal of the reset signal Vini. The controlled terminal of the reset transistor T1 is connected to the first scan signal input terminal. The output terminal of the reset transistor T1 is connected to the output terminal of the seventh transistor T3 in the write compensation circuit 12. The driving circuit 13 includes a driving transistor T5. The input terminal of the driving transistor T5 is connected to the first voltage terminal VDD. The controlled terminal of the driving transistor T5 is connected to the display control signal input terminal. The output terminal of the driving transistor T5 is connected to the input terminal of the eighth transistor T2 in the write compensation circuit 12.

[0061] For ease of explanation, in combination with Figure 5 the working timing diagram shown, the working process of the pixel driving circuit within one frame period is described.

[0062] In the first stage t1, that is, the reset stage, the first scan signal G1 is at a high level, and the second scan signal G2 is at a low level; the reset transistor T1 is turned on, the reset signal Vini is written, which is a low level, to remove the charge stored on the third capacitor C3 in the previous frame, and at the same time, the eighth transistor T2 is turned on. At the same time, the third transistor T10 is also in an on state, and the pulse width selection signal D2 is written to the gate of the fourth transistor T8 and stored in the first capacitor C1.

[0063] In the t2 stage: that is, the write compensation stage, the first scan signal G1 becomes a low level, and the second scan signal G2 becomes a high level. The seventh transistor T3 and the write transistor T4 are turned on. The display data signal D1 charges the gate of the eighth transistor T2 through the eighth transistor T2, the seventh transistor T3, and the seventh transistor T4. When the potential is Vdata + Vth (that is, the sum of the voltage of the display data signal D1 and the threshold voltage), it is stored in the third capacitor C3, and the eighth transistor T2 is turned off. At the same time, the fifth transistor T9 is turned on, and the pulse width selection signal D2 is written to the gate of the sixth transistor T7 and stored in the second capacitor C2.

[0064] The display panel can support different grayscale levels. When the total grayscale is 8bit and 10bit, the timing of the pulse width selection signal D2 corresponding to different grayscale levels can be set according to the actual situation. In one embodiment, as Figure 5As shown, when the gray levels are 129 - 256 in 8 - bit and 513 - 1024 in 10 - bit, the potential of the pulse - width selection signal D2 in both the t1 stage and the t2 stage is high; when the gray levels are 43 - 128 in 8 - bit and 169 - 512 in 10 - bit, the potential of the pulse - width selection signal D2 in the t1 stage is high, and the potential of the pulse - width selection signal D2 in the t2 stage is low; when the gray levels are 1 - 43 in 8 - bit and 1 - 169 in 10 - bit, the potential of the pulse - width selection signal D2 in the t1 stage is low, and the potential of the pulse - width selection signal D2 in the t2 stage is high.

[0065] t3 stage: That is, the light - emitting stage. The potential of the display control signal EM is low, and the sixth transistor T7 is turned on. The first transistor T6 and the second transistor T11 will control whether the pulse - width modulation signal PWM is written according to the potentials stored in the gates of the sixth transistor T7 and the fourth transistor T8 during the t1 and t2 stages. When the gate of the fourth transistor T8 is at a high potential and a PWM signal is written to the gate of the first transistor T6, the first transistor T6 will conduct when the PWM signal is low; when the gate of the sixth transistor T7 is high and a pulse - width modulation signal PWM is written to the gate of the second transistor T11, the second transistor T11 will conduct when the pulse - width modulation signal PWM is high. When conducting, the current in the path is determined by the potential stored in the gate of T2. The driving current I = K(V gs -V th ) 2 = K(V data +V th -VDD - V th ) 2 = K(V data -VDD) 2 , where Vgs represents the gate - source voltage of the eighth transistor T2, Vth represents the threshold voltage of the eighth transistor T2, Vdata represents the voltage of the display data signal, and VDD represents the first voltage.

[0066] In this pixel driving circuit, the first transistor T6 and the second transistor T11 are of opposite types. When either the first transistor T6 or the second transistor T11 is turned on, a current path will be formed, and the light - emitting element 300 can be turned on. When positive - negative alternating signal square waves are simultaneously applied to the gates of the first transistor T6 and the second transistor T11, the first transistor T6 and the second transistor T11 will alternately turn on, and there will always be current passing through the light - emitting element 300.

[0067] In one embodiment, the waveform of the pulse - width modulation signal PWM is as Figure 6As shown, its period is T, which is set to n times of (t1 + t2), where n ≥ 3 and n is an integer multiple of 3. This can ensure that during the writing stage, both t1 and t2 are within a high level or a low level period of the pulse width modulation signal PWM and do not experience signal jumps, so as to guarantee the stability during data writing. Figure 6 In the shown embodiment, the high level duration of the pulse width modulation signal PWM is 1 / 3*T, and the low level duration is 2 / 3*T. The setting of the specific duration is related to the pulse width transition time corresponding to the gray scale.

[0068] As Figure 7 Shown is the on state of the first switching tube T6 and the second switching tube T11 within one frame period. When the gray scale is 129 - 256 in 8-bit or 513 - 1024 in 10-bit, PWM signals enter the gates of both the first switching tube T6 and the second switching tube T11. Therefore, the first switching tube T6 and the second switching tube T11 conduct alternately, and a current path is formed at all times, and the organic light-emitting diode D emits light continuously. When the gray scale is 43 - 128 in 8-bit or 169 - 512 in 10-bit, only the PWM signal enters the gate of the first switching tube T6. When the PWM signal is at a low level, a current path is formed. Therefore, the organic light-emitting diode D emits light only for 2 / 3 of the time. When the gray scale is 1 - 43 in 8-bit or 1 - 169 in 10-bit, only the PWM signal enters the gate of the second switching tube T11. When the PWM signal is at a high level, a current path is formed. Therefore, the organic light-emitting diode D emits light only for 1 / 3 of the time.

[0069] The above can select signals according to the pulse widths corresponding to different gray scales and drive the light-emitting element 300 for different durations to achieve displays of different gray scales. Thus, the light-emitting element 300 does not need to be in a low current state when displaying gray scales, avoiding the screen flicker phenomenon that occurs during low gray scale displays. In addition, since the pixel driving circuit can drive the light-emitting element with three durations, it increases the voltage gradient between gray scales and improves the display effect and display stability of the display panel.

[0070] In one embodiment, as Figure 8 Shown, a pixel driving method is provided for the pixel driving circuit in the above embodiments. This method includes step 100 and step 200.

[0071] Step 100, the current driving circuit receives a display data signal and a display control signal, and when receiving the display control signal, outputs a driving current corresponding to the intensity of the display data signal.

[0072] Step 200, the grayscale control circuit receives a driving current, a pulse width selection signal, and a pulse width modulation signal, and drives the light-emitting element according to the pulse width modulation signal for a preset duration. The preset duration is the first duration, the second duration, or the third duration corresponding to the pulse width selection signal.

[0073] The above method can drive the light-emitting element to display different grayscales for different durations according to the pulse width selection signal corresponding to different grayscales, so that the light-emitting element does not need to be at a low current when displaying grayscales, avoiding the screen flicker phenomenon that occurs during low grayscale display. And it can drive the light-emitting element with three durations, increasing the voltage gradient between grayscales, improving the display effect and display stability of the display panel.

[0074] In one embodiment, a display panel is provided, including a plurality of light-emitting elements and a plurality of pixel circuits. Each pixel circuit is correspondingly connected to a light-emitting element for driving the light-emitting element. The structure of the pixel circuit can be set with reference to the above embodiments and will not be elaborated here.

[0075] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0076] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A pixel driving circuit, characterized in that, for driving a light-emitting element, the circuit comprising: a current driving circuit for receiving a display data signal and a display control signal, and outputting a driving current corresponding to the intensity of the display data signal when receiving the display control signal; a grayscale control circuit for receiving the driving current, a pulse width selection signal, and a pulse width modulation signal, and driving the light-emitting element to reach a preset duration according to the pulse width modulation signal; wherein the preset duration is a first duration, a second duration, or a third duration corresponding to the pulse width selection signal; wherein the grayscale control circuit includes a first pulse width selection circuit and a second pulse width selection circuit, and both the first pulse width selection circuit and the second pulse width selection circuit receive the driving current, the pulse width selection signal, and the pulse width modulation signal; under the control of the pulse width selection signal, the first pulse width selection circuit and the second pulse width selection circuit alternately drive the light-emitting element to reach the first duration according to the pulse width modulation signal; or the first pulse width selection circuit drives the light-emitting element to reach the second duration according to the pulse width modulation signal under the control of the pulse width selection signal; or the second pulse width selection circuit drives the light-emitting element to reach the third duration according to the pulse width modulation signal under the control of the pulse width selection signal, wherein the first duration is the sum of the second duration and the third duration.

2. The pixel driving circuit according to claim 1, characterized in that, the first pulse width selection circuit includes a first transistor and a first pulse width selection sub-circuit; the first transistor is respectively connected to the current driving circuit, the light-emitting element, and the first pulse width selection sub-circuit; the first pulse width selection sub-circuit is configured to receive the pulse width selection signal and the pulse width modulation signal, and under the control of the pulse width selection signal, control the first transistor to conduct / disconnect the current driving circuit and the light-emitting element according to the pulse width modulation signal; the second pulse width selection circuit includes a second transistor and a second pulse width selection sub-circuit; the second transistor is respectively connected to the current driving circuit, the light-emitting element, and the second pulse width selection sub-circuit, and the second pulse width selection sub-circuit is configured to receive the pulse width selection signal and the pulse width modulation signal, and under the control of the pulse width selection signal, control the second transistor to conduct / disconnect the current driving circuit and the light-emitting element according to the pulse width modulation signal; the first transistor is a first type transistor, and the second transistor is a second type transistor.

3. The pixel driving circuit according to claim 2, characterized in that, The first pulse width selection sub-circuit includes a third transistor, a fourth transistor, and a first capacitor. The input end of the third transistor is used to access a pulse width selection signal, the controlled end of the third transistor is used to receive a first scan signal, the output end of the third transistor is respectively connected to the controlled end of the fourth transistor and the first end of the first capacitor. The input end of the fourth transistor is used to receive a pulse width modulation signal, the output end of the fourth transistor is connected to the first transistor, and the second end of the first capacitor receives a regulated voltage signal.

4. The pixel driving circuit according to claim 2, wherein, the second pulse width selection sub-circuit includes a fifth transistor, a sixth transistor, and a second capacitor. The input end of the fifth transistor is used to access a pulse width selection signal, the controlled end of the fifth transistor is used to receive a second scan signal, the output end of the fifth transistor is respectively connected to the controlled end of the sixth transistor and the first end of the second capacitor. The input end of the sixth transistor is used to receive a pulse width modulation signal, the output end of the sixth transistor is connected to the second transistor, and the second end of the second capacitor receives a regulated voltage signal.

5. The pixel driving circuit according to claim 1, wherein, the current driving circuit includes a reset circuit, a write compensation circuit, and a driving circuit; the write compensation circuit is respectively connected to the reset circuit, the driving circuit, and the grayscale control circuit; the reset circuit is used to receive a reset signal and a first scan signal, and reset the write compensation circuit according to the first scan signal; the write compensation circuit is further used to receive a display data signal, and write the display data signal according to a second scan signal; the driving circuit is used to access a first voltage and a display control signal, and control the write compensation circuit to output a driving current corresponding to the intensity of the display data signal according to the first voltage and the display control signal.

6. The pixel driving circuit according to claim 5, wherein, the write compensation circuit includes a data write transistor and a compensation sub-circuit. The controlled end of the data write transistor is used to access a second scan signal, the input end of the data write transistor is used to access a display data signal, and the output end of the data write transistor is connected to the compensation sub-circuit; the compensation sub-circuit is connected to the driving circuit and receives the first voltage output by the driving circuit; the compensation sub-circuit is further used to receive the second scan signal, and perform voltage compensation according to the first voltage and the display data signal under the control of the second scan signal.

7. The pixel driving circuit according to claim 6, wherein, The compensation sub-circuit includes a seventh transistor, an eighth transistor, and a third capacitor; a control terminal of the seventh transistor is configured to receive a second scan signal, an input terminal of the seventh transistor is connected to an output terminal of the eighth transistor, and an output terminal of the seventh transistor, a first terminal of the third capacitor, and a control terminal of the eighth transistor are respectively connected to the reset circuit; a second terminal of the third capacitor is configured to receive a regulated signal, and an input terminal of the eighth transistor is connected to an output terminal of the write transistor.

8. A pixel driving method, characterized in that, for the pixel driving circuit as described in claims 1-7, the method includes: The current driving circuit receives a display data signal and a display control signal, and when receiving the display control signal, outputs a driving current corresponding to the intensity of the display data signal; The grayscale control circuit receives the driving current, a pulse width selection signal, and a pulse width modulation signal, and drives the light-emitting element to reach a preset duration according to the pulse width modulation signal; wherein, the preset duration is a first duration, a second duration, or a third duration corresponding to the pulse width selection signal; the grayscale control circuit includes a first pulse width selection circuit and a second pulse width selection circuit, and both the first pulse width selection circuit and the second pulse width selection circuit receive the driving current, the pulse width selection signal, and the pulse width modulation signal; the first pulse width selection circuit and the second pulse width selection circuit alternately drive the light-emitting element to reach the first duration according to the pulse width modulation signal under the control of the pulse width selection signal; or the first pulse width selection circuit drives the light-emitting element to reach the second duration according to the pulse width modulation signal under the control of the pulse width selection signal; or the second pulse width selection circuit drives the light-emitting element to reach the third duration according to the pulse width modulation signal under the control of the pulse width selection signal, wherein the first duration is the sum of the second duration and the third duration.

9. A display panel, characterized in that, comprising: a plurality of light-emitting elements and a plurality of pixel circuits, the pixel circuits are used to drive the light-emitting elements, and the pixel circuits are the pixel driving circuits as described in any one of claims 1-7.

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