A power module contact detection method

Abstract

A power module contact detection method is disclosed. The power module consists of three phases (U, V, and W) and is connected to a high-voltage power supply and a three-phase load. The U, V, and W phases of the power module are respectively connected to the three loads L1, L2, and L3 of the three-phase load. The power module is placed on a test bench, and its temperature pin, control pin, PN power terminal, and three-phase power terminals are in contact with the test bench to sequentially perform temperature, low-voltage, busbar, and high-voltage contact tests. This invention eliminates the need for additional detection wiring harnesses. Utilizing the pin characteristics of the power module, and through software control algorithms and sampling, the contact points of the control pin, temperature pin, PN power terminal, and three-phase power terminals between the power module and the test bench are detected. This not only ensures contact reliability by performing contact detection at every contact point but also monitors contact reliability in real time during the aging process, thereby improving the stability of the equipment.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power module testing technology, and more specifically to a power module contact detection method. Background Technology

[0002] Currently, most domestic semiconductor power module testing technologies employ a combination of static and dynamic testing to verify module quality. Each test cycle is on the order of microseconds. The defect rate after static testing is approximately 1%, and the defect rate after dynamic testing is approximately 0.1%, as the wafer only experiences transient heating. To ensure the reliability of power modules in practical applications, high-current aging tests are required on aging benches. These tests, conducted on the order of seconds, minutes, and hours, allow the wafer to undergo prolonged heating to simulate actual operating conditions in customer applications. This testing of the module's current capability can reduce the defect rate to 0.01%, thereby minimizing the defect rate in customer applications.

[0003] There are generally two ways to fix power modules to the test bench: one is by screwing, and the other is by crimping. The screwing method has the advantage of high reliability in module-to-beam contact; however, it is less efficient and impractical for production lines. For example, a skilled operator might spend half an hour disassembling and reassembling screws to replace a module for testing, significantly impacting production cycle time. The crimping method is highly efficient, requiring only a few seconds to replace a module for testing. The tested module is simply removed from the fixture, and a new module is placed on top. However, the crimping method has lower reliability in module-to-beam contact. Poor contact can cause the equipment to report a fault, mistaking a working module for a faulty one. In more serious cases, poor contact can lead to arcing at the contact point, potentially destroying the module and causing significant losses.

[0004] To improve the contact reliability of the crimping method, contact testing must be performed on the points where the module contacts the test bench before the formal aging test begins. The traditional method for testing contact is to connect two wires to both ends of each contact point, apply voltage, measure the current, and calculate the contact impedance. The contact impedance is then used to determine if the contact is good. This method is called Kelvin testing, also known as the four-point probe method. This method requires ample fixture space and involves complex wiring and manufacturing processes. However, for power modules with high-voltage terminals, it is impossible to connect two external wires. Furthermore, doing so would increase the stray inductance of the equipment, thus affecting the test results. Summary of the Invention

[0005] To address the aforementioned technical problems in the existing technology, this invention provides a power module contact detection method. This method can detect the reliability of power module contact in real time during the testing process, thereby improving the stability of the equipment.

[0006] To achieve the above objectives, the present invention provides a power module contact detection method. The power module consists of three phases: U, V, and W. The U phase is composed of transistors T1, T2, D1, and D2; the V phase is composed of transistors T3, T4, D3, and D4; and the W phase is composed of transistors T5, T6, D5, and D6. The power module is also connected to a high-voltage power supply and a three-phase load. The high-voltage power supply provides DC power to the power module, and the U, V, and W phases of the power module are respectively connected to the three loads L1, L2, and L3 of the three-phase load.

[0007] The power module is placed on a test bench, and its temperature pin, control pin, PN power terminal, and three-phase power terminal are respectively in contact with the test bench for contact testing in the following steps:

[0008] S1. Perform temperature detection to check the contact of the temperature pins of the power module;

[0009] S2. Perform low-voltage detection to check the contact of the control pins of the power module;

[0010] S3. Perform busbar testing to check the contact of the PN high-voltage terminals of the power module;

[0011] S4. Perform high voltage testing to check the contact of the three-phase power terminals of the power module, and at the same time check the contact of the control pins and PN high voltage terminals of the power module.

[0012] As a further preferred technical solution of the present invention, the hardware sampling proportional circuit for contact detection of the temperature pin of the power module in step S1 includes a low-voltage power supply, a voltage divider resistor, the internal resistance of the temperature pin and a proportional circuit. One end of the internal resistance of the temperature pin is connected to ground, and the other end is divided into two paths. One path is connected to the low-voltage power supply through the voltage divider resistor, and the other path is used to realize the analog signal acquisition of the temperature pin through the proportional circuit.

[0013] The power module has temperature pins for each of its three phases (U, V, and W). The temperature detection performed in step S1 is divided into U-phase temperature pin contact detection, V-phase temperature pin contact detection, and W-phase temperature pin contact detection, specifically including the following steps:

[0014] S11, U-phase temperature pin contact detection

[0015] First, acquire the analog signal from the U-phase temperature pin, then calculate the U-phase temperature pin voltage using the following hardware sampling ratio formula: U-phase temperature pin voltage = ((U-phase analog signal * sampling reference voltage) / maximum value of analog signal) / sampling ratio.

[0016] Then, calculate the U-phase temperature pin resistance using the following voltage divider formula: U-phase temperature pin resistance = voltage divider resistance / ((low voltage supply voltage / U-phase temperature pin voltage) - 1), thus obtaining the U-phase temperature pin resistance;

[0017] Finally, a two-dimensional lookup table is performed based on the resistance value to obtain the current U-phase temperature. If the U-phase temperature is less than 10 degrees, it indicates poor contact of the U-phase temperature pin, prompting "U-phase temperature pin contact abnormal"; otherwise, it indicates normal contact of the U-phase temperature pin.

[0018] S12, V-phase temperature pin contact detection

[0019] First, acquire the analog signal from the V-phase temperature pin, then calculate the voltage using the following hardware sampling ratio formula: V-phase temperature pin voltage = ((V-phase analog signal * sampling reference voltage) / maximum value of analog signal) / sampling ratio, thus obtaining the V-phase temperature pin voltage;

[0020] Then, calculate the resistance of the V-phase temperature pin according to the following voltage divider formula: V-phase temperature pin resistance = voltage divider resistance / ((low voltage supply voltage / V-phase temperature pin voltage) - 1), to obtain the resistance of the V-phase temperature pin;

[0021] Finally, a two-dimensional lookup table is used based on the resistance value to obtain the current V-phase temperature. If the V-phase temperature is less than 10 degrees, it indicates poor contact of the V-phase temperature pin, prompting "abnormal contact of V-phase temperature pin"; otherwise, it indicates normal contact of the V-phase temperature pin.

[0022] S13, W-phase temperature pin contact detection

[0023] First, acquire the analog signal from the W-phase temperature pin, then calculate the W-phase temperature pin voltage using the following hardware sampling ratio formula: W-phase temperature pin voltage = ((W-phase analog signal * sampling reference voltage) / maximum value of analog signal) / sampling ratio.

[0024] Then, calculate the resistance of the W-phase temperature pin according to the following voltage divider formula: W-phase temperature pin resistance = voltage divider resistance / ((low voltage supply voltage / W-phase temperature pin voltage) - 1), to obtain the resistance of the W-phase temperature pin;

[0025] Finally, a two-dimensional lookup table is used based on the resistance value to obtain the current W-phase temperature. If the W-phase temperature is less than 10 degrees, it indicates poor contact of the W-phase temperature pin, prompting "W-phase temperature pin contact abnormal"; otherwise, it indicates normal contact of the W-phase temperature pin.

[0026] In steps S11-S13 above, if any one of the three phase temperature pins (U, V, W) has an abnormal contact, the contact detection ends; if all three phase temperature pins (U, V, W) have normal contact, proceed to the next detection step to perform low-voltage detection.

[0027] As a further preferred technical solution of the present invention, the PWM waveform generation method used for contact detection of the control pin of the power module in step S2 is the center alignment method. The six transistors T1-T6 in the power module are set to output a 50% duty cycle in the default state. The PWM comparison register values ​​of the six transistors T1-T6 are all 1 / 2P, where a high level indicates that the corresponding transistor is on and a low level indicates that the transistor is off. The state when there is no current in the six transistors T1-T6 is the initialization state.

[0028] The low-voltage test in step S2 is performed in three stages, with only one phase tested each time. The upper and lower bridges of the same phase are activated in each test. The test sequentially checks the T1 and T2 tubes of phase U, the T3 and T4 tubes of phase V, and the T5 and T6 tubes of phase W. The specific steps are as follows:

[0029] The U-phase low-voltage detection first clears hardware faults, then uses a PWM comparator register value of 1 / 2P to generate a PWM waveform with a 50% duty cycle for the U-phase, and waits for 100 milliseconds. During these 100 milliseconds, it checks in real time whether the hardware reports a fault. If the hardware reports a fault, the U-phase fault flag is set to 1. If the 100 milliseconds expire and the hardware does not report a fault, the U-phase fault flag is set to 0. Then the PWM waveform is turned off, and the V-phase low-voltage detection begins.

[0030] The V-phase low-voltage detection first clears hardware faults, then uses a PWM comparator register value of 1 / 2P to generate a PWM waveform with a 50% duty cycle for the V phase, and waits for 100 milliseconds. During these 100 milliseconds, it checks in real time whether the hardware reports a fault. If the hardware reports a fault, the V-phase fault flag is set to 1. If the 100 milliseconds expire and the hardware does not report a fault, the V-phase fault flag is set to 0. Then the PWM waveform is turned off, and the W-phase low-voltage detection begins.

[0031] The low-voltage detection of phase W first clears the hardware fault, then with the PWM comparator register value of 1 / 2P, phase W PWM is emitted with a 50% duty cycle, and waits for 100 milliseconds; within these 100 milliseconds, it checks in real time whether the hardware reports a fault. If the hardware reports a fault, the fault flag of phase W is set to 1; if the 100 milliseconds expire and the hardware does not report a fault, the fault flag of phase W is set to 0; then the PWM is turned off, and the hardware fault is cleared.

[0032] Determine if the fault flags for phase U, phase V, and phase W are all 0. If any phase's fault flag is not 0, the corresponding phase's control pin has an abnormal contact, and the contact detection ends. If all are 0, it means the power module's control pin has normal contact, and proceed to the next step, bus detection.

[0033] As a further preferred technical solution of the present invention, when performing contact detection on the PN high-voltage terminal of the power module in step S3, the high-voltage power supply is first powered on, and then the AD analog quantity of the bus voltage is collected. The bus voltage refers to the voltage on the PN high-voltage terminal of the power module, and the bus voltage is calculated according to the following formula:

[0034] Bus voltage = AD analog quantity * hardware voltage base value / maximum analog quantity

[0035] Determine if the bus voltage is within ±5% of the set value. If it exceeds ±5%, indicate "PN high voltage terminal contact abnormality"; if it is within ±5%, it indicates that the PN high voltage terminal contact is normal, and proceed to the next step of high voltage detection.

[0036] As a further preferred technical solution of the present invention, in order to maintain consistency with the waveform generation situation in actual applications, the upper and lower transistors of the same phase of the power module have complementary outputs during high-voltage detection in step S4. The specific steps are as follows:

[0037] First, set the contact marks of the U-phase terminal, V-phase terminal, and W-phase terminal of the power module to 0. Then, output a fixed small target current to allow the U, V, and W phases to output AC current. Then wait for 3 seconds. The small target current refers to the maximum current that the power module can achieve without external heat dissipation, relying on its own heat dissipation without causing the power module to fail.

[0038] During the aforementioned 3-second timeout period, the system continuously monitors whether the U-phase current is within the set target ±1A range. If it is, the U-phase terminal contact flag is set to 1; otherwise, it continues to wait. The system also continuously monitors whether the V-phase current is within the set target ±1A range. If it is, the V-phase terminal contact flag is set to 1; otherwise, it continues to wait. The system also continuously monitors whether the W-phase current is within the set target ±1A range. If it is, the W-phase terminal contact flag is set to 1; otherwise, it continues to wait.

[0039] If the contact indicator of the U-phase terminal, V-phase terminal, and W-phase terminal is not all 1 after the 3-second countdown ends, it indicates that there is a contact abnormality in the three-phase terminals, prompting a contact abnormality in the corresponding phase terminal and exiting the detection.

[0040] If the contact indicators of the U-phase terminal, V-phase terminal, and W-phase terminal are all 1 within the aforementioned 3-second timer, the timer will stop, and the output will continue to use the rated current of the power module as the target current. The absolute values ​​of the current differences between the UV and U-phase, the U and W-phase, and the V and W-phase will be monitored in real time to see if they are within 1A. If they are, the test will continue according to the set operating time. The test will stop when the operating time is up. If not, it indicates that there is a contact abnormality in the U, V, and W-phase terminals, and the test will stop.

[0041] The power module contact detection method of the present invention does not require the addition of additional detection wiring harness. Utilizing the pin characteristics of the power module, and through software control algorithms and sampling, it detects the contact points of the control pins, temperature pins, PN power terminals, and three-phase power terminals that are in contact with the test bench. This not only ensures the reliability of the contact by detecting the contact at every contact point, but also monitors the reliability of the contact in real time during the aging process, thereby improving the stability of the equipment.

[0042] Moreover, by adopting the above-described technical solution, the present invention can also achieve the following beneficial effects:

[0043] 1) Capable of performing contact detection on all pins and high-voltage terminals of the power module;

[0044] 2) The power module can be detected in real time for any contact abnormalities during the test;

[0045] 3) The test structure is highly reliable and easy to operate. Attached Figure Description

[0046] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0047] Figure 1 This is a system topology diagram for power module contact detection;

[0048] Figure 2 This is the control flow chart for contact detection;

[0049] Figure 3 This is a topology diagram for temperature detection;

[0050] Figure 4 This is a flowchart for temperature detection;

[0051] Figure 5 The waveform diagram for one PWM cycle;

[0052] Figure 6 This is a flowchart of the low-pressure testing process;

[0053] Figure 7 Here is a flowchart of the busbar testing process;

[0054] Figure 8 This is a flowchart of the high-voltage testing process.

[0055] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0056] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Terms such as "upper," "lower," "left," "right," "middle," and "one" used in the preferred embodiments are merely for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention.

[0057] This invention provides a power module contact detection method that eliminates the need for additional detection wiring harnesses. Utilizing the pin (terminal) characteristics of the power module, and through software control algorithms and sampling, the method tests the control pins, temperature pins, PN power terminals, and three-phase power terminals that are in contact with the test bench. This ensures the reliability of the contact, as contact testing is performed on every contact point. Furthermore, the reliability of the contact is monitored in real time during the aging process, thereby improving the stability of the equipment.

[0058] Figure 1 The diagram shows the system topology of the power module. The power module consists of three phases: U, V, and W. Phase U is composed of transistors T1, T2, D1, and D2; phase V is composed of transistors T3, T4, D3, and D4; and phase W is composed of transistors T5, T6, D5, and D6. The power module is also connected to a high-voltage power supply and a three-phase load. The high-voltage power supply provides DC power to the power module. The U, V, and W phases of the power module are respectively connected to the three loads L1, L2, and L3 of the three-phase load. It should be noted that the power module has a temperature sampling pin; for simplicity, the corresponding temperature pin is not shown in the diagram. Figure 1 As shown in the image.

[0059] The power module is placed on a test bench. The temperature pin, control pin, PN power terminal, and three-phase power terminal of the power module are in contact with the test bench. The control flowchart for contact detection is shown below. Figure 2 As shown, it includes the following steps in sequence;

[0060] S1. Perform temperature detection to check the contact of the temperature pins of the power module;

[0061] S2. Perform low-voltage detection to check the contact of the control pins of the power module;

[0062] S3. Perform busbar testing to check the contact of the PN high-voltage terminals of the power module;

[0063] S4. Perform high voltage testing to check the contact of the three-phase power terminals of the power module, and at the same time check the contact of the control pins and PN high voltage terminals of the power module.

[0064] Specifically, for temperature detection, please refer to... Figure 3 and 4 A hardware sampling ratio circuit for contact detection of the temperature pins of the power module ( Figure 3 The power module includes a low-voltage power supply, voltage divider resistors, internal resistance of temperature pins, and a proportional circuit. One end of the internal resistance of the temperature pins is connected to ground, and the other end is split into two paths. One path is connected to the low-voltage power supply through the voltage divider resistors, and the other path is used to acquire the analog signal from the temperature pins through the proportional circuit. Each of the three phases (U, V, and W) of the power module has a temperature pin. The temperature detection performed in step S1 is divided into U-phase temperature pin contact detection, V-phase temperature pin contact detection, and W-phase temperature pin contact detection, specifically including the following steps:

[0065] S11, U-phase temperature pin contact detection

[0066] First, acquire the analog signal from the U-phase temperature pin, then calculate the U-phase temperature pin voltage using the following hardware sampling ratio formula: U-phase temperature pin voltage = ((U-phase analog signal * sampling reference voltage) / maximum value of analog signal) / sampling ratio.

[0067] Then, calculate the U-phase temperature pin resistance using the following voltage divider formula: U-phase temperature pin resistance = voltage divider resistance / ((low voltage supply voltage / U-phase temperature pin voltage) - 1), thus obtaining the U-phase temperature pin resistance;

[0068] Finally, a two-dimensional lookup table is performed based on the resistance value to obtain the current U-phase temperature. If the U-phase temperature is less than 10 degrees, it indicates poor contact of the U-phase temperature pin, prompting "U-phase temperature pin contact abnormal"; otherwise, it indicates normal contact of the U-phase temperature pin.

[0069] S12, V-phase temperature pin contact detection

[0070] First, acquire the analog signal from the V-phase temperature pin, then calculate the voltage using the following hardware sampling ratio formula: V-phase temperature pin voltage = ((V-phase analog signal * sampling reference voltage) / maximum value of analog signal) / sampling ratio, thus obtaining the V-phase temperature pin voltage;

[0071] Then, calculate the resistance of the V-phase temperature pin according to the following voltage divider formula: V-phase temperature pin resistance = voltage divider resistance / ((low voltage supply voltage / V-phase temperature pin voltage) - 1), to obtain the resistance of the V-phase temperature pin;

[0072] Finally, a two-dimensional lookup table is used based on the resistance value to obtain the current V-phase temperature. If the V-phase temperature is less than 10 degrees, it indicates poor contact of the V-phase temperature pin, prompting "abnormal contact of V-phase temperature pin"; otherwise, it indicates normal contact of the V-phase temperature pin.

[0073] S13, W-phase temperature pin contact detection

[0074] First, acquire the analog signal from the W-phase temperature pin, then calculate the W-phase temperature pin voltage using the following hardware sampling ratio formula: W-phase temperature pin voltage = ((W-phase analog signal * sampling reference voltage) / maximum value of analog signal) / sampling ratio.

[0075] Then, calculate the resistance of the W-phase temperature pin according to the following voltage divider formula: W-phase temperature pin resistance = voltage divider resistance / ((low voltage supply voltage / W-phase temperature pin voltage) - 1), to obtain the resistance of the W-phase temperature pin;

[0076] Finally, a two-dimensional lookup table is used based on the resistance value to obtain the current W-phase temperature. If the W-phase temperature is less than 10 degrees, it indicates poor contact of the W-phase temperature pin, prompting "W-phase temperature pin contact abnormal"; otherwise, it indicates normal contact of the W-phase temperature pin.

[0077] In steps S11-S13 above, if any one of the three phase temperature pins (U, V, W) has an abnormal contact, the contact detection ends; if all three phase temperature pins (U, V, W) have normal contact, proceed to the next detection step to perform low-voltage detection.

[0078] Specifically, for low-pressure testing, please refer to [link / reference]. Figure 5 and 6 During low-voltage detection, the PWM waveform is center-aligned. When counting upwards, a high level is output when the counter value matches the comparison register value; when counting downwards, a low level is output when the counter value matches the comparison register value. Figure 5 The waveform shown is for one PWM cycle. The default state of the six transistors (T1-T6) is to output a 50% duty cycle. The PWM compare register values ​​of the six transistors are all 1 / 2P, where a high level indicates that the corresponding transistor is on, and a low level indicates that the transistor is off. The initialization state is defined as the state in which there is no current in the six transistors.

[0079] Figure 6 This is a flowchart for low-pressure testing. To ensure the reliability of contact testing and identify which specific phase has an abnormal contact, it facilitates problem identification. Low-pressure testing is performed in three stages, testing one phase at a time. For each contact test, the upper and lower bridges of the corresponding phase are activated. First, tubes T1 and T2 are tested, followed by tubes T3 and T4, and finally tubes T5 and T6. The specific steps are as follows:

[0080] The U-phase low-voltage detection first clears hardware faults, then generates a PWM waveform with a 50% duty cycle (PWM comparator register value is 1 / 2P), and waits for 100 milliseconds. During these 100 milliseconds, it continuously monitors for hardware fault reports. If a hardware fault is reported, the U-phase fault flag is set to 1; if no hardware fault is reported after 100 milliseconds, the U-phase fault flag is set to 0. Then, the PWM waveform is turned off, and the V-phase low-voltage detection begins. If there is a contact problem, the hardware will report a fault when the switch generates the waveform; therefore, hardware faults must be cleared before performing low-voltage detection on the corresponding phase.

[0081] The V-phase low-voltage detection first clears hardware faults, then generates a PWM waveform with a 50% duty cycle in the V phase (the PWM compare register value is 1 / 2P), and waits for 100 milliseconds. During these 100 milliseconds, it continuously monitors whether the hardware reports a fault. If the hardware reports a fault, the V-phase fault flag is set to 1; if no fault is reported by the end of the 100 milliseconds, the V-phase fault flag is set to 0; then the PWM waveform is turned off, and the W-phase low-voltage detection begins.

[0082] The W-phase low-voltage detection first clears hardware faults, then generates a PWM waveform with a 50% duty cycle (PWM comparator register value is 1 / 2P), and waits for 100 milliseconds. During these 100 milliseconds, it continuously monitors for hardware fault reports. If a hardware fault is reported, the W-phase fault flag is set to 1; if no hardware fault is reported within 100 milliseconds, the W-phase fault flag is set to 0. Next, the PWM waveform is turned off, the hardware fault is cleared, and it is checked whether the U-phase, V-phase, and W-phase fault flags are all 0. If not, any phase's fault flag that is not 0 indicates a contact abnormality in that phase's control pin, and the contact detection ends. If yes, it indicates that the power module control pin contact is normal, and the process proceeds to the next step, bus detection.

[0083] Specifically, busbar detection parameters Figure 7 First, the high-voltage power supply is powered on. Then, the analog signal (AD) of the bus voltage is acquired, and the bus voltage is calculated (bus voltage = AD analog signal * hardware voltage base value / maximum analog signal value). When acquiring the bus voltage using AD analog signal acquisition, the analog signal refers to the voltage sampled by the MCU. The actual voltage value corresponding to 1V is called the hardware voltage base value, and the maximum analog signal value refers to the maximum value of the AD analog signal sampled by the MCU. The system checks whether the bus voltage is within ±5% of a set value (this set value is related to the high-voltage power supply and hardware sampling accuracy, and is adjusted according to actual needs in practical applications). If it exceeds ±5%, a "PN terminal contact abnormality" message is displayed. If it is within ±5%, it indicates normal PN terminal contact, and the system continues to the next step of high-voltage detection.

[0084] Specifically, see high voltage testing. Figure 8To maintain consistency with actual power output in real-world applications, the upper and lower transistors of the same phase of the power module provide complementary outputs (i.e., the lower transistor is off when the upper transistor is on, or vice versa). The specific testing procedure is as follows:

[0085] First, set the contact flags for the U-phase, V-phase, and W-phase terminals to 0. Then, output a fixed small target current to allow the U, V, and W phases to output AC current. Wait for 3 seconds. The contact flags are software flags; when a phase experiences poor contact and a hardware fault is reported, the corresponding flag is set to 1. The small current target refers to the maximum current the module can achieve without external heat dissipation, relying solely on its own cooling without causing module failure; it is generally below 20A.

[0086] Within the aforementioned 3-second timeframe, the system continuously monitors whether the U-phase current is within the set target range of ±1A (where ±1A is determined by the accuracy of the current Hall sensor; in practical applications, other suitable deviations can also be set). If it is, the U-phase terminal contact flag is set to 1; otherwise, the system continues to wait. Similarly, the system continuously monitors whether the V-phase current is within the set target range of ±1A. If it is, the V-phase terminal contact flag is set to 1; otherwise, the system continues to wait. Finally, the system continuously monitors whether the W-phase current is within the set target range of ±1A. If it is, the W-phase terminal contact flag is set to 1; otherwise, the system continues to wait.

[0087] If the contact indicator of the U-phase terminal, V-phase terminal, and W-phase terminal is not all 1 after the 3-second countdown ends, it indicates that there is a contact abnormality in the three-phase terminals, prompting a message that the corresponding phase terminal is in contact abnormality and exiting the detection.

[0088] If the contact indicators of the U-phase terminal, V-phase terminal, and W-phase terminal are all 1 within these 3 seconds, the timing will stop, and the high current target (the rated current of the module) will continue to be output. The absolute values ​​of the current differences between the U and V phases, the U and W phases, and the V and W phases will be monitored in real time to see if they are within 1A. If they are, the test will run according to the set operating time. The test will stop when the operating time is up. If not, it indicates that there is a contact abnormality in the U, V, and W phase terminals, and the test will stop.

[0089] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and various changes or modifications can be made to these embodiments without departing from the principles and essence of the present invention. The scope of protection of the present invention is defined only by the appended claims.

Claims

1. A power module contact detection method, characterized by, The power module is divided into three phases: U, V, and W. The U phase consists of transistors T1, T2, D1, and D2; the V phase consists of transistors T3, T4, D3, and D4; and the W phase consists of transistors T5, T6, D5, and D6. The power module is also connected to a high-voltage power supply and a three-phase load. The high-voltage power supply provides DC power to the power module, and the U, V, and W phases of the power module are respectively connected to the three loads L1, L2, and L3 of the three-phase load. The power module is placed on a test bench, and its temperature pin, control pin, PN power terminal, and three-phase power terminal are respectively in contact with the test bench for contact testing in the following steps: Step S1: Perform temperature detection to check the contact of the temperature pins of the power module; Step S2: Perform low voltage detection to check the contact of the control pins of the power module; Step S3: Perform busbar testing to check the contact of the PN high-voltage terminals of the power module; Step S4: Perform high-voltage testing to check the contact of the three-phase power terminals of the power module, and simultaneously check the contact of the control pins and PN high-voltage terminals of the power module; wherein, The hardware sampling proportional circuit for contact detection of the temperature pin of the power module in step S1 includes a low-voltage power supply, a voltage divider resistor, the internal resistance of the temperature pin, and a proportional circuit. One end of the internal resistance of the temperature pin is connected to ground, and the other end is split into two paths. One path is connected to the low-voltage power supply through the voltage divider resistor, and the other path is used to realize the analog signal acquisition of the temperature pin through the proportional circuit. The power module has temperature pins for each of its three phases (U, V, and W). The temperature detection performed in step S1 is divided into U-phase temperature pin contact detection, V-phase temperature pin contact detection, and W-phase temperature pin contact detection, specifically including the following steps: S11, U-phase temperature pin contact detection First, acquire the analog signal from the U-phase temperature pin, then calculate the U-phase temperature pin voltage using the following hardware sampling ratio formula: U-phase temperature pin voltage = ((U-phase analog signal * sampling reference voltage) / maximum value of analog signal) / sampling ratio. Then, calculate the U-phase temperature pin resistance using the following voltage divider formula: U-phase temperature pin resistance = voltage divider resistance / ((low voltage supply voltage / U-phase temperature pin voltage) - 1), thus obtaining the U-phase temperature pin resistance; Finally, a two-dimensional lookup table is performed based on the resistance value to obtain the current U-phase temperature. If the U-phase temperature is less than 10 degrees, it indicates poor contact of the U-phase temperature pin, prompting "U-phase temperature pin contact abnormal"; otherwise, it indicates normal contact of the U-phase temperature pin.

2. The power module contact detection method of claim 1, wherein, The hardware sampling proportional circuit for contact detection of the temperature pin of the power module in step S1 includes a low-voltage power supply, a voltage divider resistor, the internal resistance of the temperature pin, and a proportional circuit. One end of the internal resistance of the temperature pin is connected to ground, and the other end is split into two paths. One path is connected to the low-voltage power supply through the voltage divider resistor, and the other path is used to realize the analog signal acquisition of the temperature pin through the proportional circuit. The power module has temperature pins for each of its three phases (U, V, and W). The temperature detection performed in step S1 is divided into U-phase temperature pin contact detection, V-phase temperature pin contact detection, and W-phase temperature pin contact detection, specifically including the following steps: S11, U-phase temperature pin contact detection First, acquire the analog signal from the U-phase temperature pin, then calculate the U-phase temperature pin voltage using the following hardware sampling ratio formula: U-phase temperature pin voltage = ((U-phase analog signal * sampling reference voltage) / maximum value of analog signal) / sampling ratio. Then, calculate the U-phase temperature pin resistance using the following voltage divider formula: U-phase temperature pin resistance = voltage divider resistance / ((low voltage supply voltage / U-phase temperature pin voltage) - 1), thus obtaining the U-phase temperature pin resistance; Finally, a two-dimensional lookup table is performed based on the resistance value to obtain the current U-phase temperature. If the U-phase temperature is less than 10 degrees, it indicates poor contact of the U-phase temperature pin, prompting "U-phase temperature pin contact abnormal"; otherwise, it indicates normal contact of the U-phase temperature pin. S12, V-phase temperature pin contact detection First, acquire the analog signal from the V-phase temperature pin, then calculate the voltage using the following hardware sampling ratio formula: V-phase temperature pin voltage = ((V-phase analog signal * sampling reference voltage) / maximum value of analog signal) / sampling ratio, thus obtaining the V-phase temperature pin voltage; Then, calculate the resistance of the V-phase temperature pin according to the following voltage divider formula: V-phase temperature pin resistance = voltage divider resistance / ((low voltage supply voltage / V-phase temperature pin voltage) - 1), to obtain the resistance of the V-phase temperature pin; Finally, a two-dimensional lookup table is performed based on the resistance value to obtain the current V-phase temperature. If the V-phase temperature is less than 10 degrees, it indicates poor contact of the V-phase temperature pin, prompting "abnormal contact of V-phase temperature pin"; otherwise, it indicates normal contact of the V-phase temperature pin. S13, W-phase temperature pin contact detection First, acquire the analog signal from the W-phase temperature pin, then calculate the W-phase temperature pin voltage using the following hardware sampling ratio formula: W-phase temperature pin voltage = ((W-phase analog signal * sampling reference voltage) / maximum value of analog signal) / sampling ratio. Then, calculate the resistance of the W-phase temperature pin according to the following voltage divider formula: W-phase temperature pin resistance = voltage divider resistance / ((low voltage supply voltage / W-phase temperature pin voltage) - 1), to obtain the resistance of the W-phase temperature pin; Finally, a two-dimensional lookup table is used based on the resistance value to obtain the current W-phase temperature. If the W-phase temperature is less than 10 degrees, it indicates that the W-phase temperature pin has poor contact, and the message "W-phase temperature pin contact abnormal" is displayed; otherwise, it indicates that the W-phase temperature pin has normal contact. In steps S11-S13 above, if any one of the three phase temperature pins (U, V, W) has an abnormal contact, the contact detection ends; if all three phase temperature pins (U, V, W) have normal contact, proceed to the next detection step to perform low-voltage detection.

3. The power module contact detection method according to claim 1, characterized in that, In step S2, the PWM waveform generation method used for contact detection of the control pins of the power module is the center alignment method. The six transistors T1-T6 in the power module are set to output a 50% duty cycle by default. The PWM comparison register values ​​of the six transistors T1-T6 are all 1 / 2P, where a high level indicates that the corresponding transistor is on and a low level indicates that the transistor is off. The state when there is no current in the six transistors T1-T6 is the initialization state. The low-voltage test in step S2 is performed in three stages, with only one phase tested each time. The upper and lower bridges of the same phase are activated in each test. The test sequentially checks the T1 and T2 tubes of phase U, the T3 and T4 tubes of phase V, and the T5 and T6 tubes of phase W. The specific steps are as follows: The U-phase low-voltage detection first clears hardware faults, then uses a PWM comparator register value of 1 / 2P to generate a PWM waveform with a 50% duty cycle for the U-phase, and waits for 100 milliseconds. During these 100 milliseconds, it checks in real time whether the hardware reports a fault. If the hardware reports a fault, the U-phase fault flag is set to 1. If the 100 milliseconds expire and the hardware does not report a fault, the U-phase fault flag is set to 0. Then the PWM waveform is turned off, and the V-phase low-voltage detection begins. The V-phase low-voltage detection first clears hardware faults, then uses a PWM comparator register value of 1 / 2P to generate a PWM waveform with a 50% duty cycle for the V phase, and waits for 100 milliseconds. During these 100 milliseconds, it checks in real time whether the hardware reports a fault. If the hardware reports a fault, the V-phase fault flag is set to 1. If the 100 milliseconds expire and the hardware does not report a fault, the V-phase fault flag is set to 0. Then the PWM waveform is turned off, and the W-phase low-voltage detection begins. The low-voltage detection of phase W first clears the hardware fault, then with the PWM comparator register value of 1 / 2P, phase W PWM is emitted with a 50% duty cycle, and waits for 100 milliseconds; within these 100 milliseconds, it checks in real time whether the hardware reports a fault. If the hardware reports a fault, the fault flag of phase W is set to 1; if the 100 milliseconds expire and the hardware does not report a fault, the fault flag of phase W is set to 0; then the PWM is turned off, and the hardware fault is cleared. Determine if the fault flags for phase U, phase V, and phase W are all 0. If any phase's fault flag is not 0, the corresponding phase's control pin has an abnormal contact, and the contact detection ends. If all are 0, it means the power module's control pin has normal contact, and proceed to the next step, bus detection.

4. The power module contact detection method according to claim 1, characterized in that, In step S3, when performing contact detection on the PN high-voltage terminal of the power module, first control the high-voltage power supply to power on, and then collect the AD analog quantity of the bus voltage. The bus voltage refers to the voltage on the PN high-voltage terminal of the power module, and the bus voltage is calculated according to the following formula: Bus voltage = AD analog quantity * hardware voltage base value / maximum analog quantity Determine if the bus voltage is within ±5% of the set value. If it exceeds ±5%, indicate "PN high voltage terminal contact abnormality"; if it is within ±5%, it indicates that the PN high voltage terminal contact is normal, and proceed to the next step of high voltage detection.

5. The power module contact detection method according to claim 1, characterized in that, In step S4, during high-voltage detection, to maintain consistency with the waveform generation in actual applications, the upper and lower transistors of the same phase of the power module provide complementary outputs. The specific steps are as follows: First, set the contact marks of the U-phase terminal, V-phase terminal, and W-phase terminal of the power module to 0. Then, output a fixed small target current to allow the U, V, and W phases to output AC current. Then wait for 3 seconds. The small target current refers to the maximum current that the power module can achieve without external heat dissipation, relying on its own heat dissipation without causing the power module to fail. During the aforementioned 3-second timeout period, the system continuously monitors whether the U-phase current is within the set target ±1A range. If it is, the U-phase terminal contact flag is set to 1; otherwise, it continues to wait. The system also continuously monitors whether the V-phase current is within the set target ±1A range. If it is, the V-phase terminal contact flag is set to 1; otherwise, it continues to wait. The system also continuously monitors whether the W-phase current is within the set target ±1A range. If it is, the W-phase terminal contact flag is set to 1; otherwise, it continues to wait. If the contact indicator of the U-phase terminal, V-phase terminal, and W-phase terminal is not all 1 after the 3-second countdown ends, it indicates that there is a contact abnormality in the three-phase terminals, prompting a contact abnormality in the corresponding phase terminal and exiting the detection. If the contact indicators of the U-phase terminal, V-phase terminal, and W-phase terminal are all 1 within the aforementioned 3-second timer, the timer will stop, and the output will continue to use the rated current of the power module as the target current. The absolute values ​​of the current differences between the UV and U-phase, the U and W-phase, and the V and W-phase will be monitored in real time to see if they are within 1A. If they are, the test will continue according to the set operating time. The test will stop when the operating time is up. If not, it indicates that there is a contact abnormality in the U, V, and W-phase terminals, and the test will stop.

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