Display panel and display device

Abstract

A display panel and a display device are provided, including: a substrate including an active area and a non-active area surrounding the active area and including first, second, and third areas spaced apart from each other; at least one signal line disposed in each of the first to third areas; at least one connection pattern disposed on the at least one signal line; a sealant disposed in the non-active area. In at least one of the first to third areas of the non-active area of the display panel and the display device, i) the at least one signal line and the at least one connection pattern overlap each other, ii) the at least one signal line includes a mesh-shaped area having at least one opening, iii) the at least one connection pattern can not overlap a part or all of the at least one opening, and iv) the sealant can overlap a part or all of at least one of the first, second, and third areas of the non-active area. With this configuration, a material as the sealant can be easily or sufficiently hardened or cured.

Description

[0001] This application is a divisional application of the parent application with the application date of December 2, 2019, the application number of 201911213981.7, and the invention name of "Display panel and display device".

[0002] Cross Reference to Related Applications

[0003] This application claims the priority of Korean Patent Application No. 10-2018-0165764 filed on December 20, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0004] The present disclosure relates to a display panel and a display device. BACKGROUND

[0005] A liquid crystal display device has a high contrast ratio and a low power consumption. The liquid crystal display device is advantageous in displaying a moving image, and thus is used for various types of electronic devices such as a notebook computer, a monitor, and a TV. Liquid crystal has a thin and long molecular structure, has optical anisotropy (directionality in alignment), and has a polarization property (a direction of molecular alignment is changed according to its size when located in an electric field). The liquid crystal display device displays an image on a screen using such optical anisotropy and polarization property of the liquid crystal.

[0006] A typical process of manufacturing a liquid crystal display is divided into a substrate manufacturing process for forming an array substrate and a color filter substrate, a cell process for manufacturing a liquid crystal panel, and a module process for integrating the liquid crystal panel and a backlight unit.

[0007] In the process of manufacturing the liquid crystal panel, in order to bond the array substrate and the color filter substrate together, a sealant is formed at the periphery of the substrate. The sealant also serves to maintain a cell gap. In order for the reliability of the liquid crystal panel, it is necessary to sufficiently harden the sealant, and it is also important to shorten the time required to harden the sealant. SUMMARY

[0008] Accordingly, the present disclosure relates to a display panel and a display device that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0009] At least one object of the present disclosure is to provide a display panel and a display device having a structure that enables a sealant disposed in an unactive area to be sufficiently hardened or cured.

[0010] At least one object of the present disclosure is to provide a display panel and a display device having a structure that enables a sealant material disposed in an unactive area to be rapidly hardened or cured.

[0011] At least one object of the present disclosure is to provide a display panel and a display device having a structure that enables a size of an inactive area to be reduced.

[0012] According to one aspect of the present disclosure, a display panel and a display device are provided, the display panel and the display device comprising: a substrate including an active area and an inactive area, the inactive area surrounding the active area and including a first area, a second area, and a third area spaced apart from each other; at least one signal line disposed in each of the first area, the second area, and the third area; at least one connection pattern disposed on the at least one signal line; and a sealant disposed in the inactive area. In at least one of the first area, the second area, and the third area of ​​the inactive area of ​​the display panel and the display device, i) the at least one signal line and the at least one connection pattern overlap with each other, ii) the at least one signal line includes a grid-shaped area having at least one opening, iii) the at least one connection pattern may not overlap with a portion or all of the at least one opening, and iv) the sealant may overlap with a portion or all of at least one of the first area, the second area, and the third area of ​​the inactive area.

[0013] In the first region, the region in which the at least one signal line has the at least one opening may further include at least one active layer, and the at least one active layer overlaps at least a portion of the at least one signal line.

[0014] First and second connection patterns may be disposed over the at least one active layer, and each of the first and second connection patterns may be electrically connected to the at least one active layer.

[0015] The first and second connection patterns are disposed to be spaced apart from each other, and each of the first and second connection patterns may be connected to a plurality of data lines arranged in the active area.

[0016] In the second region, the at least one connection pattern may have at least one opening at a position corresponding to the at least one opening of the at least one signal line.

[0017] At least one insulating film can be disposed between the at least one connection pattern and the at least one signal line in the second area, and the at least one connection pattern can be electrically connected to the at least one signal line through at least one hole formed in the insulating film in an area where the at least one connection pattern overlaps the at least one signal line.

[0018] At least one gate driving circuit is disposed in the third area, and the at least one connection pattern disposed in the third area can be electrically connected to the gate driving circuit.

[0019] The encapsulant can overlap the at least one opening of the at least one signal line.

[0020] According to an aspect of the disclosure, a display panel includes a first substrate including an active area and a non-active area surrounding the active area and including a first area, a second area, and a third area spaced apart from each other, at least one signal line disposed in each of the first area, the second area, and the third area, at least one connection pattern disposed above the at least one signal line, a second substrate facing the first substrate, and an encapsulant disposed between the first substrate and the second substrate and in the non-active area, wherein, in at least one of the first area, the second area, and the third area, the at least one signal line and the at least one connection pattern overlap each other, and the at least one signal line includes an area having at least one opening, wherein the at least one connection pattern does not overlap all or a part of the at least one opening.

[0021] According to embodiments of the disclosure, it is possible to provide a display panel and display device having a structure enabling an encapsulant disposed in a non-active area to be sufficiently hardened or cured.

[0022] According to embodiments of the disclosure, it is possible to provide a display panel and display device having a structure enabling an encapsulant material disposed in a non-active area to be rapidly hardened or cured.

[0023] According to embodiments of the disclosure, it is possible to provide a display panel and display device having a structure enabling a size of a non-active area to be reduced.

[0024] Additional features and advantages of the disclosure will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the disclosure. The objectives and other advantages of the disclosure will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a view schematically illustrating a system configuration of an electronic device according to an embodiment of the disclosure.

[0026] Figure 2 is a view illustrating a system implementation of an electronic device according to an embodiment of the disclosure.

[0027] Figure 3 is a view illustrating a portion of a display device according to an embodiment of the disclosure.

[0028] Figure 4 is a cross-sectional view illustrating a first region corresponding to a portion of an X region of Figure 2 .

[0029] Figure 5 is a cross-sectional view taken along line A-B of Figure 4 .

[0030] Figure 6 is a cross-sectional view taken along line C-D of Figure 4 .

[0031] Figure 7 is a cross-sectional view illustrating a second region corresponding to a portion of an X region of Figure 2 .

[0032] Figure 8 is a cross-sectional view taken along line E-F of Figure 7 .

[0033] Figure 9 is a cross-sectional view taken along line G-H of Figure 7 .

[0034] Figure 10 is a cross-sectional view illustrating a third region corresponding to a portion of an X region of Figure 2 .

[0035] Figure 11 is a cross-sectional view taken along line I-J of Figure 10 .

[0036] Figure 12 is a cross-sectional view taken along line K-L of Figure 10 . DETAILED DESCRIPTION

[0037] Advantages and features of the present disclosure and methods for implementing the same can become apparent from the following detailed description of the present disclosure and the accompanying drawings. However, the present disclosure is not limited to the following aspects set forth below but can be implemented in various forms. The following aspects are provided only to more completely disclose the present disclosure and to fully convey the scope thereof to those skilled in the art, and the present disclosure is only defined by the appended claims.

[0038] Further, shapes, sizes, ratios, angles, numbers, and the like shown in the drawings for describing exemplary embodiments of the present disclosure are merely examples and the present disclosure is not limited thereto. Throughout the specification, like drawing reference numerals will be understood to refer to like parts throughout the specification and / or drawings, and similar elements will not be described again. Further, in the following description of the present disclosure, when it is determined that a detailed description of known functions and configurations included herein can make the subject matter rather unclear in some embodiments of the present disclosure, the detailed description will be omitted. The terms such as "include", "have", "comprise", "consist of", and "consist" used herein are generally intended to allow additional components to be added, unless these terms are used with the term "only". As used herein, the singular form is intended to include the plural form as well, unless the context clearly dictates otherwise.

[0039] When explaining any element or feature of the embodiments of the present disclosure, even if not specifically described, it should be considered that any dimension and relative size of a layer, a part, and a region include a tolerance or an error range.

[0040] Terms such as first, second, A, B, (A), or (B) can be used herein to describe elements of the present disclosure. Each term is not used to define the nature, order, sequence, or number of elements, but is used only to distinguish the corresponding element from other elements. When referring to one element "connected" or "coupled" to another element, it should be interpreted that a third element can be "interposed" between the elements or the elements can be "connected" or "coupled" to each other through the third element, as well as one element being directly connected or coupled to another element. Spatially relative terms such as "on", "above", "upper", "below", "lower", "down", "up", "proximate", "near", "adjacent", and the like can be used herein to describe the relationship of one element or feature to other elements or features as shown in the drawings, and should be interpreted that one or more elements can be further "interposed" between the elements, unless terms such as "directly", "only" are used.

[0041] Any element or feature of the embodiments of the present disclosure is not limited to the specific meaning of the above terms. The terms used herein are only used to describe the purpose of examples and are not intended to limit the present disclosure. Although the terms "first", "second" etc. are used to describe various elements or features, these elements are not limited by these terms. These terms are only used to distinguish one element from other elements. Therefore, the first element mentioned below can be the second element in the technical concept of the present disclosure.

[0042] As those skilled in the art can fully understand, the elements or features of each exemplary embodiment of the present disclosure can be partially or completely combined or combined with each other and can be technically associated and operated in various ways, and each exemplary embodiment can be implemented independently or in association with each other.

[0043] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 is a view schematically showing a system configuration of an electronic device according to an embodiment of the present disclosure.

[0045] The electronic device according to the embodiment of the present disclosure may include a display device, an illumination device, a light-emitting device, etc. In the following, for ease of description, the electronic device is discussed based on the display device. It should be understood that the embodiments or examples of the present disclosure can be equally applied to any electronic device including transistors such as an illumination device, a light-emitting device, etc. and a display device. It is also part of the present disclosure to incorporate any whole or part of one or more embodiments or examples of the present disclosure into such an electronic device.

[0046] According to an embodiment of the present disclosure, the electronic device may include a panel PNL for displaying an image or outputting light and a driving circuit (or driver) for driving the panel PNL.

[0047] The panel PNL may include a plurality of data lines DL, a plurality of gate lines GL, and a plurality of sub-pixels SP, and the plurality of sub-pixels SP may be arranged in a matrix form in a region defined by the plurality of data lines DL and the plurality of gate lines GL.

[0048] A plurality of data lines DL and a plurality of gate lines GL may be arranged in the panel PNL such that the data lines DL and the gate lines GL intersect each other. For example, the plurality of gate lines GL may be arranged in rows or columns, and the plurality of data lines DL may be arranged in columns or rows. Hereinafter, for ease of description and understanding, it may be assumed that the plurality of gate lines GL are arranged in rows, and the plurality of data lines DL are arranged in columns.

[0049] In addition to the plurality of gate lines GL and the plurality of data lines DL, the panel PNL can include other types of signal lines depending on the structure of the sub-pixels, etc. For example, the display panel can further include at least one driving voltage line, at least one reference voltage line, at least one common voltage line, etc.

[0050] The panel PNL can be one of various types of panels such as a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) panel, etc.

[0051] The type of signal lines arranged in the panel PNL can differ depending on the sub-pixel structure, the type of panel (LCD panel, OLED panel, etc.), etc. In this context, the signal lines can include electrodes to which signals are applied.

[0052] The panel PNL can include an active area A / A in which an image is displayed and a non-active area N / A which is a peripheral area of the active area A / A in which an image is not displayed. Here, the non-active area N / A can sometimes be referred to as a bezel area or a margin of the panel or display device.

[0053] The plurality of sub-pixels SP can be arranged in the active area A / A to display an image.

[0054] The conductive pads electrically connected to the data driver DDR can be arranged in the non-active area N / A, and the plurality of data link lines can be arranged to be connected between the conductive pads and the plurality of data lines DL. Here, the conductive pads can be formed of an array or other arrangement of conductive traces or conductive patches. Here, the plurality of data link lines can be a portion of the plurality of data lines DL extending into the non-active area N / A or a separate pattern electrically connected to the plurality of data lines DL.

[0055] In addition, lines related to gate driving can be arranged in the non-active area N / A to deliver a voltage (signal) required to drive a gate of at least one transistor contained in at least one sub-pixel to the gate driver GDR through the conductive pads electrically connected to the data driver DDR. For example, the lines related to gate driving can include a clock line for delivering a clock signal, a gate voltage line for delivering a gate voltage VGH and VGL, a gate driving control signal line for delivering various control signals required to generate a scan signal, etc. Unlike the gate lines GL arranged in the active area A / A, the lines related to gate driving can be arranged in the non-active area N / A.

[0056] The driving circuit can include a data driver DDR for driving the plurality of data lines DL, a gate driver GDR for driving the plurality of gate lines GL, and a controller CTR for controlling the data driver DDR and the gate driver GDR.

[0057] The data driver DDR can drive the plurality of data lines DL by supplying data voltages to the plurality of data lines DL.

[0058] The gate driver GDR can drive the plurality of gate lines GL by supplying scan signals to the plurality of gate lines GL.

[0059] The controller CTR can control the driving operations of the data driver DDR and the gate driver GDR by supplying various control signals DCS and GCS required to drive the data driver DDR and the gate driver GDR. The controller CTR can supply the image data DATA to the data driver DDR.

[0060] The controller CTR enables the start of scanning of the subpixels according to the timing processed in each frame. The controller CTR converts the image data input from other devices or an image supply source into a form of a data signal used in the data driver DDR, outputs the image data DATA obtained by the conversion, and enables the update of the data lines during the scanning of the subpixels.

[0061] To control the data driver (DDR) and the gate driver (GDR), the controller (CTR) receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE) signal, a clock signal (CLK), etc. from other devices or an image supply source such as a host system, and generates various control signals and outputs the generated signals to the data driver (DDR) and the gate driver (GDR).

[0062] For example, to control the gate driver GDR, the controller CTR outputs several types of gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, etc.

[0063] In addition, to control the data driver DDR, the controller CTR outputs various data control signals DCS including a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, etc.

[0064] The controller can be a timing controller used in typical display technology, or can be a control device / apparatus capable of additionally performing other control functions in addition to the typical functions of the timing controller.

[0065] The controller CTR can be implemented as a component separate from the data driver DDR, or can be implemented as an integrated circuit by being integrated with the data driver DDR.

[0066] After receiving the image data DATA from the controller CTR, the data driver DDR drives the plurality of data lines DL by supplying data voltages to the plurality of data lines DL. Herein, the data driver DDR can sometimes be referred to as a source driver.

[0067] The data driver DDR can transmit and / or receive various signals to and / or from the controller CTR through various interfaces.

[0068] The gate driver GDR sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Herein, the gate driver GDR can sometimes be referred to as a scan driver.

[0069] According to the control of the controller CTR, the gate driver GDR sequentially supplies scan signals having an on-voltage level or an off-voltage level to the plurality of gate lines GL.

[0070] When a particular gate line is driven by a scan signal from the gate driver GDR, the data driver DDR converts the image data DATA received from the controller CTR into an analog data voltage, and supplies the obtained analog data voltage to the plurality of data lines DL.

[0071] According to a driving scheme, a panel design scheme, etc., the data driver DDR can be located at only one side (e.g., an upper side or a lower side) of the panel PNL, without being limited thereto, or in some embodiments, the data driver DDR can be located at both sides (e.g., an upper side and a lower side) of the panel PNL, without being limited thereto.

[0072] According to a driving scheme, a panel design scheme, etc., the gate driver GDR can be located at only one side (e.g., a left side or a right side) of the panel PNL, without being limited thereto, or in some embodiments, the gate driver GDR can be located at both sides (e.g., a left side and a right side) of the panel PNL, without being limited thereto.

[0073] The data driver DDR can be implemented by including one or more source driving integrated circuits SDICs.

[0074] Each source driving integrated circuit SDIC can include a shift register, a latch circuit, a digital-to-analog converter DAC, an output buffer, etc. In some embodiments, the data driver DDR can further include one or more analog-to-digital converters ADCs.

[0075] Each source driving integrated circuit SDIC can be connected to at least one pad such as a bonding pad of the panel PNL in a tape automated bonding (TAB) type or a chip on glass (COG) type, or can be directly disposed on the panel PNL. In some embodiments, each source driving integrated circuit SDIC can be integrated and disposed on the panel PNL. Further, each source driving integrated circuit SDIC can be implemented in a chip on film (COF) type. In this case, each source driving integrated circuit SDIC can be mounted on a circuit film, and electrically connected with the data line DL arranged in the panel PNL through the circuit film.

[0076] The gate driver GDR can include a plurality of gate driving circuits GDC. Here, each of the plurality of gate driving circuits GDC can correspond to one or more of the plurality of gate lines.

[0077] Each gate driving circuit GDC can include a shift register, a level shifter, etc.

[0078] Each gate driving circuit GDC can be connected to at least one pad such as a bonding pad of the panel PNL in a tape automated bonding (TAB) type or a chip on glass (COG) type. Here, the bonding pad can be formed of a conductive line or a conductive patch. Further, each gate driving circuit GDC can be implemented in a chip on film (COF) type. In this case, each gate driving circuit GDC can be mounted on a circuit film, and electrically connected with the gate line GL arranged in the panel PNL through the circuit film. Each gate driving circuit GDC can be integrated into the panel PNL by being implemented in a gate in panel (GIP) type. That is, each gate driving circuit GDC can be directly formed in the panel PNL.

[0079] Figure 2 is a view illustrating a system implementation of an electronic device according to an embodiment of the disclosure.

[0080] Reference Figure 2 In the electronic device according to the embodiment of the disclosure, the data driver DDR can be implemented in a chip on film (COF) type among various types such as a TAB, a COG, a COF, a GIP, etc. Further, the gate driver GDR can be implemented in a gate in panel (GIP) type among the various types such as a TAB, a COG, a COF, a GIP, etc.

[0081] The data driver DDR can be implemented as one or more source driving integrated circuits SDIC. Figure 2 An example of the data driver DDR implemented as a plurality of source driving integrated circuits SDIC is illustrated.

[0082] When the data driver DDR is implemented in a COF type, each source driving integrated circuit SDIC performing a function of the data driver DDR can be mounted on a source side circuit film SF.

[0083] The conductive pad disposed in the non-active area N / A of the panel PNL can be electrically connected to one side of the source side circuit film SF.

[0084] One or more lines electrically connected between the source driving integrated circuit SDIC and the panel PNL can be disposed on the source side circuit film SF.

[0085] For the circuit connection between the plurality of source driving integrated circuits SDIC and other units or electronic elements, the electronic device can include at least one source printed circuit board SP CB, a control printed circuit board CPCB for mounting a control unit or component, and other electrical components, units, or devices.

[0086] The other side of the source side circuit film SF in which the source driving integrated circuit SDIC is mounted can be connected to the at least one source printed circuit board SP CB.

[0087] That is, one side and the other side of the source side circuit film SF in which the source driving integrated circuit SDIC is mounted can be electrically connected to the non-active area N / A of the panel PNL and the source printed circuit board SP CB, respectively.

[0088] The controller CTR for controlling the data driver DDR, the gate driver GDR, or the like can be provided on the control printed circuit board CPCB.

[0089] In addition, a power management integrated circuit PMIC for supplying various voltages or currents to the panel PNL, the data driver DDR, the gate driver GDR, or the like, or controlling various voltages or currents to be supplied, can be provided on the control printed circuit board CPCB.

[0090] The source printed circuit board SP CB and the control printed circuit board CPCB can be connected to each other to enable the current to be transmitted through at least one connector CBL. Here, the connector CBL can be a flexible printed circuit FPC, a flexible flat cable, or the like.

[0091] The at least one source printed circuit board SP CB and the control printed circuit board CPCB can be integrated into one printed circuit board.

[0092] When the gate driver GDR is implemented in a gate-in-panel (GIP) type, a plurality of gate driving circuits GDC included in the gate driver GDR can be directly formed in the non-active area N / A of the panel PNL.

[0093] Each of the plurality of gate driving circuits GDC can output a scan signal to a corresponding gate line arranged in the active area A / A of the panel PNL.

[0094] The plurality of gate driving circuits GDC arranged in the panel PNL can receive various signals (a clock signal, a high-level gate voltage (VGH), a low-level gate voltage (VGL), a start signal (VST), a reset signal (RST), etc.) required to generate a scan signal through gate driving-related lines arranged in the non-active area N / A.

[0095] The gate driving-related lines arranged in the non-active area N / A can be electrically connected to the source side circuit film SF disposed closest to the plurality of gate driving circuits GDC.

[0096] Figure 3 is a view illustrating a portion of a display apparatus according to an embodiment of the disclosure.

[0097] Referring to Figure 3 , the display apparatus DP can include a first substrate SUB1 and a second substrate facing the first substrate SUB1.

[0098] Here, the first substrate SUB1 can be a transistor (TR) array substrate, and the second substrate SUB2 can be a color filter substrate. However, embodiments of the disclosure are not limited thereto. For example, a color filter can be disposed on the first substrate SUB1.

[0099] A liquid crystal layer can be disposed between the first substrate SUB1 and the second substrate SUB2, but embodiments of the disclosure are not limited thereto.

[0100] Further, a sealant SEAL for bonding the first substrate SUB1 and the second substrate SUB2 can be disposed between the first substrate SUB1 and the second substrate SUB2. The sealant SEAL can be disposed along the respective peripheral areas of the first substrate SUB1 and the second substrate SUB2. The sealant SEAL can also be disposed to cover the respective peripheral areas of the first substrate SUB1 and the second substrate SUB2.

[0101] As shown in Figure 1 , a plurality of data lines DL, a plurality of gate lines GL, and a plurality of sub-pixels SP defined by the plurality of data lines DL and the plurality of gate lines GL in a matrix form can be arranged in the active area A / A of the first substrate SUB1.

[0102] As shown in Figure 1The conductive pads electrically connected with the data driver DDR can be disposed in the non-active area N / A of the first substrate SUB1, as illustrated. Further, the plurality of data link lines connected between the conductive pads and the plurality of data lines DL can be disposed in the non-active area N / A of the first substrate SUB1. Further, lines related to gate driving can be disposed in the non-active area N / A to transmit a voltage (a signal) required to drive a gate of at least one transistor included in at least one sub-pixel to the gate driver GDR through the conductive pads electrically connected with the data driver DDR.

[0103] The color filter for providing colors and the black matrix for preventing color mixing can be located in the second substrate SUB2, but embodiments of the present disclosure are not limited thereto.

[0104] As described above, the plurality of lines for transmitting signals (hereinafter, can be referred to as "signal lines") can be disposed in the non-active area N / A of the first substrate SUB1.

[0105] The plurality of signal lines can be disposed in a part or all of the non-active area N / A of the first substrate SUB1 provided with the sealant.

[0106] The first substrate SUB1 provided with the sealant SEAL can include a plurality of regions. Hereinafter, for convenience of description, the plurality of regions of the first substrate SUB1 provided with the sealant SEAL and including a first region, a second region, and a third region are discussed.

[0107] At least one of the first region, the second region, and the third region can be a region overlapping the sealant.

[0108] Here, the first region can be closer to the active area A / A of the display device DP than the second region, and the second region can be closer to the active area A / A than the third region. That is, the first region among the first region, the second region, and the third region can be closest to the active area A / A, and the third region can be farthest from the active area A / A.

[0109] Figure 4 is a cross-sectional view illustrating a first region corresponding to a part of an X region of Figure 2 is a cross-sectional view illustrating a first region corresponding to a part of an X region of Figure 5 is a cross-sectional view illustrating a first region corresponding to a part of an X region of Figure 4 is a cross-sectional view taken along line A-B of

[0110] The first region A1 of the non-active area N / A can be an inspection region. For example, the inspection region can be a region required to inspect defects of a plurality of types of signal lines disposed above the first substrate SUB1 and including a plurality of transistors and a plurality of signal lines.

[0111] Referring to Figure 4In the first area A1 of the non-active area N / A, a plurality of signal lines can be disposed above the first substrate SUB1.

[0112] Some of the plurality of signal lines SL disposed in the first area A1 can have a mesh shape including at least one opening OPN. For example, the signal line SL can include at least one opening OPN formed by intersecting or overlapping at least two signal line patterns extending in a first direction and at least two signal line patterns extending in a second direction, which intersects the first direction at an angle. Here, the at least two signal line patterns extending in the first direction can have different patterns in width, length, or thickness of the signal line patterns from the at least two signal line patterns extending in the second direction.

[0113] The plurality of connection patterns CP1 and CP2 can overlap the signal line SL having the mesh shape. Each of the plurality of connection patterns CP1 and CP2 can have a form of a line extending in one direction in the first area A1, but embodiments of the disclosure are not limited thereto.

[0114] The at least one active layer ACT can overlap the signal line SL having the mesh shape and the plurality of connection patterns CP1 and CP2. The first connection pattern CP1 and the second connection pattern CP2 disposed on the same active layer ACT can be disposed to be spaced apart from each other.

[0115] The plurality of connection patterns CP1 and CP2 and the active layer ACT can not overlap all or a part of the opening OPN of the signal line SL. That is, the plurality of connection patterns CP1 and CP2 and the active layer ACT overlapping the signal line SL having the at least one opening OPN can be disposed not to cover the at least one opening of the signal line SL.

[0116] Meanwhile, although Figure 4 The signal line SL having the at least one opening OPN can be connected to a signal line disposed in the active area A / A, which is not shown in FIG. 1. Also, each of the first connection pattern CP1 and the second connection pattern CP2 is connected to a plurality of data lines arranged in the active area A / A.

[0117] In the non-active area N / A, the signal line SL having the at least one opening OPN, the connection patterns CP1 and CP2, and the active layer ACT can overlap each other and function as a transistor.

[0118] Referring to Figure 5 , the signal line SL can be disposed on the substrate SUB.

[0119] The first insulating film INS1 can be disposed on the signal line SL. The active layer ACT can be disposed on the first insulating film INS1.

[0120] The active layer ACT can be disposed to overlap the signal line SL.

[0121] The first connection pattern CP1 and the second connection pattern CP2 can be disposed to be spaced apart from each other on the active layer ACT.

[0122] The second insulating film INS2 and the third insulating film INS3 can be disposed on the first connection pattern CP1 and the second connection pattern CP2. Here, the third insulating film INS3 can be used to planarize the substrate SUB on which the plurality of transistors TR are disposed, but embodiments of the present disclosure are not limited thereto.

[0123] The sealing agent SEAL can be disposed on the third insulating film INS3.

[0124] Meanwhile, the signal line SL, the active layer ACT, the first connection pattern CP1, and the second connection pattern CP2 can function as one transistor TR.

[0125] The transistor TR can be used to inspect defects of the plurality of signal lines arranged in the active area A / A.

[0126] The sealing agent SEAL can be disposed in the first area A1. Referring to Figure 6 This structure is further discussed.

[0127] Figure 6 is a cross-sectional view taken along Figure 4 the line C-D.

[0128] Referring to Figure 6 , two transistors TR can be disposed to be spaced apart from each other over the substrate SUB in the first area A1.

[0129] In other words, only the insulating films INS1, INS2, and INS3, not the signal line or the active layer ACT, can be arranged between one transistor TR and another transistor TR.

[0130] The third insulating film INS3 can be disposed over the substrate on which the transistor TR is disposed.

[0131] Meanwhile, the signal line SL arranged in the first area A1 can be arranged on the same layer as the plurality of gate lines arranged in the active area A / A, but embodiments of the present disclosure are not limited thereto.

[0132] The first connection pattern CP1 and the second connection pattern CP2 can be arranged on the same layer as the gate lines arranged in the active area A / A, but embodiments of the present disclosure are not limited thereto.

[0133] The sealing agent can be disposed on the third insulating film INS3.

[0134] The sealant SEAL can be an ultraviolet-cured resin cured by ultraviolet light UV, but embodiments of the present disclosure are not limited thereto.

[0135] To form the sealant SEAL, ultraviolet light can be irradiated from the back surface of the first substrate SUB1 to the region where the resin as the sealant is provided.

[0136] The ultraviolet light passing through the first substrate SUB1 reaches the material as the sealant SEAL through the first, second, and third insulating films INS1, INS2, and INS3, and the material as the sealant SEAL can be hardened or cured by the ultraviolet light.

[0137] As such, in the first region A1 where the sealant SEAL is provided, since the signal line SL has at least one opening OPN, and the active layer ACT and the connection patterns CP1 and CP2 provided on the signal line SL are provided not to overlap with all or a part of the opening OPN, the ultraviolet light for curing or hardening the material as the sealant SEAL can easily or sufficiently reach the sealant SEAL.

[0138] On the contrary, when the signal line SL, the active layer ACT, or the connection patterns CP1 and CP2 are provided in the region through which the ultraviolet light passes, there is a possibility that the ultraviolet light can not sufficiently reach the sealant SEAL; thus, a defect of the display device due to insufficient curing or hardening of the material as the sealant SEAL can occur. For example, due to the insufficient curing or hardening of the material as the sealant SEAL, the sealant SEAL can not maintain the gap between the first substrate SUB1 and the second substrate SUB2, or a defect can occur that enables the material as the sealant SEAL to flow.

[0139] However, according to embodiments of the present disclosure, to harden or cure the material as the sealant SEAL, the region through which the ultraviolet light passes is provided in the first region A1; thus, the material as the sealant SEAL can be sufficiently hardened or cured.

[0140] Further, since the ultraviolet light sufficiently reaches the material as the sealant SEAL, the hardening or curing time of the material as the sealant SEAL can be reduced.

[0141] Further, according to embodiments of the present disclosure, in the non-active region N / A, at least one signal line SL is provided to overlap with at least one connection pattern CP and at least one active layer ACT; thus, the size of the non-active region N / A can be reduced.

[0142] Next, the second region of the non-active region N / A is discussed.

[0143] Figure 7 is shown in relation toFigure 2 a cross-sectional view of a second region corresponding to a portion of the X region of Figure 8 is a cross-sectional view taken along line E-F of Figure 7 Figure 9 is a cross-sectional view taken along line F-G of Figure 7

[0144] The second region A2 of the non-active region N / A can be a region to which at least one signal line SL and at least one connection pattern CP are electrically connected to transmit a signal transmitted from the circuit film to the active region A / A.

[0145] For example, referring to Figure 7 , a signal (e.g., a common voltage, etc.) from the circuit film is applied to the plurality of signal line extension lines SCL1 and SCL2, and a signal supplied from the circuit film is transmitted to the plurality of signal lines SL integrated with each of the signal line extension lines SCL1 and SCL2.

[0146] At least one opening OPN formed by the plurality of signal lines SL crossing each other can be provided in the second region A2. Accordingly, the plurality of signal lines SL can be arranged to cross each other, thus having a mesh shape.

[0147] In a region in which the signal lines SL are arranged to have a mesh shape by crossing each other, at least one connection pattern CP can overlap the signal lines SL, and can be provided not to overlap all or a portion of the openings OPN.

[0148] Specifically, in the second region A2, the connection pattern CP can have a shape corresponding to the signal lines SL having a mesh shape. In other words, the connection pattern CP provided in the second region A2 can have a mesh shape having an opening at a position corresponding to the opening OPN defined by the signal lines SL.

[0149] Further, as Figure 7 indicated, in at least one region in which the signal lines SL and the connection pattern CP overlap each other, the signal lines and the connection pattern can be electrically connected to each other.

[0150] A signal transmitted to the signal lines SL can be transmitted to the connection pattern CP, and a signal transmitted to the connection pattern CP can be transmitted to the active region A / A.

[0151] The connection pattern CP can extend to the active region A / A, which is not specifically shown in Figure 7 for simplicity. The connection pattern CP extending to the active region A / A can be connected to a common line provided in the active region A / A.

[0152] ​​The connection pattern CP can be provided on the same layer as the source and drain of one of the plurality of thin film transistors provided in the active region A / A. The connection pattern CP can be electrically connected to the common line through a contact hole provided on at least one insulating film provided between the connection pattern CP and the common line.

[0153] Specifically, referring to Figure 8 , the signal line SL can be provided on the substrate SUB.

[0154] The first insulating film INS1 can be provided on the signal line SL.

[0155] The connection pattern CP can be provided on the first insulating film INS1.

[0156] The connection pattern CP can be electrically connected to the signal line SL through a plurality of holes HOL1 and HOL2 formed in the first insulating film INS1.

[0157] Although not specifically shown in Figure 8 , the signal line SL can be provided on the same layer as the gate line GL provided in the active region A / A, and the connection pattern CP can be provided on the same layer as the data line DL provided in the active region A / A; but embodiments of the present disclosure are not limited thereto.

[0158] The second insulating film INS2 and the third insulating film INS3 can be provided on the connection pattern CP.

[0159] The sealant SEAL can be provided on the third insulating film INS3.

[0160] As shown in Figure 9 , the material that is the sealant SEAL can be hardened or cured by ultraviolet light from the region in which the opening OPN of the signal line SL is located.

[0161] Specifically, in the second region A2, since only the insulating films INS1, INS2, and INS3 are provided above the substrate SUB in the region corresponding to the opening OPN of the signal line SL, the ultraviolet light can sufficiently reach the material that is the sealant SEAL.

[0162] Next, the third region of the non-active region N / A is discussed.

[0163] Figure 10 is a cross-sectional view showing the third region corresponding to a portion of the X region of Figure 2 . Figure 11 is a cross-sectional view taken along the line I-J of Figure 10 . Figure 12 is a cross-sectional view taken along the line K-L of Figure 10 .

[0164] The third area A3 of the non-active area N / A can include all or a part of at least one gate driver circuit GDC. The gate driver circuit GDC can include one or more transistors TR.

[0165] The plurality of signal lines SL disposed in the third area A3 can be electrically connected to the at least one gate driver circuit. For example, as shown in Figure 10 one gate driver circuit GDC can be electrically connected to at least three signal lines SL, but embodiments of the present disclosure are not limited thereto.

[0166] In detail, referring to Figure 10 , the plurality of connection pattern extension lines CPL1, CPL2, and CPL3 can be electrically connected to the gate driver circuit GDC. Each of the plurality of connection pattern extension lines CPL1 and CPL2 can be electrically connected to at least one transistor TR included in the gate driver circuit GDC.

[0167] Here, the first connection pattern extension line CPL1 can be connected to the connection pattern CP overlapping the first signal line SL1. In addition, the second connection pattern extension line CPL2 can be connected to the connection pattern CP overlapping the second signal line SL2.

[0168] Here, each of the signal lines SL1 and SL2 overlapping the connection pattern CP can include at least one opening OPN.

[0169] In addition, the third connection pattern extension line CPL3 can be electrically connected to the third signal line SL3. The third signal line SL3 can overlap at least one connection pattern disposed on the third signal line SL3.

[0170] Here, a timing signal can be applied to one of the first signal line SL1 and the second signal line SL2, and a voltage can be applied to the other of the first signal line SL1 and the second signal line SL2. However, embodiments of the present disclosure are not limited thereto.

[0171] The timing signal and the voltage applied to the first signal line SL1 and the second signal line SL2 can be supplied to the gate driver circuit GDC through the connection pattern CP and the first connection pattern extension line CPL1 and the second connection pattern extension line CPL2. In addition, a gate scan signal from the gate driver circuit GDC can be applied to the third connection pattern extension line CPL3; embodiments of the present disclosure are not limited thereto.

[0172] Meanwhile, the plurality of connection patterns CP disposed in the third area A3 can overlap the signal lines SL having at least one opening OPN, and the connection patterns CP can be disposed to be spaced apart from each other. The plurality of connection patterns CP can be disposed not to cover all or a part of the openings OPN of the signal lines SL.

[0173] In Figure 10 , the plurality of connection patterns CP are provided so as to be spaced apart from each other on the signal line SL; embodiments of the present disclosure are not limited thereto. For example, as Figure 7 indicated, the connection patterns CP can have a mesh shape, and can be provided so as not to overlap the openings OPN of the signal line SL.

[0174] That is, the plurality of connection patterns CP provided in the third region A3 can be provided so as not to cover the openings OPN of the signal line SL; thus, the sealant SEAL provided in the third region A3 can be easily or sufficiently hardened or cured.

[0175] Further, as Figure 11 indicated, in a region in which the plurality of connection patterns CP and the signal line SL overlap each other, each of the connection patterns CP can be electrically connected to the signal line SL.

[0176] Specifically, referring to Figure 11 , the signal line SL can be provided on the substrate SUB.

[0177] The first insulating film INS1 can be provided on the signal line SL.

[0178] The plurality of connection patterns CP can be provided on the first insulating film INS1. Each of the plurality of connection patterns CP can be electrically connected to the signal line SL through the plurality of holes HOL3 and HOL4 formed in the first insulating film INS1.

[0179] Although not specifically shown in Figure 11 for the sake of simplicity, the signal line SL can be provided on the same layer as the gate line GL provided in the active region A / A, and the connection pattern CP can be provided on the same layer as the data line DL provided in the active region A / A; embodiments of the present disclosure are not limited thereto.

[0180] The second insulating film INS2 and the third insulating film INS3 can be provided on the connection pattern CP.

[0181] The sealant SEAL can be provided on the third insulating film INS3.

[0182] As Figure 12 indicated, the material as the sealant SEAL can be hardened or cured by ultraviolet light from a region in which the opening OPN of the signal line SL is located.

[0183] Specifically, in the third region A3, since only the insulating films INS1, INS2, and INS3 are provided above the substrate SUB in a region corresponding to the opening OPN of the signal line SL, the ultraviolet light can sufficiently reach the material as the sealant SEAL.

[0184] Meanwhile, the sealant SEAL is disposed in a first area A1 in Figure 5 and Figure 6 , the sealant SEAL is disposed in a second area A2 in Figure 8 and Figure 9 , and the sealant SEAL is disposed in a third area A3 in Figure 11 and Figure 12 . However, embodiments of the disclosure are not limited thereto.

[0185] Specifically, in some embodiments, the sealant SEAL can be disposed in at least one of the first area A1, the second area A2, and the third area A3.

[0186] According to embodiments of the disclosure, it is possible to provide a display panel and a display device having a structure that enables a sealant disposed in a non-active area to be sufficiently hardened or cured.

[0187] According to embodiments of the disclosure, it is possible to provide a display panel and a display device having a structure that enables a sealant material disposed in a non-active area to be rapidly hardened or cured.

[0188] According to embodiments of the disclosure, it is possible to provide a display panel and a display device having a structure that enables the size of a non-active area to be reduced.

[0189] The features, structures, configurations, and effects described in the disclosure are included in at least one embodiment, but are not necessarily limited to a particular embodiment. A person skilled in the art can apply the features, structures, configurations, and effects shown in the specific embodiments to one or more other additional embodiments by combining or modifying the features, structures, configurations, and effects. It should be understood that all such combinations and modifications are included in the scope of the disclosure. Although the exemplary embodiments have been described, those skilled in the art will understand that various modifications and applications can be made without departing from the essential characteristics of the disclosure. For example, various modifications can be made to the specific components of the exemplary embodiments. The scope of protection of the disclosure should be interpreted based on the following claims, and all technical ideas within the equivalent scope thereof should be interpreted as being included in the scope of the disclosure.

Claims

1. A display device, comprising a panel, comprising: a substrate comprising an active area and an inactive area, wherein the inactive area surrounds the active area and comprises a first area, a second area, and a third area spaced apart from each other, and at least one gate driving circuit is disposed in the third area; at least one signal line, the at least one signal line being disposed in the third region on the substrate; a plurality of connection patterns, the plurality of connection patterns being arranged above the at least one signal line; a sealant disposed on the plurality of connection patterns; as well as at least one connection pattern extension line, wherein the at least one connection pattern extension line connects at least a portion of the plurality of connection patterns with the at least one gate driving circuit, wherein the at least one signal line and at least one connection pattern among the plurality of connection patterns overlap each other, and the at least one signal line includes a grid-shaped region having at least one opening, The at least one connection pattern among the plurality of connection patterns does not overlap with all or a portion of the at least one opening.

2. The display device according to claim 1, further comprising: a first insulating film provided between the plurality of connection patterns and the at least one signal line; Each of the plurality of connection patterns is electrically connected to the signal line through a plurality of holes formed in the first insulating film.

3. The display device according to claim 1, wherein The plurality of connection patterns have a grid shape.

4. The display device according to claim 1, wherein Each of the plurality of connection patterns is disposed at an intersection of a signal line disposed in a first direction and another signal line disposed in a second direction crossing the first direction.

5. The display device according to claim 1, wherein The plurality of connection patterns are provided in the grid-shaped region of the at least one opening of the at least one signal line. The display device according to claim 1 , wherein: The sealant overlaps the at least one opening of the at least one signal line.

7. The display device according to claim 1, wherein The first region is closer to the active region than the second region, and the second region is closer to the active region than the third region.

8. The display device according to claim 1, further comprising: a gate line, the gate line being arranged in the active area; as well as a data line, the data line being arranged in the active area, The at least one signal line and the gate line are arranged on the same layer, and the plurality of connection patterns and the data line are arranged on the same layer. 9 . The display device according to claim 2 , further comprising a second insulating film and a third insulating film disposed on the plurality of connection patterns under the sealant.

10. The display device according to claim 9, wherein In the third region, only the first insulating film, the second insulating film, and the third insulating film are provided over the substrate in a region corresponding to the at least one opening of the at least one signal line.

11. The display device according to claim 2, wherein: In the first area: The at least one signal line is provided on the substrate, The first insulating film is provided on the at least one signal line, An active layer is provided on the first insulating film, The plurality of connection patterns are arranged to be spaced apart from each other on the active layer, and The sealant is disposed on the plurality of connection patterns.

12. The display device according to claim 11, wherein The active layer is disposed to overlap with the at least one signal line.

13. The display device according to claim 11, wherein The at least one signal line has at least one opening, and the plurality of connection patterns do not overlap with the at least one opening.

14. The display device according to claim 2, wherein: In the second region, The at least one signal line is provided on the substrate, The first insulating film is provided on the at least one signal line, The connection pattern is provided on the first insulating film, the connection pattern being electrically connected to the signal line through a plurality of holes formed in the first insulating film, and The sealant is disposed on the plurality of connection patterns.

15. The display device according to claim 14, further comprising: a gate line, the gate line being arranged in the active area; as well as a data line, the data line being arranged in the active area, The at least one signal line and the gate line are arranged on the same layer, and the connection pattern and the data line are arranged on the same layer.

16. A display panel comprising: a first substrate, the first substrate including an active area and an inactive area, the inactive area surrounding the active area and including a first area, a second area, and a third area spaced apart from each other, at least one gate driving circuit being disposed in the third area; at least one signal line, the at least one signal line being disposed in the third region on the first substrate; a plurality of connection patterns, the plurality of connection patterns being arranged above the at least one signal line; a sealant disposed on the plurality of connection patterns; at least one connection pattern extension line, wherein the at least one connection pattern extension line connects at least a portion of the plurality of connection patterns and the at least one gate driving circuit; as well as a second substrate facing the first substrate and disposed on the sealant, wherein, in at least one of the first region, the second region, and the third region, the at least one signal line and the plurality of connection patterns overlap with each other, and the at least one signal line includes a grid-shaped region having at least one opening, wherein the plurality of connection patterns do not overlap with all or part of the at least one opening, At least one gate driving circuit is disposed in the third region, and at least a portion of the plurality of connection patterns are respectively connected to at least one connection pattern extension line. wherein the at least one connection pattern extension line is connected to at least one transistor of the gate drive circuit; Each of the plurality of connection patterns is arranged at an intersection of a signal line arranged along a first direction and another signal line arranged along a second direction intersecting the first direction.

17. The display panel according to claim 16, wherein: The plurality of connection patterns are separated from each other.

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