A method for improving the resistance of high-resistivity regions through via etching

Abstract

This invention provides a method for improving the resistance of high-resistivity regions through via etching. The semiconductor structure includes a metal layer, a first SiN layer, a TiN layer, a TiO layer, and a second SiN layer. A high-resistivity region is defined by photolithography. The TiO layer, the second SiN layer, and the TiN layer are etched according to the defined high-resistivity region to form a stacked structure. A PEOX layer is formed on the first SiN layer to cover the stacked structure. The PEOX layer and the first SiN layer below it are etched to form vias. Simultaneously with the etching to form the vias, the PEOX layer and the second SiN layer on the stacked structure are also etched to form grooves. The TiO layer at the bottom of the grooves is removed, exposing the upper surface of the TiN layer in the stacked structure. This invention, based on conventional processes, modifies the film structure by depositing a 50Å TiO layer on the TiN layer as a stop layer and sacrificial layer in the high-resistivity region during via etching. After the via etching is completed, the sacrificial layer is removed. By changing the film structure in the high-resistivity region, the resistance is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the resistance of high-resistivity regions through via etching. Background Technology

[0002] With the continuous development of integrated circuits, there are increasingly higher requirements for turn-on voltage. However, due to the limitations of integrated circuit structure and materials, there is little room for optimization on the gate. At this time, high-resistivity (TIN) technology has emerged and plays the role of voltage divider. However, the challenge it brings is that during via etching, due to the height difference between the high-resistivity region and other regions, the high-resistivity region is exposed to plasma for too long during via etching, which damages and roughens the TiN surface. In severe cases, it may even break down the high-resistivity region, resulting in abnormal resistance values ​​and affecting product performance. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the resistance of high-resistivity regions through through-hole etching, which solves the problem that through-hole etching causes damage to the TiN surface in high-resistivity regions, resulting in abnormally high resistance values ​​and affecting product performance.

[0004] To achieve the above and other related objectives, the present invention provides a method for improving the resistance of high-resistivity regions through through-hole etching, comprising at least:

[0005] Step 1: Provide a semiconductor structure, the semiconductor structure comprising: a metal layer, a first SiN layer located on the metal layer, a TiN layer located on the first SiN layer, a TiO layer located on the TiN layer, and a second SiN layer located on the TiO layer;

[0006] Step 2: Define a high-resistivity region on the semiconductor structure using photolithography.

[0007] Step 3: Etch the TiO layer, the second SiN layer, and the TiN layer according to the defined high-resistivity region, stopping the etching at the upper surface of the first SiN layer; forming a stacked structure;

[0008] Step 4: Form a PEOX layer on the first SiN layer to cover the stacked structure;

[0009] Step 5: Etch the PEOX layer and the first SiN layer below the PEOX layer to form a via; while etching to form the via, the PEOX layer on the stacked structure and the second SiN layer on the stacked structure are also etched until the TiO layer is exposed to form a groove;

[0010] Step 6: Remove the TiO layer at the bottom of the groove to expose the upper surface of the TiN layer in the stacked structure.

[0011] Preferably, the material of the metal layer in step one is Co.

[0012] Preferably, the thickness of the TiO layer in step one is

[0013] Preferably, the TiO layer in step one serves as a sacrificial layer and a stop layer for via etching.

[0014] Preferably, the method for defining the high-resistivity region on the semiconductor structure in step two is as follows: forming a bottom anti-reflective coating on the second SiN layer of the semiconductor structure; then spin-coating a photoresist layer on the bottom anti-reflective coating; followed by exposure and development, and the semiconductor region covered by the developed photoresist layer and the bottom anti-reflective coating is the high-resistivity region.

[0015] Preferably, in step six, the TiO layer at the bottom of the groove is removed by wet etching.

[0016] Preferably, in step six, NH4OH is used as a wet etching agent to remove the TiO layer at the bottom of the groove.

[0017] Preferably, the wet etching rate in step six is:

[0018] As described above, the method of improving the resistance of high-resistivity regions by via etching of the present invention has the following beneficial effects: Based on the traditional process, the present invention changes the film structure by depositing a 50 Å TiO layer on TiN as a stop layer and sacrificial layer in the high-resistivity region during via etching. After the via etching is completed, this sacrificial layer is removed by a wet process. By changing the film structure in the high-resistivity region, the resistance is improved. Attached Figure Description

[0019] Figures 1 to 4 The diagram shows the structural schematics of each stage of the method for improving the resistance of high-resistivity regions by through-hole etching according to the present invention.

[0020] Figure 5 The diagram shows a flowchart of the method for improving the resistance of high-resistivity regions by etching through-holes according to the present invention. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0022] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0023] This invention provides a method for improving the resistance of high-resistivity regions through through-hole etching, such as... Figure 5 As shown, Figure 5 The flowchart shown is a method for improving the resistance of high-resistivity regions by etching vias according to the present invention, the method comprising at least:

[0024] Step 1: Provide a semiconductor structure, the semiconductor structure comprising: a metal layer, a first SiN layer located on the metal layer, a TiN layer located on the first SiN layer, a TiO layer located on the TiN layer, and a second SiN layer located on the TiO layer;

[0025] Furthermore, in this embodiment, the material of the metal layer in step one is Co.

[0026] Furthermore, in this embodiment, the thickness of the TiO layer in step one is... In a further embodiment of the present invention, the TiO layer in step one serves as a sacrificial layer and a stop layer for via etching.

[0027] like Figure 1 As shown, step one provides a semiconductor structure, which includes: a metal layer, a first SiN layer on the metal layer, a TiN layer on the first SiN layer, a TiO layer on the TiN layer, and a second SiN layer on the TiO layer. Figure 1 It can be seen that the material of the metal layer in step one of this embodiment is Co.

[0028] Step 2: Define a high-resistivity region on the semiconductor structure using photolithography.

[0029] In a further step of this invention, the method for defining the high-resistivity region on the semiconductor structure in step two of this embodiment is as follows: forming a bottom anti-reflective coating on the second SiN layer of the semiconductor structure; then spin-coating a photoresist layer on the bottom anti-reflective coating; followed by exposure and development, and the semiconductor region covered by the developed photoresist layer and the bottom anti-reflective coating is the high-resistivity region.

[0030] like Figure 1 As shown, step two defines a high-resistivity region on the semiconductor structure using photolithography. The method for defining the high-resistivity region on the semiconductor structure is as follows: a bottom anti-reflective coating is formed on the second SiN layer of the semiconductor structure; then a photoresist layer is spin-coated on the bottom anti-reflective coating; followed by exposure and development. The semiconductor region covered by the developed photoresist layer (PR) and the bottom anti-reflective coating (Barc) constitutes the high-resistivity region.

[0031] Step 3: Etch the TiO layer, the second SiN layer, and the TiN layer according to the defined high-resistivity region, stopping the etching at the upper surface of the first SiN layer; forming a stacked structure; as shown. Figure 2 As shown, in step three, the TiO layer, the second SiN layer, and the TiN layer are etched according to the defined high-resistivity region, and the etching stops at the upper surface of the first SiN layer; thus forming a stacked structure (HR).

[0032] Step 4: Form a PEOX layer on the first SiN layer to cover the stacked structure;

[0033] Step 5: Etch the PEOX layer and the first SiN layer below the PEOX layer to form a via; simultaneously with etching to form the via, the PEOX layer on the stacked structure and the second SiN layer on the stacked structure are also etched until the TiO layer is exposed, forming a groove; as shown Figure 3 As shown, in step five, the PEOX layer and the first SiN layer below the PEOX layer are etched to form a via. While the via is being etched to form the via, the PEOX layer on the stacked structure and the second SiN layer on the stacked structure are also etched until the TiO layer is exposed, forming a groove.

[0034] Step 6: Remove the TiO layer at the bottom of the groove to expose the upper surface of the TiN layer in the stacked structure.

[0035] In a further step of this invention, in step six of this embodiment, the TiO layer at the bottom of the groove is removed by wet etching.

[0036] In a further step of this invention, NH4OH is used as a wet etching agent in step six of this embodiment to remove the TiO layer at the bottom of the groove.

[0037] like Figure 4 As shown, step six removes the TiO layer at the bottom of the groove, exposing the upper surface of the TiN layer in the stacked structure, forming a layer as shown in the figure. Figure 4 The structure shown.

[0038] Furthermore, in this embodiment, the wet etching rate in step six is...

[0039] In summary, this invention, based on traditional processes, modifies the film structure by depositing a 50 Å TiO layer on TiN as a stop layer and sacrificial layer in the high-resistivity region during via etching. After via etching, this sacrificial layer is removed using a wet process. By altering the film structure in the high-resistivity region, the resistance is improved. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0040] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the resistance of high-resistivity regions through through-hole etching, characterized in that, At least including: Step 1: Provide a semiconductor structure, the semiconductor structure comprising: a metal layer, a first SiN layer located on the metal layer, a TiN layer located on the first SiN layer, a TiO layer located on the TiN layer, and a second SiN layer located on the TiO layer; Step 2: Define a high-resistivity region on the semiconductor structure using photolithography. Step 3: Etch the TiO layer, the second SiN layer, and the TiN layer according to the defined high-resistivity region, stopping the etching at the upper surface of the first SiN layer; forming a stacked structure; Step 4: Form a PEOX layer on the first SiN layer to cover the stacked structure; Step 5: Etch the PEOX layer and the first SiN layer below the PEOX layer to form a via; while etching to form the via, the PEOX layer on the stacked structure and the second SiN layer on the stacked structure are also etched until the TiO layer is exposed to form a groove; Step 6: Remove the TiO layer at the bottom of the groove to expose the upper surface of the TiN layer in the stacked structure.

2. The method for improving the resistance of high-resistivity regions by etching through-holes according to claim 1, characterized in that: The material of the metal layer in step one is Co.

3. The method for improving the resistance of high-resistivity regions by etching through-holes according to claim 1, characterized in that: The thickness of the TiO layer in step one is 50 Å.

4. The method for improving the resistance of high-resistivity regions by etching through-holes according to claim 1, characterized in that: The TiO layer mentioned in step one serves as a sacrificial layer and a stop layer for via etching.

5. The method for improving the resistance of high-resistivity regions by etching through-holes according to claim 1, characterized in that: The method for defining the high-resistivity region on the semiconductor structure in step two is as follows: forming a bottom anti-reflection coating on the second SiN layer of the semiconductor structure; A photoresist layer is then spin-coated onto the bottom anti-reflective coating; followed by exposure and development. The semiconductor region covered by the developed photoresist layer and the bottom anti-reflective coating is the high-resistivity region.

6. The method for improving the resistance of high-resistivity regions by etching through-holes according to claim 1, characterized in that: In step six, the TiO layer at the bottom of the groove is removed by wet etching.

7. The method for improving the resistance of high-resistivity regions by etching through-holes according to claim 6, characterized in that: In step six, NH4OH is used as a wet etching agent to remove the TiO layer at the bottom of the groove.

8. The method for improving the resistance of high-resistivity regions by etching through-holes according to claim 7, characterized in that: The wet etching rate in step six is ​​0.05 Å / Min.

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