A high spurious-free dynamic range segmented r-2r ladders network

Abstract

The application claims a segmented R-2R inverting ladder resistor network with high spurious-free dynamic range, which improves the spurious-free dynamic range (SFDR) of the circuit by segmenting the R-2R inverting ladder resistor network and performing non-overlapping rotation selection processing on the high-bit segment resistor network. The circuit mainly comprises: a thermometer decoder for converting a high-4-bit binary code into a 15-level thermometer code; an accumulator for accumulating the high-4-bit binary code to generate a shift control signal (also called a pointer) required by a logarithmic shifter; a logarithmic shifter for performing a shift operation according to the shift control signal input by the accumulator and the thermometer code input; a level holding circuit for compensating for the level lost during the shift operation of the logarithmic shifter; a latch for time-domain alignment of the signals of the low-12-bit and high-4-bit; and a segmented R-2R inverting ladder resistor network for receiving the digital signal of the latch and then decoding the digital signal.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design technology, and specifically relates to a segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range. Background Technology

[0002] Data converters are crucial modules in modern signal processing systems, and also represent a bottleneck limiting the overall system's signal processing capabilities. The performance metrics of a data converter determine the quality of a product, and high-performance products are naturally favored by consumers. In digital-to-analog converters (DACs), spurious-free dynamic range (SFDR) refers to the ratio of the RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the second-maximum distortion component. As a vital dynamic performance parameter of the data converter, it is extremely important in communication systems. For example, in small-signal analog-to-digital conversion, if the spurious signals generated by a large-signal channel are close to the frequency of the signal channel, the information within the small-signal channel can be blocked.

[0003] For Nyquist-based digital-to-analog converters (DACs), there are three design directions: voltage-mode, charge-mode, and current-mode. For oversampling DACs, there is the Sigma Delta DAC. However, for high-precision DACs, design choices are severely constrained: voltage-mode and charge-mode converters are unsuitable for high-precision applications due to their structure, so only current-mode and Sigma Delta DACs are viable options. The advantage of Sigma Delta DACs is their ability to achieve high or even ultra-high precision, but they involve complex digital and analog circuits, making them less cost-effective. In current-mode DACs, the R-2R inverted trapezoidal resistor network is a good solution, as its circuitry is largely composed of R and 2R resistors, offering high matching accuracy and a small area. Although the R-2R inverted trapezoidal resistor network can be used for high-precision data converters, the actual resistor matching accuracy is generally limited to a maximum of 12 bits, which is insufficient for the 16-bit high-precision requirements. Therefore, the designers proposed a segmented R-2R inverted trapezoidal resistor network, which is generally divided into two or three segments. For example, a 12-bit R-2R inverted trapezoidal resistor network is designed as a (4+8) segmented network, which means that the high 4 bits are decoded into 15-level thermometer code, and the low 8 bits are kept as binary code. Then, the precision requirement of the low segment only needs to be 8 bits, and the precision requirement of the high segment needs to be 12 bits, which meets the precision requirement of the 12-bit data converter, and it is not necessary for all segments to be 12 bits of precision.

[0004] However, for 16-bit data converters, if designed in a segmented manner, a portion of the resistors will inevitably need to achieve 16-bit precision. This means that the units composed of analog components cannot be perfectly matched, and this mismatch affects the overall performance of the converter, including its SFDR, in the form of nonlinear errors. Therefore, to ensure high SFDR performance, designers generally choose to compensate for this mismatch in the switching process.

[0005] In a segmented R-2R inverted trapezoidal resistor network, the thermometer encoding used in the high-order switching of the circuit leads to some cells being selected at frequencies far exceeding those of others. This mismatch manifests as harmonics in the power spectral density graph, significantly reducing the system's free-current characteristic (SFDR). To mitigate this, an algorithm is added to the high-order switching: an accumulator accumulates the binary code of the high-order segment and uses the result as a pointer signal to control a logarithmic shifter to shift the thermometer code. The output code of the logarithmic shifter ensures that the selected frequency of each high-order switch is the same, greatly suppressing harmonic generation and improving the system's SFDR. Summary of the Invention

[0006] This invention aims to solve the problems of the prior art. It proposes a segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range. The technical solution of this invention is as follows:

[0007] A segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range includes: a thermometer decoder, an accumulator, a logarithmic shifter, a level holding circuit, a latch, and a segmented R-2R inverted trapezoidal resistor network.

[0008] Thermometer decoder, used to convert the high 4 bits of binary code into 15-level thermometer code;

[0009] The accumulator is used to accumulate the high 4 bits of binary code to generate the shift control signal required by the logarithmic shifter.

[0010] A logarithmic shifter is used to perform shift operations based on the shift control signal input from the accumulator and the input 15-level thermometer code.

[0011] A level holding circuit is used to compensate for the level loss during the shift operation of a logarithmic shifter;

[0012] A latch is used to time-domain align the lower 12 bits and the higher 4 bits of a signal.

[0013] A segmented R-2R inverted trapezoidal resistor network is used to receive digital signals from the latch and then decode them.

[0014] 2. Furthermore, the thermometer decoder is used to convert the high 4 bits of binary code into 15-level thermometer code, specifically including basic gate-level circuits such as NAND gates, NOR gates, and NOT gates. For example, the high 4 bits of binary code are D. in3 D in2 D in1 D in0 If it's 0001, then the transcoded thermometer code is temp. 15 temp 14 ...temp1 is 000000000000001, It consists of two NOR gates and one NAND gate; for example, the high 4 bits of the binary code are D. in3 D in2 D in1 D in0 If it's 0110, then the transcoded thermometer code is temp. 15 temp 14 ...temp1 is 000000000111111, It consists of two NAND gates and one NOT gate.

[0015] Furthermore, the accumulator consists of four full adders and eight D flip-flops. The carry output of full adder 1 is connected to the carry input of full adder 2; the carry output of full adder 2 is connected to the carry input of full adder 3; the carry output of full adder 3 is connected to the carry input of full adder 4; and the carry output of full adder 4 is connected to the carry input of full adder 1, thus completing the end-to-end carry algorithm. The outputs S1 to S4 of each full adder serve as inputs to D flip-flops 1 to 4. The eight D flip-flops are controlled by two inverted clocks. D flip-flops 1 to 4 are latched, and D flip-flops 5 to 8 are read. After one latching operation, the results p[3:0] of D flip-flops 5 to 8 are returned to the inputs B1 to B4 of the full adders and used as control signals for the logarithmic shifter to control the thermometer code for shifting.

[0016] Furthermore, a logarithmic shifter is used to perform shift operations based on the shift control signal p[3:0] input from the accumulator and the input 15-level thermometer code temp[1~15]. Specifically, it includes 60 (15×4) MUXs, supporting fixed-width cyclic shift operations. Each MUX includes two NMOS switches, one of which receives the shift control signal and the other receives the inverted signal of the shift control signal.

[0017] Furthermore, the level holding circuit has 15 branches, each branch consisting of two inverters and one PMOS transistor. The source of the PMOS transistor is connected to the power supply VDD, the gate is connected to the output of inverter n_1 and the input of inverter n_2 in that branch, and the drain is connected to the input of inverter n_1. Together with the logarithmic shifter, it completes the shift operation and ensures the correct result.

[0018] Furthermore, the latch is used to time-domain align the lower 12 bits and the higher 4 bits of the signal. Specifically, it includes 12 D flip-flops that receive the lower 12 bits of the signal and 15 D flip-flops that receive the higher 4 bits of the signal and transcode them into 15 levels of thermometer code. The lower 12 bits of the signal always arrive at the D flip-flops first. The higher 4 bits of the signal will have a certain delay due to transcoding and the algorithm. Both are output to the segmented R-2R inverted trapezoidal resistor network when the next rising edge of the clock arrives.

[0019] Furthermore, the segmented R-2R inverted trapezoidal resistor network is divided into (4+12) segments; the 4-bit binary code of the high segment is converted into a 15-level thermometer code, and the 12-bit binary code of the low segment is not converted; each branch of the high segment consists of two large resistors R, one small resistor r, and a single-pole double-throw switch, and the single-pole double-throw switch receives the control signal d[1~15] of the high 4 bits; except for one branch of the low segment which consists of two large resistors R and two small resistors r, the other 12 branches are all composed of three large resistors R, two small resistors r, and a single-pole double-throw switch, and the single-pole double-throw switch receives the control signal b[11:0] of the low 12 bits.

[0020] The advantages and beneficial effects of this invention are as follows:

[0021] This invention provides a segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range. It involves segmenting a traditional R-2R inverted trapezoidal resistor network and then adding small resistors *r* between the R values ​​to offset the influence of the CMOS switch's on-resistance on the network. Due to the inherent mismatch in analog devices, the segmented R-2R inverted trapezoidal resistor network still exhibits a high second harmonic component. Therefore, this invention incorporates simple digital circuitry to design the switch switching as a non-overlapping rotational selection scheme, ensuring that each CMOS switch has an equal probability of being selected. This avoids individual branches being selected far more frequently than others, thereby suppressing harmonics caused by input codes and achieving high spurious-free dynamic range. Attached Figure Description

[0022] Figure 1 This is a block diagram of a conventional R-2R inverted trapezoidal resistor network provided by a preferred embodiment of the present invention.

[0023] Figure 2 This is a block diagram of an R-2R inverted trapezoidal resistor network according to an embodiment of the present invention.

[0024] Figure 3 This is a top-level circuit block diagram for achieving low cost and high spurious-free dynamic range according to an embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of the full adder portion of an accumulator according to an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of a D flip-flop array used in an accumulator according to an embodiment of the present invention.

[0027] Figure 6 This is a schematic diagram of a logarithmic shifter structure according to an embodiment of the present invention.

[0028] Figure 7 This is a schematic diagram of a level-holding circuit according to an embodiment of the present invention.

[0029] Figure 8 This is a schematic diagram of a switching scheme that uses thermometer codes to control branch circuit switches.

[0030] Figure 9 This is a schematic diagram of a switch switching scheme with non-overlapping rotation selection according to an embodiment of the present invention.

[0031] Figure 10 This is the power spectral density diagram of the output signal of a traditional R-2R inverted trapezoidal resistor network under resistor mismatch conditions.

[0032] Figure 11 This is the power spectral density diagram of the output signal of the R-2R inverted trapezoidal resistor network that achieves low cost and high spurious-free dynamic range according to an embodiment of the present invention under resistor mismatch conditions. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0034] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0035] like Figure 1 The diagram shows a traditional R-2R inverted trapezoidal resistor network, except for the branch at the highest position ( Figure 1 The leftmost branch consists of two R's and a single-pole double-throw switch, as well as the lowest-order branch ( Figure 1 Except for the rightmost branch, which consists of two resistors and a gate connected to the power supply VDD, all other branches consist of three resistors and a single-pole double-throw switch. When the input code is applied to b1~b 16When the circuit is closed, an R-2R inverted trapezoidal resistor network is used for digital-to-analog conversion. This structure is easy to implement, but it has obvious drawbacks: on the one hand, it is limited by the matching accuracy of the resistor R itself; on the other hand, because the single-pole double-throw switch is composed of two CMOS switches, the on-resistance of the CMOS switches themselves will affect the simple double resistance relationship between R and 2R in the R-2R inverted trapezoidal resistor network.

[0036] like Figure 2 As shown, this invention presents a segmented R-2R inverted trapezoidal resistor network. The traditional R-2R inverted trapezoidal resistor network is segmented into (4+12) segments. The 4-bit binary code of the high-order segment is converted into a 15-level thermometer code, while the 12-bit binary code of the low-order segment is not converted. Each branch of the high-order segment includes two large resistors R, one small resistor r, and a single-pole double-throw (SPDT) switch. The SPDT switch receives the control signal d [1-15] of the high 4 bits. In the low-order segment, except for one branch composed of two large resistors R and two small resistors r, the remaining 12 branches each include three large resistors R, two small resistors r, and a SPDT switch. The SPDT switch receives the control signal b [11:0] of the low 12 bits. It is particularly important to note that the value of r should be consistent with the on-resistance of the CMOS switch, thus transforming R and 2R in the R-2R inverted trapezoidal resistor network into (R+r) and 2(R+r), still satisfying the simple double resistance relationship.

[0037] like Figure 3 The diagram shows the top-level circuit block diagram designed in this invention. The 16-bit binary code Din[15:0] is divided into two parts: one part directly enters the latch to wait for the latch to receive the instruction and then outputs it; the other part serves as the input of the thermometer decoder. The 4-bit binary code is converted into a 15-level thermometer code and also serves as the input of the accumulator. The accumulator performs an accumulation operation on each input and uses the result as a pointer p[3:0] to control the shift of the 15-level thermometer code in the logarithmic shifter. Since the on-resistance and open-circuit resistance of the CMOS switches in the traditional logarithmic shifter will cause the output high level of the logarithmic shifter to not reach the power supply voltage value, the output of the logarithmic shifter is connected to a level holding circuit to ensure that the output high level reaches the power supply voltage value. The output of the level holding circuit is connected to the latch and output together with the code to be output, as the control signal of the segmented R-2R inverted trapezoidal resistor network.

[0038] like Figure 4 and Figure 5As shown, the main components of the accumulator designed in this invention include four full adders and eight D flip-flops. The carry output of full adder 1 is connected to the carry input of full adder 2; the carry output of full adder 2 is connected to the carry input of full adder 3; the carry output of full adder 3 is connected to the carry input of full adder 4; and the carry output of full adder 4 is connected to the carry input of full adder 1 to complete the end-to-end carry algorithm. The outputs S1 to S4 of each full adder serve as inputs to D flip-flops 1 to 4. The eight D flip-flops are controlled by two inverted clocks. D flip-flops 1 to 4 are latched, and D flip-flops 5 to 8 are read. After one latching operation, the results p[3:0] of D flip-flops 5 to 8 are returned to the inputs B1 to B4 of the full adders and used as control signals for the logarithmic shifter to control the thermometer code for shifting.

[0039] like Figure 6 As shown, this is the logarithmic shifter designed in this invention, used to perform shift operations based on the shift control signal p[3:0] input from the accumulator and the input 15-level thermometer code temp[1~15]. Specifically, it includes 60 (15×4) MUXs, supporting fixed-width cyclic shift operations. Each MUX includes two NMOS switches, one of which receives the shift control signal and the other receives the inverted signal of the shift control signal.

[0040] like Figure 7 As shown, the level-holding circuit designed in this invention includes 15 branches. Each branch consists of two inverters and one PMOS transistor. The source of the PMOS transistor is connected to the power supply VDD, the gate is connected to the output of inverter n_1 and the input of inverter n_2 in that branch, and the drain is connected to the input of inverter n_1. Together with the logarithmic shifter, it completes the shift operation and ensures the correct result.

[0041] like Figure 8 The diagram shows a schematic of switching a branch switch using a thermometer code. As can be seen, despite different inputs, the selection of a branch always starts with branch 1. This results in branch 1 being selected more frequently than other branches. Consequently, the mismatch error present in branch 1 will cause harmonic components. The analysis of other branches is similar.

[0042] like Figure 9 The diagram shown is a schematic representation of a switch switching scheme with non-overlapping rotation selection according to an embodiment of the present invention. Figure 8With the same input, the difference is that when the next input arrives, the selection of the branch no longer starts from branch 1, but from the next branch after the previously selected branch. This switching scheme makes each branch selected at the same frequency, thereby greatly suppressing the harmonic components caused by the first few branches with higher selected frequencies.

[0043] Simulation results are as follows Figure 10 and Figure 11 As shown, Figure 9 This is the power spectral density diagram of the output signal of a traditional R-2R inverted trapezoidal resistor network under resistor mismatch conditions. The second harmonic component of the signal severely reduces the SFDR of the system. Figure 11 This is the power spectral density diagram of the output signal of the R-2R inverted trapezoidal resistor network with low cost and high spurious-free dynamic range according to an embodiment of the present invention under resistor mismatch conditions. The second and third harmonics of the signal are suppressed, and the SFDR is increased by 11dB.

[0044] In summary, the present invention has the following technical features: (1) It proposes a segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range, which is segmented into (4+12) segments in the traditional R-2R inverted trapezoidal resistor network; (2) It does not have complex algorithm logic, and can implement the non-overlapping rotation selection algorithm with basic circuits such as full adders, D flip-flops and various gate circuits, thereby compensating for the mismatch of analog components and achieving the purpose of high spurious-free dynamic range; (3) The resistor network structure and algorithm circuit used in the present invention are scalable and are not limited to the number of bits in the present invention.

[0045] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0046] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0047] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range, characterized in that, include: The thermometer decoder, accumulator, logarithmic shifter, level holding circuit, latch, and segmented R-2R inverted trapezoidal resistor network, among which, Thermometer decoder, used to convert the high 4 bits of binary code into 15-level thermometer code; The accumulator is used to accumulate the high 4 bits of binary code to generate the shift control signal required by the logarithmic shifter. A logarithmic shifter is used to perform shift operations based on the shift control signal input from the accumulator and the input 15-level thermometer code. A level holding circuit is used to compensate for the level loss during the shift operation of a logarithmic shifter; A latch is used to time-domain align the lower 12 bits and the higher 4 bits of a signal. The segmented R-2R inverted trapezoidal resistor network is divided into 4+12 segments. The 4-bit binary code of the high segment is converted into a 15-level thermometer code, while the 12-bit binary code of the low segment is not converted. Each branch of the high segment consists of two large resistors R, one small resistor r, and a single-pole double-throw switch. The single-pole double-throw switch receives the control signal d[1~15] of the high 4 bits. Except for one branch of the low segment which consists of two large resistors R and two small resistors r, the other 12 branches consist of three large resistors R, two small resistors r, and a single-pole double-throw switch. The single-pole double-throw switch receives the control signal b[11:0] of the low 12 bits.

2. The segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range according to claim 1, characterized in that, The thermometer decoder is used to convert the high 4 bits of binary code into a 15-level thermometer code. Specifically, it includes basic gate-level circuits such as NAND gates, NOR gates, and NOT gates. The high 4 bits of binary code are D. in3 D in2 D in1 D in0 If it's 0001, then the transcoded thermometer code is temp. 15 temp 14 ...temp1 is 000000000000001, temp1= It consists of two NOR gates and one NAND gate; the high 4 bits are represented by the binary code D. in3 D in2 D in1 D in0 If it's 0110, then the transcoded thermometer code is temp. 15 temp 14 ...temp1 is 000000000111111, temp1= It consists of two NAND gates and one NOT gate.

3. The segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range according to claim 1, characterized in that, The accumulator consists of four full adders and eight D flip-flops. The carry output of full adder 1 is connected to the carry input of full adder 2; the carry output of full adder 2 is connected to the carry input of full adder 3; the carry output of full adder 3 is connected to the carry input of full adder 4; and the carry output of full adder 4 is connected to the carry input of full adder 1, thus completing the end-to-end carry algorithm. The outputs S1 to S4 of each full adder serve as inputs to D flip-flops 1 to 4. The eight D flip-flops are controlled by two inverted clocks. D flip-flops 1 to 4 are latched, and D flip-flops 5 to 8 are read. After one latching operation, the results p[3:0] of D flip-flops 5 to 8 are returned to the inputs B1 to B4 of the full adders and used as control signals for a logarithmic shifter to control the thermometer code for shifting.

4. A segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range according to claim 1, characterized in that, A logarithmic shifter is used to perform shift operations based on the shift control signal p[3:0] input from the accumulator and the input 15-level thermometer code temp[1~15]. Specifically, it includes 15×4 MUXs and supports fixed-width cyclic shift operations. Each MUX includes two NMOS switches, one of which receives the shift control signal and the other receives the inverted signal of the shift control signal.

5. A segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range according to claim 1, characterized in that, The level holding circuit has 15 branches, each consisting of two inverters and one PMOS transistor. The source of the PMOS transistor is connected to the power supply VDD, the gate is connected to the output of inverter n_1 and the input of inverter n_2 in that branch, and the drain is connected to the input of inverter n_1. Together with the logarithmic shifter, it completes the shift operation and ensures the correct result.

6. A segmented R-2R inverted trapezoidal resistor network with high spurious-free dynamic range according to claim 1, characterized in that, The latch is used to time-domain align the lower 12 bits and the higher 4 bits of the signal. Specifically, it includes 12 D flip-flops that receive the lower 12 bits of the signal and 15 D flip-flops that receive the higher 4 bits of the signal and transcode them into 15 levels of thermometer code. The lower 12 bits of the signal will always arrive at the D flip-flops first. The higher 4 bits of the signal will have a certain delay due to transcoding and algorithm. Both will be output to the segmented R-2R inverted trapezoidal resistor network when the next rising edge of the clock arrives.

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