Chip testing method and apparatus
By adjusting the data input time point of the test equipment to match the data receiving window of each chip, the problem of data receiving errors caused by performance differences in chip testing was solved, and the accuracy and consistency of test results were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-12-06
- Publication Date
- 2026-07-03
AI Technical Summary
During chip testing, due to differences in the performance of the data receivers of each chip under test, some chips cannot accurately receive the data input from the testing equipment, resulting in incorrect test results.
By determining the data receiving window for each chip under test and adjusting the data input time of the test equipment to each chip according to its performance differences, each chip can receive data within its corresponding data receiving window.
This improves the accuracy and consistency of chip test results, avoiding data reception failures caused by performance differences.
Smart Images
Figure CN116224013B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing technology, and in particular to a chip testing method and equipment. Background Technology
[0002] In the manufacturing process of electronic components, various testing steps exist according to the needs of the process. The purpose is to screen out defective products, prevent them from entering the next process, and reduce redundant manufacturing costs in the next process.
[0003] Currently, chips typically use a shared set of timing information during testing, meaning that the data input time for each chip under test is consistent, and the input data provided by the test equipment arrives at the chip under test at the same time.
[0004] However, since each chip under test is independent of the others, the data receivers of each chip under test may have inconsistent data reception windows due to performance differences. Therefore, if multiple chips under test use the same timing information to receive data, some chips under test may not be able to accurately receive the data input by the test equipment, resulting in data writing abnormalities and thus incorrect test results. Summary of the Invention
[0005] This application provides a chip testing method and device, which can solve the technical problem that when multiple chips under test use the same timing information to receive data, some chips under test may not be able to accurately receive data due to performance differences.
[0006] In some embodiments, a chip testing method is provided, the method comprising:
[0007] Determine the data receiving window corresponding to each chip under test;
[0008] Based on the data receiving window corresponding to each chip under test and the data input window preset by the test machine, the time adjustment parameter corresponding to each chip under test is determined;
[0009] Based on the time adjustment parameters corresponding to each chip under test, the actual input time point corresponding to each chip under test is determined;
[0010] Data is input to the corresponding chip under test at the actual input time point for each chip under test, so that each chip under test receives the data input by the test machine in the corresponding data receiving window.
[0011] In one feasible implementation, determining the data receiving window corresponding to each chip under test includes:
[0012] Each chip under test is tested using a preset test method, and the data receiving window corresponding to each chip under test is determined based on the test results.
[0013] In one feasible implementation, determining the time adjustment parameter corresponding to each chip under test based on the data receiving window corresponding to each chip under test and the data input window preset by the testing machine includes:
[0014] Determine the time intervals on the time axis for the data input window and the data receiving window corresponding to each chip under test;
[0015] Based on the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis, the time adjustment parameter corresponding to each chip under test is determined.
[0016] In one feasible implementation, determining the time adjustment parameter corresponding to each chip under test based on the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis includes:
[0017] When there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is greater than or equal to a preset duration threshold, the time adjustment parameter corresponding to the i-th chip under test is determined to be 0.
[0018] When there is an intersection between the first time interval and the second time interval, and the duration of the intersection is less than the preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined according to the preset duration threshold.
[0019] In one feasible implementation, determining the time adjustment parameter corresponding to the i-th chip under test based on the preset duration threshold includes:
[0020] When there is an intersection between the first time interval and the second time interval, and the duration of the intersection t is less than the preset duration threshold P, the time adjustment parameter corresponding to the i-th chip under test is determined to be T1; where,
[0021] Pt < T1 < (t1 + t2 - Pt)
[0022] When there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined to be T2; where...
[0023] P + t3 < T2 < (t1 + t2 + t3 - P)
[0024] Where t1 is the duration of the first time interval, t2 is the duration of the second time interval, and t3 is the interval between the first time interval and the second time interval.
[0025] In one feasible implementation, determining the time adjustment parameter corresponding to each chip under test based on the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis includes:
[0026] When there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is less than a preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the center values of the data input window and the data receiving window corresponding to the i-th chip under test on the time axis are determined respectively.
[0027] The time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to the i-th chip under test on the time axis is determined as the time adjustment parameter corresponding to the i-th chip under test.
[0028] In one feasible implementation, determining the time adjustment parameter corresponding to each chip under test based on the data receiving window corresponding to each chip under test and the data input window preset by the testing machine includes:
[0029] Determine the center value of the data input window and the data receiving window corresponding to each chip under test on the time axis;
[0030] The time adjustment parameter for each chip under test is determined based on the time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to each chip under test on the time axis.
[0031] In one feasible implementation, determining the time adjustment parameter corresponding to each chip under test based on the time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to each chip under test on the time axis includes:
[0032] The time adjustment parameter T corresponding to the i-th chip under test is determined using the following method. delay (i):
[0033] T delay (i)=T i -T0
[0034] Among them, T i T0 represents the center value of the data receiving window corresponding to the i-th chip under test on the time axis; T0 represents the center value of the data input window on the time axis.
[0035] In one feasible implementation, after determining the actual input time point corresponding to each chip under test, the method further includes:
[0036] Adjust the data transmission time point of the test pin connected to the test machine and the i-th chip under test so that the adjusted data transmission time point is consistent with the actual input time point corresponding to the i-th chip under test.
[0037] In one feasible implementation, after determining the actual input time point corresponding to each chip under test, the method further includes:
[0038] When the preset data input window of the test instrument is detected, or when the data receiving method of each chip under test changes, the process returns to the step of determining the data receiving window corresponding to each chip under test.
[0039] In some embodiments, a chip testing apparatus is provided, the apparatus comprising:
[0040] The first processing module is used to determine the data receiving window corresponding to each chip under test;
[0041] The second processing module is used to determine the time adjustment parameters corresponding to each chip under test based on the data receiving window corresponding to each chip under test and the data input window preset by the test machine.
[0042] The third processing module is used to determine the actual input time point corresponding to each chip under test based on the time adjustment parameters corresponding to each chip under test.
[0043] The data transmission module is used to input data to the corresponding chip under test at the actual input time point corresponding to each chip under test, so that each chip under test can receive the data input by the test machine in the corresponding data receiving window.
[0044] In one feasible implementation, the first processing module is specifically used for:
[0045] Each chip under test is tested using a preset test method, and the data receiving window corresponding to each chip under test is determined based on the test results.
[0046] In one feasible implementation, the second processing module is specifically used for:
[0047] Determine the time intervals on the time axis for the data input window and the data receiving window corresponding to each chip under test;
[0048] Based on the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis, the time adjustment parameter corresponding to each chip under test is determined.
[0049] In one feasible implementation, the second processing module is specifically used for:
[0050] When there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is greater than or equal to a preset duration threshold, the time adjustment parameter corresponding to the i-th chip under test is determined to be 0.
[0051] When there is an intersection between the first time interval and the second time interval, and the duration of the intersection is less than the preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined according to the preset duration threshold.
[0052] In one feasible implementation, the second processing module is specifically used for:
[0053] When there is an intersection between the first time interval and the second time interval, and the duration of the intersection t is less than the preset duration threshold P, the time adjustment parameter corresponding to the i-th chip under test is determined to be T1; where,
[0054] Pt < T1 < (t1 + t2 - Pt)
[0055] When there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined to be T2; where...
[0056] P + t3 < T2 < (t1 + t2 + t3 - P)
[0057] Where t1 is the duration of the first time interval, t2 is the duration of the second time interval, and t3 is the interval between the first time interval and the second time interval.
[0058] In one feasible implementation, the second processing module is specifically used for:
[0059] When there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is less than a preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the center values of the data input window and the data receiving window corresponding to the i-th chip under test on the time axis are determined respectively.
[0060] The time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to the i-th chip under test on the time axis is determined as the time adjustment parameter corresponding to the i-th chip under test.
[0061] In one feasible implementation, the second processing module is specifically used for:
[0062] Determine the center value of the data input window and the data receiving window corresponding to each chip under test on the time axis;
[0063] The time adjustment parameter for each chip under test is determined based on the time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to each chip under test on the time axis.
[0064] In one feasible implementation, the second processing module is used to:
[0065] The time adjustment parameter T corresponding to the i-th chip under test is determined using the following method. delay (i):
[0066] T delay (i)=T i -T0
[0067] Among them, T i T0 represents the center value of the data receiving window corresponding to the i-th chip under test on the time axis; T0 represents the center value of the data input window on the time axis.
[0068] In one feasible implementation, the third processing module is further configured to:
[0069] Adjust the data transmission time point of the test pin connected to the test machine and the i-th chip under test so that the adjusted data transmission time point is consistent with the actual input time point corresponding to the i-th chip under test.
[0070] In one feasible implementation, it further includes:
[0071] The update module is used to return to the execution of the first processing module when the preset data input window of the test machine is detected, or when the data receiving method of each chip under test changes.
[0072] In some embodiments, an electronic device is provided, including: at least one processor and a memory;
[0073] The memory stores computer-executed instructions;
[0074] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the chip testing method provided in the above embodiments.
[0075] In some embodiments, a computer-readable storage medium is provided that stores computer-executable instructions, which, when executed by a processor, implement the chip testing method provided in the above embodiments.
[0076] In some embodiments, a computer program product is provided, including a computer program that, when executed by a processor, implements the chip testing method provided in the above embodiments.
[0077] The chip testing method and equipment provided in this application can determine the time adjustment parameters for each chip under test according to the data receiving window corresponding to each chip under test and the preset data input window of the testing machine during the chip testing process. Based on the time adjustment parameters corresponding to each chip under test, the actual time point at which the testing machine inputs data to each chip under test is adjusted so that each chip under test receives the data input by the testing machine in the corresponding data receiving window. This can effectively avoid the problem that some chips under test cannot accurately receive data due to performance differences, and improve the consistency and accuracy of the test results. Attached Figure Description
[0078] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments of this application or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0079] Figure 1 This is a schematic diagram of the architecture of a chip testing system provided in the embodiments of this application;
[0080] Figure 2 This is a schematic diagram of the data receiving windows of multiple chips under test in the prior art.
[0081] Figure 3 A schematic flowchart of a chip testing method provided in an embodiment of this application;
[0082] Figure 4 This is a schematic diagram of a chip test result provided in an embodiment of this application;
[0083] Figure 5 This is a schematic diagram showing the distribution of data receiving windows for multiple chips under test in an embodiment of this application;
[0084] Figure 6 This is a schematic diagram showing the distribution of the adjusted data input window in an embodiment of this application;
[0085] Figure 7 A schematic flowchart illustrating another chip testing method provided in an embodiment of this application;
[0086] Figure 8 This is a schematic diagram of a program module for a chip testing device provided in an embodiment of this application;
[0087] Figure 9 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0088] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, although the disclosure in this application is described with reference to one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation on its own.
[0089] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.
[0090] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities, and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, to implement the embodiments in a sequence other than those given in the illustrations or descriptions of this application.
[0091] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.
[0092] As used in this application, the term "module" means any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.
[0093] In the field of integrated circuits (ICs), there is a need to verify the authenticity of electronic components (devices) in all manufacturing processes. This need is actually a testing process used to check the integrity of the device under test (DUT) to ensure the quality of integrated circuit manufacturing. To achieve this process, various testing equipment is needed, which is usually called automatic test equipment (ATE) or test benches.
[0094] Reference Figure 1 , Figure 1 This is a schematic diagram of the architecture of a chip testing system provided in an embodiment of this application. In this embodiment, the chip testing system includes a test bench 101 and multiple chips under test, namely DUT1, DUT2, DUT3, ..., DUTn.
[0095] Optionally, the test equipment 101 includes multiple test pins 1011, each of which is connected to a device under test (DUT). During testing, the test equipment 101 needs to input test data into each DUT.
[0096] like Figure 1 In the test, the test machine 101 is connected to n chips under test, namely DUT1, DUT2, DUT3, ..., DUTn.
[0097] Optionally, the above tests include continuity check, boundary scan chain test, automatic test pattern generation (ATPG) test, burn-in test, stress test, etc., which are not limited in the embodiments of this application.
[0098] Optionally, the chip under test can be a memory chip, microprocessor, standard chip, or system-on-a-chip (SoC), etc., and no limitation is made in this application embodiment.
[0099] For example, the chip under test can be a chip with data storage function such as Dynamic Random Access Memory (DRAM), Asynchronous Dynamic Random Access Memory (ADRAM), Read-Only Memory (ROM), NAND flash memory chip, or FLASH chip.
[0100] In some embodiments, the chip under test may also be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a microcontroller unit (MCU), etc., which will not be listed one by one in the embodiments of this application.
[0101] In traditional testing, each chip under test typically uses a shared set of timing information, meaning that the data input time of each chip under test is consistent, so that the input data provided by the test equipment 101 can reach each chip under test at the same time.
[0102] However, since each chip under test is independent of the others, the data receivers of each chip under test may have inconsistent data reception windows due to performance differences. Therefore, if multiple chips under test use the same timing information to receive data, some chips under test may not be able to accurately receive the data input by the test equipment, resulting in data writing abnormalities and thus incorrect test results.
[0103] To better understand the embodiments of this application, please refer to... Figure 2 , Figure 2 This is a schematic diagram of the data receiving windows of multiple chips under test in the prior art.
[0104] Among them, Figure 2 In this process, a signal is maintained at VIH (Input High Voltage) or VIL (Input Low Voltage) for a period of time to represent data. Only when the chip samples the data and recognizes the corresponding signal is a data transmission completed.
[0105] from Figure 2 As can be seen, the position of the data receiving window corresponding to the chip under test (DUT1) and DUTn on the time axis is inconsistent with the position of the data input window preset by the test equipment on the time axis. As a result, when the test equipment inputs data to each chip under test through the data input window, the chips under test (DUT1, DUT3, and DUTn) may not be able to accurately receive the data transmitted by the test equipment.
[0106] Especially when the chip under test is writing data at high speed, the effective data receiving window of the chip under test will become smaller, which will make it more difficult for the chip under test to accurately receive the data input by the test machine.
[0107] To address the aforementioned technical issues, this application provides a chip testing method. By testing each chip under test (DUT), the data receiving window of each DUT is determined. Then, based on the data receiving window of each DUT, the actual time point at which the testing machine inputs data to each DUT is adjusted to ensure that each DUT can receive data within its data receiving window. This avoids data reception failures due to differences in the performance of the DUTs and helps improve the consistency and accuracy of test results.
[0108] The following detailed embodiments will be used to illustrate the point.
[0109] Reference Figure 3 , Figure 3 This is a flowchart illustrating a chip testing method provided in an embodiment of this application. The execution entity of this embodiment can be... Figure 1 The testing equipment shown in the illustrated embodiment is not particularly limited in this embodiment. In one feasible implementation, the above chip testing method includes:
[0110] Step S301: Determine the data receiving window corresponding to each chip under test.
[0111] In this embodiment of the application, when testing each chip under test, test conditions can be selected first, such as data write rate, clock cycle (Tck), transmission delay time (TPD), etc., and then under the selected test conditions, some preset detection techniques are used to detect each chip under test and determine the position of the data receiving window corresponding to each chip under test on the time axis.
[0112] Here, TPD is the time required for a digital signal to travel from the input to the output of a logic gate. The smaller the TPD, the faster the chip under test (DUT) operates. In the embodiments of this application, the aforementioned transmission delay time can be understood as the delay time during which the DUT can successfully receive data in a given clock cycle.
[0113] In one feasible implementation, the data receiver corresponding to each chip under test can be tested to determine the position of the data receiving window corresponding to each chip under test on the time axis.
[0114] Step S302: Determine the time adjustment parameters for each chip under test based on the data receiving window corresponding to each chip under test and the preset data input window of the test machine.
[0115] In one feasible implementation, after determining the data receiving window corresponding to each chip under test, the position of the data input window of the test instrument on the time axis is determined. Then, based on the position of the data receiving window corresponding to each chip under test on the time axis and the position of the data input window of the test instrument on the time axis, the time adjustment parameters corresponding to each chip under test are determined.
[0116] It is understandable that for the data receiving window of the chip under test (DUT) to receive data from the data input window of the test equipment, the DUT's data receiving window and the test equipment's data input window must intersect on the time axis. Within this intersection, the DUT's data receiving window can receive the data from the test equipment's data input window. Therefore, in one feasible implementation, the time adjustment parameters for each DUT can be determined based on the positions of the DUT's data receiving window and the test equipment's data input window on the time axis, ensuring that the adjusted DUT's data receiving window and the test equipment's data input window intersect on the time axis.
[0117] Step S303: Determine the actual input time point for each chip under test based on the time adjustment parameters corresponding to each chip under test.
[0118] In this embodiment of the application, after determining the time adjustment parameter corresponding to each chip under test, the timing point at which the test machine inputs data to each chip under test is adjusted according to the time adjustment parameter, so that each chip under test can receive the data sent by the test machine in its data receiving window.
[0119] In one feasible implementation, the center position of the data input window of the adjusted test instrument for inputting data to each chip under test on the time axis can be used as the actual input time point corresponding to each chip under test.
[0120] For example, if the time adjustment parameter corresponding to the chip under test (DUT1) is -50ps, the data input window of the test equipment for inputting data to the chip under test (DUT1) will be advanced by 50ps; if the time adjustment parameter corresponding to the chip under test (DUT1) is 50ps, the data input window of the test equipment for inputting data to the chip under test (DUT1) will be delayed by 50ps.
[0121] Step S304: Input data to the corresponding chip under test at the actual input time point for each chip under test, so that each chip under test receives the data input by the test machine in the corresponding data receiving window.
[0122] In this embodiment, after adjusting the position of the data input window of the test machine to input data to each chip under test according to the time adjustment parameter corresponding to each chip under test, the test machine can input data to each chip under test through the data input window corresponding to each chip under test.
[0123] The chip testing method provided in this application determines the time adjustment parameters for each chip under test (DUT) based on the data receiving window corresponding to each DUT and the preset data input window of the testing machine during the chip testing process. Based on these time adjustment parameters, the actual time point at which the testing machine inputs data to each DUT is adjusted. This ensures that each DUT receives the data input by the testing machine within its corresponding data receiving window, effectively avoiding the problem of some DUTs failing to accurately receive data due to performance differences, and improving the consistency and accuracy of the test results.
[0124] Based on the content described in the above embodiments, in one feasible implementation of this application, when determining the data receiving window corresponding to each chip under test, some preset test methods for testing chip performance can be used to test each chip under test, and the data receiving window corresponding to each chip under test can be determined according to the test results.
[0125] In one feasible implementation, the aforementioned preset test method can be SHMOO testing. By performing SHMOO testing on each chip under test and determining the data receiving window corresponding to each chip under test based on the SHMOO test results, the data receiving window corresponding to each chip under test can be determined.
[0126] Among them, SHMOO testing can scan each condition parameter related to the chip under test within a certain value range to obtain the state of the chip under test under different operating conditions, thereby conducting a comprehensive evaluation of the chip performance.
[0127] For example, when performing SHMOO testing, multiple performance-related metrics can be selected, such as maximum operating frequency and power supply voltage. These two metrics can be scanned in two dimensions, and the scan results can be displayed in a two-dimensional XY coordinate system. This allows for a more intuitive understanding of the relationship between the two selected variables.
[0128] In one feasible implementation, the test equipment can determine the data receiving window corresponding to each chip under test based on the SHMOO test results, i.e., the SHMOO diagram.
[0129] To better understand the embodiments of this application, please refer to... Figure 4 , Figure 4 This is a schematic diagram of a chip test result provided in an embodiment of this application.
[0130] exist Figure 4 In the diagram, "Area 1" represents the area where data reception failed (Fail), "Area 2" represents the area where data reception was successful (Pass), and the boundary between "Area 1" and "Area 2" is the fault boundary.
[0131] In actual testing, the transmission delay time of the chip under test (DUT) when using different clock cycles can be measured first. Then, the data receiving window of the DUT can be determined based on the transmission delay time of the chip under test when using different clock cycles.
[0132] In some embodiments, the location of the data receiving window corresponding to the chip under test can be determined based on the distribution of "Region 2".
[0133] For example, the center position of "Region Two" on the time axis (T) i (This is the center position of the data receiving window of the chip under test.)
[0134] In some embodiments, other testing methods may be used to test each chip under test in order to determine the data receiving window corresponding to each chip under test. Examples will not be given in this application.
[0135] The chip testing method provided in this application determines the data receiving window for each chip under test (DUT) by employing SHMOO testing during the chip testing process. Then, based on the data receiving window of each DUT and the preset data input window of the testing equipment, the time adjustment parameter for each DUT can be determined. Subsequently, based on the time adjustment parameter of each DUT, the actual time point at which the testing equipment inputs data to each DUT is adjusted, thereby ensuring that each DUT receives the data input by the testing equipment within its corresponding data receiving window, thus improving the consistency and accuracy of the test results.
[0136] Based on the content described in the above embodiments, in some embodiments of this application, after determining the data receiving window corresponding to each chip under test, the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis can be determined respectively, and the time adjustment parameter corresponding to each chip under test can be determined according to the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis.
[0137] In one feasible implementation, when there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is greater than or equal to a preset duration threshold, it can be assumed that the data receiving window corresponding to the i-th chip under test can receive the data input by the data input window. In this case, there is no need to adjust the data receiving window of the i-th chip under test, so the time adjustment parameter corresponding to the i-th chip under test can be determined to be 0.
[0138] When there is an intersection between the first time interval and the second time interval, and the duration of the intersection is less than the preset duration threshold, or when there is no intersection between the first time interval and the second time interval, it is determined that the data receiving window corresponding to the i-th chip under test cannot receive the data input from the data input window. At this time, the time adjustment parameter corresponding to the i-th chip under test can be determined according to the preset duration threshold.
[0139] In one feasible implementation, when there is an intersection between the first time interval and the second time interval, and the duration of the intersection t is less than the preset duration threshold P, the time adjustment parameter corresponding to the i-th chip under test is determined to be T1; wherein,
[0140] Pt < T1 < (t1 + t2 - Pt)
[0141] When there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined to be T2; where...
[0142] P + t3 < T2 < (t1 + t2 + t3 - P)
[0143] Where t1 is the duration of the first time interval, t2 is the duration of the second time interval, and t3 is the interval between the first and second time intervals.
[0144] It should be noted that the two endpoints of the first time interval are the start and end times of the data input window of the test instrument on the time axis, and t1 is the difference between the two endpoints of the first time interval; the two endpoints of the second time interval are the start and end times of the data receiving window corresponding to the i-th chip under test on the time axis, and t2 is the difference between the two endpoints of the second time interval; t3 is the interval between the end time of the first time interval and the start time of the second time interval, or the interval between the end time of the second time interval and the start time of the first time interval.
[0145] In another feasible embodiment of this application, when there is an intersection between the first time interval and the second time interval, and the duration of the intersection is less than the preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the center values of the data input window and the data receiving window corresponding to the i-th chip under test are determined on the time axis, and the time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to the i-th chip under test is determined as the time adjustment parameter corresponding to the i-th chip under test, so that the position of the data input window of the test machine inputting data to each chip under test on the time axis is consistent with the position of the data receiving window corresponding to each chip under test on the time axis.
[0146] In another feasible embodiment of this application, after determining the data receiving window corresponding to each chip under test, the center value of the data input window and the data receiving window corresponding to each chip under test on the time axis can be determined respectively, and the time adjustment parameter corresponding to each chip under test can be determined based on the time difference between the center value of the data input window of the test machine on the time axis and the center value of the data receiving window corresponding to each chip under test on the time axis.
[0147] In some embodiments, the time adjustment parameters for each chip under test can be determined using the following methods:
[0148] T delay (i)=T i -T0
[0149] Among them, T delay (i) represents the time adjustment parameter corresponding to the i-th chip under test, T i T0 represents the center value of the data receiving window corresponding to the i-th chip under test on the time axis; T0 represents the center value of the data input window of the test instrument on the time axis.
[0150] For example, if the center position of the data receiving window corresponding to the chip under test (DUT1) on the time axis differs from the center position of the data input window of the test instrument on the time axis by -50ps, then the time adjustment parameter corresponding to the chip under test (DUT1) can be determined to be -50ps; if the center position of the data receiving window corresponding to the chip under test (DUT2) on the time axis differs from the center position of the data input window of the test instrument on the time axis by 150ps, then the time adjustment parameter corresponding to the chip under test (DUT2) can be determined to be 150ps.
[0151] To better understand the embodiments of this application, please refer to... Figure 5 , Figure 5 This is a schematic diagram showing the distribution of data receiving windows for multiple chips under test in an embodiment of this application.
[0152] exist Figure 5 In this example, assuming the preset data input window of the test equipment has a center value of 0 ps on the time axis, the center value of chip DUT1 on the time axis is -50 ps, and the center value of chip DUT2 on the time axis is also -50 ps, then the time adjustment parameter T of chip DUT1 can be determined. delay (1) The time adjustment parameter T of the chip under test (DUT2) is -50ps. delay (2) is 150ps.
[0153] In some embodiments, after determining the time adjustment parameters corresponding to each chip under test, the actual input time point corresponding to each chip under test can be determined based on the time adjustment parameters corresponding to each chip under test. Then, the data transmission time point of the test pins connected to the test machine and each chip under test is adjusted so that the adjusted data transmission time point is consistent with the actual input time point corresponding to each chip under test.
[0154] For example, suppose the time adjustment parameter T of the chip under test (DUT1) is determined. delay (1) If the value is -50ps, then the data transmission time of the test pins connected to the test instrument and the chip under test (DUT1) needs to be advanced by 50ps, and the test instrument needs to input data to the DUT1 50ps earlier than the original timing information. Assume that the timing adjustment parameter T of the DUT2 is determined. delay (2) If it is 150ps, then the data transmission time of the test pin connected to the test machine and the chip under test DUT2 needs to be delayed by 150ps, and the test machine should input data to the chip under test DUT1 after a delay of 150ps based on the original timing information.
[0155] To better understand the embodiments of this application, please refer to... Figure 6 , Figure 6This is a schematic diagram showing the distribution of the adjusted data input window in the embodiments of this application.
[0156] like Figure 6 As shown, the test equipment inputs data to the chip under test (DUT1) through data input window 1 and inputs data to the chip under test (DUT2) through data input window 2.
[0157] The chip testing method provided in this application determines the time adjustment parameter for each chip under test based on the time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to each chip under test on the time axis. Then, based on the time adjustment parameter corresponding to each chip under test, the data transmission time point of the test pins connected to the test instrument and each chip under test is adjusted, so that each chip under test can receive the data input by the test instrument in its corresponding data receiving window, which helps to improve the consistency and accuracy of the test results.
[0158] Based on the content described in the above embodiments, referring to Figure 7 , Figure 7 This is a flowchart illustrating another chip testing method provided in this application embodiment. The execution entity of this embodiment can be... Figure 1 The testing equipment shown in the illustrated embodiment is not particularly limited in this embodiment. In one feasible implementation, the above chip testing method includes:
[0159] S701. Determine the data receiving window corresponding to each chip under test.
[0160] S702. Determine the time adjustment parameters for each chip under test based on the data receiving window corresponding to each chip under test and the data input window preset by the test machine.
[0161] S703. Determine the actual input time point for each chip under test based on the time adjustment parameters corresponding to each chip under test;
[0162] S704. Input data to the corresponding chip under test at the actual input time point corresponding to each chip under test, so that each chip under test can receive the data input by the test machine in the corresponding data receiving window.
[0163] The content described in steps S701 to S704 above is consistent with the content described in steps S301 to S304 in the above embodiments. For details, please refer to the content described in the above embodiments. This application will not repeat the description in the embodiments.
[0164] S705. Monitor whether the test conditions have changed. If yes, return to step S701; if no, return to step S704.
[0165] In one feasible implementation of this application, after determining the actual input time point corresponding to each chip under test, it is monitored whether the test conditions of the chip under test or the test equipment have changed; if they have changed, it is necessary to return to step S701, redetermine the data receiving window corresponding to each chip under test, and redetermine the time adjustment parameters corresponding to each chip under test.
[0166] In one feasible implementation, if the preset data input window of the test instrument is detected, or if the data receiving method of each chip under test changes, the test conditions can be considered to have changed.
[0167] For example, when the data write rate, clock cycle (Tck), transmission delay (TPD), etc. change during the test, it can be considered that the test conditions have changed.
[0168] The chip testing method provided in this application, after adjusting the actual input time point corresponding to each chip, requires re-determining the actual input time point corresponding to each chip if the test conditions change. This can prevent some chips under test from failing to receive data accurately due to changes in test conditions.
[0169] Based on the content described in the above embodiments, this application also provides a chip testing apparatus that can be applied to a testing machine. (Refer to...) Figure 8 , Figure 8 This is a schematic diagram of a program module for a chip testing device provided in an embodiment of this application. The chip testing device includes:
[0170] The first processing module 801 is used to determine the data receiving window corresponding to each chip under test.
[0171] The second processing module 802 is used to determine the time adjustment parameters corresponding to each chip under test based on the data receiving window corresponding to each chip under test and the data input window preset by the test machine.
[0172] The third processing module 803 is used to determine the actual input time point corresponding to each chip under test based on the time adjustment parameters corresponding to each chip under test.
[0173] The data transmission module 804 is used to input data to the corresponding chip under test at the actual input time point of each chip under test, so that each chip under test can receive the data input by the test machine in the corresponding data receiving window.
[0174] The chip testing apparatus provided in this application can determine the time adjustment parameters for each chip under test according to the data receiving window corresponding to each chip under test and the preset data input window of the testing machine during the chip testing process. Based on the time adjustment parameters corresponding to each chip under test, the actual time point at which the testing machine inputs data to each chip under test is adjusted so that each chip under test receives the data input by the testing machine in the corresponding data receiving window. This can effectively avoid the problem that some chips under test cannot accurately receive data due to performance differences, and improve the consistency and accuracy of the test results.
[0175] In one feasible implementation, the first processing module 801 is specifically used for:
[0176] Each chip under test is tested using a preset test method, and the data receiving window corresponding to each chip under test is determined based on the test results.
[0177] Optionally, the above-mentioned preset test method can be SHMOO test, which involves performing SHMOO test on each chip under test and determining the data receiving window corresponding to each chip under test based on the SHMOO test results.
[0178] In one feasible implementation, the second processing module 802 is specifically used for:
[0179] Determine the time intervals on the time axis for the data input window and the data receiving window corresponding to each chip under test;
[0180] Based on the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis, the time adjustment parameter corresponding to each chip under test is determined.
[0181] In one feasible implementation, the second processing module 802 is specifically used for:
[0182] When there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is greater than or equal to a preset duration threshold, the time adjustment parameter corresponding to the i-th chip under test is determined to be 0.
[0183] When there is an intersection between the first time interval and the second time interval, and the duration of the intersection is less than the preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined according to the preset duration threshold.
[0184] In one feasible implementation, the second processing module 802 is specifically used for:
[0185] When there is an intersection between the first time interval and the second time interval, and the duration of the intersection t is less than the preset duration threshold P, the time adjustment parameter corresponding to the i-th chip under test is determined to be T1; where,
[0186] Pt < T1 < (t1 + t2 - Pt)
[0187] When there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined to be T2; where...
[0188] P + t3 < T2 < (t1 + t2 + t3 - P)
[0189] Where t1 is the duration of the first time interval, t2 is the duration of the second time interval, and t3 is the interval between the first time interval and the second time interval.
[0190] In one feasible implementation, the second processing module 802 is specifically used for:
[0191] When there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is less than a preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the center values of the data input window and the data receiving window corresponding to the i-th chip under test on the time axis are determined respectively.
[0192] The time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to the i-th chip under test on the time axis is determined as the time adjustment parameter corresponding to the i-th chip under test.
[0193] In one feasible implementation, the second processing module 802 is specifically used for:
[0194] Determine the center value of the data input window and the data receiving window corresponding to each chip under test on the time axis; based on the time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to each chip under test on the time axis, determine the time adjustment parameter corresponding to each chip under test.
[0195] In one feasible implementation, the second processing module 802 is used for:
[0196] The time adjustment parameter T corresponding to the i-th chip under test is determined using the following method.delay (i):
[0197] T delay (i)=T i -T0
[0198] Among them, T i T0 represents the center value of the data receiving window corresponding to the i-th chip under test on the time axis; T0 represents the center value of the data input window on the time axis.
[0199] In one feasible implementation, the third processing module 803 is further configured to:
[0200] Adjust the data transmission time point of the test pin connected to the test machine and the i-th chip under test so that the adjusted data transmission time point is consistent with the actual input time point corresponding to the i-th chip under test.
[0201] In one feasible implementation, the above-mentioned apparatus further includes:
[0202] The update module is used to return to the execution of the first processing module 801 when the preset data input window of the test machine is detected, or when the data receiving method of each chip under test changes.
[0203] It should be noted that the specific execution of the first processing module 801, the second processing module 802, the third processing module 803, and the data transmission module 804 described in the above embodiments can be found in the [reference needed]. Figures 3 to 7 Each step in the chip testing method described in the illustrated embodiment will not be elaborated here.
[0204] Furthermore, based on the content described in the above embodiments, this application also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement each step in the chip testing method described in the above embodiments, and the specific details can be referred to the description in the above embodiments, which will not be repeated here.
[0205] Optionally, the aforementioned electronic equipment can be a testing machine.
[0206] To better understand the embodiments of this application, please refer to... Figure 9 , Figure 9 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application.
[0207] Optionally, the aforementioned electronic equipment can be a testing machine.
[0208] like Figure 9As shown, the electronic device 90 of this embodiment includes: a processor 901 and a memory 802; wherein:
[0209] Memory 902 is used to store instructions executed by the computer;
[0210] The processor 901 is used to execute computer execution instructions stored in the memory, and can implement each step of the chip testing method described in the above embodiments. For details, please refer to the description in the above embodiments, which will not be repeated here.
[0211] Alternatively, the memory 902 can be either standalone or integrated with the processor 901.
[0212] When the memory 902 is set up independently, the device also includes a bus 903 for connecting the memory 902 and the processor 901.
[0213] Furthermore, based on the content described in the above embodiments, this application also provides a computer-readable storage medium storing computer-executable instructions. When the processor executes the computer-executable instructions, each step in the chip testing method described in the above embodiments can be implemented. For details, please refer to the description in the above embodiments, which will not be repeated here.
[0214] Furthermore, based on the content described in the above embodiments, this application also provides a computer program product, including a computer program. When the computer program is executed by a processor, it can implement each step of the chip testing method described in the above embodiments. For details, please refer to the description in the above embodiments, which will not be repeated here.
[0215] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.
[0216] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0217] Furthermore, in each embodiment of this application, the functional modules can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit integrating the above modules can be implemented in hardware or in the form of hardware plus software functional units.
[0218] The integrated modules implemented as software functional modules described above can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute certain steps of the methods described in each embodiment of this application.
[0219] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.
[0220] The memory may include high-speed RAM, and may also include non-volatile storage (NVM), such as at least one disk storage device, and may also be a USB flash drive, external hard drive, read-only memory, disk or optical disc, etc.
[0221] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0222] The aforementioned storage medium can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.
[0223] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.
[0224] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
[0225] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A chip testing method, characterized in that, The method includes: Determine the data receiving window corresponding to each chip under test; Based on the data receiving window corresponding to each chip under test and the data input window preset by the test machine, the time adjustment parameter corresponding to each chip under test is determined; Based on the time adjustment parameters corresponding to each chip under test, the actual input time point corresponding to each chip under test is determined; Data is input to the corresponding chip under test at the actual input time point corresponding to each chip under test, so that each chip under test receives the data input by the test machine in the corresponding data receiving window; The step of determining the time adjustment parameter corresponding to each chip under test based on the data receiving window corresponding to each chip under test and the data input window preset by the test equipment includes: Determine the time intervals on the time axis for the data input window and the data receiving window corresponding to each chip under test; Based on the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis, the time adjustment parameter corresponding to each chip under test is determined. The step of determining the time adjustment parameter corresponding to each chip under test based on the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis includes: When there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is greater than or equal to a preset duration threshold, the time adjustment parameter corresponding to the i-th chip under test is determined to be 0. When there is an intersection between the first time interval and the second time interval, and the duration of the intersection is less than the preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined according to the preset duration threshold. The step of determining the time adjustment parameter corresponding to the i-th chip under test according to the preset duration threshold includes: When there is an intersection between the first time interval and the second time interval, and the duration of the intersection t is less than the preset duration threshold P, the time adjustment parameter corresponding to the i-th chip under test is determined to be T1; where, Pt < T1 < (t1 + t2 - Pt) When there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined to be T2; where... P + t3 < T2 < (t1 + t2 + t3 - P) Where t1 is the duration of the first time interval, t2 is the duration of the second time interval, and t3 is the interval between the first time interval and the second time interval.
2. The method according to claim 1, characterized in that, The process of determining the data receiving window corresponding to each chip under test includes: Each chip under test is tested using a preset test method, and the data receiving window corresponding to each chip under test is determined based on the test results.
3. The method according to claim 1, characterized in that, The step of determining the time adjustment parameter corresponding to each chip under test based on the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis includes: When there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is less than a preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the center values of the data input window and the data receiving window corresponding to the i-th chip under test on the time axis are determined respectively. The time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to the i-th chip under test on the time axis is determined as the time adjustment parameter corresponding to the i-th chip under test.
4. The method according to claim 1, characterized in that, The step of determining the time adjustment parameter corresponding to each chip under test based on the data receiving window corresponding to each chip under test and the data input window preset by the test equipment includes: Determine the center value of the data input window and the data receiving window corresponding to each chip under test on the time axis; The time adjustment parameter for each chip under test is determined based on the time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to each chip under test on the time axis.
5. The method according to claim 4, characterized in that, The step of determining the time adjustment parameter for each chip under test based on the time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to each chip under test on the time axis includes: The timing adjustment parameter Tdelay(i) corresponding to the i-th chip under test is determined using the following method: Tdelay(i) = Ti - T0 Where Ti represents the center value of the data receiving window corresponding to the i-th chip under test on the time axis; T0 represents the center value of the data input window on the time axis.
6. The method according to claim 1, characterized in that, After determining the actual input time point corresponding to each chip under test, the method further includes: Adjust the data transmission time point of the test pin connected to the test instrument and the i-th chip under test so that the adjusted data transmission time point is consistent with the actual input time point corresponding to the i-th chip under test.
7. The method according to any one of claims 1 to 6, characterized in that, After determining the actual input time point corresponding to each chip under test, the method further includes: When the preset data input window of the test instrument is detected, or when the data receiving method of each chip under test changes, the process returns to the step of determining the data receiving window corresponding to each chip under test.
8. A chip testing device, characterized in that, The device includes: The first processing module is used to determine the data receiving window corresponding to each chip under test; The second processing module is used to determine the time adjustment parameters corresponding to each chip under test based on the data receiving window corresponding to each chip under test and the data input window preset by the test machine. The third processing module is used to determine the actual input time point corresponding to each chip under test based on the time adjustment parameters corresponding to each chip under test. The data transmission module is used to input data to the corresponding chip under test at the actual input time point corresponding to each chip under test, so that each chip under test can receive the data input by the test machine in the corresponding data receiving window; The second processing module is specifically used for: Determine the time intervals on the time axis for the data input window and the data receiving window corresponding to each chip under test; Based on the time interval occupied by the data input window and the data receiving window corresponding to each chip under test on the time axis, the time adjustment parameter corresponding to each chip under test is determined. The second processing module is specifically used for: When there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is greater than or equal to a preset duration threshold, the time adjustment parameter corresponding to the i-th chip under test is determined to be 0. When there is an intersection between the first time interval and the second time interval, and the duration of the intersection is less than the preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined according to the preset duration threshold. The second processing module is specifically used for: When there is an intersection between the first time interval and the second time interval, and the duration of the intersection t is less than the preset duration threshold P, the time adjustment parameter corresponding to the i-th chip under test is determined to be T1; where, Pt < T1 < (t1 + t2 - Pt) When there is no intersection between the first time interval and the second time interval, the time adjustment parameter corresponding to the i-th chip under test is determined to be T2; where... P + t3 < T2 < (t1 + t2 + t3 - P) Where t1 is the duration of the first time interval, t2 is the duration of the second time interval, and t3 is the interval between the first time interval and the second time interval.
9. The apparatus according to claim 8, characterized in that, The first processing module is specifically used for: Each chip under test is tested using a preset test method, and the data receiving window corresponding to each chip under test is determined based on the test results.
10. The apparatus according to claim 8, characterized in that, The second processing module is specifically used for: When there is an intersection between the first time interval occupied by the data input window on the time axis and the second time interval occupied by the data receiving window corresponding to the i-th chip under test on the time axis, and the duration of the intersection is less than a preset duration threshold, or when there is no intersection between the first time interval and the second time interval, the center values of the data input window and the data receiving window corresponding to the i-th chip under test on the time axis are determined respectively. The time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to the i-th chip under test on the time axis is determined as the time adjustment parameter corresponding to the i-th chip under test.
11. The apparatus according to claim 8, characterized in that, The second processing module is specifically used for: Determine the center value of the data input window and the data receiving window corresponding to each chip under test on the time axis; The time adjustment parameter for each chip under test is determined based on the time difference between the center value of the data input window on the time axis and the center value of the data receiving window corresponding to each chip under test on the time axis.
12. The apparatus according to claim 11, characterized in that, The second processing module is used for: The timing adjustment parameter Tdelay(i) corresponding to the i-th chip under test is determined using the following method: Tdelay(i) = Ti - T0 Where Ti represents the center value of the data receiving window corresponding to the i-th chip under test on the time axis; T0 represents the center value of the data input window on the time axis.
13. The apparatus according to claim 8, characterized in that, The third processing module is also used for: Adjust the data transmission time point of the test pin connected to the test instrument and the i-th chip under test so that the adjusted data transmission time point is consistent with the actual input time point corresponding to the i-th chip under test.
14. The apparatus according to any one of claims 8 to 13, characterized in that, Also includes: The update module is used to return to the execution of the first processing module when the preset data input window of the test machine is detected, or when the data receiving method of each chip under test changes.
15. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the chip testing method as described in any one of claims 1 to 7.
16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by the processor, implement the chip testing method as described in any one of claims 1 to 7.
17. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the chip testing method according to any one of claims 1 to 7.