Error positioning method and device, storage medium and processor

Abstract

The application discloses an error positioning method and device, a storage medium and a processor. The method comprises the following steps: obtaining a to-be-detected algorithm; performing program segmentation on the to-be-detected algorithm to obtain a program segmentation result, wherein the program segmentation result is obtained based on different functions of a plurality of algorithm modules in the to-be-detected algorithm; testing the program segmentation result based on a test sample set to obtain a target test matrix; and inputting the target test matrix into a neural network model to obtain an error positioning result. The application solves the technical problem of low accuracy of the existing error positioning method.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically, to an error location method and apparatus, a storage medium, and a processor. Background Technology

[0002] Spectrum-based error localization methods propose a formula for calculating suspicious values, but they struggle to accurately measure the contribution weights of failed and passed tests. For a large number of statements exhibiting the same execution pattern, their suspicious values ​​are identical, making it impossible to further differentiate the priority of inspections. Information retrieval-based error localization methods mostly only locate errors at a coarse-grained level down to the source file level. Furthermore, high-quality error reports are difficult to obtain, resulting in poor effectiveness of this technology in practical applications.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This invention provides an error location method, apparatus, storage medium, and processor to at least address the technical problem of low accuracy in existing error location methods.

[0005] According to one aspect of the present invention, an error localization method is provided, comprising: acquiring an algorithm to be detected; performing program segmentation on the algorithm to be detected to obtain a program segmentation result, wherein the program segmentation result is obtained based on the different functions of multiple algorithm modules in the algorithm to be detected; testing the program segmentation result based on a test sample set to obtain a target test matrix; and inputting the target test matrix into a neural network model to obtain an error localization result.

[0006] Optionally, the above-mentioned program segmentation of the algorithm to be detected to obtain the program segmentation result includes: organizing the program of the algorithm to be detected to determine the algorithm modules, wherein each algorithm module includes at least one source program and each algorithm module corresponds to an algorithm function; numbering the algorithm modules to determine the module number; annotating error-prone modules to determine the annotation information, wherein the error-prone modules are determined based on sample data; and determining the program segmentation result based on the module number and the annotation information.

[0007] Optionally, the above-mentioned testing of the program segmentation results based on the test sample set to obtain the target test matrix includes: determining multiple algorithm modules based on the program segmentation results; testing multiple algorithm modules using multiple test cases from the test sample set to obtain multiple first-order test matrices; and determining the target test matrix based on the multiple first-order test matrices.

[0008] Optionally, the above-mentioned use of multiple test cases from the test sample set to test multiple algorithm modules respectively to obtain multiple first-order test matrices includes: testing multiple algorithm modules with multiple test cases to determine multiple test times and multiple test results, wherein each algorithm module corresponds to one test time and one test result; arranging the multiple test results into a first-order matrix based on the multiple test times to obtain multiple first-order test matrices, wherein the test result of each algorithm module corresponds to one first-order test matrix.

[0009] Optionally, determining the target test matrix based on the plurality of first-order test matrices includes: determining the maximum number of columns in the plurality of first-order test matrices; padding empty spaces in the first-order test matrices with fewer columns than the maximum number of columns to obtain the target first-order matrix; and constructing the target test matrix based on the plurality of target first-order matrices.

[0010] Optionally, the target test matrix is ​​input into the neural network model to obtain the error localization result, including: constructing a fully connected layer using a two-layer long short-term memory network and an activation function; inputting the target test matrix into the fully connected layer to determine the module error probability; and determining the error localization result based on the module error probability.

[0011] According to another aspect of the present invention, an error localization apparatus is also provided, comprising: an acquisition module for acquiring an algorithm to be detected; a segmentation module for performing program segmentation on the algorithm to be detected to obtain a program segmentation result, wherein the program segmentation result is obtained based on the different functions of multiple algorithm modules in the algorithm to be detected; a testing module for testing the program segmentation result based on a set of test samples to obtain a target test matrix; and a processing module for inputting the target test matrix into a neural network model to obtain an error localization result.

[0012] According to another aspect of the present invention, a non-volatile storage medium is also provided, wherein the non-volatile storage medium stores a plurality of instructions, the instructions being adapted to be loaded by a processor and executed any one of the above-described error location methods.

[0013] According to another aspect of the present invention, a processor is also provided, which is used to run a program, wherein the program is configured to execute any of the above-described error location methods during runtime.

[0014] According to another aspect of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform any of the above-described error location methods.

[0015] In this embodiment of the invention, the algorithm to be detected is obtained; the algorithm to be detected is segmented to obtain a segmentation result, wherein the segmentation result is obtained based on the different functions of multiple algorithm modules in the algorithm to be detected; the segmentation result is tested based on a test sample set to obtain a target test matrix; the target test matrix is ​​input into a neural network model to obtain an error localization result. This achieves the purpose of segmenting the algorithm and constructing a test matrix based on the segmentation result, thereby realizing the technical effect of designing a deep learning error localization method based on the modularity of the algorithm, and thus solving the technical problem of low accuracy of existing error localization methods. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0017] Figure 1 This is a flowchart of an error location method according to an embodiment of the present invention;

[0018] Figure 2 This is a schematic flowchart of an optional error location method according to an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of an optional model structure according to an embodiment of the present invention;

[0020] Figure 4 A schematic diagram of the structure of an error location device according to an embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] Example 1

[0024] According to an embodiment of the present invention, an embodiment of an error location method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0025] Figure 1 This is a flowchart of an error location method according to an embodiment of the present invention, such as... Figure 1 As shown, the method includes the following steps:

[0026] Step S102: Obtain the algorithm to be detected;

[0027] Step S104: Perform program segmentation on the above-mentioned algorithm to be detected to obtain program segmentation results, wherein the program segmentation results are obtained based on the different functions of multiple algorithm modules in the above-mentioned algorithm to be detected.

[0028] Step S106: Test the above program segmentation results based on the test sample set to obtain the target test matrix;

[0029] Step S108: Input the above target test matrix into the neural network model to obtain the error localization result.

[0030] In this embodiment of the invention, the execution subject of the error localization method in steps S102 to S108 is an error localization system. The system obtains the algorithm to be detected; performs program segmentation on the algorithm to be detected to obtain program segmentation results; tests the program segmentation results based on the test sample set to obtain a target test matrix; and inputs the target test matrix into a neural network model to obtain error localization results.

[0031] As an optional embodiment, such as Figure 2The flowchart of the error localization method shown first illustrates the modularization of the artificial intelligence algorithm. The algorithm is divided into n different basic functional units, which are then numbered. Next, a two-dimensional matrix is ​​constructed. This matrix, constructed using test cases, the modules each test case traverses in the algorithm, and the test case results, serves as the input to the error localization algorithm. The algorithm's error condition is the output. Finally, an LSTM (Long Short-Term Memory) network and a fully connected network are constructed and trained as the error localization model.

[0032] In an optional embodiment, the above-mentioned program segmentation of the algorithm to be detected to obtain the program segmentation result includes: organizing the program of the algorithm to be detected to determine the algorithm modules, wherein each algorithm module includes at least one source program and each algorithm module corresponds to an algorithm function; numbering the algorithm modules to determine the module number; annotating error-prone modules to determine the annotation information, wherein the error-prone modules are determined based on sample data; and determining the program segmentation result based on the module number and the annotation information.

[0033] As an optional implementation, artificial intelligence algorithm code differs from general system programs. An AI algorithm typically integrates multiple models to process data, with each model containing data processing, model execution, and model output. When dividing an AI algorithm into modules, the overall program can be divided accordingly, with the source program P = {1, 2, 3, ..., n}.

[0034] In an optional embodiment, the above-mentioned testing of the program segmentation results based on the test sample set to obtain the target test matrix includes: determining multiple algorithm modules based on the program segmentation results; testing the multiple algorithm modules using multiple test cases from the test sample set to obtain multiple first-order test matrices; and determining the target test matrix based on the multiple first-order test matrices.

[0035] As an optional implementation, for the source program P = {1, 2, 3, ... m} and the test case set T = {t1, t2, t3, ... t...} n The execution order and result of a program module after a test are represented as a 1×(j+1) matrix, where x j Represents test case t i The module number in the algorithm through which the execution proceeds, and y represents the result of the algorithm's execution on the test case:

[0036] t i [x1 x2 ... x j y]

[0037] x j∈{1, 2, 3, ..., m}

[0038] It should be noted that the above-mentioned use of multiple test cases from the test sample set to test multiple algorithm modules respectively to obtain multiple first-order test matrices includes: testing multiple algorithm modules with multiple test cases to determine multiple test times and multiple test results, wherein each algorithm module corresponds to one test time and one test result; arranging the multiple test results into a first-order matrix based on the multiple test times to obtain multiple first-order test matrices, wherein the test result of each algorithm module corresponds to one first-order test matrix.

[0039] In an optional embodiment, determining the target test matrix based on the plurality of first-order test matrices includes: determining the maximum number of columns in the plurality of first-order test matrices; padding empty spaces in the first-order test matrices with fewer columns than the maximum number of columns with zeros to obtain a target first-order matrix; and constructing the target test matrix based on the plurality of target first-order matrices.

[0040] As an optional implementation, each test case will form a row of data. The test case that has gone through the most models is selected as the standard for the number of columns in the matrix, that is, the largest j value is selected. If the number of models that other test cases have gone through is insufficient, zeros are added to make the data volume the same, and finally an n×(j+1) order matrix is ​​formed.

[0041] In one optional embodiment, the target test matrix is ​​input into the neural network model to obtain the error localization result, including: constructing a fully connected layer using a two-layer long short-term memory network and an activation function; inputting the target test matrix into the fully connected layer to determine the module error probability; and determining the error localization result based on the module error probability.

[0042] As an alternative implementation, the matrices are generated in the order of execution when they are constructed, and the execution results are closely related to the execution order. In other words, there is a temporal relationship between the matrices. Therefore, using LSTM networks to construct error localization models is suitable for solving error localization in artificial intelligence algorithms.

[0043] Optional, such as Figure 3 The diagram shows the model structure, which consists of two layers of Long Short-Term Memory (LSTM) networks and a fully connected layer consisting of a sigmoid activation function. LSTM strengthens the temporal relationships between data, the dropout layer reduces computation and prevents overfitting, and the fully connected layer with sigmoid outputs the probability of an error in a particular module.

[0044] By following the steps above, the temporal characteristics of program execution can be incorporated into the localization research, making it more suitable for research on artificial intelligence algorithms. Transforming the prediction problem into an error classification problem can reduce errors, more accurately determine the location of errors, and achieve higher accuracy.

[0045] Example 2

[0046] According to an embodiment of the present invention, an apparatus embodiment for implementing the above-described error location method is also provided. Figure 4 A schematic diagram of the structure of an error location device according to an embodiment of the present invention is shown below. Figure 4 As shown, the above-mentioned error location device includes: an acquisition module 40, a segmentation module 42, a testing module 44, and a processing module 46, wherein:

[0047] Module 40 is used to acquire the algorithm to be detected;

[0048] Segmentation module 42 is used to segment the above-mentioned algorithm to be detected and obtain the program segmentation result, wherein the program segmentation result is obtained based on the different functions of multiple algorithm modules in the above-mentioned algorithm to be detected.

[0049] Test module 44 is used to test the segmentation results of the above program based on the test sample set to obtain the target test matrix;

[0050] Processing module 46 is used to input the above target test matrix into the neural network model to obtain the error localization result.

[0051] It should be noted that the acquisition module 40, segmentation module 42, testing module 44, and processing module 46 mentioned above correspond to steps S102 to S108 in Embodiment 1. The instances and application scenarios implemented by these modules and their corresponding steps are the same, but they are not limited to the content disclosed in Embodiment 1. It should also be noted that these modules, as part of the device, can run on a computer terminal.

[0052] It should be noted that the optional or preferred implementation methods of this embodiment can be found in the relevant description in Embodiment 1, and will not be repeated here.

[0053] The aforementioned error location device may further include a processor and a memory. The aforementioned acquisition module 40, segmentation module 42, testing module 44, and processing module 46 are all stored in the memory as program units, and the processor executes the aforementioned program units stored in the memory to realize the corresponding functions.

[0054] The processor contains a core that retrieves corresponding program units from memory. One or more cores may be configured. Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory includes at least one memory chip.

[0055] According to an embodiment of this application, an embodiment of a non-volatile storage medium is also provided. Optionally, in this embodiment, the non-volatile storage medium includes a stored program, wherein, when the program is running, it controls the device where the non-volatile storage medium is located to execute any of the aforementioned error location methods.

[0056] Optionally, in this embodiment, the non-volatile storage medium may be located in any computer terminal in a group of computer terminals in a computer network, or in any mobile terminal in a group of mobile terminals, and the non-volatile storage medium includes stored programs.

[0057] Optionally, during program execution, the device containing the non-volatile storage medium is controlled to perform the following functions: acquire the algorithm to be tested; segment the algorithm to be tested to obtain a segmentation result, wherein the segmentation result is obtained based on the different functions of multiple algorithm modules in the algorithm to be tested; test the segmentation result based on a set of test samples to obtain a target test matrix; and input the target test matrix into a neural network model to obtain an error localization result.

[0058] Optionally, during program execution, the device containing the non-volatile storage medium performs the following functions: organizing the algorithm to be tested, identifying algorithm modules, wherein each algorithm module includes at least one source program, and each algorithm module corresponds to an algorithm function; numbering the algorithm modules to determine module numbers; labeling error-prone modules to determine labeling information, wherein the error-prone modules are determined based on sample data; and determining the program segmentation result based on the module numbers and the labeling information.

[0059] Optionally, during program execution, the device containing the non-volatile storage medium is controlled to perform the following functions: determine multiple algorithm modules based on the program segmentation results; test multiple algorithm modules using multiple test cases from the test sample set to obtain multiple first-order test matrices; and determine the target test matrix based on the multiple first-order test matrices.

[0060] Optionally, during program execution, the device containing the non-volatile storage medium is controlled to perform the following functions: test multiple algorithm modules using multiple test cases, determine multiple test times and multiple test results, wherein each algorithm module corresponds to one test time and one test result; arrange the multiple test results into a first-order matrix based on the multiple test times to obtain multiple first-order test matrices, wherein the test result of each algorithm module corresponds to one first-order test matrix.

[0061] Optionally, during program execution, the device containing the non-volatile storage medium is controlled to perform the following functions: determine the maximum number of columns in the plurality of first-order test matrices; fill empty spaces in the plurality of first-order test matrices with fewer than the maximum number of columns to obtain a target first-order matrix; and construct the target test matrix based on the plurality of target first-order matrices.

[0062] Optionally, during program execution, the device containing the non-volatile storage medium is controlled to perform the following functions: construct a fully connected layer using a two-layer long short-term memory network and an activation function; input the aforementioned target test matrix into the aforementioned fully connected layer to determine the module error probability; and determine the aforementioned error localization result based on the aforementioned module error probability.

[0063] According to an embodiment of this application, an embodiment of a processor is also provided. Optionally, in this embodiment, the processor is used to run a program, wherein the program executes any of the above-described error location methods during runtime.

[0064] According to an embodiment of this application, an embodiment of an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform any of the above-described error location methods.

[0065] According to an embodiment of this application, an embodiment of a computer program product is also provided, which, when executed on a data processing device, is adapted to execute a program that initializes the error location method steps described above.

[0066] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0067] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0068] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0069] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0070] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0071] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0072] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An error localization method, characterized in that, include: Obtain the algorithm to be detected, wherein the algorithm to be detected is an artificial intelligence algorithm, including multiple functional modules; The algorithm to be detected is segmented to obtain a segmentation result, wherein the segmentation result is obtained based on the different functions of multiple algorithm modules in the algorithm to be detected. The program segmentation results are tested based on the test sample set to obtain a target test matrix, wherein the target test matrix is ​​generated according to the execution order; The target test matrix is ​​input into the neural network model to obtain the error localization results; The process of inputting the target test matrix into a neural network model to obtain the error localization result includes: constructing a fully connected layer using a two-layer long short-term memory network and an activation function; inputting the target test matrix into the two-layer long short-term memory network and the fully connected layer to determine the module error probability; and determining the error localization result based on the module error probability. The step of segmenting the algorithm to be detected to obtain a segmentation result includes: organizing the algorithm to be detected to determine algorithm modules, wherein each algorithm module includes at least one source program and each algorithm module corresponds to an algorithm function; numbering the algorithm modules to determine module numbers; labeling error-prone modules to determine labeling information, wherein the error-prone modules are determined based on sample data; and determining the segmentation result based on the module numbers and the labeling information.

2. The method according to claim 1, characterized in that, The step of testing the program segmentation results based on the test sample set to obtain the target test matrix includes: Based on the program segmentation results, multiple algorithm modules are determined; Multiple test cases from the test sample set are used to test multiple algorithm modules respectively, resulting in multiple first-order test matrices; The target test matrix is ​​determined based on the plurality of first-order test matrices.

3. The method according to claim 2, characterized in that, The algorithm modules are tested using multiple test cases from a test sample set, resulting in multiple first-order test matrices, including: Multiple test cases are used to test multiple algorithm modules to determine multiple test times and multiple test results, wherein each algorithm module corresponds to one test time and one test result; The multiple test results are arranged into a first-order matrix based on the multiple test times to obtain multiple first-order test matrices, wherein the test result of each algorithm module corresponds to one first-order test matrix.

4. The method according to claim 3, characterized in that, Determining the target test matrix based on the plurality of first-order test matrices includes: Determine the maximum number of columns in the plurality of first-order test matrices; Empty spaces in the first-order test matrices with fewer columns than the maximum number of columns are filled with zeros to obtain the target first-order matrix; The target test matrix is ​​constructed based on multiple target first-order matrices.

5. An error location device, characterized in that, include: An acquisition module is used to acquire the algorithm to be detected, wherein the algorithm to be detected is an artificial intelligence algorithm, and includes multiple functional modules; A segmentation module is used to segment the algorithm to be detected and obtain a segmentation result, wherein the segmentation result is obtained based on the different functions of multiple algorithm modules in the algorithm to be detected. The testing module is used to test the program segmentation results based on the test sample set to obtain a target test matrix, wherein the target test matrix is ​​generated according to the execution order; The processing module is used to input the target test matrix into the neural network model to obtain the error localization result; The processing module is further configured to construct a fully connected layer using a two-layer long short-term memory network and an activation function; input the target test matrix into the two-layer long short-term memory network and the fully connected layer to determine the module error probability; and determine the error localization result based on the module error probability. The segmentation module is further configured to organize the algorithm to be detected, determine the algorithm modules, wherein each algorithm module includes at least one source program and each algorithm module corresponds to an algorithm function; number the algorithm modules to determine the module number; label error-prone modules to determine the labeling information, wherein the error-prone modules are determined based on sample data; and determine the program segmentation result based on the module number and the labeling information.

6. A non-volatile storage medium, characterized in that, The non-volatile storage medium stores multiple instructions, which are adapted to be loaded by a processor and executed by the error location method according to any one of claims 1 to 4.

7. A processor, characterized in that, The processor is used to run a program, wherein the program is configured to execute the error location method according to any one of claims 1 to 4 at runtime.

8. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the error location method according to any one of claims 1 to 4.

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