Topology simulation of layout design

Abstract

The present application is directed to topological simulation of a layout design. Disclosed are an apparatus, a computer-implemented method, and a non-transitory computer-readable medium storing instructions for simulating topological features of a layout design. An example method includes: receiving information about the layout design in a verification area, the information including topological parameters; defining a width of one or more windows in a first direction and a length in a second direction; for the one or more windows, defining a first step length independently of the width in the first direction and a second step length independently of the length in the second direction, the first step length being the distance between adjacent center points of the one or more windows in the first direction, and the second step length being the distance between adjacent center points of the one or more windows in the second direction; extracting information about the layout design in the one or more windows at each of a plurality of window positions; and storing the information in a database.

Description

Technical Field

[0001] This application is aimed at topological simulation of layout design. Background Art

[0002] High data reliability, high-speed memory access, low power consumption, and reduced chip size are desirable features of semiconductor devices. To achieve reduced chip size and high data reliability, precision manufacturing of semiconductor devices has been developed. With the miniaturization and multi-layer wiring structures of semiconductor devices, chemical mechanical polishing (CMP) has been introduced. After a circuit pattern is formed on a wafer, the wafer may have a surface with steps between different levels. CMP is a technique that flattens the surface of a wafer through the interaction of chemical reactions and mechanical reactions (e.g., physical contact) on the surface, so that the surface is substantially level. Basic CMP characteristics are based on process conditions (e.g., platen rotation speed and polishing pressure), specific physical properties of the wafer and polishing pad materials (e.g., slurry, abrasiveness), etc. In actual CMP processes, these basic CMP characteristics are also affected by the basic physical shape of each wafer layout design, such as pattern density, wiring (e.g., line) dimensions, etc. Furthermore, the basic CMP characteristics of each pattern are also affected by the basic CMP characteristics of adjacent patterns.

[0003] In recent years, design for manufacturing (DFM) technology has been introduced to improve CMP planarization performance by suppressing corrosion and dishing. Using DFM, device pattern shape or pattern density can be optimized to achieve suitable basic CMP characteristics for each CMP process. Layout design simulators have been introduced to assist in checking and optimizing each CMP process by predicting the physical parameters of each wafer layout design after each CMP process. For example, such physical parameters may include pattern density D, line width Lw, line spacing Ls, line length Lg, pattern perimeter P, perimeter density Pd, and so on. During each simulation, a window size optimized for each process level can be defined on the simulator, and the simulator extracts these physical parameters. In conventional techniques, the window size definition is limited to a resolution of two dimensions (e.g., the X / Y axes), and the step size in each direction is also limited to the resolution of the two dimensions. To improve simulator accuracy, a more flexible window resolution and step size that are independent of the window size is needed. Summary of the Invention

[0004] On the one hand, the present application relates to a computer-implemented method for simulating topological features of a layout design, the method comprising: receiving information about a layout design in a verification area, the information about the layout design including one or more topological parameters; defining a width in a first direction and a length in a second direction of one or more windows in the verification area; defining a first step length independently of the width of the one or more windows in the first direction, the first step length being the distance between adjacent center points of the one or more windows in the first direction; defining a second step length independently of the length of the one or more windows in the second direction, the second step length being the distance between adjacent center points of the one or more windows in the second direction; extracting information about the layout design in one or more windows at each of a plurality of window positions in the entire verification area; and storing information about the layout design of the one or more windows at each of the plurality of window positions in a database.

[0005] On the other hand, the present application relates to an apparatus for simulating topological features of a layout design, the apparatus comprising: an input device configured to receive information about the layout design in a verification area; one or more processors configured to: define a width in a first direction and a length in a second direction of one or more windows in the verification area; define a first step length independently of the width of the one or more windows in the first direction, the first step length being the distance between adjacent center points of the one or more windows in the first direction; define a second step length independently of the length of the one or more windows in the second direction, the second step length being the distance between adjacent center points of the one or more windows in the second direction; and extract information about the layout design in one or more windows at each of a plurality of window positions in the entire verification area; and a storage device comprising a database configured to store information about the layout design of one or more windows at each of a plurality of window positions.

[0006] On the other hand, the present application relates to a non-transitory computer-readable medium, which includes instructions stored thereon for simulating topological features of a layout design in a verification area, and the instructions, when executed by one or more processors, cause the one or more processors to perform the following operations: define a width of one or more windows in the verification area in a first direction and a length in a second direction; define a first step length independently of the width of the one or more windows in the first direction, the first step length being the distance between adjacent center points of the one or more windows in the first direction; define a second step length independently of the length of the one or more windows in the second direction, the second step length being the distance between adjacent center points of the one or more windows in the second direction; extract information about the layout design in one or more windows at each of multiple window positions in the entire verification area; and store information about the layout design of one or more windows at each of the multiple window positions in a database. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a simulator according to an embodiment of the present disclosure.

[0008] Figure 2 Schematic diagram of a verification area Va of a simulator according to an embodiment of the present disclosure.

[0009] Figure 3A Schematic diagram of the line patterns designed for the example layout.

[0010] Figures 3B to 3E To cover the windows of different sizes according to the embodiment of the present disclosure Figure 3A Schematic diagram of the verification area Va of the line pattern.

[0011] Figure 4 Schematic diagram of the verification area Va according to an embodiment of the present disclosure.

[0012] Figures 5A to 5C Schematic diagram of the verification area Va according to an embodiment of the present disclosure.

[0013] Figures 6A to 6C Schematic diagram of the verification area Va according to an embodiment of the present disclosure.

[0014] Figures 7A to 7C Schematic diagram of the verification area Va according to an embodiment of the present disclosure.

[0015] Figure 8 is a flowchart of a computer-implemented method including a simulation process according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which, by way of illustration, show specific aspects and embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0017] Figure 1 FIG2 is a block diagram of a simulator 102 according to an embodiment of the present disclosure. The simulator 102 includes a processor 104, a storage device 106, and a memory 108. The simulator 102 may further include a bus 110 that transmits information, including communications between devices in the simulator 102, such as the processor 104, the storage device 106, and the memory 108.

[0018] Simulator 102 can receive information about layout design 116. As input data, information about layout design 116 can include, for example, circuit layouts, rules for lines and layers in semiconductor devices formed on a wafer. Input data can be provided online or offline. In some embodiments, layout design 116 can be provided as a file in a streaming format. When receiving input data online, simulator 102 can further include a transmitter-receiver that communicates, including transmitting and receiving data, via a network (e.g., the Internet), wired communications (e.g., a universal serial bus, an Ethernet cable, etc.), a wireless fidelity (Wi-Fi) network, a cellular network, or the like. Alternatively, simulator 102 can include a media drive that can receive input data from media installed in a media drive. Input data can be provided to processor 104 via bus 110. In some embodiments, processor 104 can be a central processing unit (CPU) that performs various calculations and controls. Furthermore, if simulator 102 includes a graphics processing unit (GPU), then a portion of the various calculations and controls can be performed by the GPU. Simulator 102 can be implemented as a computer, such as a network computer such as a server, a personal computer, or a dedicated computer. Simulator 102 can be used by processor 104 to appropriately perform various information processing to simulate the shape of a wafer surface after a chemical mechanical polishing (CMP) process based on a layout design (e.g., a layout design of a semiconductor device). For example, simulator 102 can simulate the topological characteristics of the wafer surface shape, which may include the height between the highest and lowest points on the surface. To perform information processing, processor 104 can temporarily store data in memory 108 and obtain processing results using information about the layout design and the physical and chemical characteristics of the CMP process. After obtaining the processing results including the topological characteristics, processor 104 can store the processing results in storage device 106.

[0019] The storage device 106 can serve as a storage medium for storing various information. The configuration of the storage device 106 is not particularly limited. In some embodiments, the storage device 106 can store, for example, a program 114 run by the processor 104 and a database 112 that stores processing results in a meaningful manner for future use. In some embodiments, the program 114 and / or the database 112 can be in the form of one or more files. The files can be in binary format or text format. In some embodiments, a separate storage device or separate area in each device can be provided for the program 114 and the database 112. For example, the storage device 106 can include a hard disk drive (HDD) and a solid-state drive (SSD). The processor 104 in the simulator 102 can perform the various processes described above according to the various control programs (e.g., wafer surface topology simulation program) stored in the storage device 106.

[0020] Figure 2 FIG2 is a schematic diagram of a verification area Va 202 of a simulator according to an embodiment of the present disclosure. Information about the layout design covered by the verification area Va can be obtained using one or more windows 208. The one or more windows 208 can have a size that can be defined by the simulator 102. For example, once the simulator 102 receives information about a layout design (e.g., layout design 116), the processor 104 in the simulator 102 can define the size of the window 208 in the verification area Va 202 based on the layout design. The processor 104 of the simulator 102 can perform a simulation process on the layout design. A window 208 is an area unit in the verification area Va 202 that the simulator 102 can use to extract information about a portion of the layout design, including circuit layout, line, and layer rules. In some embodiments, the window size can be defined as the width Wx of the window 208 in one direction (e.g., the X direction 204) and the height Wy of the window 208 in another direction (e.g., the Y direction 206). In some embodiments, the X direction 204 and the Y direction 206 can be perpendicular to each other. In some embodiments, the width Wx and height Wy of the window 208 may be equal (Wx=Wy). In some embodiments, the width Wx and height Wy of the window 208 may be different (Wx≠Wy).

[0021] Information about the layout design can be extracted for the entire verification area Va 202 using one or more windows 208. The one or more windows 208 cover the verification area Va 202. For example, in some embodiments, the one or more windows are moved across the verification area Va. Information about the layout design can be obtained at each position of the one or more windows 208 in the verification area Va. The one or more windows can be moved by a step size that is smaller than the window size (e.g., smaller than the width Wx) in one direction (e.g., X direction 204) and / or smaller than the height Wy of the window 208 in another direction (e.g., Y direction 206). Extraction of information about the layout design from each window 208 can be performed in one direction (e.g., X direction 204) and then in another direction (e.g., Y direction 206). The number of one or more windows 208 in one direction (e.g., X direction 204) is greater than the width of the verification area Va divided by the width Wx of each window. The number of one or more windows 208 in another direction (e.g., Y direction 206) is greater than the length of the verification area Va divided by the length Wy of each window. In some embodiments, the first window 208 and the last window 208 may be at the ends of the diagonal line of the verification area Va 202.

[0022] In some embodiments, the window size may be carefully defined for the layout design in the wafer 200 on which the simulation process is performed. Figure 3ASchematic diagram of an example pattern of lines designed for an example layout. Region 302 includes lines, each of which has a line width Lw(a). Region 302 may include a line spacing Ls(a) between adjacent lines in region 302. Region 304 includes lines, each of which has a line width Lw(b). Region 304 may include a line spacing Ls(b) between adjacent lines in region 304. Figure 3A In the example of , line width Lw(a) and line spacing Ls(a) are the same (Lw(a)=Ls(a)), and line width Lw(b) and line spacing Ls(b) are the same (Lw(b)=Ls(b)). In this example, line width Lw(b) is half of line width Lw(a), (Lw(b)=Lw(a) / 2), and line spacing Ls(b) is approximately half of line spacing Ls(a), (Ls(b)=Ls(a) / 2). Verification area Va can cover lines of areas 302 and 304.

[0023] As previously described, the size of the window of the verification area Va may be based on the layout design. Figures 3B to 3E To cover the windows of different sizes according to the embodiment of the present disclosure Figure 3A Schematic diagram of verification areas Va 306, 308, 310 and 312 of a pattern of lines.

[0024] Figure 3B Verification region Va 306 includes windows where the width Wx of each window is approximately half the line width of the lines in region 302 (e.g., Wx = Lw(a) / 2 = Ls(a) / 2 = Lw(b) = Ls(b)) (e.g., "Case I"). Here, the density of one or more patterns in each window (e.g., pattern density D) may be 100% or 0%. Even if such a change exists, the pattern density from this case may not provide a gradual change in pattern density. Furthermore, it may not be possible to extract the line width or line spacing by analyzing each window separately because the width Wx of each window is less than the line width Lw(a) and the line spacing Ls(a). Therefore, the width Wx in Case I may be too small and may not be applicable to verification region 306.

[0025] Figure 3CThe verification area Va 308 includes windows, wherein the width Wx of each window is approximately the line width or line spacing of the lines in the area 302 (e.g., Wx = Lw(a) = Ls(a) = Lw(b) + Ls(b)) (e.g., "Case II"). Here, in the area 302, the pattern density of each window may be 100% or 0%. On the other hand, in the area 304, the pattern density of each window may be between 100% and 0%, for example 50%. Therefore, more changes in pattern density can be obtained. However, because the line width or line spacing in the area 302 may be greater than the window width Wx, it may not be possible to extract the line width Lw(a) or line spacing Ls(a) in the area 302 by analyzing each window separately. In addition, since the sum of the line width Lw(b) and the line spacing Ls(b) is equal to the width Wx of each window, it may not be possible to extract the line width Lw(b) and the line spacing Ls(b). Similarly, Figure 3D The verification area Va 310 includes windows, where the width Wx of each window is approximately the sum of the line width and the line spacing of the lines in the area 302 (e.g., Wx = Lw(a) + Ls(a)) (e.g., "Case III"), and the line width Lw(a) and the line spacing Ls(a) may not be extracted.

[0026] Figure 3E Verification region Va 312 includes windows where each window has a width Wx of approximately one and a half times the sum of the line width and line spacing of the lines in region 302 (e.g., Wx = Lw(a) + Ls(a) + Lw(a) / 2) (e.g., "Case IV"). Here, in regions 302 and 304, some windows may have a pattern density of 60%, and other windows may have another pattern density of 40%. Thus, more variation in pattern density is available. The line spacing Ls(a) can be obtained from the leftmost window in region 302, and the line width Lw(a) can be obtained from the rightmost window in region 302. The line width Lw(b) and the line spacing Ls(b) can be obtained from any window in region 304.

[0027] The above combinations of line patterns, windows, areas 302 and 304, and verification areas Va 306, 308, 310, and 312 are merely examples. In general, a relatively large window size (e.g., window width Wx and window height Wy) is likely to help accurately extract size information, such as line width Lw and line spacing Ls in the X direction (e.g., X direction 204), line length Lg in the Y direction (e.g., Y direction 206), and perimeter P of one or more patterns in each window.

[0028] Figure 4FIG4 is a schematic diagram of a verification area Va 402 according to an embodiment of the present disclosure. After defining the window size, the processor 104 in the simulator 102 may define the window step size in multiple directions (e.g., X direction 404 and Y direction 406). In some embodiments, the window step size S x and S y The corresponding stepping directions (e.g., X direction 404 and Y direction 406) of each window 408 (e.g., window 208) in the verification area Va 402 can be defined separately. In some embodiments, the window step sizes Sx and Sy can be defined independently of the window width Wx and length Wy. In some embodiments, the window step size Sx of the window 408 in the X direction 404 and the window step size Sy of the window 408 in the Y direction 406 can be equal (Sx=Sy). In some embodiments, the window step sizes Sx and Sy of the window 408 can be different (Sx≠Sy).

[0029] Figures 5A to 5C , 6A to 6C and 7A to 7C are schematic diagrams of the verification area Va 402 according to an embodiment of the present disclosure. Figures 5A to 5C 、 Figures 6A to 6C and Figures 7A to 7C Different window steps Sx and Sy that may be defined by processor 104 for window 408 are shown. Each position of window 408 may be identified by a center point 410. Center point 410 of window 408 may be represented by coordinates (Cx, Cy) in X-direction 404 and Y-direction 406.

[0030] In some embodiments, Figures 5A to 5C The verification area Va 402 has a window step Sx, which is the distance between the center points 410 of adjacent windows 408 in the X direction 404. That is, the window step Sx may be equal to the width Wx of the window 408.

[0031] In some embodiments, information of the window 408 may be extracted in a sequential order. Information about the layout design includes, for example, topological parameters. Examples of topological parameters include size-related topological parameters and other types of topological parameters. Examples of size-related topological parameters include line width Lw, line spacing Ls, line length Lg, and perimeter. An example of another type of topological parameter is density, such as pattern density D, perimeter density Pd, etc. After extracting the information, the window 408 may be moved by at least one of the first and second step sizes to a plurality of window positions in the verification area. Figure 5A, after extracting information in a window 408 (e.g., window 408 (5-1)) on the left side of the verification area Va 402, the window 408 is moved by a window step Sx, which is a width Wx in the X direction 404, to reach the next window 408 (e.g., window 408 (5-2)). After extracting information of window 408 (5-2), the window 408 may be moved again by the window step Sx in the X direction 404 in the verification area Va 402, which causes another window 408 to reach the right side of the verification area Va 402 (e.g., window 408 (5-3)). After extracting information about the layout design of the window 408 (5-3) at the right side of the verification area Va 402, as shown in FIG. Figure 5B Information on the layout design of three adjacent windows 408 in the X direction 404 in the verification area Va 402 shown in FIG has been extracted.

[0032] After extracting information about the layout design of the windows 408 (5-1)-408 (5-3) in the X direction, the window 408 may be moved in the Y direction. In some embodiments, the window 408 may be moved to the left of the verification area Va 402 and also moved in the Y direction 406 by a window step size Sy, which is a height Wy in the Y direction 404 (e.g., Figure 5C After extracting information about the layout design of the window 408 (5-4) at the upper left of the verification area Va 402, the window 408 (e.g., the window 408 (5-5)) may be moved in the X direction. The extraction of information and the movement of the window 408 in the X direction are repeated until the window 408 (5-4) is displayed. Figure 5C As shown in FIG, the process reaches the right side of the verification area 402 (eg, window 408 (5-6)).

[0033] In some embodiments, the order in which the windows 408 in the verification area Va 402 are moved is different from the previously described examples. For example, the window 408 may be moved in the Y direction 406 by a window step size Sy, which is a height Wy in the Y direction 404, to reach the window 408 (e.g., window 408 (5-6)) along the right side of the verification area Va 402. Figure 5C After extracting information about the layout design of window 408 (5-6) at the upper right of verification area Va 402 shown in FIG, window 408 may be moved in a direction opposite to the X direction (e.g., window 408 (5-5)), and the extraction of information and the movement of window 408 in the direction opposite to the X direction are repeated until the left side of the verification area 402 is reached (e.g., window 408 (5-4)).

[0034] In other embodiments, multiple windows 408 may be used to extract information about the layout design from the verification area Va. For example, in some embodiments, information may be extracted simultaneously from multiple windows 408 in a row (e.g., windows 408(5-1)-408(5-3)), and the multiple windows 408 may be moved in the Y direction. Alternatively, information may be extracted simultaneously from multiple windows 408 in a column, and the windows 408 may be moved in the X direction. Alternatively, information may be extracted from all windows 408 simultaneously.

[0035] By moving the window 408 in the verification area Va 402 by a window step size Sy, which is equal to the height Wy of the window 408 in the Y direction 406, information about the layout design contained in the verification area Va can be extracted, such as Figure 5C As shown. The distance between the center points 410 of two adjacent windows 408 in the Y direction 404 may be equal to the height Wy of the window 408. Therefore, the number of center points 410 in the verification area Va 402 is equal to the number of different positions of the window 408 in the verification area Va 402, which is Figures 5A to 5C In the example of , it can be six.

[0036] A database (eg, database 112) may store the extracted information for each window 408 in conjunction with the coordinates (Cx, Cy) of the center point 410 of the window 408. Figures 5A to 5C In the example of FIG4 , the number of entries stored in the database in connection with the coordinates (Cx, Cy) of the center point 410 may be six. In some embodiments, the topological characteristics of the shape of the surface of the verification area (e.g., the height between the highest position and the lowest position of the surface) may be calculated based on the extracted information about the layout design of the one or more windows 408.

[0037] In some embodiments, the window step Sx in the X direction 404 may be configured to be smaller than the width Wx of the window 408 in the X direction 404 , and the window step Sy in the Y direction 406 may be configured to be smaller than the height Wy of the window 408 in the Y direction 406 .

[0038] For example, Figures 6A to 6C The window step Sx of the verification area Va 402 is equal to half the width (= 1 / 2Wx) of the window 408 between adjacent windows 408 in the X direction 404. In some embodiments, after the information about the layout design can be extracted for the window 408 (6-1), Figure 6AThe window 408 on the left side of the verification area Va 402 in FIG. 4 (e.g., window 408 (6-1)) can be moved in the X direction 404 by a window step size Sx equal to half the width (= 1 / 2Wx) of the window 408 to reach the next window 408 (e.g., window 408 (6-2)). Before moving, the center point 410 of the next window 408 (6-2) can be on the right side of the previous window 408 (6-1). The extraction of information and the movement of the window 408 in the X direction are repeated until the right side of the verification area 402 is reached (e.g., window 408 (6-5)). After extracting information about the layout design of the window 408 (6-5) at the right side of the verification area Va 402, as shown in FIG. Figure 6B Information on the layout design of five adjacent windows 408 ( 6 - 1 ) to 408 ( 6 - 5 ) in the X direction 404 in the verification area Va 402 shown in FIG has been extracted.

[0039] After extracting information about the layout design of the window 408 in the X direction, the window 408 may be moved in the Y direction. In some embodiments, the window 408 may be moved to the left side of the verification area Va 402 and also moved in the Y direction 406 by a window step size Sy that is half the height (= 1 / 2Wy) in the Y direction 404 (e.g., Figure 6C After extracting information about the layout design of the window 408 (6-6) on the left side of the verification area Va 402, the window 408 may be moved in the X direction. The extraction of information and the movement of the window 408 in the X and Y directions are repeated until the window 408 (6-6) is displayed. Figure 6C As shown in FIG, the verification process continues until the upper right corner of the verification area 402 is reached (eg, window 408 (6-15)).

[0040] In some embodiments, the window 408 may be moved in the Y direction 406 by a window step size Sy that is half the height (= 1 / 2Wy) in the Y direction 404 to reach the next window (e.g., window 408 (6-10)) along the right side of the verification area Va 402. After extracting information about the layout design of the next window 408, the window 408 (6-10) may be moved in a direction opposite to the X direction ("reverse X direction") by half the width (= 1 / 2Wx). The extraction of information and the movement of the window 408 in the reverse X direction by half the width (= 1 / 2Wx) are repeated until the left side of the verification area 402 is reached. The extraction of information and the movement of the window 408 in the X direction or the reverse X direction and the Y direction are repeated in an alternating manner until, as shown in FIG. Figure 6C As shown in , it reaches the upper right corner of the verification area 402.

[0041] In other embodiments, information may be extracted from windows 408 in a row simultaneously, and the windows 408 may be moved in the Y direction. In some embodiments, information may be extracted from windows 408 in a column simultaneously, and the windows 408 may be moved in the X direction. Alternatively, information may be extracted from all windows 408 simultaneously.

[0042] By moving the window 408 in the verification area Va 402 by a window step size Sy, which is equal to half the height of the window 408 in the Y direction 406 (= 1 / 2Wy), information about the layout design included in the verification area Va can be extracted, such as Figure 6C As shown. The distance between adjacent center points 410 of two adjacent window positions of the window 408 in the Y direction 404 can be equal to half the height of the window 408 (= 1 / 2Wy). Therefore, the number of center points 410 in the verification area Va 402 is equal to the number of windows 408 in the verification area Va 402. Figures 6A to 6C In the example of , it can be fifteen. Figures 5A to 5C Compared with the example, Figures 6A to 6C The number of center points 410 in the example is greater.

[0043] A database (eg, database 112) may store the calculated topology information for each window 408 in conjunction with the coordinates (Cx, Cy) of the center point 410 of the window 408. Figures 6A to 6C For example, the number of entries stored in the database in connection with the coordinates (Cx, Cy) of the center point 410 may be fifteen. In some embodiments, the topological characteristics of the shape of the surface of the verification area (e.g., the height between the highest position and the lowest position of the surface) may be calculated based on the extracted information about the layout design of the one or more windows 408.

[0044] In some embodiments, Figures 7A to 7C The window step Sx of the verification area Va 402 is equal to 20% width (=1 / 5Wx) of the window 408 between adjacent windows 408 in the X direction 404. In some embodiments, after the information about the layout design can be extracted for the window 408 (7-1), Figure 7AThe window 408 on the left side of the verification area Va 402 in FIG. 4 (e.g., window 408 (7-1)) can be moved in the X direction 404 by a window step Sx equal to 20% of the width (= 1 / 5Wx) of the window 408 to reach the next window 408 (e.g., window 408 (7-2)). Before moving, the center point 410 of the next window 408 (7-2) can be to the right of the center point 410 of the previous window 408 (7-1). Repeat the extraction of information and moving the window 408 in the X direction by 20% of the width (= 1 / 5Wx) until the right side of the verification area 402 is reached (e.g., window 408 (7-11)). After extracting information about the layout design of the window 408 at the right side of the verification area Va 402, the following information can be extracted: Figure 7B 4 shows information on the layout design of eleven adjacent windows 408 ( 7 - 1 ) to 408 ( 7 - 11 ) in the X direction 404 in the verification area Va 402 .

[0045] After extracting information about the layout design of the window 408 in the X direction, the window 408 may be moved in the Y direction. In some embodiments, the window 408 may be moved to the left side of the verification area Va 402 and also moved in the Y direction 406 by a window step size Sy that is 20% height (=1 / 5 Wy) in the Y direction 404 (e.g., Figure 7C After extracting information about the layout design of the window 408 (7-12) on the left side of the verification area Va 402, the window 408 may be moved in the X direction by 20% width (= 1 / 5 Wx). The extraction of information and the movement of the window 408 in the X and Y directions are repeated until the window 408 (7-12) on the left side of the verification area Va 402 is as shown in FIG. Figure 7C As shown in FIG, the verification process continues until the upper right corner of the verification area 402 is reached (eg, window 408 (7-66)).

[0046] In some embodiments, the window 408 may be moved in the Y direction 406 by a window step size Sy that is 20% of the height (=1 / 5 Wy) in the Y direction 404 to reach the next window (e.g., window 408 (7-22)) along the right side of the verification area Va 402. After extracting information about the layout design of the next window 408, the window 408 may be moved in the reverse X direction by 20% of the width (=1 / 5 Wx). The extraction of information and the movement of the window 408 in the reverse X direction by 20% of the width (=1 / 5 Wx) are repeated until the left side of the verification area 402 is reached. The extraction of information and the movement of the window 408 in the X direction or the reverse X direction and the Y direction are repeated in an alternating manner until the verification area 402 is reached. Figure 7C As shown in , it reaches the upper right corner of the verification area 402.

[0047] In other embodiments, information may be extracted from windows 408 in a row simultaneously, and the windows 408 may be moved in the Y direction. In some embodiments, information may be extracted from windows 408 in a column simultaneously, and the windows 408 may be moved in the X direction. Alternatively, information may be extracted from all windows 408 simultaneously.

[0048] By moving the window 408 in the verification area Va 402 by a window step size Sy, which is equal to 20% of the height of the window 408 in the Y direction 406 (= 1 / 5Wy), information about the layout design contained in the verification area Va can be extracted, such as Figure 7C As shown. The distance between adjacent center points 410 of two adjacent window positions of the window 408 in the Y direction 404 may be equal to 20% of the height of the window 408 (= 1 / 5 Wy). Therefore, the number of center points 410 in the verification area Va 402 is equal to the number of windows 408 in the verification area Va 402, which is equal to the number of windows 408 in the verification area Va 402. Figures 7A to 7C In the example of , it can be sixty-six (=eleven times six), that is, greater than fifteen. Figures 6A to 6C Compared with the example, Figures 7A to 7C The number of center points 410 in the example is greater.

[0049] A database (eg, database 112) may store the calculated topology information for each window 408 in conjunction with the coordinates (Cx, Cy) of the center point 410 of the window 408. Figures 7A to 7C For example, the number of entries stored in the database in connection with the coordinates (Cx, Cy) of the center point 410 may be fifty-five. In some embodiments, the topological characteristics of the shape of the surface of the verification area (e.g., the height between the highest position and the lowest position of the surface) may be calculated based on the extracted information about the layout design of the one or more windows 408.

[0050] like Figures 5A to 7C As shown in FIG, by providing a smaller window step size, changes in topological parameters over the window, such as pattern density D and the density of perimeters of one or more patterns in each window (perimeter density Pd), can be obtained at a higher resolution without sacrificing the advantage of having a larger window size for accurate extraction of some other topological parameters, such as line width Lw, line spacing Ls and line length Lg.

[0051] Figure 8FIG5 is a flow chart 500 of a computer-implemented method including a simulation process according to an embodiment of the present disclosure. Once the simulation process begins (S502), the simulator 102 may receive information about the layout design 116 as input data (S504). In some embodiments, the simulator 102 may receive a file in a stream format containing information about the layout design 116 to be implemented on a wafer. The file containing information about the layout design 116 may be as previously described with reference to FIG5. Figure 1 The mentioned are available online or offline.

[0052] The processor 104 of the simulator 102 may define the size of one or more windows in the verification area Va on the wafer where the simulation process is to be performed (S506). For example, the size of the one or more windows may be defined as the width Wx of the one or more windows in one direction (e.g., the X direction 204 or the X direction 404) and the height Wy of the one or more windows in another direction (e.g., the Y direction 206 or the Y direction 406). The size of the one or more windows may be selected based on the layout design 116 to facilitate reasonably accurate extraction of size-related topological parameters (e.g., line width Lw, line spacing Ls, line length Lg, and perimeter P). For example, the width Wx of the one or more windows may be defined to be greater than the sum of the maximum line width Lw and the maximum line spacing Ls in the layout design (e.g., the layout design 116).

[0053] The processor 104 of the simulator 102 may define a window step size for one or more windows in the verification area Va in which the simulation process is to be performed (S508). The window step sizes Sx and Sy of the one or more windows may be defined independently of the size of the one or more windows, such as the width Wx of the one or more windows in one direction (e.g., the X direction 204 or the X direction 404) and the height Wy of the one or more windows in another direction (e.g., the Y direction 206 or the Y direction 406). For example, the window step size Sx of the one or more windows may be defined to be smaller than the width Wx, and the window step size Sy of the one or more windows may be defined to be smaller than the height Wy. Therefore, by defining the window step sizes Sx and Sy smaller than the width Wx and height Wy of the one or more windows, the pattern density D and the perimeter density Pd on the windows can be obtained at a higher resolution (e.g., S510).

[0054] Once the window size and window step are defined, the processor 104 of the simulator 102 may extract information about the layout design 116, such as topology parameters, for each window (S510). The extracted topology parameters may include size-related topology parameters (e.g., line width Lw, line spacing Ls, line length Lg, and perimeter P) and other topology parameters (e.g., pattern density D and perimeter density Pd).

[0055] After extracting topology parameters from each window position in the verification area Va (e.g., for each center point 410), the extracted topology parameters may be stored in the database 112 (S512). In some embodiments, the topology parameters for each window position may be stored in conjunction with the coordinates of the center of each window (e.g., center point 410). In some embodiments, for multiple windows, the processor 104 may extract topology parameters and temporarily store them in the memory 108 (S510). The processor 104 may later move the temporarily stored topology parameters in batches to the storage device 106 in conjunction with the coordinates of the centers of the multiple windows in the database 112 (S512). In other embodiments, the processor 104 may temporarily extract and store the topology parameters for each window position in the memory 108 during the topology parameter extraction process, and then immediately store the topology parameters for each window position in the database 112 in conjunction with the coordinates of the center of each window (S512). In such embodiments, the sequence of S510 and S511 is repeated for each of the multiple window positions. The database 112 may be stored in the storage device 106 as one or more files. The one or more files may be in binary or text format. The database 112 may be used by a user to perform various analyses. For example, the database 112 may be used to improve a CMP process.

[0056] As described above, the step size of each window in each direction can be defined independently of the size of the window, such as the window width and window height. By flexibly defining the window step size in the corresponding dimension, changes in pattern density can be simulated at a resolution that is reasonably higher than the resolution produced by a fixed window step size for the window width or window height. Because simulations can be performed without having a resolution constrained by the window size, the flexible definition of the window step size can provide more accurate simulation results. Although high-resolution density changes are obtained with a smaller window step size, a relatively large window size defined by the width and height of each window can be maintained. Therefore, the advantages of accurately extracting line width, line spacing, line length, perimeter, etc. with a relatively large window can be maintained.

[0057] The above simulation process with flexible resolution achieved through flexible window step size can be applied to simulating the manufacturing process of metal or non-metal components in a semiconductor layout design using a CMP simulator, such as extracting topological parameters and calculating topological features. Furthermore, the above simulation process with flexible resolution of the layout design can be applied to the calculation of physical contact polishing, without necessarily involving the semiconductor layout design.

[0058] Although various embodiments have been disclosed in this disclosure, it will be understood by those skilled in the art that the scope of this disclosure extends beyond the specific disclosed embodiments to other alternative embodiments and / or uses and obvious modifications and equivalents thereof. In addition, based on this disclosure, other modifications within the scope of this disclosure will be apparent to those skilled in the art. It is contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may also be made and still fall within the scope of this disclosure. It will be understood that the various features and aspects of the disclosed embodiments may be combined with each other or substituted for each other to form variations of the disclosed embodiments. Therefore, it is contemplated that the scope of at least some of the present disclosure should not be limited by the specific disclosed embodiments described above.

Claims

1. A computer-implemented method for simulating topological features of a layout design, the method comprising: receiving information about the layout design in a verification area, the information about the layout design comprising one or more topological parameters; defining a width of one or more windows in the verification area in a first direction and a length in a second direction; defining a first step length independently of the width of the one or more windows in the first direction, the first step length being a distance between adjacent center points of the one or more windows in the first direction; defining a second step length independently of the length of the one or more windows in the second direction, the second step length being a distance between adjacent center points of the one or more windows in the second direction; extracting information about the layout design in the one or more windows at each of a plurality of window positions throughout the verification area; as well as The information about the layout design of the one or more windows at each of the plurality of window positions is stored in a database.

2. The computer-implemented method of claim 1 , wherein the extracted information about the layout design of the one or more windows at each of the plurality of window positions comprises at least one of: the line width of at least one line in each window; the line length of at least one line in each window; a line spacing of at least one line spacing between adjacent lines in each window; the density of one or more patterns in each window; the perimeter of the one or more patterns in each window; or The density of the perimeters in each window.

3. The computer-implemented method of claim 1 , further comprising: The one or more windows are moved by at least one of the first and second step sizes to a plurality of window positions in the verification area.

4. The computer-implemented method of claim 1 , wherein the extracted information about the layout design of the one or more windows at each of the plurality of window positions is stored in the database in conjunction with coordinates of a center point of each window at each of the plurality of window positions.

5. The computer-implemented method according to claim 4 further comprises simulating at least one height between the highest position and the lowest position of the surface in the verification area as a topological feature based on the extracted information of multiple windows in the verification area stored in the database.

6. The computer-implemented method of claim 1 , wherein defining the first step length independently of the width comprises defining the first step length different from the width, and Wherein defining the second step size independently of the length comprises defining the second step size different from the length. The computer-implemented method of claim 6 , wherein the first step length is smaller than the width. The computer-implemented method of claim 6 , wherein the second step size is smaller than the length.

9. The computer-implemented method of claim 1, wherein the one or more windows are configured to cover the verification area.

10. The computer-implemented method of claim 2, wherein the number of the one or more windows in the first direction is greater than the number obtained by dividing the width of the verification area by the width of each window, and The number of the one or more windows in the second direction is greater than a number obtained by dividing the length of the verification area by the length of each window. The computer-implemented method of claim 1 , wherein the width and the length are defined in response to the layout design. 12 . The computer-implemented method of claim 11 , wherein the width is greater than a sum of a maximum line width of at least one line in the window and a maximum line spacing of at least one line spacing between two adjacent lines in the window.

13. A device for simulating topological characteristics of a layout design, the device comprising: an input device configured to receive information about the layout design in the verification area; One or more processors configured to: defining a width of one or more windows in the verification area in a first direction and a length in a second direction; defining a first step length independently of the width of the one or more windows in the first direction, the first step length being a distance between adjacent center points of the one or more windows in the first direction; defining a second step length independently of the length of the one or more windows in the second direction, the second step length being a distance between adjacent center points of the one or more windows in the second direction; as well as extracting information about the layout design in the one or more windows at each of a plurality of window positions throughout the verification area; as well as A storage device includes a database configured to store the information about the layout design of the one or more windows at each of the plurality of window positions.

14. The apparatus of claim 13 , wherein the extracted information about the layout design of the one or more windows at each of the plurality of window positions comprises at least one of: the line width of at least one line in each window; the line length of at least one line in each window; a line spacing of at least one line spacing between adjacent lines in each window; the density of one or more patterns in each window; the perimeter of the one or more patterns in each window; or The density of the perimeters in each window.

15. The apparatus of claim 13, wherein the one or more processors are further configured to move the one or more windows by at least one of the first and second step sizes to a plurality of window positions in the verification area.

16. The apparatus of claim 13, wherein the database is configured to store the extracted information about the layout design of the one or more windows at each of the plurality of window positions in conjunction with coordinates of a center point of each window at each of the plurality of window positions.

17. An apparatus according to claim 16, wherein the one or more processors are configured to simulate at least one height between the highest position and the lowest position of the surface in the verification area as a topological feature based on the extracted information of multiple windows in the verification area stored in the database.

18. The apparatus of claim 13, wherein the first step length is different from the width and the second step length is different from the length.

19. The apparatus of claim 18, wherein the first step length is less than the width and the second step length is less than the length.

20. The device of claim 13, wherein the one or more windows are configured to cover the verification area.

21. The apparatus of claim 20, wherein the number of the one or more windows in the first direction is greater than the number obtained by dividing the width of the verification area by the width of each window, and The number of the one or more windows in the first direction is greater than a number obtained by dividing the length of the verification area by the length of each window.

22. The apparatus of claim 13, wherein the one or more processors are configured to define the width and the length in response to the layout design. 23 . The apparatus of claim 22 , wherein the width is greater than a sum of a maximum line width of at least one line in the window and a maximum line spacing of at least one line spacing between two adjacent lines in the window.

24. A non-transitory computer-readable medium comprising instructions stored thereon for simulating topological features of a layout design in a verification region, the instructions, when executed by one or more processors, causing the one or more processors to: defining a width of one or more windows in the verification area in a first direction and a length in a second direction; defining a first step length independently of the width of the one or more windows in the first direction, the first step length being a distance between adjacent center points of the one or more windows in the first direction; defining a second step length independently of the length of the one or more windows in the second direction, the second step length being a distance between adjacent center points of the one or more windows in the second direction; extracting information about the layout design in the one or more windows at each of a plurality of window positions throughout the verification area; as well as The information about the layout design of the one or more windows at each of the plurality of window positions is stored in a database.

25. The non-transitory computer-readable medium of claim 24, wherein the extracted information about the layout design of the one or more windows at each of the plurality of window positions comprises at least one of: the line width of at least one line in each window; the line length of at least one line in each window; a line spacing of at least one line spacing between adjacent lines in each window; the density of one or more patterns in each window; the perimeter of the one or more patterns in each window; or The density of the perimeters in each window.

26. The non-transitory computer-readable medium of claim 24, wherein the extracted information about the layout design of each window of a plurality of windows is stored in the database in conjunction with coordinates of a center point of each window at each of the plurality of window positions.

27. The non-transitory computer-readable medium of claim 26, further comprising simulating at least one height between a highest position and a lowest position of a surface in the verification area as a topological feature based on the extracted information of the multiple windows in the verification area stored in the database.

28. The non-transitory computer-readable medium of claim 24, wherein defining the first step length independently of the width comprises defining the first step length different from the width, and Wherein defining the second step size independently of the length comprises defining the second step size different from the length.

29. The non-transitory computer-readable medium of claim 28, wherein the first step length is less than the width.

30. The non-transitory computer-readable medium of claim 28, wherein the second step size is less than the length.

31. The non-transitory computer-readable medium of claim 24, wherein the one or more windows are configured to cover the authentication area.

32. The non-transitory computer-readable medium of claim 31 , wherein the number of the one or more windows in the first direction is greater than the number obtained by dividing the width of the verification area by the width of each window, and The number of the one or more windows in the first direction is greater than a number obtained by dividing the length of the verification area by the length of each window.

33. The non-transitory computer-readable medium of claim 24, wherein the width and the length are defined in response to the layout design.

34. The non-transitory computer-readable medium of claim 33, wherein the width is greater than the sum of a maximum line width of at least one line in the window and a maximum line spacing of at least one line spacing between two adjacent lines in the window.

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