Impedance adjustment method, device, core particle and storage medium

Abstract

The present invention discloses an impedance adjustment method, device, chip, and storage medium, relating to the field of chip technology, including: if it is determined that the main band channel is in a source-end negotiation state, a first verification signal is sent to the opposite-side chip through a transmitter and a source-end impedance module, so that the opposite-side chip generates a first quality evaluation result based on the first verification signal, and adjusts the impedance value of the source-end impedance module according to the first quality evaluation result; if it is determined that the main band channel is in a terminal negotiation state, a second verification signal sent by the opposite-side chip is received through a receiver and a terminal impedance module, and a second quality evaluation result is generated according to the second verification signal, so that the impedance value of the terminal impedance module is adjusted according to the second quality evaluation result. The technical solution of the embodiment of the present invention realizes dynamic matching of impedance values ​​in the chip interface, greatly improves the compatibility of the chip, and at the same time reduces the emission generated by the transmission signal, greatly improving the signal transmission quality of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an impedance adjustment method, device, core particle and storage medium. Background Art

[0002] Compared to the process limitations of traditional chips, chiplets, thanks to their advanced packaging technology, break through traditional process limitations and enable the integration of high-computing-power chips. To facilitate data transmission between multiple chiplets, a high-speed inter-chip interconnect interface is used.

[0003] The interface electrical parameters of existing chiplets are all fixed designs. Due to impedance mismatch, chiplets in different packaging methods cannot be applied to different packaging scenarios. For example, the CEI-112G-XSR serial interface is used for inter-chip interconnection. The usage scenario is inter-chip interconnection on the packaging substrate and is not suitable for interconnection on the silicon interposer. The AIB (Advanced Interface Bus) parallel interface is suitable for interconnection on the silicon interposer and is not suitable for packaging substrates or long-distance interconnection.

[0004] As a result, the compatibility of existing chiplets is poor, which greatly limits the applicable scenarios of each chiplet. At the same time, even for chiplets with the same packaging method, impedance mismatch may occur due to deviations during manufacturing, thereby increasing the reflection generated by the signal and seriously affecting the signal transmission quality. Summary of the Invention

[0005] The present invention provides an impedance adjustment method, device, core particle and storage medium to solve the problem of impedance mismatch of main band channels.

[0006] According to one aspect of the present invention, there is provided an impedance adjustment method applied to a chip, comprising:

[0007] In response to obtaining the power-on start signal, obtaining the working state of the main band channel to be adjusted;

[0008] If it is determined that the main band channel is in the source-end negotiation state, a first verification signal is sent to the opposite-side chiplet through the transmitter and the source-end impedance module, so that the opposite-side chiplet generates a first quality evaluation result based on the first verification signal, and adjusts the impedance value of the source-end impedance module according to the first quality evaluation result;

[0009] If it is determined that the main band channel is in the terminal negotiation state, the second verification signal sent by the opposite-side core particle is received through the receiver and the terminal impedance module, and a second quality evaluation result is generated according to the second verification signal, so as to adjust the impedance value of the terminal impedance module according to the second quality evaluation result.

[0010] According to one aspect of the present invention, an impedance adjustment device is provided, which is applied to a chip, comprising:

[0011] a channel status acquisition module, configured to acquire the operating status of the main band channel to be adjusted in response to acquiring the power-on start signal;

[0012] a verification signal sending module, configured to, if determining that the primary band channel is in the source-end negotiation state, send a first verification signal to the opposite-side chiplet via a transmitter and a source-end impedance module, so that the opposite-side chiplet generates a first quality evaluation result based on the first verification signal, and adjusts the impedance value of the source-end impedance module according to the first quality evaluation result;

[0013] An evaluation result generation module is used to receive a second verification signal sent by the opposite-side core particle through a receiver and a terminal impedance module if it is determined that the main band channel is in a terminal negotiation state, and generate a second quality evaluation result based on the second verification signal, so as to adjust the impedance value of the terminal impedance module according to the second quality evaluation result.

[0014] According to another aspect of the present invention, a core particle is provided, which includes a transmitter, a receiver and an impedance adjustment system; the impedance adjustment system includes a source impedance module, a terminal impedance module and a control module; the control module is used to execute the impedance adjustment method described in any embodiment of the present invention.

[0015] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the impedance adjustment method according to any embodiment of the present invention when executed.

[0016] The technical solution of the embodiment of the present invention is to send a first verification signal to the opposite-side chip through the transmitter and the source-end impedance module, so that the opposite-side chip generates a first quality evaluation result based on the first verification signal, and adjusts the impedance value of the source-end impedance module according to the first quality evaluation result; receive the second verification signal sent by the opposite-side chip through the receiver and the terminal impedance module, and generate a second quality evaluation result according to the second verification signal, so as to adjust the impedance value of the terminal impedance module according to the second quality evaluation result, thereby realizing dynamic matching of the impedance value in the chip interface, greatly improving the compatibility of the chip; at the same time, the dynamic matching of the impedance value also reduces the emission generated by the transmission signal, greatly improving the signal transmission quality of the chip.

[0017] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 2 is a schematic diagram of an application scenario of the impedance adjustment method provided in an embodiment of the present invention;

[0020] Figure 2 This is a flow chart of an impedance adjustment method provided according to the first embodiment of the present invention;

[0021] Figure 3 This is a flow chart of an impedance adjustment method provided according to the second embodiment of the present invention;

[0022] Figure 4 This is a flow chart of an impedance adjustment method provided according to a third embodiment of the present invention;

[0023] Figure 5 This is a schematic structural diagram of an impedance adjustment device provided according to a fourth embodiment of the present invention;

[0024] Figure 6 Schematic diagram of the structure of the core particle for implementing the impedance adjustment method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] An impedance adjustment method provided by an embodiment of the present invention can be applied to Figure 1 In the core particles shown, Figure 1 The control module in the device is implemented to adjust the impedance value of the source impedance module connected to the transmitter and the impedance value of the terminal impedance module connected to the receiver; wherein the interface of the core particle can be a parallel interface or a serial interface. In the embodiment of the present invention, the interface type of the core particle is not specifically limited; the core particle includes multiple interfaces, different interfaces can be connected to different core particles, and can also be connected to the same core particle; and each interface can correspond to multiple main band communication channels (i.e., main band channels). A main band channel corresponds to a transmitting circuit (i.e., a transmitter) and a receiving circuit (i.e., a receiver) in one interface, that is, a main band channel between two core particles is actually composed of two transmission lines. The main band channels are composed of a transmitter of the current chiplet and a receiver of the opposite chiplet, and a receiver of the current chiplet and a transmitter of the opposite chiplet. For example, one interface may correspond to 64 main band channels, and the interface may be composed of 64 transmitters and 64 receivers. In particular, each main band channel in one interface may be connected to the same chiplet or to different chiplets. In the embodiment of the present invention, there is no specific limitation on the number of interfaces and main band channels of the chiplet. In particular, the main band channel in the embodiment of the present invention may be used to transmit a clock signal, i.e., a clock signal channel, and may also be used to transmit a data signal, i.e., a data signal channel.

[0028] The source-end impedance module is connected to the transmitter and is a combination circuit composed of one or more devices among resistors, capacitors and inductors. The number of source-end impedance modules matches the number of transmitters, and each transmitter corresponds to a source-end impedance module; the source-end impedance module and the transmitter can be connected in parallel termination, series termination, Thevenin termination or RC (Resistor-Capacitance circuit, resistor-capacitor) termination. The terminal impedance module is connected to the receiver and is a combination circuit composed of one or more devices among resistors, capacitors and inductors. The number of terminal impedance modules matches the number of receivers, and each receiver corresponds to a terminal impedance module; similarly, the source-end impedance module and the transmitter can also be connected in parallel termination, series termination, Thevenin termination or RC termination. In particular, the terminal impedance module can be connected to the receiver as an independent device, or it can be configured inside the receiver and serve as a part of the receiver; the source impedance module can be connected to the transmitter as an independent device, or it can be configured inside the transmitter and serve as a part of the transmitter; in the embodiment of the present invention, there is no specific limitation on the connection method between the terminal impedance module and the receiver, and there is no specific limitation on the connection method between the source impedance module and the transmitter.

[0029] In an embodiment of the present invention, a control module can be configured for each interface of the core particle, that is, each source impedance module and terminal impedance module in an interface can be controlled by one control module. Alternatively, multiple control modules can be configured. For example, a control module can be configured for each main band channel, and this control module is only used to control the source impedance module and terminal impedance module of the current main band channel. Alternatively, a common control module can be configured for all interfaces, and this control module is used to control the impedance values ​​of the source impedance modules and terminal impedance modules in all interfaces. In an embodiment of the present invention, there is no specific limitation on the number of control modules in the core particle. Figure 1 For the sake of convenience, the opposite core particle adopts the same composition structure as the current core particle. In fact, in the embodiment of the present invention, the composition structure of the opposite core particle is not specifically limited.

[0030] Example 1

[0031] Figure 2 This is a flowchart of an impedance adjustment method provided in the first embodiment of the present invention. This embodiment is applicable to impedance adjustment of the main band channel connected to the chiplet interface. This method can be performed by the impedance adjustment device in the embodiment of the present invention. The impedance adjustment device can be implemented in the form of hardware and / or software and configured in the control module of the chiplet. Figure 2 As shown, the method includes:

[0032] S101 : In response to receiving a power-on start signal, obtaining an operating state of a main band channel to be adjusted.

[0033] The control module can perform corresponding impedance adjustment operations after the chip is powered on for the first time or each time it is powered on. After the chip is powered on, if it is detected that a transmitter of the current chip has been connected to the receiver of the opposite chip, it is determined that the main band channel where the transmitter is located is in the source negotiation state, that is, it is necessary to adjust the impedance value of the source impedance module to ensure the communication quality of the communication line where the transmitter is located. If it is detected that a receiver of the current chip has been connected to the transmitter of the opposite chip, it is determined that the main band channel where the receiver is located is in the terminal negotiation state, that is, it is necessary to adjust the impedance value of the terminal impedance module to ensure the communication quality of the communication line where the receiver is located. Obviously, when two chiplets are interconnected, data is often transmitted separately through the two transmission lines in each main band channel. Therefore, after the chip is powered on, it may be detected that a main band channel is in both the source negotiation state and the terminal negotiation state.

[0034] S102: If it is determined that the main band channel is in the source-end negotiation state, send a first verification signal to the opposite-side chiplet through the transmitter and the source-end impedance module, so that the opposite-side chiplet generates a first quality evaluation result based on the first verification signal, and adjusts the impedance value of the source-end impedance module according to the first quality evaluation result.

[0035] Specifically, Figure 1 For example, the control module in the chiplet sends the first verification signal generated by itself to the opposite chiplet through the transmitter and the source-end impedance module; wherein the verification signal can be generated based on a pseudo-random binary sequence (PRBS) or based on other methods. In the embodiment of the present invention, there is no specific limitation on the generation method of the first verification signal and the second verification signal; after the opposite chiplet obtains the above-mentioned first verification signal through the opposite terminal impedance module and the opposite receiver, it obtains the quality evaluation result of the first verification signal, that is, the first quality evaluation result; wherein the opposite chiplet can obtain the first quality evaluation result by obtaining eye diagram parameters such as eye width, eye height, overshoot, undershoot, eye amplitude and Q factor of the first verification signal, or by obtaining the bit error rate of the first verification signal.

[0036] In particular, one or more of the above-mentioned eye width, eye height, overshoot, undershoot, eye width, Q factor and bit error rate can be used as evaluation criteria for transmission quality. When the first quality evaluation result meets a specified number or all numbers of evaluation criteria, it is determined that the first quality evaluation result meets the expected result; the quality scores corresponding to one or more of the eye width, eye height, overshoot, undershoot, eye width, Q factor and bit error rate can also be multiplied by their respective corresponding weights, and the multiplication results are then summed, and the sum result is compared with the expected score to determine whether the first quality evaluation result meets the expected result.

[0037] If the opposite-side chip determines that the first quality evaluation result does not meet the expected result, it will adjust the impedance value of the opposite-side terminal impedance module and send an impedance adjustment instruction to the current chip through the sideband channel; after obtaining the impedance adjustment instruction, the control module adjusts the impedance value of the source-end impedance module, and after the impedance adjustment is completed, it sends a first verification signal to the opposite-side chip again through the sideband channel; the opposite-side chip obtains the first quality evaluation result again based on the first verification signal sent again, until the first quality evaluation result meets the expected result, it sends an adjustment completion instruction to the control module of the current chip through the sideband channel, the opposite-side chip will use the current impedance value of the opposite-side terminal impedance module as its working impedance value, and the current chip will use the current impedance value of the source-end impedance module as its working impedance value, thereby completing the impedance adjustment of the line where the transmitter is located in the main band channel.

[0038] S103: If it is determined that the main band channel is in the terminal negotiation state, receive a second verification signal sent by the opposite-side core particle through a receiver and a terminal impedance module, and generate a second quality evaluation result according to the second verification signal, so as to adjust the impedance value of the terminal impedance module according to the second quality evaluation result.

[0039] Specifically, still Figure 1 For example, the opposite-side control module in the opposite-side chiplet sends the second verification signal generated by it to the current chiplet through the opposite-side transmitter and the opposite-side source-end impedance module; the control module of the current chiplet obtains the above-mentioned second verification signal through the terminal impedance module and the receiver, and obtains the quality evaluation result of the second verification signal, that is, the second quality evaluation result; wherein, the current chiplet can also obtain the second quality evaluation result by obtaining evaluation criteria such as eye width, eye height, overshoot, undershoot, eye amplitude, Q factor and bit error rate of the second verification signal.

[0040] If it is determined that the second quality evaluation result does not meet the expected result, the impedance value of the terminal impedance module is adjusted, and an impedance adjustment instruction is sent to the opposite chip through the sideband channel; after obtaining the impedance adjustment instruction, the opposite chip adjusts the impedance value of the opposite source impedance module, and after the impedance adjustment is completed, a second verification signal is sent to the current chip again through the sideband channel; the control module obtains the second quality evaluation result again based on the second verification signal sent again, until the second quality evaluation result meets the expected result, and sends an adjustment completion instruction to the opposite chip through the sideband channel. The opposite chip will use the current impedance value of the opposite source impedance module as its working impedance value, and the current chip will use the current impedance value of the terminal impedance module as its working impedance value, thereby completing the impedance adjustment of the line where the receiver is located in the main band channel.

[0041] Optionally, in an embodiment of the present invention, before sending a first verification signal to the opposite-side chip through the transmitter and the source-end impedance module, it also includes: sending an impedance negotiation signal to the opposite-side chip through the sideband channel; before receiving a second verification signal sent by the opposite-side chip through the receiver and the terminal impedance module, it also includes: obtaining the impedance negotiation signal sent by the opposite-side chip through the sideband channel.

[0042] Specifically, after the chip is powered on and started, if it is detected that the transmitter of the current chip is already connected to the receiver of the opposite chip, it sends an impedance negotiation signal to the opposite chip through the sideband channel, and enters the negotiation state of the source end impedance, and also causes the opposite chip to enter the negotiation state of the opposite terminal impedance. In this way, without occupying the main band channel resources, it avoids the opposite chip from mistaking the verification signal for the working signal, thereby ensuring the impedance adjustment of the communication line where the transmitter is located; similarly, after the chip is powered on and started, if it is detected that the receiver of the current chip is already connected to the transmitter of the opposite chip, it waits for the opposite chip to send an impedance negotiation signal through the sideband channel, so that it enters the negotiation state of the terminal impedance. After sending the impedance negotiation signal, the opposite chip also enters the negotiation state of the opposite source end impedance. In this way, without occupying the main band channel resources, it avoids the verification signal from being misunderstood as the actual working signal, thereby ensuring the impedance adjustment of the communication line where the receiver is located.

[0043] The technical solution of the embodiment of the present invention is to send a first verification signal to the opposite-side chip through the transmitter and the source-end impedance module, so that the opposite-side chip generates a first quality evaluation result based on the first verification signal, and adjusts the impedance value of the source-end impedance module according to the first quality evaluation result; receive the second verification signal sent by the opposite-side chip through the receiver and the terminal impedance module, and generate a second quality evaluation result according to the second verification signal, so as to adjust the impedance value of the terminal impedance module according to the second quality evaluation result, thereby realizing dynamic matching of the impedance value in the chip interface, greatly improving the compatibility of the chip; at the same time, the dynamic matching of the impedance value also reduces the emission generated by the transmission signal, greatly improving the signal transmission quality of the chip.

[0044] Example 2

[0045] Figure 3 This is a flowchart of an impedance adjustment method provided in the first embodiment of the present invention. The relationship between this embodiment and the above embodiment is that different impedance adjustment operations are performed according to different second quality evaluation results. Figure 3 As shown, the method includes:

[0046] S201 : In response to receiving a power-on start signal, obtaining an operating state of a main band channel to be adjusted.

[0047] S202: If it is determined that the primary band channel is in the terminal negotiation state, receive a second verification signal sent by the opposite-side chiplet through a receiver and a terminal impedance module, and generate a second quality evaluation result according to the second verification signal.

[0048] S203: If it is determined that the second quality evaluation result does not meet the first expected result, send an impedance adjustment instruction to the opposite-side chiplet, so that the opposite-side chiplet adjusts the impedance value of the opposite-side source impedance module, and causes the opposite-side chiplet to send a second verification signal again after each adjustment is completed.

[0049] The second expected result is the quality evaluation result in which all evaluation indicators meet the expected standards. If the second quality evaluation result meets the second expected result, the current impedance value is the target impedance value to be obtained, that is, the impedance adjustment is completed, and the current impedance value is used as the impedance value during actual work; the first expected result is the quality evaluation result in which some evaluation indicators meet the expected standards, but at least one evaluation indicator does not meet the expected standards. At this time, based on the current impedance value, further accuracy adjustment of the impedance value is required to ensure that all evaluation indicators of the verification signal meet the expected standards when the impedance value adjustment is completed.

[0050] Specifically, first, when the current chip enters the terminal negotiation state, the impedance value of the terminal impedance module is set to the initial impedance value; wherein, the initial impedance value can be pre-set according to the experience value, for example, the initial impedance value is set to 25 ohms; then after obtaining the second verification signal sent by the opposite chip, based on the second verification signal, the quality evaluation result of the current second verification signal is obtained, that is, the second quality evaluation result; if the second quality evaluation result does not meet the first expected result, an impedance adjustment instruction is sent to the opposite chip, so that the opposite chip adjusts the impedance value of the opposite source end impedance module, and the opposite chip continues to send the second verification signal to the current chip after each adjustment is completed.

[0051] S204: If it is determined that the second quality evaluation result meets the first expected result but does not meet the second expected result, an impedance maintenance instruction is sent to the opposite-side chiplet to enable the opposite-side chiplet to maintain the impedance value of the opposite-side source impedance module unchanged, and adjust the impedance value of the terminal impedance module based on the adjustment step size, and after each adjustment is completed, a verification retransmission instruction is sent to the opposite-side chiplet to enable the opposite-side chiplet to send the second verification signal again.

[0052] If the second quality evaluation result meets the first expected result but does not meet the second expected result, it is necessary to keep the impedance value of the opposite chip unchanged, and continue to perform signal quality evaluation by adjusting the impedance value of the current chip. Thus, an impedance maintenance instruction is sent to the opposite chip through the sideband channel, so that the opposite chip keeps the impedance value of the opposite source impedance module unchanged. At the same time, the current chip adjusts the impedance value of the terminal impedance based on the adjustment step, and after each adjustment is completed, a verification retransmission instruction is sent to the opposite chip through the sideband channel, so that the opposite chip will send a second verification signal after each adjustment of the terminal impedance by the current chip. The adjustable range and adjustment step of the impedance value can be pre-set as needed. For example, the adjustable range of the impedance value can be set to 10 ohms to 50 ohms; the adjustment step of the impedance value can be set to 5 ohms.

[0053] S205. If it is determined that the second quality evaluation result meets the second expected result, the current impedance value of the terminal impedance module is used as the working impedance value, and an adjustment completion instruction is sent to the opposite-side chiplet, so that the opposite-side chiplet uses the current impedance value of the opposite-side source impedance module as the working impedance value.

[0054] If the second quality evaluation result meets the second expected result, the terminal impedance module of the current chip and the opposite source impedance module of the opposite chip have been adjusted. The impedance value of the terminal impedance module and the impedance value of the opposite source impedance module can be used as their respective working impedance values.

[0055] Optionally, in an embodiment of the present invention, after sending the impedance adjustment instruction to the opposite-side chip, it also includes: if it is determined that the opposite-side chip has traversed all impedance values ​​of the opposite-side source-end impedance module and the second quality evaluation result does not meet the first expected result, then adjusting the impedance value of the terminal impedance module based on the adjustment step, and sending the impedance adjustment instruction to the opposite-side chip again after the adjustment is completed; after sending the impedance maintenance instruction to the opposite-side chip, it also includes: if it is determined that all impedance values ​​of the terminal impedance module have been traversed and the second quality evaluation result does not meet the second expected result, then sending the impedance adjustment instruction to the opposite-side chip, so that the opposite-side chip adjusts the impedance value of the opposite-side source-end impedance module, and so that the opposite-side chip sends the second verification signal again after each adjustment is completed.

[0056] Specifically, taking the above technical solution as an example, after the initial impedance of the terminal impedance module is set to 25 ohms, if the impedance value of the opposite source end impedance module of the opposite core particle has traversed the entire adjustable range, that is, 10 ohms to 50 ohms, and the second quality evaluation result obtained for the second verification signal under any impedance combination, that is, the terminal impedance module 25 ohms + any value of the opposite source end impedance module, does not meet the first expected result, then it indicates that the initial impedance setting of the terminal impedance module is incorrect. Therefore, the initial impedance of the terminal impedance module is adjusted, for example, the initial impedance of the terminal impedance module is adjusted from 25 ohms to 30 ohms, and then an impedance adjustment instruction is sent to the opposite core particle again, so that the opposite core particle traverses the impedance value of the opposite source end impedance module again, until under a certain impedance combination, that is, the terminal impedance module 30 ohms + a certain value of the opposite source end impedance module, the second quality evaluation result obtained for the second verification signal meets the first expected result or the second expected result.

[0057] In addition, as described in the above technical solution, if the second quality evaluation result obtained for the second verification signal meets the first expected result and does not meet the second expected result under the terminal impedance module 30 ohms + a certain value of the opposite source end impedance module (for example, 20 ohms), the opposite source end impedance module is fixed to 20 ohms, and the impedance value of the terminal impedance module is adjusted. If the terminal impedance module is at a certain value (for example, 28 ohms), that is, the terminal impedance module is 28 ohms + the source end impedance module is 20 ohms, the second quality evaluation result meets the first expected result, then 28 ohms and 20 ohms are the terminal impedances, respectively. The working impedance value of the impedance module and the opposite source end impedance module; if the second quality evaluation result of the terminal impedance module does not meet the second expected result at each value, then the terminal impedance module remains at 30 ohms, and the opposite side core particle continues to adjust the opposite source end impedance module until the next impedance value (for example, 26 ohms) is obtained, that is, under the terminal impedance module 30 ohms + the opposite source end impedance module 26 ohms, the second quality evaluation result obtained for the second verification signal meets the second expected result, then 30 ohms and 26 ohms are the working impedance values ​​of the terminal impedance module and the opposite source end impedance module, respectively. In this way, precise adjustment of the terminal impedance module and the opposite source end impedance module on both sides of the main band channel is achieved, which not only speeds up the adjustment efficiency of the main band channel impedance value, but also ensures the accuracy of the impedance value.

[0058] The technical solution of the embodiment of the present invention is to send an impedance adjustment instruction to the opposite-side chip after determining that the second quality evaluation result does not meet the first expected result, so that the opposite-side chip adjusts the impedance value of the opposite-side source impedance module, and causes the opposite-side chip to send a second verification signal again after each adjustment is completed, thereby guiding the opposite-side chip to complete the impedance value adjustment of the opposite-side source impedance module; after determining that the second quality evaluation result meets the first expected result but does not meet the second expected result, send an impedance maintain instruction to the opposite-side chip so that the opposite-side chip maintains the impedance value of the opposite-side source impedance module unchanged, and adjusts the impedance value of the terminal impedance module based on the adjustment step size, and sends a verification resend instruction to the opposite-side chip after each adjustment is completed, so that the opposite-side chip sends the second verification signal again, thereby completing the impedance value adjustment of the terminal impedance module; and when it is determined that the second quality evaluation result meets the second expected result, send an adjustment completion instruction to the opposite-side chip so that the opposite-side chip uses the current impedance value of the opposite-side source impedance module as the working impedance value, thereby completing the impedance adjustment of the transmission line where the transmitter is located.

[0059] Example 3

[0060] Figure 4 This is a flowchart of an impedance adjustment method provided by the third embodiment of the present invention. The relationship between this embodiment and the above embodiment is that different impedance adjustment operations are performed according to different first quality evaluation results. Figure 4 As shown, the method includes:

[0061] S301 : In response to receiving a power-on start signal, obtaining the operating state of a main band channel to be adjusted.

[0062] S302: If it is determined that the main band channel is in the source-end negotiation state, send a first verification signal to the opposite-side chiplet through the transmitter and the source-end impedance module, so that the opposite-side chiplet generates a first quality evaluation result based on the first verification signal.

[0063] S303 : In response to obtaining the impedance adjustment instruction sent by the opposite chiplet, adjust the impedance value of the source impedance module based on the adjustment step size, and send a first verification signal to the opposite chiplet after each adjustment is completed.

[0064] The opposite-side chip generates a first quality evaluation result based on the first verification signal. If it is determined that the first quality evaluation result does not meet the first expected result, an impedance adjustment instruction is sent to the current chip. After the control module of the current chip adjusts the impedance value of the source-end impedance module, a second verification signal is sent again to complete the impedance value adjustment of the source-end impedance module.

[0065] S304 : In response to receiving the impedance maintain instruction sent by the opposite chiplet, maintaining the impedance value of the source impedance module unchanged, and re-issuing the first verification signal to the opposite chiplet when receiving the verification resend instruction sent by the opposite chiplet.

[0066] If the opposite chip determines that the first quality evaluation result does not meet the first expected result and does not meet the second expected result, it sends an impedance maintenance instruction to the current chip; the control module of the current chip keeps the impedance value of the source impedance module unchanged, and when it obtains the verification resend instruction sent by the opposite chip, it sends the first verification signal to the opposite chip again, thereby guiding the opposite chip to complete the impedance value adjustment of the opposite terminal impedance module.

[0067] S305 : In response to obtaining the adjustment completion instruction sent by the opposite-side chiplet, use the current impedance value of the source-end impedance module as the working impedance value.

[0068] If the opposite chip determines that the second quality evaluation result meets the second expected result, the source end impedance module of the current chip and the opposite terminal impedance module of the opposite chip have been adjusted. The impedance value of the source end impedance module and the impedance value of the opposite terminal impedance module can be used as their respective working impedance values.

[0069] Optionally, in an embodiment of the present invention, adjusting the impedance value of the source-end impedance module according to the first quality evaluation result specifically includes: obtaining a matching source-end adjustment step according to the first quality evaluation result, and adjusting the impedance value of the source-end impedance module according to the source-end adjustment step; and / or adjusting the impedance value of the terminal impedance module according to the second quality evaluation result specifically includes: obtaining a matching terminal adjustment step according to the second quality evaluation result, and adjusting the impedance value of the terminal impedance module according to the terminal adjustment step.

[0070] Specifically, when the control module adjusts the impedance value of the terminal impedance module according to the second quality evaluation result, the greater the difference between the second quality evaluation result and the second expected result, the larger the terminal adjustment step, so as to accelerate the impedance adjustment speed of the terminal impedance module through a larger adjustment step; the smaller the difference between the second quality evaluation result and the second expected result, the smaller the source adjustment step, so as to achieve precise adjustment of the terminal impedance module through a smaller adjustment step; similarly, when the control module adjusts the impedance value of the source impedance module according to the first quality evaluation result, the greater the difference between the first quality evaluation result and the second expected result, the larger the adjustment step, so as to accelerate the impedance adjustment speed of the source impedance module through a larger adjustment step; the smaller the difference between the second quality evaluation result and the second expected result, the smaller the adjustment step, so as to achieve precise adjustment of the source impedance module through a smaller adjustment step.

[0071] Optionally, in an embodiment of the present invention, after determining that the main band channel is in a source-end negotiation state, it specifically includes: obtaining a first associated main band channel of the main band channel, and using the working impedance value of the associated source-end impedance module in the first associated main band channel as the initial impedance value of the source-end impedance module; after determining that the main band channel is in a terminal negotiation state, it specifically includes: obtaining a second associated main band channel of the main band channel, and using the working impedance value of the associated terminal impedance module in the second associated main band channel as the initial impedance value of the terminal impedance module.

[0072] Specifically, as described in the above technical solution, whether the control module adjusts the impedance value of the terminal impedance module based on the second quality evaluation result generated by itself, or adjusts the impedance value of the source impedance module based on the first quality evaluation result generated by the opposite-side core particle, it is necessary to set the initial impedance value as the adjustment starting point at the beginning of the adjustment, and then adjust based on the adjustment step. The main band channels within the same interface are usually connected to the same opposite-side core particle and are used to transmit similar data information. Therefore, the source impedance module and the terminal impedance module of each main band channel within the same interface usually have similar impedance values. Therefore, other main band channels within the same interface can be used as associated main band channels, and the working impedance value adjusted by the associated main band channel can be used as the initial impedance value of the main band channel to be adjusted, thereby further improving the impedance adjustment efficiency of the main band channel.

[0073] The technical solution of the embodiment of the present invention is as follows: when an impedance adjustment instruction sent by the opposite-side chip is obtained, the impedance value of the source-end impedance module is adjusted based on the adjustment step size, and a first verification signal is sent to the opposite-side chip after each adjustment is completed, thereby completing the impedance adjustment of the source-end impedance module; when an impedance hold instruction sent by the opposite-side chip is obtained, the impedance value of the source-end impedance module is kept unchanged, and when a verification resend instruction sent by the opposite-side chip is obtained, the first verification signal is sent to the opposite-side chip again, thereby guiding the opposite-side chip to complete the impedance adjustment of the opposite-side terminal impedance module; and when an adjustment completion instruction sent by the opposite-side chip is obtained, the current impedance value of the terminal impedance module is used as the working impedance value, thereby completing the impedance adjustment of the transmission line where the receiver is located.

[0074] Example 4

[0075] Figure 5 : is a structural block diagram of an impedance adjustment device provided by a fourth embodiment of the present invention, the impedance adjustment device specifically includes:

[0076] The channel status acquisition module 401 is configured to acquire the operating status of the main band channel to be adjusted in response to receiving the power-on start signal;

[0077] a verification signal sending module 402 configured to, if determining that the primary band channel is in the source-end negotiation state, send a first verification signal to the opposite-side chiplet via a transmitter and a source-end impedance module, so that the opposite-side chiplet generates a first quality evaluation result based on the first verification signal, and adjusts the impedance value of the source-end impedance module according to the first quality evaluation result;

[0078] The evaluation result generation module 403 is used to receive the second verification signal sent by the opposite-side core particle through the receiver and the terminal impedance module if it is determined that the main band channel is in the terminal negotiation state, and generate a second quality evaluation result based on the second verification signal, so as to adjust the impedance value of the terminal impedance module according to the second quality evaluation result.

[0079] The technical solution of the embodiment of the present invention is to send a first verification signal to the opposite-side chip through the transmitter and the source-end impedance module, so that the opposite-side chip generates a first quality evaluation result based on the first verification signal, and adjusts the impedance value of the source-end impedance module according to the first quality evaluation result; receive the second verification signal sent by the opposite-side chip through the receiver and the terminal impedance module, and generate a second quality evaluation result according to the second verification signal, so as to adjust the impedance value of the terminal impedance module according to the second quality evaluation result, thereby realizing dynamic matching of the impedance value in the chip interface, greatly improving the compatibility of the chip; at the same time, the dynamic matching of the impedance value also reduces the emission generated by the transmission signal, greatly improving the signal transmission quality of the chip.

[0080] Optionally, a verification signal sending module 402 is specifically configured to send an impedance negotiation signal to the opposite chiplet via a sideband channel;

[0081] The evaluation result generating module 403 is specifically configured to obtain the impedance negotiation signal sent by the opposite-side chiplet through the sideband channel.

[0082] Optionally, the evaluation result generation module 403 is specifically configured to, if it is determined that the second quality evaluation result does not meet the first expected result, send an impedance adjustment instruction to the opposite-side chiplet, so that the opposite-side chiplet adjusts the impedance value of the opposite-side source-end impedance module, and enables the opposite-side chiplet to send a second verification signal again after each adjustment is completed; if it is determined that the second quality evaluation result meets the first expected result but does not meet the second expected result, send an impedance maintenance instruction to the opposite-side chiplet, so that the opposite-side chiplet maintains the impedance value of the opposite-side source-end impedance module unchanged, and adjusts the impedance value of the terminal impedance module based on the adjustment step size, and sends a verification retransmission instruction to the opposite-side chiplet after each adjustment is completed, so that the opposite-side chiplet sends the second verification signal again; if it is determined that the second quality evaluation result meets the second expected result, use the current impedance value of the terminal impedance module as the working impedance value, and send an adjustment completion instruction to the opposite-side chiplet, so that the opposite-side chiplet uses the current impedance value of the opposite-side source-end impedance module as the working impedance value.

[0083] Optionally, the evaluation result generation module 403 is further specifically used to adjust the impedance value of the terminal impedance module based on the adjustment step if it is determined that the opposite-side chip has traversed all impedance values ​​of the opposite-side source-end impedance module and the second quality evaluation result does not meet the first expected result, and send an impedance adjustment instruction to the opposite-side chip again after the adjustment is completed; if it is determined that all impedance values ​​of the terminal impedance module have been traversed and the second quality evaluation result does not meet the second expected result, send an impedance adjustment instruction to the opposite-side chip so that the opposite-side chip adjusts the impedance value of the opposite-side source-end impedance module and causes the opposite-side chip to send a second verification signal again after each adjustment is completed.

[0084] Optionally, the verification signal issuing module 402 is specifically used to respond to the impedance adjustment instruction sent by the opposite chip, adjust the impedance value of the source-end impedance module based on the adjustment step, and send a first verification signal to the opposite chip after each adjustment is completed; respond to the impedance maintenance instruction sent by the opposite chip, keep the impedance value of the source-end impedance module unchanged, and when the verification resend instruction sent by the opposite chip is obtained, send the first verification signal to the opposite chip again; respond to the adjustment completion instruction sent by the opposite chip, use the current impedance value of the source-end impedance module as the working impedance value.

[0085] Optionally, the verification signal issuing module 402 is specifically configured to obtain a matching source-end adjustment step length according to the first quality evaluation result, and adjust the impedance value of the source-end impedance module according to the source-end adjustment step length;

[0086] Optionally, the evaluation result generating module 403 is further configured to obtain a matching terminal adjustment step according to the second quality evaluation result, and adjust the impedance value of the terminal impedance module according to the terminal adjustment step.

[0087] Optionally, the verification signal issuing module 402 is specifically used to obtain a first associated main band channel of the main band channel, and use the working impedance value of the associated source end impedance module in the first associated main band channel as the initial impedance value of the source end impedance module.

[0088] Optionally, the evaluation result generating module 403 is further configured to obtain a second associated main band channel of the main band channel, and use the working impedance value of the associated terminal impedance module in the second associated main band channel as the initial impedance value of the terminal impedance module.

[0089] The impedance adjustment device provided by the present invention can execute the impedance adjustment method provided by any embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not fully described in this embodiment, please refer to the impedance adjustment method provided by any embodiment of the present invention.

[0090] Example 5

[0091] Figure 6 This is a structural block diagram of a core particle provided in Example 5 of the present invention, which includes a transmitter, a receiver and an impedance adjustment system; the impedance adjustment system includes a source impedance module, a terminal impedance module and a control module; the control module is used to execute the impedance adjustment method provided in any embodiment of the present invention.

[0092] Example 6

[0093] In some embodiments, the impedance adjustment method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program can be loaded and / or installed on a heterogeneous hardware accelerator via a ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the impedance adjustment method described above can be performed. Alternatively, in other embodiments, the processor can be configured to perform the impedance adjustment method in any other appropriate manner (e.g., by means of firmware).

[0094] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0095] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0096] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0097] To provide interaction with a user, the systems and techniques described herein can be implemented on a heterogeneous hardware accelerator that has: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the heterogeneous hardware accelerator. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0098] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0099] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0100] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0101] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. An impedance adjustment method, characterized in that: The control module applied to the core particle includes: In response to obtaining a power-on start signal, obtaining the working state of the main band channel to be adjusted; wherein the control module is connected to the control module of the opposite side chiplet through the side band channel; If it is determined that the main band channel is in the source-end negotiation state, a first verification signal is sent to the opposite-side chiplet through the transmitter and the source-end impedance module, so that the opposite-side chiplet generates a first quality evaluation result based on the first verification signal, and adjusts the impedance value of the source-end impedance module according to the first quality evaluation result; The adjusting the impedance value of the source-end impedance module according to the first quality evaluation result specifically includes: in response to an impedance adjustment instruction issued by the opposite-side chiplet obtained through the sideband channel, adjusting the impedance value of the source-end impedance module, and again issuing a first verification signal after the impedance value adjustment is completed, so that the opposite-side chiplet continues to obtain the first quality evaluation result until the first quality evaluation result meets the expected result; if it is determined that the mainband channel is in the terminal negotiation state, receiving a second verification signal sent by the opposite-side chiplet through a receiver and a terminal impedance module, and generating a second quality evaluation result according to the second verification signal, so as to adjust the impedance value of the terminal impedance module according to the second quality evaluation result; The adjusting the impedance value of the terminal impedance module according to the second quality evaluation result specifically includes: if it is determined that the second quality evaluation result does not meet the expected result, adjusting the impedance value of the terminal impedance module, and sending an impedance adjustment instruction to the opposite-side chip through the sideband channel, so that the opposite-side chip adjusts the impedance value of the opposite-side source impedance module according to the impedance adjustment instruction.

2. The method according to claim 1, characterized in that Before sending the first verification signal to the opposite chip through the transmitter and the source impedance module, the method further includes: an impedance negotiation signal sent to the opposite chiplet via a sideband channel; Before receiving the second verification signal sent by the opposite-side chiplet through the receiver and the terminal impedance module, the method further includes: The impedance negotiation signal sent by the opposite-side chiplet is obtained through the sideband channel.

3. The method according to claim 1, characterized in that Generating a second quality evaluation result according to the second verification signal, and adjusting the impedance value of the terminal impedance module according to the second quality evaluation result, specifically includes: If it is determined that the second quality evaluation result does not meet the first expected result, an impedance adjustment instruction is sent to the opposite-side chiplet, so that the opposite-side chiplet adjusts the impedance value of the opposite-side source impedance module, and the opposite-side chiplet sends a second verification signal again after each adjustment is completed; If it is determined that the second quality evaluation result meets the first expected result but does not meet the second expected result, an impedance maintenance instruction is sent to the opposite-side chiplet, so that the opposite-side chiplet maintains the impedance value of the opposite-side source impedance module unchanged, and adjusts the impedance value of the terminal impedance module based on the adjustment step size, and after each adjustment is completed, a verification retransmission instruction is sent to the opposite-side chiplet, so that the opposite-side chiplet sends the second verification signal again; If it is determined that the second quality evaluation result meets the second expected result, the current impedance value of the terminal impedance module is used as the working impedance value, and an adjustment completion instruction is sent to the opposite-side chip so that the opposite-side chip uses the current impedance value of the opposite-side source impedance module as the working impedance value.

4. The impedance adjustment method according to claim 3, wherein: After sending the impedance adjustment instruction to the opposite chiplet, the method further includes: If it is determined that the opposite-side chiplet has traversed all impedance values ​​of the opposite-side source impedance module and the second quality evaluation result does not meet the first expected result, adjust the impedance value of the terminal impedance module based on the adjustment step size, and send an impedance adjustment instruction to the opposite-side chiplet again after the adjustment is completed; After sending the impedance maintenance instruction to the opposite chiplet, the method further includes: If it is determined that all impedance values ​​of the terminal impedance module have been traversed and the second quality evaluation result does not meet the second expected result, an impedance adjustment instruction is sent to the opposite-side chip so that the opposite-side chip adjusts the impedance value of the opposite-side source impedance module and causes the opposite-side chip to send a second verification signal again after each adjustment is completed.

5. The impedance adjustment method according to claim 1, wherein: The adjusting the impedance value of the source impedance module according to the first quality evaluation result specifically includes: In response to obtaining an impedance adjustment instruction sent by the opposite chiplet, adjusting the impedance value of the source impedance module based on an adjustment step, and sending a first verification signal to the opposite chiplet after each adjustment is completed; In response to receiving an impedance maintain instruction sent by the opposite chiplet, maintaining the impedance value of the source impedance module unchanged, and re-issuing a first verification signal to the opposite chiplet when receiving a verification resend instruction sent by the opposite chiplet; In response to obtaining the adjustment completion instruction sent by the opposite-side chiplet, the current impedance value of the source-end impedance module is used as the working impedance value.

6. The impedance adjustment method according to claim 1, wherein: The adjusting the impedance value of the source impedance module according to the first quality evaluation result specifically includes: Acquire a matching source-end adjustment step length according to the first quality evaluation result, and adjust the impedance value of the source-end impedance module according to the source-end adjustment step length; And / or adjusting the impedance value of the terminal impedance module according to the second quality evaluation result specifically includes: A matching terminal adjustment step length is acquired according to the second quality evaluation result, and the impedance value of the terminal impedance module is adjusted according to the terminal adjustment step length.

7. The impedance adjustment method according to claim 1, wherein: After determining that the primary band channel is in the source end negotiation state, the method specifically includes: Acquire a first associated main band channel of the main band channel, and use the working impedance value of the associated source end impedance module in the first associated main band channel as the initial impedance value of the source end impedance module; After determining that the primary band channel is in the terminal negotiation state, the method specifically includes: A second associated main band channel of the main band channel is acquired, and a working impedance value of an associated terminal impedance module in the second associated main band channel is used as an initial impedance value of the terminal impedance module.

8. An impedance adjustment device, characterized in that: The control module applied to the core particle includes: a channel status acquisition module, configured to acquire the working status of the main band channel to be adjusted in response to receiving the power-on start signal; wherein the control module is connected to the control module of the opposite chiplet via the sideband channel; a verification signal sending module, configured to, if determining that the primary band channel is in the source-end negotiation state, send a first verification signal to the opposite-side chiplet via a transmitter and a source-end impedance module, so that the opposite-side chiplet generates a first quality evaluation result based on the first verification signal, and adjusts the impedance value of the source-end impedance module according to the first quality evaluation result; The verification signal issuing module is specifically configured to: in response to an impedance adjustment instruction issued by the opposite-side chiplet obtained through the sideband channel, adjust the impedance value of the source impedance module, and re-issue the first verification signal after the impedance value adjustment is completed, so that the opposite-side chiplet continues to obtain the first quality evaluation result until the first quality evaluation result meets the expected result; an evaluation result generating module, configured to, if it is determined that the primary band channel is in a terminal negotiation state, receive, through a receiver and a terminal impedance module, a second verification signal sent by the opposite-side chiplet, and generate a second quality evaluation result based on the second verification signal, so as to adjust the impedance value of the terminal impedance module based on the second quality evaluation result; Among them, the evaluation result generation module is specifically used to: if it is determined that the second quality evaluation result does not meet the expected result, adjust the impedance value of the terminal impedance module, and send an impedance adjustment instruction to the opposite side chip through the sideband channel, so that the opposite side chip adjusts the impedance value of the opposite side source end impedance module according to the impedance adjustment instruction.

9. A core particle, characterized in that The core particle includes a transmitter, a receiver and an impedance adjustment system; the impedance adjustment system includes a source impedance module, a terminal impedance module and a control module; the control module is used to execute the impedance adjustment method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the impedance adjustment method according to any one of claims 1 to 7 when executed.

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