A method for preparing a fluorinated polymer dielectric-based organic field effect transistor

Abstract

The application discloses a preparation method of an organic field effect transistor based on fluorinated polymer dielectric, and belongs to the technical field of microelectronic materials and devices. The preparation method comprises the following steps: firstly, forming source and drain electrodes by evaporation above a substrate; then forming a semiconductor layer and a dielectric layer above the source and drain electrodes by spin coating; and finally, forming a gate electrode above the dielectric layer by evaporation. In the application, DPPT-TT is selected as the semiconductor layer, and CYTOP is selected as the dielectric layer. The optimal annealing temperature of the CYTOP dielectric layer can generate the maximum number of dipoles at the interface between the dielectric layer and the semiconductor layer, so that the organic transistor device with the optimal electrical performance is obtained. The preparation method of the high-performance organic field effect transistor based on fluorinated polymer dielectric provided by the application can optimize the mobility, threshold voltage and on-off ratio of the organic thin film transistor by confirming the optimal annealing temperature of the dielectric layer under the condition of ensuring the optimal working state of the device.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of microelectronic materials and devices, and particularly relates to a preparation method of an organic field effect transistor based on a fluorinated polymer dielectric. BACKGROUND

[0002] With the development of semiconductor technology and preparation processes, the area of semiconductor chips is smaller and smaller, and the market has higher and higher requirements for the performance of semiconductor devices, so how to improve the performance of the devices and reduce the power consumption of the devices has become an important problem to be solved in the electronic process field.

[0003] In recent years, with the in-depth study of the transport mechanism, it is found that the performance of the field effect transistor is closely related to many factors, including the gate voltage, the device structure, the temperature, the external radiation and the like. The mobility is an important performance parameter of the organic field effect transistor, which reflects the transport ability of the electric charge, the higher the mobility, the easier the electric charge is transported in the device, and the higher the working efficiency of the device. The factors affecting the mobility in the organic field effect transistor include the contact resistance, the roughness and the dipole at the interface of the organic semiconductor / dielectric layer, the charge trapping in the organic thin film and the gate dielectric and the related Coulomb scattering, wherein the physical and chemical properties of the semiconductor / dielectric layer interface have a greater influence on the transport of the carriers, because in the process of the transport of the carriers in the channel, the carriers are generally distributed in the 2-5 molecular layers close to the interface, and the large amount of traps and dislocations at the interface of the dielectric / semiconductor layer affect the electrical performance of the device, and further affect the function and performance of the circuit.

[0004] In the literature Shin E S, Park W T, Kwon Y W, et al. Spontaneous Doping at the Polymer-Polymer Interface for High-Performance Organic Transistors [J]. Acs Applied Materials & Interfaces, 2019., it is found that the dipole is generated between the fluorine-containing polymer CYTOP and the D-A copolymer DPPT-TT through thermal annealing, the semiconductor / dielectric layer interface forms a regularly arranged dipole layer under the action of the strong C-F bond, greatly improves the accumulation of holes, produces a self-doping effect, increases the concentration of the hole carriers in the channel, and makes the intrinsic bipolar semiconductor material change into a p-type unipolar device. The self-doping greatly simplifies the manufacture of the unipolar OFET, improves the carrier mobility, reduces the off-state current and the power consumption, and also improves the carrier transport performance.

[0005] In the above documents, the dipoles need to be generated under special conditions such as thermal annealing, but the specific generation mechanism of the dipoles, such as the change trend of the dipoles with the change of the annealing temperature, the device performance, and especially the promotion condition of the mobility, needs to be further studied. SUMMARY

[0006] The application aims to provide a preparation method of an organic field effect transistor based on fluorinated polymer dielectric, and the optimal annealing temperature of the CYTOP dielectric layer can generate the maximum number of dipoles at the interface between the dielectric layer and the semiconductor layer, so that the organic transistor device with the optimal electrical performance is obtained.

[0007] The application aims to achieve the above-mentioned purpose by the following technical scheme.

[0008] The application aims to achieve the above-mentioned purpose by the following technical scheme.

[0009] Step S1: selecting a glass sheet as a substrate and cleaning;

[0010] Step S2: preparation of source-drain electrodes: vacuum evaporation of a nickel layer and a gold layer on the cleaned substrate as source-drain electrodes, the nickel layer directly contacts the substrate, and the gold layer is on the nickel layer;

[0011] Step S3: preparation of a semiconductor layer: spin coating of a stock solution of perfluoro-1-butenyl vinyl ether polymer, i.e. CYTOP stock solution, on the substrate with source-drain electrodes, and then heating and annealing at 200 DEG C in a pure nitrogen environment for 1 h to form a semiconductor layer;

[0012] Step S4: preparation of a dielectric layer: spin coating of a dielectric layer solution on the top surface of the semiconductor layer obtained in step S3, and heating and annealing at 80-200 DEG C to form a dielectric layer;

[0013] Step S5: preparation of a gate: evaporation of an aluminum layer on the dielectric layer obtained in step S4 as a gate using a stainless steel mask plate.

[0014] Further, the thickness of the nickel layer prepared in step S2 is 5 nm, and the thickness of the gold layer is 38 nm.

[0015] Further, in step S3, the semiconductor solution is configured as follows: the semiconductor material and the high-boiling organic solvent are configured at a mass-volume ratio of 5 mg / ml; the semiconductor material is a high-molecular-weight organic conjugated polymer, and the high-boiling organic solvent is dichlorobenzene.

[0016] Further, the organic conjugated polymer is a polymer DPPT-TT of 1,4-dioxadipyrrone and thiophene.

[0017] Further, the annealing temperature in step S4 is 100 DEG C.

[0018] Further, in step S2, the thermal evaporation current is 115 A, and the evaporation rate is

[0019] Further, in step S5, the thermal evaporation current is 130-170 A, and the evaporation rate is

[0020] Further, the thickness of the aluminum layer deposited in step S5 is 80 nm.

[0021] The application provides a preparation method of an organic field effect transistor based on a fluorinated polymer dielectric, a D-A copolymer DPPT-TT is selected as a semiconductor layer, and a fluorinated polymer CYTOP stock solution is selected as a dielectric layer. Dipole is generated between the fluorinated polymer CYTOP and the D-A copolymer DPPT-TT through thermal annealing, the dipole greatly improves the accumulation of holes, and the intrinsic bipolar semiconductor material is converted into a p-type unipolar device. Further, the optimal annealing temperature of the CYTOP dielectric layer can generate the maximum number of dipoles at the interface between the dielectric layer and the semiconductor layer. By fixing the annealing temperature of the semiconductor layer and adjusting the annealing temperature of the dielectric layer, the main performance parameters of the prepared device are studied, and the optimal annealing temperature under the top gate bottom contact structure is determined as 100 DEG C. The device obtained by the annealing temperature treatment has the optimal electrical performance, for example, the highest mobility and the largest on-off ratio. Compared with the existing preparation process, the application can confirm the optimal dielectric layer annealing temperature that can be used under the condition of ensuring the optimal working state of the device, and optimize the mobility, threshold voltage and on-off ratio of the organic thin film transistor. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 A structure diagram of the organic thin film transistor prepared by the preparation method of the application;

[0023] Figure 2 Saturated region transfer characteristic curves under different annealing temperatures in the embodiment of the application;

[0024] Figure 3 A mobility average statistical diagram of the organic thin film transistor under different dielectric layer annealing temperatures in the embodiment of the application;

[0025] Figure 4 A threshold voltage average statistical diagram of the organic thin film transistor under different dielectric layer annealing temperatures in the embodiment of the application;

[0026] Figure 5 A on-off ratio average statistical diagram of the organic thin film transistor under different dielectric layer annealing temperatures in the embodiment of the application.

[0027] Reference Signs

[0028] 1, substrate; 2, source-drain electrode; 3, semiconductor layer; 4, dielectric layer; 5, gate. DETAILED DESCRIPTION

[0029] For the person skilled in the relevant art to better understand the content of the present patent, the embodiments of the present application are described in detail below, which are implemented on the premise of the technical solution of the present application, and give detailed implementation modes and specific operation processes, but the content of the present application is not limited to the examples described below.

[0030] Example 1

[0031] As Figure 1 shown is an organic thin film transistor with top-gate bottom-contact structure prepared by a preparation method of an organic field effect transistor based on fluorinated polymer dielectric, comprising a substrate 1, a source-drain electrode 2, a semiconductor layer 3, a dielectric layer 4 and a metal gate 5; the source-drain electrode 2 of the device is formed by evaporation on the substrate 1; then the semiconductor layer 3 and the dielectric layer 4 are respectively formed on the source-drain electrode 2 by the method of spin coating, and finally the metal gate 5 of the device is formed by evaporation on the dielectric layer 4. The specific preparation process is as follows:

[0032] 1) Semiconductor solution preparation: 1,4-dioxadithiophene and thiophene polymer (DPPT-TT) is configured with dichlorobenzene at a mass-volume ratio of 5 mg / ml to obtain a semiconductor solution; the configured solution is placed on a heating table at 80°C and dissolved for 24 hours.

[0033] 2) Select a glass sheet with a size of about 1.5 cm x 1.5 cm as a substrate 1, and place the substrate 1 in alcohol and deionized water for ultrasonic cleaning for 20 minutes respectively. After one round of cleaning, the substrate 1 is placed in alcohol for ultrasonic cleaning for 20 minutes, and then dried with a nitrogen gun; then placed on a 100°C heating table for 15 minutes, and finally cleaned with UV Ozone and plasma for 30 minutes.

[0034] 3) A stainless steel mask is used to evaporate a nickel layer and a gold layer on the substrate 1 as a source-drain electrode 2 by vacuum thermal evaporation, with a channel length of 150 μm and a width of 1200 μm. During the evaporation process, the current used is 115 A, and the evaporation rate is controlled at The thickness of the evaporated nickel layer is 5 nm, and the thickness of the gold layer is 38 nm. The nickel layer is in direct contact with the substrate 1, and the gold layer is on the nickel layer;

[0035] 4) Preparation of semiconductor layer 3: The prepared semiconductor solution was spin-coated onto the surface of the substrate 1 on which the active drain electrode 2 was prepared using a pipette. The spin-coating method was as follows: first, the sample was spin-coated at 500 rpm for 5 seconds, and then at 2000 rpm for 60 seconds. After spin-coating, the sample was placed on a heating stage at 200°C and heated and annealed in pure nitrogen atmosphere for 1 hour to form semiconductor layer 3.

[0036] 5) Preparation of dielectric layer 4: The CYTOP stock solution was spin-coated onto the surface above semiconductor layer 3 using a pipette. The spin-coating method was as follows: first, spin coating at 500 rpm for 5 seconds, then at 1500 rpm for 60 seconds. After spin coating, the sample was placed on a heating stage, and the temperature of the heating stage was adjusted to 80℃, 100℃, 150℃, 180℃, and 200℃ respectively. The sample was then annealed in a pure nitrogen atmosphere for 2 hours to ensure a smooth and dense film, thus forming dielectric layer 4.

[0037] 6) An 80nm thick aluminum layer was deposited on top of dielectric layer 4 using a stainless steel mask via vacuum thermal evaporation to serve as the gate electrode. The current during the evaporation process was 130-170A, and the deposition rate was controlled at [value missing]. The organic thin-film transistor is thus obtained.

[0038] Related performance tests

[0039] Depend on Figure 2 It can be seen that the saturation region transfer curves at different annealing temperatures are all unipolar P-type, and a dipole is generated at the interface between semiconductor layer 3 and dielectric layer 4, indicating that a self-doping effect has occurred. (Comparison) Figure 3 , Figure 4 and Figure 5 It is known that the low-field mobility is maximized at an annealing temperature of 100°C. This is mainly due to the P-doping of dipoles formed at the interface between semiconductor layer 3 and dielectric layer 4, which increases the hole carrier density, resulting in the maximum mobility at an annealing temperature of 100°C. The on / off ratio of the organic field-effect transistor obtained in this embodiment also conforms to the pattern of first increasing and then decreasing with increasing annealing temperature.

[0040] The above description is only a preferred embodiment of the present invention and is not limited to the above implementation method. Any equivalent modifications, substitutions and improvements made by those skilled in the art based on the content disclosed in the present invention should be included in the protection scope of the claims. Figure 1 This is a schematic diagram of an idealized embodiment of the present invention. The embodiments shown in the figure should not be considered as limited to the specific shapes of the areas shown. In this embodiment, each layer is represented by a rectangle. The representations in the figure are schematic and should not be considered as limiting the scope of the invention.

Claims

1. A method for preparing a fluorinated polymer dielectric based organic field effect transistor, characterized in that, The method comprises the following steps: Step S1: selecting a glass sheet as a substrate (1) and cleaning; Step S2: preparation of source-drain electrodes (2): vacuum evaporation of a nickel layer and a gold layer on the cleaned substrate (1) as source-drain electrodes (2), the nickel layer being in direct contact with the substrate (1) and the gold layer being on the nickel layer; Step S3: preparation of a semiconductor layer (3): spin coating a semiconductor solution on the substrate (1) provided with the source-drain electrodes (2) to form a semiconductor layer (3), the spin coating method being: first, uniform coating at a speed of 500 rpm for 5 seconds, and then uniform coating at a speed of 2000 rpm for 60 seconds; then, heating annealing under a pure nitrogen atmosphere on a heating table at 200°C for 1 hour; the semiconductor solution being a polymer of 1,4-dioxo-dipyrryl and thiophene and dichlorobenzene configured at a mass-volume ratio of 5 mg / ml; Step S4: preparation of a dielectric layer (4): spin coating CYTOP stock solution on the top surface of the semiconductor layer (3) obtained in step S3, the spin coating method being: first, uniform coating at a speed of 500 rpm for 5 seconds, and then uniform coating at a speed of 1500 rpm for 60 seconds; then, heating annealing under a pure nitrogen atmosphere on a heating table at 100°C for 2 hours to form a dielectric layer (4); Step S5: preparation of a gate electrode (5): using a stainless steel mask to evaporate an aluminum layer on the dielectric layer (4) obtained in step S4 as a gate electrode (5).

2. The method of claim 1, wherein the method is a method of fabricating a fluorinated polymer dielectric based organic field effect transistor. The thickness of the nickel layer prepared in step S2 is 5 nm, and the thickness of the gold layer is 38 nm.

3. The method of claim 1, wherein the method is a method of fabricating a fluorinated polymer dielectric based organic field effect transistor, and wherein the method further comprises: In step S2, the thermal evaporation current is 115 A, and the evaporation rate is 0.2 Å / s. ​ 4. The method of claim 1, wherein the method is a method of fabricating a fluorinated polymer dielectric based organic field effect transistor. In step S5, the thermal evaporation current is 130-170 A, and the evaporation rate is 0.5 Å / s.

5. A method for fabricating an organic field-effect transistor based on a fluorinated polymer dielectric according to claim 1, characterized in that, The thickness of the aluminum layer evaporated in step S5 is 80 nm.

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