processing device

Abstract

A processing device (20) has a processor (200) including a plurality of delay push processor registers (214) and a processor register control circuit (220, 222, 224, 226, 228). The processor register control circuit (220, 222, 224, 226, 228) includes a plurality of status registers (226), each status register (226) corresponding to a respective different delay push register (214). The processor register control circuit (220, 222, 224, 226, 228) is configured to detect a write of a new value to a register (214) in the delay push registers (214) and determine whether a status register (226) of the delay push register (214) has a first value indicating an unsaved state of the delay push register (214). The processor control circuit (220, 222, 224, 226, 228) is configured, when the status register (226) has the first value, to read a current value from the delay push register (214) before completion of the write of the new value to the delay push register (214), write the current value to a memory (202), and set the status register (226) of the delay push register (214) to a second value indicating a saved state of the delay push register (214).

Description

Background Technology

[0001] This invention relates to a processing apparatus.

[0002] A processor typically includes a set of processor registers (often called a register file) for storing digital values, an arithmetic and logic unit (ALU) for performing arithmetic and logical operations on the values ​​stored in the processor registers, and a control unit for loading software instructions into the computing unit. It also has a bus interface for receiving software instructions into the processor and for reading data values ​​from the processor and writing data values ​​to other components, such as random access memory (RAM) and peripheral devices. A processor usually also has an interface for receiving hardware interrupt signals.

[0003] A normal instruction cycle involves fetching the next instruction into the processor from a memory address represented by a special processor register called the program counter (PC). The processor then executes the instruction and updates the program counter to fetch the appropriate next instruction.

[0004] However, if the processor receives an interrupt request, the processor must perform a context switch by saving the current values ​​of the program counter and certain processor registers (such as registers saved by the caller) to a stack structure in RAM.

[0005] Some processors perform this stack operation automatically before jumping to the interrupt handler to serve the interrupt; this is done as a hardware action. The interrupt handler can then freely use the saved processor register values ​​during its execution. When the interrupt handler returns, the processor automatically reads (pops) the saved register values ​​from the stack and writes them to the corresponding processor registers. The processor also sets the program counter so that the software can continue execution from the point where the interrupt was received.

[0006] However, saving register values ​​to RAM in this way comes at a cost in terms of both processor time (clock cycles) and bus load. Therefore, it can have a significant impact on system responsiveness or latency.

[0007] Some processors attempt to reduce the need to push register values ​​into RAM by providing a second register file that can be used when switching contexts. However, this approach increases the processor's size and complexity and does not support nested interrupts.

[0008] In other processors, the pushing of processor registers that must be restored after an interrupt is implemented in software, i.e., by the processor executing the instructions contained in the function preamble of the interrupt handler. However, this also adds latency because these instructions need to be fetched and executed.

[0009] This invention seeks to provide a new method that enables more efficient processor context switching. Summary of the Invention

[0010] From a first aspect, the present invention provides a processing apparatus, including a processor, wherein:

[0011] The processor includes multiple delayed push-in processor registers;

[0012] The processor includes processor register control circuitry;

[0013] The processor register control circuitry includes multiple status registers, each corresponding to its own different delay push register;

[0014] The processor register control circuitry is configured to detect new values ​​being written to the register in the delayed push register;

[0015] The processor register control circuitry is configured to determine whether the status register of the delayed push register stores a first value indicating the unstored state of the delayed push register; and

[0016] The processor register control circuit is configured such that, when the status register saves a first value: the current value is read from the delayed push register before the new value is written to the delayed push register; the current value is written to memory; and the status register of the delayed push register is set to a second value indicating the saved state of the delayed push register.

[0017] In a second aspect, the present invention provides a method for operating a processing apparatus, wherein:

[0018] The processing device includes a processor;

[0019] The processor includes multiple delayed push-in processor registers; and

[0020] The processor includes multiple status registers, each corresponding to its own different delay push register.

[0021] The method includes:

[0022] Detects the writing of a new value to the register in the delayed push register;

[0023] The status register of the delayed push register is determined to hold a first value indicating the unsaved state of the delayed push register;

[0024] Read the current value from the deferred push register before the new value is written to the deferred push register;

[0025] Write the current value to memory; and

[0026] Set the status register of the delayed push register to a second value that indicates the saved state of the delayed push register.

[0027] Therefore, it will be seen that, according to the present invention, the processor is provided with: additional status registers associated with certain processor registers (referred to herein as “delayed push” registers for ease of reference), and circuitry enabling the processor to use the status registers to determine whether each delayed push register has been pushed into memory (e.g., onto the RAM stack). In this case, the processor does not need to push these registers onto the stack immediately upon performing a context switch, but can delay doing so until, for example, when each corresponding register is actually written to in the new context. If one or more of these delayed push registers never change in the new context, this mechanism allows the processor to completely avoid having to push these registers onto the stack, thereby saving bus transactions and / or processor cycles.

[0028] Therefore, this approach promotes greater efficiency compared to the processor hardware immediately pushing all processor registers that need to be restored upon returning from an interrupt handler after a context switch. It is also more efficient than requiring called routines (such as interrupt handlers) to push and pop these processor registers using software instructions, as it avoids the need to fetch and execute these instructions.

[0029] In some implementations, the status registers are single-bit registers. They can be individual flip-flops. They can be flags in multi-bit status registers. The first and second values ​​can be opposite logic levels, i.e., logic 1 and logic 0. The same first value can represent an unsaved state in all status registers.

[0030] Delayed-push processor registers can be caller-saved registers, meaning registers that are not typically pushed onto the stack by software within the called function. These can be multi-bit registers, such as both 32-bit or 64-bit registers. The processor may include other processor registers that are not delayed-push registers, such as caller-saved registers and special registers that do not have corresponding status registers and whose processor register control circuitry is not configured to detect writes to them.

[0031] The processor may include one or more hardware interrupt inputs for receiving hardware interrupt requests. Processor register control circuitry may be configured to set all status registers to a first (unsaved) value in response to the processor receiving a hardware interrupt request.

[0032] The memory may be random access memory, such as SRAM. The processing device may include memory. It may include a bus connecting the processor to the memory. The processor may be configured to write current values ​​to a stack structure in memory. The processor may include a stack pointer register, which can be used to determine the address to which processor register values ​​are pushed and / or popped. Specifically, it may use a stack pointer value stored in the stack pointer register to determine the memory address to which a processor register that is not one of a plurality of delayed push processor registers is pushed. In some embodiments, processor register control circuitry may also use the stack pointer register to determine (possibly indirectly) the memory address to which the current value of the delayed push register is pushed, but this is not required in all embodiments, as explained below.

[0033] Processor register control circuitry may include registers, referred to herein as the context stack pointer or CSP, whose size is preferably set to hold addresses in memory, for example, within a stack structure in memory; sometimes, it may be a copy of the current value of the stack pointer. Processor register control circuitry may be configured to use the context stack pointer value stored in the context stack pointer register to determine the memory address to be pushed or popped from the delayed push register.

[0034] In some implementations, the processor register control circuitry can store pushed delayed push register values ​​together with other pushed processor register values ​​in a common stack structure, while in other implementations, it can maintain a separate context stack to receive pushed delayed push register values, which is different from the main stack used to receive other pushed processor register values.

[0035] In the first set of embodiments, the processor can be configured to store delayed push register values ​​and other processor register values ​​in a common stack structure. It can be configured to, in response to a received hardware interrupt request, change the stack pointer (i.e., the value of the stack pointer register) according to an amount (referred to herein as the stack frame size) that corresponds to at least a portion of the memory large enough to hold all delayed push register values. It can change the stack pointer according to an amount sufficient to store at least the following: all delayed push register values, the program counter value, the status register associated with the delayed push registers, and the context stack pointer. This allows sufficient space to be reserved in the stack to receive any delayed push registers that need to be pushed later.

[0036] Processor register control circuitry can be configured, in response to a received hardware interrupt request, to push the program counter and / or status register (e.g., by pushing a multi-bit status register that includes the status register) and / or context stack pointer onto an address in memory determined by the size value stored in the stack pointer register. Processor register control circuitry can be configured to copy a value (i.e., the current stack pointer) from the stack pointer register to the context stack pointer register after the context stack pointer is pushed. The stack pointer may have changed according to the stack frame size before the copy. By pushing the status register and context stack pointer onto the stack, the processing device can support nested interrupts (e.g., a higher-priority interrupting a lower-priority interrupt handler), potentially reaching any depth, limited only by the available stack space.

[0037] The processor register control circuitry can be configured to use the context stack pointer to determine the address at which a delayed push value is pushed into a processor register. It determines the address by applying an offset to the value in the context stack pointer register. The processor register control circuitry may include hardwired logic for determining the address. Each delayed push register may be associated with its own distinct constant offset. Thus, each delayed push register has its own reserved location within a reserved stack frame.

[0038] In the second implementation, the processor can be configured to store delayed push register values ​​in a context stack, distinct from the stack used to store values ​​of one or more other processor registers. A context stack pointer register can be used to maintain the context stack independently of the stack pointer register. The processor register control circuitry can include multiple multi-bit location registers, each corresponding to a distinct delayed push register. The processor register control circuitry can be configured to store a value in the corresponding location register when a delayed push register is pushed into memory, the value of which is encoded relative to the value in the context stack pointer register, for example as an offset from the address value in the CSP at the time the delayed push register is pushed. This eliminates the need for a fixed predetermined offset for the delayed push registers, avoiding the need to reserve a sufficiently large stack frame to receive all delayed push registers even when only a subset needs to be pushed; instead, the pushed values ​​can be loaded into memory more efficiently. The processor register control circuitry can be configured to push the values ​​of delayed push registers into addresses whose associated status registers are equal to the number of delayed push registers with a second (saved) value. A delayed push register can be pushed into memory at the next unoccupied address following the context stack pointer in a predetermined direction (i.e., incrementing or decrementing throughout the address space). This allows for more efficient memory use by pushing the delayed push register into consecutive (i.e., adjacent) memory addresses, rather than leaving gaps in reserved stack frames. This address can also depend on the context stack pointer. In these implementations, the context stack pointer can be completely independent of the stack pointer (i.e., never set to equal the stack pointer) and can point to an address in a separate region of memory from the address pointed to by the stack pointer—that is, a separate context stack different from the main call stack. Processor register control circuitry can push the program counter and / or status register and / or context stack pointer into an address in memory determined by the value stored in the context stack pointer register, rather than the stack pointer itself.

[0039] In some implementations, the processor register control circuitry is configured to, in response to detecting a return from an interrupt handler routine, determine whether the status register of each delayed push register holds a second value indicating the saved state of the delayed push register. It can be configured to, when the status register holds the second value, read the pushed value from memory and write the pushed value back to the delayed push register. By only restoring (popping) delayed push registers whose contents were actually modified by the interrupt handler, implementations can further limit the number of processor cycles and / or bus transactions required upon returning from an interrupt.

[0040] The processor register control circuitry can be configured to support tail-chain interrupt handling, i.e., handling two or more interrupts consecutively without returning to the process that was executing when the first interrupt request was received. The processor can be configured not to pop the pushed context stack pointer and register status values ​​when returning from the first interrupt handler when the second interrupt is suspended.

[0041] The processor register control circuitry can detect writes to the delayed push register in any suitable manner. For example, it can be configured to receive a multiplexer control signal output from the instruction decoder in the processor. This control signal can then be used to detect writes to the delayed push register.

[0042] The memory may store software executed by the processor. The memory may store an interrupt vector table. This software may include one or more interrupt handlers, which may be stored at addresses identified in the interrupt vector table. The processor may be configured to jump to an interrupt handler in response to receiving a hardware interrupt request signal. In some implementations, the interrupt handler may be configured to push one or more additional processor registers into memory. It may include instructions that change the values ​​in one or more delayed-push processor registers.

[0043] The processing device can be an integrated circuit device. It can be a system-on-a-chip (SoC).

[0044] Features of any aspect or implementation described herein may be applied to any other aspect or implementation described herein where appropriate. Where different implementations or groups of implementations are referred to, it should be understood that they are not necessarily different but may overlap. Attached Figure Description

[0045] Some preferred embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, wherein:

[0046] Figure 1 This is a schematic diagram of a traditional System-on-a-Chip (SoC);

[0047] Figure 2 This is a schematic diagram of a system-on-a-chip (SoC) implementing the present invention;

[0048] Figure 3 It is shown in Figure 2 Timing diagrams of different stages when the SoC handles interrupt requests;

[0049] Figure 4 It refers to different stages in processing interrupt requests. Figure 2 A schematic diagram of the memory contents of a SoC;

[0050] Figure 5It is shown in Figure 2 Timing diagram of different stages when the SoC handles two interrupt requests in a preemptive manner;

[0051] Figure 6 and Figure 7 It refers to different stages of handling interrupt requests in a preemptive manner. Figure 2 A schematic diagram of the memory contents of a SoC;

[0052] Figure 8 It is shown in Figure 2 The timing diagram of the SoC handling different stages of two interrupts with fast interrupt switching;

[0053] Figure 9 and Figure 10 It refers to the different stages of handling interrupt requests using fast interrupt transition. Figure 2 A schematic diagram of the memory contents of a SoC;

[0054] Figure 11 This is a schematic diagram of a second system-on-a-chip (SoC) implementing the present invention, which uses register position bits to provide higher memory space efficiency;

[0055] Figure 12 yes Figure 11 A schematic diagram of the local stack status register of the SoC;

[0056] Figure 13 It is shown in Figure 11 The SoC handles the timing diagrams of different stages when two interrupts are processed with efficient memory utilization; and

[0057] Figure 14 and Figure 15 It handles different stages of interrupt requests with efficient memory utilization. Figure 11 A schematic diagram of the contents of the SoC's memory. Detailed Implementation

[0058] For reference purposes, Figure 1 A schematic diagram of a conventional system-on-a-chip (SoC) 10 including a processor 100 coupled to memory 102 is shown. Memory 102 may include SRAM connected to processor 100 via a system bus. It may also include non-volatile memory, such as flash memory. Processor 100 may optionally include a memory cache (not shown). SoC 10 may include additional processors, peripherals, etc.

[0059] Processor 100 includes an instruction decoder 104, an arithmetic logic unit (ALU) 106, a register file 108, multiple multiplexers 109-110, and a demultiplexer 112. Register file 108 includes multiple (e.g., eight) caller-stored processor registers 114, multiple callee-stored processor registers 116, a program counter (PC) register 117, and a stack pointer (SP) register 118. Register file 108 also contains other standard processor registers (from... for simplicity...). Figure 1 (omitted), such as the status register and link register. The program counter (PC) register 117 contains the address of the instruction currently being executed by the processor 100. Each register within the register file 108 includes multiple flip-flops, such as thirty-two flip-flops, for storing values ​​needed by the processor 100 during instruction execution.

[0060] The caller-saved register 114 is used to store temporary values. Unlike the callee-saved register 116, the called function does not need to save these values ​​upon entry and restore them before returning. Instead, if the calling function needs to retain these registers 114, it is responsible for storing their values ​​in memory 102. The callee-saved register 116 is used to store long-term values ​​that should be retained across function calls; the storage and restoration of these values ​​in memory 102 are controlled by the called routine (i.e., the callee).

[0061] Under normal operating conditions, ALU 106 writes to and reads from registers in register file 108 to execute instructions. To write to a register, ALU 106 outputs the value to multiplexer 109, which in turn outputs the value to demultiplexer 112. Instruction decoder 104 outputs the desired write location (i.e., the desired register) to demultiplexer 112, enabling demultiplexer 112 to direct the value to the desired register in register file 108. To read data from a register, the data is output from the desired register to multiplexer 110. Instruction decoder 104 outputs the desired read location (i.e., the desired register) to multiplexer 110, enabling multiplexer to connect the desired register as an input to ALU 106. All calculations using the values ​​stored in register file 108 are performed within ALU 106.

[0062] To execute an instruction, ALU 106 sends an instruction fetch bus request to memory 102, which contains the address (corresponding to the PC) for storing the next expected instruction. Memory 102 then outputs the instruction stored at that address to decoder 104, which in turn decodes the instruction to determine the instruction to be executed by ALU 106.

[0063] Processor 100 is also capable of writing data values ​​to and reading data values ​​from memory 102. To write a value stored in a register within register file 108 to memory 102, as previously described, the value stored in the register is read by ALU 106. This value is then output by processor 100 to memory 102 along with an address pointing to the location where the value is stored. To read a value stored in memory 102 and store it in a register, processor 100 sends a read request (containing the address of the desired read location) to memory 102. The memory then forwards the value stored at the desired address to multiplexer 109, which outputs the value to demultiplexer 112. As previously described, decoder 104 controls demultiplexer 112 to set which register the value output by multiplexer 109 should be stored in.

[0064] During instruction execution, processor 100 may receive a hardware interrupt request, for example, from a peripheral device. The interrupt request instructs processor 100 to suspend the execution of the current routine in order to execute a different, more urgent set of instructions, returning to the same state of execution of the original routine after the interrupt handler completes.

[0065] After the software is loaded into memory 102, memory 102 will contain an interrupt vector table (IVT). This includes a data structure that associates a list of interrupt requests with a list of interrupt handlers. When processor 100 receives an interrupt request, processor 100 uses the vector table to determine the address of the associated interrupt handler (i.e., the instructions required to execute the interrupt) so that processor 100 can execute the interrupt handler instructions.

[0066] In order to resume the original routine after handling an interrupt, processor 100 needs to restore the values ​​in caller-saved register 114 to the same state they were in before the instruction handler was executed. During instruction handler execution, it is permissible to overwrite caller-saved registers (e.g., the 32-bit Arm register). TM The processor uses registers R0-R3, so if the data value stored therein is not stored elsewhere, the processor 100 cannot resume execution of the original instructions from the point reached before handling the interrupt. Unlike routine function calls, hardware interrupts can occur at any time without warning the currently executing routine. Therefore, the software cannot execute instructions to save the caller-saved register 114 to memory 102 as it could do before calling a routine function call.

[0067] Therefore, upon receiving an interrupt request, processor 100 automatically stores all data contained in caller-saved register 114 onto the stack in memory 102. The "stack" is a last-in, first-out (LIFO) data structure. Used in conjunction with the stack is a stack pointer (SP), which records the address of the most recently added item to the stack; it is stored in the stack pointer (SP) register 118. The program counter (PC) register 117, containing the memory address of the instruction currently being executed by processor 100, is also pushed onto the stack. Other registers, such as the program status register and link register, may also be pushed. The values ​​from caller-saved register 114 and special registers stored by processor 100 within the stack in memory 102 are hereinafter referred to as the interrupt's "context" data. Context data typically has a fixed, predetermined size.

[0068] To store data on the stack, processor 100 performs a "push" operation, storing the data at the top of the stack (i.e., the next available address indicated by the stack pointer), and SP increments to accommodate the size of the newly stored data. (Equivalently, if the stack grows downwards in the address space, SP can decrement.) To read data from the stack, processor 100 performs a "pop" operation, reading the data stored at the location pointed to by SP from memory, and SP decrements the size of the read data.

[0069] After storing the context data, processor 100 reads the address of the interrupt handler associated with the received interrupt request from the IVT stored in memory and stores it in the program counter register 117. Processor 100 is then able to begin executing the interrupt handler. The interrupt handler may include any caller-saved registers 116 (e.g., 32-bit Arm) that will be modified. TM The function prologue pushes registers R4-R11 in the processor onto the stack, and the function epilogue pops these values ​​back into the appropriate register 116 before returning.

[0070] Once the interrupt handler has completed execution, the processor 100 no longer needs the values ​​saved in the caller-saved register 114 during the interrupt handler's execution. Therefore, the processor 100 restores the context data from the stack to the caller-saved register 114 by popping the context data from the stack and saving it in the caller-saved register 114. This allows the processor 100 to resume execution of the interrupted function from the point where process 100 began executing the interrupt handler.

[0071] If processor 100 receives a second, higher-priority interrupt request during the execution of the first interrupt handler, it executes the exact same process again: processor 100 pushes all values ​​saved in register 114 (the context data of the second interrupt) onto the stack and begins execution of the second interrupt handler. Multiple nested interrupts can be handled in this way.

[0072] Figure 2 A schematic diagram illustrating a system-on-a-chip (SoC) 20 implementing the present invention is shown, comprising a processor 200 coupled to a memory 202. The memory 202 may include SRAM, which is connected to the processor 200 via a system bus. It may also include non-volatile memory, such as flash memory. The processor 200 may optionally include a memory cache (not shown). The SoC 20 may include additional processors, peripheral devices, etc. (not shown for simplicity). Figure 2 (as shown in the image).

[0073] Parts 204-218 and Figure 1 The corresponding parts 104-118 shown are similar or identical.

[0074] However, processor 200 also includes two multiplexers 220 and 222, and a logic unit 228. Furthermore, register file 208 includes a context stack pointer (CSP) register 224 and a local stack state (LSS) register 226, which includes multiple flip-flops (i.e., multiple bit flags) for storing multiple individual status bits, each status bit associated with one of the caller-saved registers 214. The number of status bits equals the number of caller-saved registers 214 (e.g., eight). Each status bit is used to indicate whether the value saved in the associated caller-saved register since processor 200 received the latest hardware interrupt request has been pushed (i.e. saved) onto the stack, as will be described in more detail below. As disclosed above, these additional components together provide processor register control circuitry. As disclosed above, caller-saved register 214 is an example of a “delayed push” register.

[0075] Although CSP register 224 and LSS register 226 are in Figure 2 They are shown as being integrated into the main register file 208, but it should be understood that they do not have to be physically adjacent to the rest of the register file 208, but can be located anywhere on the chip 20.

[0076] When processor 200 receives an interrupt, unlike conventional processor 100, processor 200 does not automatically push all values ​​(context data) saved in caller-saved register 214 onto the stack in memory 202. Instead, processor 200 pushes the values ​​saved in program counter 217, context stack pointer register 224, and local stack status register 226, and simply reserves the amount of space required to store all values ​​saved in caller-saved register 114 by incrementing the stack pointer stored in stack pointer register 218 equal to the required stack frame size for storing all values ​​saved in caller-saved register 114.

[0077] Once the PC, CSP, and LSS are stored in the stack in memory 202, the processor 200 operates as described above. Figure 1 The interrupt handler address is read from the interrupt vector table in memory 202, as described. Once the stack pointer has been incremented to reserve the stack frame size, processor 200 sets the context stack pointer (stored in CSP register 224) to the value of the stack pointer. Processor 200 then uses CSP to determine the location where the context data of the interrupt handler is stored. If SP 218 increments during interrupt handler execution, CSP remains unchanged, pointing to the location of the interrupt handler's context data, as is common during normal operation (because processor 200 may need to push more items onto the stack during execution).

[0078] Before the interrupt handler is executed, the processor 200 sets the values ​​of all status bits in the LSS to indicate that the values ​​saved in all caller-saved registers 214 have not yet been stored on the stack, i.e., indicating an "unsaved" state.

[0079] During interrupt handler execution, processor 200 may write to one or more caller-saved registers 214. To do this, ALU 206 outputs the value to be written to the desired caller-saved register to multiplexer 209, which in turn outputs the value to demultiplexer 212. Instruction decoder 204 sends the desired write location (i.e., the desired caller-saved register) to demultiplexer 212, enabling demultiplexer 212 to direct the value to the desired caller-saved register 214. Simultaneously, decoder 204 sends the same write location to multiplexer 220. Upon receiving the write location, multiplexer 220 couples the currently stored value in the register at that location to logic unit 228.

[0080] Simultaneously, logic unit 228 accesses the corresponding single-bit status value stored in LSS register 226. Based on the value of the status bit associated with register 214, logic unit 228 determines whether the caller-saved register being read by multiplexer 220 has been saved to the stack. If the status bit indicates that the register value is not yet stored on the stack, logic unit 228 outputs the value to multiplexer 222, causing the register value to be loaded into memory 202; it also indicates the address where the value should be stored on the stack. If the status bit indicates that the register value is already stored on the stack, logic unit 228 does not output the value to multiplexer 222.

[0081] Then, if the signal received by multiplexer 222 from logic unit 228 indicates that the register value, along with the desired storage address, should be output to the stack within memory 202, this is done. In this example, the desired storage address on the stack is given by subtracting a fixed offset determined by the register from which the value is read from the context stack pointer. Specifically, the storage location of the register value is given by the following formula:

[0082] addr = CSP-n reg (1),

[0083] Where addr is the expected memory address on the stack, CSP is the context stack pointer, and n reg It is the register number from which the value is read.

[0084] Logic unit 228 then changes the status bit associated with the read register to indicate that the value held in the register before being overwritten is now stored on the stack. This prevents writing any other value to the register from triggering the storage of the previous value on the stack.

[0085] For some processor designs, writing the new value to the caller-stored register 214 inherently allows sufficient time for a reliable read before the old value is overwritten. However, in other processor designs, it may be necessary to introduce delay elements to postpone the write until the read is complete.

[0086] After the interrupt handler returns, logic unit 228 reads the LSS status bits again to determine which of the caller-saved registers 214 has been saved to the stack. It pops the saved register value from the stack using the current CSP register value and the associated fixed offset. Processor 200 then pops the LSS, CSP, and PC values ​​from the stack, causing execution to return to the original routine that was executing before the interrupt was received.

[0087] Now refer to Figures 3 to 10 A more detailed description Figure 2 The operation of system 20 is shown.

[0088] Figure 3 A timing diagram illustrating the process of implementing the present invention is shown, through which processor 200 processes receive interrupt requests while executing thread 300.

[0089] Should be combined Figure 3 View Figure 4 Several schematic diagrams are shown illustrating the state of the stack stored in memory 202 during various stages of the execution of thread 300 and interrupt handler 302 by processor 200. The stack is managed by processor 200 and, in this example, has a fixed starting address (starting point) within memory 202.

[0090] Initially, at stage 304, processor 200 executes thread 300. At time 312, processor 200 receives a hardware interrupt request. Stack state 312' describes the stack at time 312. Shown is the stack pointer (SP) 322, used stack space 324, and available stack space 326. SP 322 includes the address of data recently added (pushed) to the stack, limiting the used stack space 324 in which the stack data required by thread 300 and any other stack data required for normal operation are stored. The size of the used stack space 324 is not limited to the size shown in stack state 312', but can be any size. Below SP 322 is the available stack space 326, which includes the portion of available memory 202 that can be used for the stack. While thread 300 is executing, SP 322 (and therefore the sizes of used stack space 324 and available stack space 326) can change as processor 200 pushes and pops data from the stack as needed by thread 300.

[0091] Under normal operation, when processor 200 adds a data item to the stack, the data item is written to the address following the address indicated by SP 322, and SP 322 is adjusted according to the size of the data item being written (in...). Figure 4 , Figures 6-7 and Figures 9-10 In the example shown, it goes down, but it can also increment or decrement in the same way. As previously mentioned, the process of adding data items to the stack is referred to herein as a "push" operation. When processor 200 pops a data item from the stack, the position pointed to by SP 322 is adjusted by SP 322 (in... Figure 4 , Figures 6-7 and Figures 9-10 In the example shown, the data item is removed by the size of the stack (upwards) to release it. As mentioned earlier, the process of clearing data items from the stack is referred to as the "pop" operation in this document.

[0092] When an interrupt request is received at time 312, processor 200 begins phase 306, in which it transitions from executing thread 300 to handling the interrupt request. During phase 306, processor 200 pushes the program counter (PC), local memory state (LSS), and context stack pointer (CSP) associated with thread 300 onto the stack. SP 322 is then further adjusted to reserve a stack portion equal to the stack frame size, and CSP 328 is set to equal SP 322. All status bits associated with the caller-saved registers are then set to "unsaved." The term "unsaved" as used herein describes the state of the status bits, where the status bits are set to values ​​indicating that the values ​​stored in the associated registers have not been pushed onto the stack since the start of the current program execution. Once these steps have been performed, processor 200 is able to begin executing interrupt handler 302 at time 314. It will be understood that these steps are not limited to the order shown above, but can be performed in any reasonable order. In some implementations, assuming ideal memory conditions, the above steps can be completed within three clock cycles.

[0093] Stack state 314 describes the state of the stack at time 314 after the steps listed above are completed during stage 306. SP 322 has been downsized by ten entries (e.g., ten 32-bit words), thereby reducing the size of the available stack space 326. These ten entries include the PC, LSS, and CSP (referred to as "link entries" 330) and a reserved entry 332. In this example, there are seven reserved entries 332, corresponding to the number of registers saved by the caller, i.e., the stack frame size excluding the PC, LSS, and CSP. However, the number of reserved entries 332 is not limited to seven, but can be any number, and therefore the stack frame size is not limited to ten entries as shown in this example. In some examples, the number of reserved entries 332 is equal to eight, resulting in a stack frame size of eleven entries. As previously mentioned, the values ​​stored in link entries 330 and reserved entries 332 are referred to here as the context data of interrupt handler 302.

[0094] CSP 328 is set to be equal to SP 322. Note that the value in CSP register 328 differs from the value stored in link entry 330. The CSP stored in link entry 330 includes the address of the context data for thread 300, while CSP 328 includes the address of the context data for interrupt handler 302.

[0095] During the execution of interrupt handler 302, in stage 308, processor 200 updates the values ​​stored in two of the caller-saved registers. As described above, when processor 200 updates the values ​​stored in the caller-saved registers, it simultaneously stores the previous value in the appropriate reserved entry 332. As previously stated, processor 200 stores the previous value at the address specified by CSP328 minus the offset specified by the particular register number (assuming the stack pointer value increases as the stack grows). When this occurs, the status bit associated with the updated register is updated to "saved". The term "saved" as used herein describes the state of the status bit, where the status bit is set to a value indicating that the value saved in the associated register has been pushed onto the stack.

[0096] Similarly, during the execution of interrupt handler 302, at stage 308, processor 200 uses normal stack management to push and pop additional data required by interrupt handler 302 onto and off the stack. Stack state 316' describes the stack at time 316 during the execution of interrupt handler 302. It can be seen that the register values ​​334 saved by the two callers are already stored on the stack, and the values ​​that have been pushed onto the stack during the execution of interrupt handler 302 are included with additional stack space 336. SP 322 is adjusted accordingly, thereby reducing the amount of available stack space 326.

[0097] At time 318, processor 200 completes the execution of interrupt handler 302 and begins phase 310, in which it switches back to execution thread 300. Stack state 318' describes the stack at time 318. After the execution of interrupt handler 302 has completed, processor 200 has popped the data stored in the additional used stack space 336 from the stack, and SP 322 has been adjusted back to its position in CSP 328 accordingly. The data stored in the additional used stack space 336 is no longer needed.

[0098] During phase 310, processor 200 restores the context data from the stack to the caller-saved register 214 to continue execution of thread 300. To do this, processor 200 uses the status bits in LSS register 226 to determine which register values ​​have been pushed onto the stack by processor 200 and therefore need to be restored, and which register values ​​have not been pushed onto the stack and therefore do not need to be restored. (Refer to reference...) Figure 2The caller-saved register push process outlined in the overview does not overwrite registers not yet pushed onto the stack (as indicated by their associated status bits), thus retaining the same values ​​at time 312 as they did before processor 200 executed interrupt handler 302. Processor 200 can easily determine the address of the pushed register value 332 on the stack, as the address is given by the CSP and the specific register number, as shown in equation (1). Therefore, processor 200 restores the pushed register value 332 to its associated caller-saved register before restoring link entries 330 (PC, LSS, and CSP) for thread 300 and updating the stack pointer SP accordingly.

[0099] Once the context data has been restored, processor 200 resumes execution of thread 300 at time 320. Stack state 320' describes the stack at time 320. It can be seen that stack state 320' is the same as stack state 312', indicating that processor 200 continues execution of thread 300 at the same point (time 312) when it paused execution to begin execution of interrupt handler 302. Context data pushed onto the stack for execution of interrupt handler 302 is no longer needed, and SP 322 has been adjusted accordingly. Processor 200 then continues execution of thread 300 in stage 311.

[0100] Figure 5 A schematic diagram illustrating the time-dependent process of implementing the present invention is shown, through which the processor 200 processes the execution of the first interrupt handler 402 being preempted (interrupted) by a second interrupt request.

[0101] Should be combined Figure 5 View Figure 6 and Figure 7 Several schematic diagrams are shown illustrating the state of the stack stored in memory 202 during various stages of execution of thread 400, first interrupt handler 402, and second interrupt handler 404 by processor 200.

[0102] Initially, at stage 406, processor 200 executes thread 400. At time 424, processor 200 receives the first interrupt request. Stack state 424' illustrates the stack at time 424. SP 322 is shown, above and including it is the used stack space 324, and below it is the available stack space 326. The size of the used stack space 324 (and therefore the size of the available stack space 326 and the position of SP 322) is not limited to those shown in stack state 424', but can be any value.

[0103] When the first interrupt request is received at time 424, processor 200 begins phase 408, in which it transitions from execution thread 400 to handling the interrupt request. The steps taken by processor 200 to transfer from execution thread 400 to the first interrupt handler 402 are the same as previously referenced. Figure 3 and Figure 4 The steps outlined are the same.

[0104] At time 426, processor 200 begins execution of the first interrupt handler 402. Stack state 426' describes the stack at time 426. From stack state 426', it can be seen that the PC, LSS, and CSP (link entry 330a) associated with the thread have been pushed onto the stack, and SP 322 has been adjusted to reserve the stack frame size, creating reserved entry 332a. The values ​​stored in link entry 330a and reserved entry 332a include the context data of the first interrupt handler 402, and CSP 328a has been adjusted to point to the context data of the first interrupt handler 402. The size of the available stack space 326 has been reduced accordingly.

[0105] During phase 410, processor 200 executes the first interrupt handler 402. At time 428, processor 200 receives a second interrupt request. Stack state 428' describes the stack at time 428. During phase 410, processor 200 has pushed the caller-saved register value 334a onto the stack, storing the value at the appropriate location within the stack as given in equation (1). Simultaneously, the register holding the pushed value is updated to the new value, and the status bits held in LSS register 226 and associated with the pushed register are set to "saved". During the execution of the first interrupt handler 402, an additional portion of the used stack space 336a has been pushed onto the stack, and SP 322 is adjusted accordingly, thereby reducing the amount of available stack space 326.

[0106] The second interrupt request received by processor 200 at time 428 has a higher priority than the first interrupt; therefore, at stage 412, processor 200 switches from executing the first interrupt handler 402 to the second interrupt handler 404. The steps taken by processor 200 to switch from executing thread 400 to the first interrupt handler 402 are the same as previously referenced. Figure 3 and Figure 4 The steps outlined are the same. Stack state 430' describes the stack at time 430, when processor 200 has successfully transferred from executing the first interrupt handler 402 to the second interrupt handler 404.

[0107] As can be seen from stack state 430', processor 200 has pushed the link entry 330b associated with the first interrupt handler 302 onto the stack, leaving the used stack space associated with the first interrupt handler 336a intact. Processor 200 has reserved the stack frame size, generating a reserved entry 332b, and SP 322 has been adjusted accordingly. CSP 328b associated with the second interrupt handler 404 has been adjusted to be equal to SP 322, and the size of the available stack space 326 has been reduced accordingly. The values ​​stored in link entry 330b and reserved entry 332b include the context data of the second interrupt handler 404.

[0108] Processor 200 then executes the second interrupt handler 404 in stage 414. Stack state 432' describes the stack at time 432. From stack state 432', it can be seen that processor 200 has pushed the four caller-saved register values ​​334b ​​onto the stack, storing the values ​​in the appropriate locations on the stack as given in equation (1). During the execution of the second interrupt handler 404, additional portions of the used stack space 336a have been pushed onto the stack, and SP 322 has been adjusted accordingly, thereby reducing the amount of available stack space 326.

[0109] At time 434, processor 200 stops executing the second interrupt handler 404 and begins to return to executing the first interrupt handler 402. Stack state 434' describes the stack at time 434. From stack state 434', it can be seen that the used stack space 336b associated with the second interrupt handler 404 has been popped from the stack, and SP 322 has been adjusted accordingly.

[0110] During stage 416, processor 200 restores the context data associated with the second interrupt handler 404 from the stack to the caller-saved register 214 in order to continue execution of the first interrupt handler 402. To do this, processor 200 uses status bits in the LSS register 226 to determine which register values ​​have been pushed onto the stack by processor 20 and therefore need to be restored, and which register values ​​have not been pushed onto the stack and therefore do not need to be restored. Therefore, before restoring the link entries 330b (PC, LSS, and CSP) of the first interrupt handler 402 and removing the context data of the second interrupt handler 404 from the stack, processor 200 restores the pushed register values ​​332b to their associated caller-saved registers, adjusting the stack pointer 322 accordingly.

[0111] Once the context data of the second interrupt handler 404 has been restored to the caller-saved register 214, the processor 200 resumes execution of the first interrupt handler 402 at time 436. Stack state 436' describes the stack at time 436. It can be seen that stack state 436' is the same as stack state 428', indicating that the processor 200 resumes execution of the first interrupt handler 402 at the same point (time 428) when it paused execution of the first interrupt handler 402 to begin execution of the second interrupt handler 404. The context data pushed onto the stack for the execution of the second interrupt handler 404 has been popped from the stack, and SP 322 has been adjusted accordingly. The processor 200 then resumes execution of the first interrupt handler 402 at stage 418.

[0112] At time 438, processor 200 stops executing the first interrupt handler 402 and begins to return to execution thread 400. Stack state 438' describes the stack at time 438. From stack state 438', it can be seen that the used stack space associated with the first interrupt handler 402 has been freed from the stack, and SP 322 has been adjusted accordingly. Furthermore, processor 200 has pushed the register value 334a saved by the third caller onto the stack.

[0113] During phase 420, processor 200 restores the context data associated with the first interrupt handler 402 on the stack to the caller-saved register 214 in order to continue execution of thread 400. To do this, processor 200 uses status bits within the LSS register 226 to determine which register values ​​have been pushed onto the stack by processor 200 and therefore need to be restored, and which register values ​​have not been pushed onto the stack and therefore do not need to be restored. Therefore, before restoring the stack of link entries 330b (PC, LSS, and CSP) and releasing the context data of the second interrupt handler 404 by adjusting the stack pointer 322 accordingly, processor 200 restores the pushed register values ​​334b ​​to their associated caller-saved registers.

[0114] Once the context data of the first interrupt handler 404 has been restored to the caller-saved register 214, the processor 200 resumes execution of thread 400 at time 440. Stack state 440' describes the stack at time 440. It can be seen that stack state 440' is the same as stack state 424', indicating that the processor 200 continues execution of thread 400 at the same point (time 424) when it paused execution of thread 400 to begin execution of the first interrupt handler 402. The context data pushed onto the stack for the execution of the first interrupt handler 404 has been popped from the stack, and SP 322 has been adjusted accordingly. The processor 200 then resumes execution of thread 400 at stage 422.

[0115] Figure 8 A schematic diagram illustrating the time-dependent process of implementing the present invention is shown, through which the processor 200 is able to perform a fast interrupt transition (i.e., interrupt tail chain) when one interrupt returns and another interrupt is suspended.

[0116] Should be combined Figure 8 View Figure 9 and Figure 10 Several schematic diagrams are shown illustrating the state of the stack stored in memory 202 during various stages of execution of thread 500 and interrupt handler 502 by processor 200.

[0117] Initially, at stage 504, processor 200 executes thread 500. At time 518, processor 200 receives the first interrupt request. Stack state 518' illustrates the stack at time 518. SP 322 is shown above and includes used stack space 324, and below is available stack space 326. The size of used stack space 324 (and therefore the size of available stack space 326 and the location of SP 322) is not limited to those shown in stack state 518', but can be any value.

[0118] When the first interrupt request is received at time 518, processor 200 begins phase 506, in which it transitions from execution thread 500 to handling the interrupt request. The steps taken by processor 200 to transfer from execution thread 500 to interrupt handler 502 are the same as previously referenced. Figure 3 and Figure 4 The steps outlined are the same.

[0119] At time 520, processor 200 begins execution of interrupt handler 502. Stack state 520' describes the stack at time 520. From stack state 520', it can be seen that the PC, LSS, and CSP (link entry 330c) associated with thread 500 have been pushed onto the stack, and SP 322 has been adjusted to reserve the stack frame size, creating reserved entry 332. The values ​​stored in link entry 330c and reserved entry 332 include the context data of interrupt handler 502, and CSP 328 has been adjusted to point to the context data of interrupt handler 502. The size of the available stack space 326 has been reduced accordingly.

[0120] During phase 508, processor 200 executes interrupt handler 502. At time 522, processor 200 receives a second interrupt request. Stack state 522' describes the stack at time 522. During phase 508, processor 200 has pushed the two caller-saved register values ​​334 onto the stack, storing the values ​​at the appropriate locations within the stack given by equation (1). During the execution of interrupt handler 502, additional portions of the used stack space 336c have been pushed onto the stack, and SP 322 has been adjusted accordingly, thereby reducing the amount of available stack space 326.

[0121] The second interrupt request received by the processor 200 at time 428 has the same or lower priority as the first interrupt request. Therefore, the processor 200 continues to execute the interrupt handler 502 of the first interrupt request until it is completed at time 524, and the second interrupt request remains suspended.

[0122] Stack state 524' describes the stack at time 524. At time 524, processor 200 stops executing interrupt handler 502 associated with the first interrupt request. As can be seen from stack state 524', the used stack space 336c associated with interrupt handler 502 associated with the first interrupt request has been freed from the stack, and SP 322 has been adjusted accordingly.

[0123] If processor 200 does not perform a fast interrupt transition as disclosed herein, then immediate stack management and, as referred to Figure 3 and Figure 4 Before the context data saving steps required to transfer from execution thread 500 to another interrupt handler 502 as outlined, processor 200 restores the context data associated with interrupt handler 502 to caller-saved register 214 for execution thread 500.

[0124] Conversely, to reduce the number of memory transactions, processor 200 does not restore context data to the caller-saved register 214 during stage 510. The applicant has recognized that the context data of interrupt handler 502 does not need to be restored to the caller-saved register 214. Furthermore, the CSP 328 and LSS stored in the caller-saved register 214 can remain the same because the context data required to resume execution of thread 500 remains unchanged after the execution of interrupt handler 502 associated with the second interrupt request. Therefore, process 200 simply retrieves the new address value of interrupt handler 502 associated with the second interrupt request from the interrupt vector table in memory 202 and updates the PC accordingly, while keeping the CSP 328, LSS, and context data stored on the stack the same.

[0125] After the fast interrupt transition is executed in phase 510, processor 200 begins execution of interrupt handler 502 associated with the second interrupt request at time 526. Stack state 526' illustrates the stack at time 526. As can be seen from stack state 526', the stack state has not changed since time 524 because the context data stored in the stack was not modified by processor 200 during phase 510.

[0126] During phase 508, processor 200 executes interrupt handler 502 associated with the second interrupt request. Stack state 528' describes the stack at time 528. During phase 508, processor 200 has pushed two additional caller-saved register values ​​334 onto the stack, storing the values ​​in the appropriate locations within the stack as given in equation (1). During the execution of interrupt handler 502 associated with the second interrupt request, additional portions of the used stack space 336d have been pushed onto the stack, and SP 322 has been adjusted accordingly, thereby reducing the amount of available stack space 326.

[0127] At time 530, processor 200 stops executing interrupt handler 502 associated with the second interrupt request and begins to return to execution thread 500. Stack state 530' describes the stack at time 530. From stack state 530', it can be seen that the used stack space associated with interrupt handler 502 of the second interrupt request has been freed from the stack, and SP 322 has been adjusted accordingly.

[0128] During phase 514, processor 200 restores the context data associated with interrupt handler 502 from the stack to caller-saved register 214 in order to continue execution of thread 500. To do this, processor 200 uses status bits in LSS register 226 to determine which register values ​​have been pushed onto the stack by processor 200 and therefore need to be restored, and which register values ​​have not been pushed onto the stack and therefore do not need to be restored. Therefore, before restoring link entries 330 (PC, LSS, and CSP) and freeing the space occupied by the context data of interrupt handler 502 by adjusting the stack pointer 322 accordingly, processor 200 restores the pushed register values ​​334 to their associated caller-saved registers.

[0129] Once the context data of interrupt handler 502 has been restored to the caller-saved register 214, processor 200 resumes execution of thread 500 at time 532. Stack state 532' describes the stack at time 532. It can be seen that stack state 532' is the same as stack state 518', indicating that processor 200 resumes execution of thread 500 at the same point (time 518) when it paused execution of thread 500 to begin execution of interrupt handler 502 associated with the first interrupt request. The context data pushed onto the stack for the execution of interrupt handler 502 has been popped from the stack, and SP 322 has been adjusted accordingly. Processor 200 then resumes execution of thread 500 in stage 516.

[0130] Figure 11 A schematic diagram illustrating another system-on-chip 60 implementing the invention is shown, configured for particularly efficient memory usage. Instead of reserving stack frames large enough to hold all delayed push register values ​​during interrupts on the main stack, this SoC 60 maintains a context stack separate from the main stack. The main stack and context stack are described below as residing in a common stack area of ​​memory, but they can alternatively be stored in completely separate memory areas.

[0131] SoC 60 includes a processor 600 coupled to memory 602. Processor 600 includes... Figure 2 The processor 200 shown has the same components 604-624 as components 204-224, including eight caller-saved registers 614, and... Figure 2 The only difference between the LSS register 226 and logic unit 228 shown is that the LSS register 626 and logic unit 628 are the same.

[0132] LSS register 626 is a 32-bit register, consisting of two parts: eight status bits 630 and twenty-four position bits 632. The operation of status bits 630 is exactly the same as that of the status bits in LSS register 226, as shown in the reference... Figure 2 As described. The operation of processor 600, including position bit 632, will be referred to below. Figures 12 to 15 Further description. In addition, logic circuit 628 is composed of... Figure 2 The logic circuit 228 shown is modified because it uses the values ​​stored in position bit 632 and status bit 630 to perform logic, as explained below.

[0133] Figure 12 A schematic diagram of LSS register 626 is shown. In this example, register file 608 includes eight caller-saved registers 614. Status bits 630 and occupied bits b8-b7 are shown.31 The 24 position bits 632 are divided into eight groups of three bits each. The three bits in each group, p0-p7, are used as position registers for the corresponding one in the caller-saved registers 614. Each position register can store a position value that encodes the address of the corresponding stack location in register 614 as an offset relative to the context stack pointer value when the register was pushed onto the context stack. The three bits provide the ability to allocate eight unique position values. Of course, more bits can be provided if there are more than eight caller-saved registers.

[0134] Figure 13 A schematic diagram illustrating the time-related process of implementing the present invention is shown, in which the processor 600 processes the execution of thread 700, which is preempted (interrupted) by a first interrupt handler 702, and the first interrupt handler 702 is then preempted by a second interrupt handler 704.

[0135] Should be combined Figure 13 View Figure 14 and Figure 15 Several schematic diagrams are shown illustrating the state of the stack area of ​​memory 602 during various stages of execution of thread 700, first interrupt handler 702 and second interrupt handler 704 by processor 600.

[0136] Initially, at stage 706, processor 600 executes thread 700. At time 724, processor 600 receives the first interrupt request. Stack state 724' illustrates the stack region at time 724. SP 322 is shown above and includes the used main stack space 324, below which is the available main stack space 326. The size of the used main stack space 324 (and therefore the size of the available main stack space 326 and the location of SP 322) is not limited to those shown in stack state 724', but can be any value.

[0137] Also shown is CSP 328, which points to the location of a portion of a designated stack area dedicated to storing context data (hereinafter referred to as the context stack). Below and including CSP 328 is the available context stack space 740. The size of this portion of the stack area dedicated to storing context data is not limited to the size shown in stack state 724', but can be any size. In some embodiments, context stack data 330, 742 may be stored completely separately from the main stack data 324 in different areas of memory.

[0138] When the first interrupt request is received at time 724, processor 600 begins phase 708, in which it transitions from executing thread 700 to handling the interrupt request. To transfer the execution of thread 700 to the first interrupt handler 702, processor 600 stores the PC, LSS, and CSP associated with thread 700 at the location specified by CSP 328. Processor 600 then sets status bit 630 to "unsaved" and retrieves the address of the interrupt handler associated with the received interrupt request from the interrupt vector table stored in memory 602, and stores it in the PC register.

[0139] At time 726, processor 600 begins executing the first interrupt handler 702. Stack state 726' describes the stack region at time 726. As can be seen from stack state 726', the PC, LSS, and CSP (link entry 330e) associated with thread 700 have been stored in the context stack, and therefore the size of the available context stack space 740 has been reduced accordingly.

[0140] During phase 710, processor 600 executes the first interrupt handler 702. During this time, processor 600 updates the values ​​stored in the two caller-saved registers 614. As each of these updates occurs, processor 600 simultaneously stores the previously saved value in each register at the next available location in the context stack. In some examples, processor 600 may determine the next available location by counting the number of “saved” flags or by incrementing the CSP with each additional entry. When this happens, processor 600 updates the status bit 630 associated with the register to “saved” (1'b) and updates the associated position bit 632 to indicate the location in the context stack where the previous value was stored. For example, if the previous register value was stored at the first available location in the context stack adjacent to the linked value 330e, the value in the associated position bit of that register 632 is updated to indicate position zero (i.e., binary 000'b).

[0141] At time 728, processor 600 receives a second interrupt request. Stack state 728' describes the stack region at time 728. From stack state 728', it can be seen that during stage 710, processor 600 stores the register entries 742e saved in registers 4 and 5 (preceded by register 5) on the context stack, and the available context stack space 740 is reduced accordingly. Therefore, the values ​​stored in the corresponding position bit portions p4 and p5 are updated to zero (000'b) and 1 (001'b), respectively, and the corresponding status bits b4 and b5 are updated to "saved" (1'b). During the execution of the first interrupt handler 702, additional portions of the used main stack space 324 are pushed onto the main stack, and SP 322 is adjusted accordingly, thereby reducing the amount of available main stack space 326.

[0142] The second interrupt request received by processor 600 at time 728 has a higher priority than the first interrupt, therefore processor 600 transitions from executing the first interrupt handler 702 to the second interrupt handler 704 at stage 712. To switch from executing the first interrupt handler 702 to the second interrupt handler 704, processor 600 first updates the location of CSP 328 to the next available location in the context stack. Processor 600 then stores the PC, LSS, and CSP associated with the first interrupt handler 702 at the location specified by CSP 328. Processor 600 then sets the status bit 630 to "Unsaved" = 0'b. Processor 600 then retrieves the address of the interrupt handler associated with the second interrupt request from the interrupt vector table stored in memory 602 and saves it in the PC register.

[0143] Stack state 730' indicates that at time 730, the processor 600 has successfully transferred execution from the first interrupt handler 702 to the second interrupt handler 704. Stack state 730' shows that the PC, LSS, and CSP (link entry 330f) associated with the first interrupt handler 702 have been stored in the context stack, and the size of the available context stack space 740 has been reduced accordingly.

[0144] Processor 600 then executes second interrupt handler 704 in stage 714. During this time, processor 600 updates the value stored in one of the caller-saved registers 614. As this update occurs, processor 600 simultaneously stores the previously saved value in the register at the next available location in the context stack. When this happens, processor 600 updates the status bit 630 associated with the register to "saved" (1'b) and updates the associated position bit 632 to indicate the location in the context stack where the previous value was stored. For example, if the previous register value was stored at the first available location in the context stack adjacent to the link value 330f, the value in the associated position bit of that register 632 is updated to indicate position zero (i.e., binary 000'b).

[0145] At time 732, processor 600 stops executing the second interrupt handler 704 and begins to return to executing the first interrupt handler 702. Stack state 732' describes the stack region at time 732. From stack state 732', it can be seen that during stage 714, processor 600 stores the register entry 742f saved in the caller-saved register in the context stack, and the available context stack space 740 has been reduced accordingly. Thus, the value stored in the corresponding position bit portion p3 has been updated to zero (000'b), and the corresponding status bit has been updated to "saved" (1'b). During the execution of the first interrupt handler 702, additional portions of the used stack space 324 have been pushed onto the main stack, and SP 322 has been adjusted accordingly, thereby reducing the amount of available main stack space 326.

[0146] As can be seen from stack state 732', by combining position bit 632 and maintaining the context stack independently of the main stack, the number of entries required to store context data is reduced because there is no need to reserve (and thus waste) stack entries. Instead, context data leaves no unoccupied stack entries, thus further optimizing memory usage.

[0147] During stage 716, processor 600 restores the context data associated with the second interrupt handler 704 from the context stack to the caller-saved register 614 in order to continue execution of the first interrupt handler 702. To do this, processor 600 uses the status bit 630 in the LSS register 626 to determine which register values ​​have been pushed onto the context stack and therefore need to be restored. Processor 600 uses the position bit 632 in the LSS register 626 to determine the address where the respective register value of each caller-saved register is stored by adding the corresponding offset to the current CSP address value. In this case, register 3 is at position zero (000'b). Therefore, processor 600 restores the pushed register value 742f to the caller-saved register 3 before restoring the link entries 330f (PC, LSS, and CSP) of the first interrupt handler 702 and frees up the space occupied by the context data of the second interrupt handler 704. In addition, the processor 600 releases the normal stack data associated with the second interrupt handler 704 from the main stack and adjusts SP322 accordingly, reducing the size of the used main stack space 324 and increasing the size of the available main stack space 326.

[0148] Once the context data of the second interrupt handler 704 has been restored to the caller-saved register 614, the processor 600 resumes execution of the first interrupt handler 702 at time 734. Stack state 734' describes the stack region at time 734. It can be seen that stack state 734' is the same as stack state 728', indicating that the processor 600 continues execution of the first interrupt handler 702 at the same point (time 728) when it paused execution of the first interrupt handler 702 to begin execution of the second interrupt handler 704. The context data pushed onto the context stack for the execution of the second interrupt handler 704 has been popped from the context stack. The processor 600 then continues execution of the first interrupt handler 702 in stage 718.

[0149] At time 736, processor 600 stops executing the first interrupt handler 702 and begins to return to execution thread 700. Stack state 736' describes the stack region at time 736. From stack state 736', it can be seen that during stage 718, processor 600 stores another register entry 742e saved in caller-saved register 1 in the context stack (position value 2), and the available context stack space 740 has been reduced accordingly. Therefore, the value stored in the corresponding position bit portion p1 has been updated to 2 (010'b), and the corresponding status bit b1 has been updated to "saved" (1'b).

[0150] During phase 720, processor 600 restores the context data associated with thread 700 from the context stack to the caller-saved register 614 in order to continue execution of thread 700. To do this, processor 600 uses the status bit 630 in the LSS register 626 to determine which register values ​​have been pushed onto the context stack by processor 600 and therefore need to be restored. Processor 600 uses the position bit 632 in the LSS register 626 to determine the location where the register value of each register is stored (in this case, positions 0 (000'b), 1 (001'b), and 2 (010'b) of registers 4, 5, and 1, respectively). Therefore, processor 600 restores the pushed register values ​​742e to the caller-saved registers 4, 5, and 3 before restoring the link entries 330e (PC, LSS, and CSP) of thread 700 and freeing the space occupied by the context data of the first interrupt handler 702 from the context stack. In addition, the processor 600 releases the normal stack data associated with the first interrupt handler 702 from the main stack and adjusts SP 322 accordingly, reducing the size of the used main stack space 324 and increasing the size of the available main stack space 326.

[0151] Once the context data of the first interrupt handler 702 has been restored to the caller-saved register 614, the processor 600 resumes execution of thread 700 at time 738. Stack state 738' describes the stack at time 738. It can be seen that stack state 738' is the same as stack state 724', indicating that the processor 600 continues execution of thread 700 at the same point (at time 724) when it suspended execution of thread 700 to begin execution of the first interrupt handler 702. The context data pushed onto the context stack for the execution of the first interrupt handler 702 has been cleared from the context stack. The processor 600 then continues execution of thread 700 at stage 722.

[0152] While the hardware-based interrupt handling procedures disclosed herein are particularly useful for handling hardware interrupts (e.g., those generated by peripherals such as radio transceivers), in some implementations, they are less useful for handling software interrupts (i.e., those generated by devices such as Arm). TM These instructions can be used when an interrupt is generated by the execution of a special software instruction (SVC) on the processor, or even during a routine function call. This reduces the number of instructions the processor needs to fetch and execute.

[0153] Those skilled in the art will recognize that the invention has been described by way of one or more specific embodiments, but is not limited to these embodiments; many variations and modifications are possible within the scope of the appended claims.

Claims

1. A processing apparatus, comprising a processor, wherein: The processor includes multiple delayed push-in processor registers; The processor includes a processor register control circuit; The processor register control circuit includes multiple status registers, each status register corresponding to its own different delay push register; The processor register control circuit is configured to detect the writing of a new value to the register in the delayed push register; The processor register control circuitry is configured to determine, in response to the detection, whether the status register of the delayed push register has a first value indicating an unsaved state of the delayed push register; and The processor register control circuit is configured such that, when the status register is determined to have the first value: before writing the new value to the delayed push register is completed, the current value is read from the delayed push register; and the current value is written to memory. And set the status register of the delayed push register to a second value indicating the saved state of the delayed push register.

2. The processing apparatus of claim 1, further comprising the memory, wherein the processor register control circuitry is configured to write the current value of the delay-push register into the memory.

3. The processing apparatus according to claim 1 or 2, wherein, The processor includes one or more hardware interrupt inputs for receiving hardware interrupt requests, and wherein the processor register control circuitry is configured to set each of the plurality of status registers to the first value in response to the processor receiving a hardware interrupt request.

4. The processing apparatus according to claim 1 or 2, comprising storing an interrupt vector table and a memory storing software including one or more interrupt handlers, each interrupt handler being stored at a respective address identified in the interrupt vector table, and wherein, The processor is configured to: in response to receiving a hardware interrupt request, perform a context switch and jump to one of the interrupt handlers.

5. The processing apparatus according to claim 1 or 2, wherein, The processor includes a stack pointer register and other processor registers, and is configured to use a stack pointer stored in the stack pointer register to determine the memory address on which the value of the other processor registers is pushed.

6. The processing apparatus according to claim 5, wherein, The processor register control circuitry includes a context stack pointer register and is configured to use the context stack pointer value stored in the context stack pointer register to determine the memory address on which the current value of the delayed push register is written.

7. The processing apparatus according to claim 6, wherein, The processor is configured to, in response to receiving a hardware interrupt request, change the stack pointer by an amount corresponding to at least a portion of the values ​​of all the multiple delayed push registers and the context stack pointer register in the memory.

8. The processing apparatus according to claim 6, wherein, The processor register control circuitry is configured to, in response to receiving a hardware interrupt request, push one or more of the program counter, the status register, and the context stack pointer into the memory at an address determined by the stack pointer.

9. The processing apparatus according to claim 6, wherein, The processor register control circuitry is configured to copy values ​​from the stack pointer register to the context stack pointer register.

10. The processing apparatus according to claim 6, wherein, The processor register control circuitry is configured to determine the address at which a value to be pushed into a processor register is delayed by applying a constant offset to the value in the context stack pointer register, wherein each delayed push register in the delayed push registers is associated with its own distinct constant offset.

11. The processing apparatus according to claim 6, wherein, The processor register control circuitry is configured to push delayed push registers into consecutive memory addresses within the context stack structure of the memory by pushing each delayed push register into the next unoccupied address after the context stack pointer in the memory.

12. The processing apparatus according to claim 11, wherein, The processor register control circuit includes multiple multi-bit location registers, each corresponding to a different delayed push register, and wherein the processor register control circuit is configured to: when a delayed push register is pushed onto an address in the memory, store a value in the corresponding location register, the value of which encodes the address relative to the value of the context stack pointer register.

13. The processing apparatus according to claim 11, wherein, The processor register control circuitry is configured to, in response to receiving a hardware interrupt request, push one or more of the program counter, the status register, and the context stack pointer into the memory at an address determined by the context stack pointer value stored in the context stack pointer register.

14. The processing apparatus according to claim 1 or 2, wherein, The processor is configured to perform context switching, and when a context switch to a new context is performed, to push the values ​​stored in each delay push register into the memory until the corresponding delay push register is written in the new context.

15. The processing apparatus according to claim 1 or 2, wherein, The processor register control circuit is configured to: in response to detecting a return from an interrupt handler routine, determine whether each status register corresponding to the plurality of delayed push registers holds the second value, and when the status register holds the second value, read the push value of the corresponding delayed push register from the memory and write the push value into the delayed push register.

16. The processing apparatus according to claim 1 or 2, wherein, The processing device supports nested interrupts.

17. The processing apparatus according to claim 1 or 2, wherein, The processor register control circuitry is configured to support tail-chain interrupt handling, wherein two or more interrupts are processed consecutively without returning to the process being executed when the first interrupt request was received.

18. The processing apparatus according to claim 1 or 2, wherein, The processor is configured not to pop any pushed status register values ​​when returning from the first interrupt handler when the second interrupt is suspended.

19. The processing apparatus according to claim 1 or 2, wherein, The status register includes various binary flags within a multi-bit status register.

20. The processing apparatus according to claim 1 or 2, wherein, The processing device is a system-on-a-chip.

21. A method of operating a processing device, wherein: The processing device includes a processor; The processor includes multiple delayed push-in processor registers; as well as The processor includes multiple status registers, each corresponding to a different delay push register. The method includes: Detect the writing of a new value to the register in the delayed push register; In response to the detection, it is determined that the status register of the delayed push register has a first value indicating an unsaved state of the delayed push register; and In response to the determination, the current value is read from the delayed push register before the new value is written to the delayed push register. Write the current value to memory; and Set the status register of the delayed push register to a second value that indicates the saved state of the delayed push register.

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