A method and system for constructing and screening a spatial and feature coupled encoded geographic data index

Abstract

The application discloses a kind of space and feature coupling coding geographic data index construction and screening method and system, belong to geographic information system and distributed computing technical field.The method constructs coupling identifier containing spatial position coding domain and business feature coding domain, the identifier is the fixed bit width binary integer of adaptation processor register bit width, support two coding domain high-low configuration, and construct ordered index with it as sorting key;When screening, according to request generation space bit mask and feature bit mask, execute branchless bit operation sequence to coupling identifier, complete double determination of spatial correlation and business feature matching in single instruction stream;System supports the dynamic maintenance of fragment based on routing mapping relationship adjustment, and fragment operation only adjusts routing mapping relationship while identifier coding is unchanged, to avoid piece by piece rehashing and recoding.System includes coupling coding module, storage module, bit mask screening engine and communication module.

Description

Technical Field

[0001] This invention relates to the field of computer data processing and information retrieval technology, and in particular to the underlying index construction and composite filtering technology in Geographic Information Systems (GIS) and Location-Based Services (LBS), specifically to a method and system for constructing and filtering geographic data indexes using spatial and feature coupling coding. Background Technology

[0002] In the field of location-based services (LBS), high-frequency system requests in scenarios such as local services, instant delivery, and ride-hailing generally exhibit complex filtering requirements that combine spatial location constraints with multi-dimensional business characteristics. For example, searching for offline merchants within a specified distance that meet specific price tiers, rating levels, or business statuses. These complex filtering requests not only require the system to simultaneously process continuous spatial coordinates and discrete business characteristics, but also place high demands on the underlying computer system's concurrent throughput, I / O addressing efficiency, and low-latency, stable decision-making capabilities, especially maintaining stable response performance under high-concurrency scenarios.

[0003] Currently, to address the aforementioned complex screening requirements, common spatial data screening schemes in existing technologies mainly fall into the following categories:

[0004] (1) Independent spatial indexing mechanism: such as Redis GEO module (based on GeoHash encoding) or MongoDB2dsphere index (based on GeoJSON format). This type of solution can support spatial correlation filtering, but it usually cannot directly complete the filtering of business features at the index layer, so further filtering of the candidate set is still required at the application layer;

[0005] (2) Spatial and feature index separation architecture: such as the traditional relational architecture that separates the spatial index table from the attribute data table. This type of solution usually physically separates the spatial index from the business feature index. It is necessary to obtain the candidate set through the spatial index first, and then perform business feature filtering on the candidate set, which can easily introduce additional I / O access overhead;

[0006] (3) Multi-column composite indexes in traditional relational databases: such as multi-column B+ tree indexes in MySQL or PostgreSQL. This type of solution combines spatial columns and business feature columns into composite index keys, which supports combined queries at the logical level, but its underlying decision-making process usually still relies on multiple sets of control flow-driven "compare-jump" instruction sequences;

[0007] (4) Simple logical concatenation scheme of space and features: The spatial code and feature bitmap are concatenated into the same integer structure. Although this type of scheme achieves merging at the physical storage level, it is still usually necessary to perform spatial prefix comparison and feature mask comparison separately during querying, and to merge the judgment results.

[0008] Analysis revealed that the above solutions typically suffer from the following common problems when handling composite filtering requests that simultaneously contain both spatial location constraints and business characteristic constraints:

[0009] (1) Additional overhead caused by phased serial retrieval. Traditional solutions often adopt a phased processing path of "spatial retrieval → business feature filtering", which often requires obtaining a candidate set through spatial index first, and then performing feature filtering on the candidate set. On the one hand, this processing method may introduce two-stage I / O access and intermediate result transmission overhead, and on the other hand, it also makes the overall processing complexity affected by both the size of the spatial index and the size of the candidate set, which is not conducive to maintaining a relatively stable query latency under high concurrency conditions. In typical high-concurrency scenarios, traditional phased retrieval solutions usually exhibit significant additional query latency and index storage overhead, making it difficult to simultaneously balance response speed and resource utilization efficiency in high-frequency LBS requests;

[0010] (2) The efficiency of simple concatenation schemes is limited. Existing technologies also include schemes that combine spatial encoding and business feature encoding in the same data structure, such as combining spatial encoding values ​​with feature bitmaps into composite keys or integer composite identifiers. However, such "logical concatenation" schemes typically have the following limitations: these schemes usually only achieve the concatenation of spatial encoding and feature encoding at the physical storage level, and have not yet achieved coupling at the logical level of the judgment. During the query process, spatial prefix comparison must still be performed first, followed by feature mask comparison, and the two judgment results must be merged. Therefore, it is difficult to complete synchronous judgment in the same instruction stream.

[0011] From a processor execution perspective, this type of logical concatenation scheme typically involves conditional branches related to the input data. While modern CPUs' branch prediction units (BPUs) can predict based on historical execution patterns, in LBS query scenarios, the spatial distribution and feature combinations of candidate data often exhibit strong dispersion, making it difficult to consistently form stable prediction patterns. When the actual branch direction differs from the prediction result, a "pipeline flush" may be triggered, leading to additional instruction refetching and pipeline recovery overhead, which accumulates into significant latency fluctuations in high-concurrency scenarios.

[0012] The aforementioned conditional branching leads to at least the following problems with this type of scheme: First, the decision-making process still requires multi-step operations, necessitating separate spatial and feature comparisons, making synchronous decision-making within a single instruction stream difficult. Second, merging the results of the two decisions typically relies on additional conditional judgments, which is not conducive to reducing the execution overhead caused by control flow switching. Third, in scenarios with uneven data distribution or high combinatorial dispersion, the execution path is more prone to branch prediction mismatches, further leading to pipeline recovery losses. Therefore, although the aforementioned simple concatenation scheme achieves a certain degree of merging in terms of storage format, it still struggles to achieve synchronous completion of spatial and feature determinations at the underlying execution path, thus limiting query efficiency and response stability.

[0013] (3) Combinatorial explosion and space expansion of multidimensional composite indexes. To support combined queries with different business characteristics, traditional database solutions usually need to pre-build multiple sets of composite indexes, such as "price + rating" indexes, "type + status" indexes, etc. When it is necessary to support flexible combinations of N dimensions, theoretically 2^N composite indexes may need to be built, which can easily lead to large index storage overhead and cause index space expansion. At the same time, since the column order of composite indexes is usually fixed in advance, this type of solution has limited support for ad-hoc queries with high frequency, multidimensional and randomly combined filtering conditions, and may further increase write maintenance overhead in high-frequency update scenarios. Summary of the Invention

[0014] The technical problem to be solved by the present invention

[0015] This invention aims to address the problems in existing LBS composite retrieval technologies, such as the separation of spatial index and business feature index, large overhead of secondary filtering of candidate sets, index space expansion, and insufficient stability of decision path execution. It provides a method and system for constructing and filtering geographic data indexes with coupled spatial and feature encoding to improve query efficiency, resource utilization efficiency, and response stability in composite filtering scenarios.

[0016] To this end, the present invention integrates spatial location encoding and business feature encoding into a fixed-width binary integer to form a coupled identifier, and uses the coupled identifier as an index sorting key to organize an ordered index structure; at the same time, a branchless bit operation sequence is constructed based on the query identifier, spatial bit mask and feature bit mask to complete the dual determination of spatial correlation and business feature matching in the same instruction stream.

[0017] Furthermore, this invention, through a configurable bit width and bit weight mechanism, adapts the spatial retrieval accuracy, business feature dimension capacity, and execution path to the processor register bit width, and supports extended implementations around index maintenance, distributed routing, vectorized parallel filtering, and in-situ aggregation.

[0018] Technical solution of the present invention

[0019] The spatial and feature-coupled coding geographic data index construction and filtering technology provided by this invention includes an interrelated coupled index construction stage and a geographic data filtering stage.

[0020] 1. Spatial and Feature Coupling Index Construction Phase

[0021] This process includes the following steps:

[0022] Step S1: Construct a coupled coding structure. The coupled coding structure includes a spatial location coding field and a business feature coding field. The high and low bit arrangement of the two is configured according to the retrieval priority; in the spatial priority mode, the spatial location coding field is located in the high bit and the business feature coding field is located in the low bit, and the opposite is true in the feature priority mode. The spatial location coding field is generated based on a spatial filling curve algorithm with geographic topology order preservation; the coupled coding structure limits the bit segment division and bit weight configuration of the coupled identifier, and the coupled identifier as a whole is a fixed-width binary integer adapted to the bit width of the processor register.

[0023] Step S2: Generate a coupling identifier. Map the spatial coordinates of the data object to spatial location codes, map the business features to feature codes, and combine them by bit concatenation to form a coupling identifier; the coupling identifier conforms to the coupling coding structure, and its order in the numerical space is jointly determined by the bit weight configuration of the spatial location coding field and the business feature coding field.

[0024] Step S3: Construct an ordered index. Using the coupling identifier as the index sorting key, construct an ordered index structure for the data object, and maintain the coupling identifier in the storage unit.

[0025] 2. Geographic data screening process

[0026] This process includes the following steps:

[0027] Step S4: Generate a query identifier. The bit arrangement rule of the query identifier is consistent with that of the pre-stored coupled identifier, and it is generated by bit concatenation after mapping the spatial position and target feature conditions in the filtering request.

[0028] Step S5: Generate bitmask parameters. Determine the spatial bit prefix length based on the spatial scale parameters and generate a spatial bitmask. Generate a feature bitmask based on the target feature conditions. In feature-first mode, configure the corresponding displacement and mask coverage interval based on the feature bit segment arrangement relationship.

[0029] Step S6: Perform atomic dual-screening judgment. A branchless bitwise operation sequence is executed on the pre-stored coupled identifier and query identifier, performing target condition judgments on the high-order and low-order encoded fields respectively, and outputting the hit status. The core execution path of the branchless bitwise operation sequence does not contain conditional jump instructions dependent on input data; the judgments of spatial correlation and business feature matching are completed in the same instruction stream.

[0030] In the filtering process, the encoding structure of the query identifier is consistent with the encoding structure of the pre-stored coupled identifier, and corresponds to the corresponding space-first or feature-first coupled encoding structure.

[0031] 3. Preferred Extended Implementation

[0032] (a) Construction method subordinate to technical characteristics

[0033] Furthermore, the construction method can be configured as a fixed-width binary integer encoding structure adapted to the bit width of the processor register. The bit width boundary between the spatial location encoding field and the service feature encoding field can be asymmetrically divided according to spatial precision requirements and service dimension capacity, and additional encoding fields can be configured as needed. The service feature encoding field can be further divided into multiple subfields with different bit weights, preferably including a service type subfield and a polymorphic service payload subfield, so as to carry heterogeneous service features within a unified bit width range; any encoding field supports decision logic bypassing through preset mask and displacement parameter configuration.

[0034] Furthermore, the coupling identifier supports a local update mechanism based on bit segment separation. When a data object undergoes a spatial location change or a change in business characteristics, only the corresponding bit segment can be updated with a mask while keeping the remaining bit segments unchanged, thereby reducing the overhead of full reconstruction. The coupling identifier can also be used to generate routing sharding keys, mapping spatially related data objects to the same physical storage area or logical sharding identifier.

[0035] Furthermore, the sharding routing can be combined with a sharding parameter adaptive adjustment mechanism to perform splitting or merging. The system dynamically adjusts the sharding level based on storage bit occupancy, addressing concurrency frequency, data channel bandwidth utilization, or other physical characteristic parameters that characterize the load status; preferably, the relevant adjustments only change the mapping relationship between the routing sharding key and the storage unit, while keeping the coupled identifier encoding unchanged, thereby reducing rehashing, recoding, and invalid data transfer.

[0036] (ii) Screening methods are subordinate to technical features

[0037] Furthermore, the query identifier and the coupling identifier adopt the same bit weight allocation rule to ensure the effective execution of bit segment alignment and branchless dual determination. The dual determination preferably includes: performing an XOR operation on the coupling identifier and the query identifier to form a difference sequence; performing bit offset alignment and mask zeroing on the high-order encoded field; performing bitwise AND extraction and equivalent comparison on the low-order encoded field; and synchronously outputting the spatial correlation and feature matching results in the same branchless bit operation sequence.

[0038] Furthermore, the feature bitmask can be generated from a mask lookup table based on the service type and discrete feature conditions, and can be formed into a composite feature bitmask through bitwise OR operations or other equivalent bitwise operations to support unified determination of cross-level and multi-dimensional feature conditions. The spatial bit prefix length can be adaptively mapped according to the target spatial scale parameter and converted into the displacement amount when the processor performs spatial determination; its value range can be constrained between a preset minimum value and the total bit width of the spatial position coding field minus the reserved suffix bits.

[0039] Furthermore, the filtering method may also include: performing adaptive neighborhood expansion based on boundary determination of reserved suffix bit segments; performing dynamic density adaptation based on data scale within the logical grid; performing in-situ atomic filtering and hit truncation within the storage layer based on computational pushdown; implementing batch branchless bit operation sequence execution using a non-jump conditional execution mechanism or SIMD extended instruction set; and performing dynamic routing switching between space-priority primary index and feature-priority secondary index. The method can also, under the premise of satisfying feature matching conditions, extract target spatial prefixes through bit truncation and complete multi-scale spatial aggregation and in-situ counting statistics.

[0040] (III) System and Device Implementation Methods

[0041] Furthermore, the present invention can also be implemented as a geographic data filtering system, a non-volatile computer-readable storage medium, a geographic data filtering device, and a processor chip. The corresponding system or device preferably includes a coupling coding module, a communication module, a storage module, and a bitmask filtering engine, used to construct coupling identifiers, maintain an ordered index structure, receive filtering requests, and perform branchless dual-determination.

[0042] Furthermore, the system or device can be configured as needed with a multi-mode heterogeneous routing module, a precision mapping unit, a density adaptive unit, a neighborhood expansion unit, an atomic filtering and truncation unit, and a distributed sharding routing unit to support multi-index routing, dynamic precision control, load balancing, and in-situ aggregation. The corresponding device implementation is preferably completed collaboratively by a processor, memory, and communication interface; the corresponding chip implementation preferably includes an input register interface, a bitmask filtering engine, an output register interface, and a clock control unit, and avoids conditional jump control logic dependent on input data in the hardware execution path.

[0043] Beneficial effects of the present invention

[0044] Compared with the prior art, the present invention has at least the following beneficial effects:

[0045] Note: Here, "lower sensitivity to data-related branches" means that the core decision path does not contain conditional jump instructions that are affected by data distribution, thereby reducing the sensitivity of execution delay to the distribution of data to be filtered.

[0046] Comparison of core technology features:

[0047] In summary, this invention achieves synergistic optimization of both the index organization and underlying decision path in composite filtering requests through spatial and feature-coupled encoding and branchless bitwise operation sequences. Combined with the test conditions of the embodiments, improvements in query latency, response stability, index maintenance overhead, and high-concurrency processing capabilities are evident. Attached Figure Description

[0048] Figure 1 This diagram illustrates the bit-level structure of a spatial and feature-coupled identifier, showing the bit segment allocation of a 64-bit coupled identifier, which includes a spatial location coding field and a business feature coding field.

[0049] Figure 2 This diagram illustrates the configuration of the bit width of the coupled identifier, showcasing the configuration of the spatial location coding domain and the business feature coding domain based on the accuracy requirements of heterogeneous services.

[0050] Figure 3 The flowchart for the branchless dual screening process, taking the space-first implementation mode as an example, demonstrates the branchless bitwise operation sequence driven by data flow, reflecting the logical process of synchronous execution of spatial correlation determination and feature matching determination in the same instruction stream.

[0051] Figure 4 This is a mapping diagram of the spatial bit prefix length and spatial scale parameters, showing the nonlinear characteristics of the processor displacement operands as a function of spatial scale parameters (covering scenarios such as retrieval radius and map zoom level).

[0052] Figure 5 This is a schematic diagram of neighborhood expansion based on bit feature prediction, showing the cascaded filtering logic activated when the spatial encoding is at the boundary of the logical grid.

[0053] Figure 6 This is a diagram of the geographic data filtering system architecture, showing the interaction between the communication module and the coupling coding module and the bitmask filtering engine, as well as the data association between the storage module and the bitmask filtering engine.

[0054] Figure 7The flowchart illustrates the vectorized parallel filtering process, showcasing the hardware execution logic for performing one-to-many batch dual-decision based on the processor's vector registers.

[0055] Figure 8 The flowchart for the filtering response on the computing device side illustrates the process of the computing device performing in-situ bitwise operations filtering (dual judgment of spatial correlation and feature matching) and logical truncation after receiving a request.

[0056] Figure 9 This diagram illustrates the distributed sharding routing and storage mapping, showcasing the data sharding mapping, directional instruction distribution, and storage node routing relationships based on the spatial bit prefix corresponding to the spatial location encoding field.

[0057] Explanation of reference numerals in the attached figures:

[0058] correspond Figure 1 and Figure 2 The attached reference numerals are as follows: 100: 64-bit coupled identifier bit-level structure; 101: Spatial location coding field (47 bits); 102: Business feature coding field (17 bits); 201-203: Configuration forms of 32-bit, 64-bit, and 128-bit coupled identifiers, respectively.

[0059] correspond Figure 3 and Figure 4 The attached reference numerals are as follows: 301: Loading of coupling identifier and query identifier; 302: Generation of displacement and bitmask parameters; 303: Spatial correlation determination operation sequence (XOR, SHR, zeroing); 304: Feature matching determination operation sequence (AND, equality comparison); 305: Logical AND hit determination; 306: Hit status signal output; 307: Result bitmap (written to target register or memory); L: Spatial bit prefix length (a parameter used to determine the displacement amount of processor displacement operation); R: Spatial scale parameter (covering retrieval radius, map zoom level, etc.); R0: Preset baseline grid scale.

[0060] correspond Figure 5 The attached reference numerals are as follows: 500: Reserved suffix bit segment extraction operation; 501: Bit feature critical state detection logic; 502: Neighborhood expansion logic activation signal; 503: Single grid instruction execution path; 504: Multi-grid cascade filtering path; 505: Cascade batch query; 506: Current logic grid cell; 507-514: Candidate adjacent logic grid sequences.

[0061] correspond Figure 6The reference numerals in the attached figures are as follows: 601: Coupled coding module (configured to perform bit concatenation operation); 602: Spatial coding subunit; 603: Feature coding subunit; 604: Bit concatenation unit; 605: Storage module (maintains an ordered index structure); 606: Bitmask filtering engine (executes a branchless bit operation sequence); 607: Communication module (passively receives requests and returns results).

[0062] correspond Figure 7 The attached reference numerals are as follows: 701: Vector register load instruction; 702: Batch vectorized bitwise operation sequence; 703: Parallel vector comparison logic; 704: Bitmap hit result extraction operation.

[0063] correspond Figure 8 The attached reference numerals are as follows: 801: Filter request reception (including spatial coordinates, business conditions, and optional starting cursor); 802: Query identifier generation and bitmask parameter mapping; 803: Filter instruction stream issuance and optional starting cursor; 804: Dual filtering loop execution (spatial correlation and feature matching); 805: Hit counter accumulation; 806: Instruction stream logic truncation and underlying cursor recording; 807: Hit result set and underlying cursor extraction; 808: Filter results with cursor returned.

[0064] correspond Figure 9 The attached diagram labels are as follows: 901: Routing fragment key extraction (based on the spatial bit prefix corresponding to the spatial location coding field); 902: Fragment mapping routing logic; 903-906: Distributed storage units (nodes A / B / C / D). Detailed Implementation

[0065] Implementation Mode Overview: This invention provides two implementation modes: one is a space-first mode with spatial location encoding as the high-weight bit, used for space-first index construction and filtering, where the spatial location encoding field is located in the high-bit segment of the coupled identifier; the other is a feature-first mode with business feature encoding as the high-weight bit, used for feature-first index construction and filtering, where the business feature encoding field is located in the high-bit segment of the coupled identifier. Both modes share the underlying bitmask determination logic and branchless bit operation sequence.

[0066] Terminology Definition

[0067] To facilitate understanding of the technical solution of this invention, this specification provides clear definitions of core terms. The terminology definitions are arranged in a logical progression of "data structure fundamentals → hardware execution → operator mapping → polymorphic business characteristics → engineering implementation forms"; the implementation methods, instruction sets, numerical ranges, and hardware architectures mentioned herein are all illustrative examples.

[0068] I. Data Structure Fundamentals of Coupled Identifiers

[0069] The following terms define the underlying physical representation of spatially coupled identifiers:

[0070] 1. Coupled Identifier (CoupledID): A data identifier that integrates at least spatial location coding and business feature coding into the same binary sequence; in some implementations, it may also include one or more additional coding fields. Depending on the sorting priority, the relative weighting relationship between the spatial location coding field and the business feature coding field can be divided into two modes: ① Spatial priority mode, where the relative weighting of the spatial location coding field is higher than that of the business feature coding field; ② Feature priority mode, where the relative weighting of the business feature coding field is higher than that of the spatial location coding field.

[0071] 2. Total bit width N of the coupled identifier: refers to the total number of bits of the fixed-width binary integer, such as 64 bits or 128 bits. In the implementation containing only the spatial location coding field and the service feature coding field, Ns and Nf satisfy N = Ns + Nf; in the implementation including additional coding fields, N is the sum of the bit widths of each coding field. "Adapted to the processor register bit width" includes being equal to, an integer multiple of, the processor's native word length, or a preset fixed bit width adopted to adapt to specific hardware registers, data path widths, or computational logic. In this specification, the binary bit order adopts a right-to-left counting rule starting from 0; "bit XY" represents a continuous bit segment from bit X to bit Y (including endpoints). The "fixed bit width" refers to the total bit width being predetermined and consistent under the same implementation, the same underlying index structure, or the same runtime configuration.

[0072] 3. High / Low Bit Encoding Fields: These refer to the target encoding fields in the coupled identifier that participate in the target condition determination and have different bit weights. In a space-priority coupled encoding structure, the high bit encoding field corresponds to the spatial location encoding field, and the low bit encoding field corresponds to the business feature encoding field; in a feature-priority coupled encoding structure, the high bit encoding field corresponds to the business feature encoding field, and the low bit encoding field corresponds to the spatial location encoding field. In implementations that include one or more additional encoding fields, the high bit encoding field and low bit encoding field still specifically refer to the spatial location encoding field and the business feature encoding field, and it is not excluded that other additional encoding fields are set in between or outside of them. The physical arrangement is dynamically configured according to the retrieval priority.

[0073] 4. Bit concatenation: This refers to the action of mapping at least two independent binary encoded segments to different bit ranges in the same numerical sequence. Its implementation can include, but is not limited to: using a combination of shift instructions and bitwise OR instructions; using hardware bit segment insertion instructions (such as BFI); using arithmetic addition to map the high-order bit to the target weighted bit range and then summing it with the low-order bit; or other equivalent bit operations or combinational logic implementations that can write different encoded segments into the target bit range.

[0074] 5. Geographic Topology Preservation: This refers to the characteristic that, within a single patch or local grid space mapped by a spatial filling curve, neighboring coordinates in geographic space, after being mapped to binary encoding, still exhibit numerical proximity ordering; the closer the coordinates in geographic space, the longer the common prefix of their encoded values. To address the potential numerical discontinuity at the surface boundary or specific curve inflection points of the spatial filling curve, this invention performs cascade compensation by combining an adaptive neighborhood expansion filtering mechanism based on bit feature prediction. The spatial filling curve algorithm possessing geographic topology preservation includes, but is not limited to, the S2 geometric algorithm, Hilbert curve, Z-Order curve, Moore curve, etc.

[0075] II. Processor-level Execution and Hardware Physical Characteristics

[0076] The following terminology is intended to clarify the controlled relationship between the geographic data filtering process and the processor hardware registers and instruction pipeline:

[0077] 6. Program Counter (PC): This refers to the hardware register in the processor used to store the address of the next instruction to be executed. If the PC value does not change non-linearly with the result of the input data judgment, it corresponds to a linear instruction flow at the processor level; otherwise, it corresponds to a data-dependent conditional branch jump.

[0078] 7. Branchless Bitwise Operation Sequence and Atomic Execution Path: This refers to an execution path for the core decision-making step that does not contain conditional jump instructions dependent on the input data result, and completes the decision by forming a continuous execution sequence using native processor bitwise operation instructions such as XOR, bitwise AND, shift, and comparison. Its technical characteristics are: the instruction flow does not contain data-dependent conditional jumps; the decision logic has a relatively stable execution delay that is largely decoupled from the input data value under given hardware configuration and compilation mapping conditions; and the bitwise operation instructions are executed sequentially in the processor's arithmetic logic unit before outputting the decision result. If conditional statements at the high-level language level are compiled into conditional transfer, conditional selection, or other non-jump conditional execution mechanisms, they also fall within the scope of the branchless bitwise operation sequence described in this invention. Here, "branchless" only refers to the core execution path of candidate object-level dual decision-making, excluding outer control flow branches triggered by preset control logic in candidate set traversal, hit truncation, or exception handling.

[0079] 8. Same Instruction Stream and Core Execution Path: This refers to the sequential execution of bitwise operation instructions for spatial and feature-based decision-making within the same atomic instruction stream of the processor. The spatial bitmask and feature bitmask participate as parallel operands in the same bitwise operation sequence, and the decision result is directly output from the operation result, without any conditional jump instructions that would interrupt the instruction stream. The statement that "the core execution path is arranged as a linear instruction stream under the compiler's mapping" means that the number of non-linear jumps in the program counter (PC) value during execution does not change with the input data value.

[0080] III. Spatial and Feature Composite Screening Operators and Parameter Mapping

[0081] The following terms correspond to the core operators and parameter mapping logic of geographic data filtering methods:

[0082] 9. Query Identifier: After the computing device receives a filtering request, it generates a fixed-width binary integer by concatenating the spatial location in the request with the target feature conditions using the same bit-segment mapping rule as the coupling identifier. This identifier is loaded into the processor's register as a fixed operand for bitwise alignment and comparison with the coupling identifier.

[0083] 10. Bit Mask: A binary sequence used to isolate specific bit segments. It extracts or masks target bit segments through bitwise AND, OR, or other bitwise operations to achieve bit-level determination. In this invention, the bit mask includes a spatial bit mask for spatial correlation determination and a feature bit mask for feature matching determination. In feature-priority mode, the spatial bit mask can also serve as an isolation mask for extracting pure spatial domain difference information from the XOR operation result. It sets the corresponding bit segments in the spatial location coding domain to 1 and the corresponding bit segments in the business feature coding domain and additional coding domain to 0, so as to clear the high-order feature domain differences before logical right shift and prevent shift contamination. In space-priority mode, the spatial bit mask can be configured with all 1s to achieve logical bypass. The isolation function can be achieved by multiplexing or equivalently configuring the output signal of the spatial bit mask, without the need to introduce an additional independent third mask input channel.

[0084] 11. Spatial bit prefix length: refers to the number of effective prefix bits used for spatial correlation determination in the spatial location coding domain. Its value has a preset nonlinear mapping relationship with the spatial scale parameter that characterizes the geographical coverage or display accuracy. When the spatial scale parameter characterizes the geographical coverage, the spatial bit prefix length decreases accordingly and is used to determine the displacement amount of the processor performing the displacement operation.

[0085] 12. Spatial Scale Parameters: These are technical indicators used to define the coverage, physical size, or display level of geographic data. They encompass the radius of circular searches, the side length of rectangular searches, map zoom levels, and the coverage area of ​​directional geofences. Regardless of the geometric shape or parameter naming, any parameter that determines the geographic coverage or display accuracy falls under the category of spatial scale parameters described in this invention.

[0086] 13. Feature Filtering Strength: This refers to the ratio of the length of the business feature coding field segment covered by the feature filtering conditions to the total bit width of the business feature coding field in the retrieval request. It is used to characterize the granularity and coverage of feature filtering. The larger the value, the finer the feature filtering. Its value ranges from 0 to 1; in typical embodiments, it can be 0.1 to 1.0. Feature filtering strength is used as the basis for determining whether to use a space-first index or a feature-first auxiliary index in a multi-mode heterogeneous index routing mechanism.

[0087] 14. Logical grid (also known as geographic grid or grid cell): refers to a computational boundary unit dynamically defined by a spatial bit prefix length L. It is not a pre-defined, statically divided physical region, but rather a dynamic set of data objects with the same L-bit spatial prefix formed in the numerical space when the processor performs bitwise operations. The actual physical area of ​​the logical grid typically changes exponentially with adjustments to the value of L. In this specification, "geographic grid" or "grid cell," in the context of bit-truncation and spatial aggregation logic, refers to the logical grid as defined in this terminology.

[0088] IV. Multi-morphic dynamic mapping mechanism for heterogeneous services

[0089] The following terms correspond to polymorphic business feature encoding and dynamic mapping mechanisms:

[0090] 15. Service Type Subfield (Protocol Decoder): This refers to a specific bit segment within the service feature encoding field of the coupled identifier, used to characterize industry attributes or service classification. This subfield acts as an indicator of polymorphic logic (i.e., the "protocol decoder"), and its value determines the parsing rules for the polymorphic service payload subfield. At the hardware execution level, the value of the service type subfield is used as an index to a mask lookup table (LUT) to obtain the corresponding feature bitmask in real time.

[0091] 16. Polymorphic Business Payload Subdomain: This refers to a flexible feature domain within the business feature encoding domain of the coupled identifier, where the meaning of each bit is not fixed. The specific physical boundary division of this subdomain (such as the bit width allocation of each business field) and its logical semantics (such as whether a bit represents a rating level or a price level) are dynamically mapped according to the value of the business type subdomain. This encoding architecture of "unified total bit width, dynamic logical domain" allows the same set of fixed-bit-width coupled identifiers to carry differentiated feature dimensions from heterogeneous industries without changing the physical storage structure.

[0092] 17. Lookup Table (LUT): A set of mapping rules pre-installed in the processor cache or storage system; the table stores the mapping relationship between the service type identifier and the feature bit mask and bit segment parsing rules; it is used to provide operands for atomic bit operations in real time according to the service type during the execution of filtering instructions.

[0093] V. Project Implementation Mode and System Expansion

[0094] The following terms define the engineering implementation path, system expansion form, and related execution characteristics of this solution:

[0095] 18. Computation pushdown: This refers to the technical architecture of pushing down the bitmask operation logic of dual spatial and feature determination from the application layer to the internal storage system, encapsulating it into an atomic execution unit that resides in the data storage node and executes in place, thus avoiding the need to move the entire candidate dataset across the network or across processes.

[0096] 19. Atomic Execution Unit (also known as In-place Bitwise Operation Filtering Execution Unit): This refers to an execution entity that performs bitwise operation filtering logic in an indivisible manner within the storage layer. Its execution process directly acts on the physical storage nodes to ensure the atomicity and consistency of the decision-making process. Its implementation can include software execution modules, database extension units, filtering execution components, near-data calculation modules, or internal calculation units within the storage engine, among other hardware and software forms.

[0097] 20. Ordered Index Structure: Refers to an underlying storage structure that can maintain the physical or logical order of data based on the numerical value of the index sort key, including but not limited to B+ trees, log-structured merged trees (LSM-Tree), skip lists, or in-memory ordered arrays. The ordered index structure supports range scanning based on fixed-width integers and cursor logical truncation.

[0098] 21. In-place Counting Aggregation: refers to counting and statistical operations performed in-place at the storage layer. The aggregation process is directly based on the bit truncation results of the coupled identifiers and outputs grid count values ​​while maintaining the original state of the underlying data physical structure. Here, "atomic" is limited to the register-level execution process of the aforementioned bit truncation and bit operation instructions, rather than describing the entire batch aggregation task as a single indivisible instruction.

[0099] 22. Vectorized memory model: refers to a contiguous aligned memory layout model adapted to the Single Instruction Multiple Data (SIMD) parallel computing architecture, which maps batches of data to be processed and common constant parameters to isolated contiguous memory segments so that they can be directly processed by the processor's vector loading instructions and vector operation instructions.

[0100] 23. Logical extreme state: refers to the critical distribution of bit segment sequence as all binary 0s or all binary 1s, representing the boundary position of data object in the numerical space in the current logical grid or feature category.

[0101] 24. Edge transition interval: refers to the preset threshold interval in the bit segment value space that is adjacent to the critical state of all 0s or all 1s. When the bit segment value falls into this interval, it indicates that the data object is located near the boundary of the current logical grid.

[0102] 25. Reserved suffix bits: refers to the number of low-order bits reserved after the spatial bit prefix length in the spatial location coding domain, used to characterize the relative coordinate position of the data object within the current logical grid. Its value can be configured according to the total bit width of spatial coding, target precision, and boundary determination requirements; in typical embodiments, it can be 2 to 8 bits, preferably 4 to 6 bits.

[0103] 26. Filtering Request: Refers to any request, instruction, or control signal that triggers the geographic data filtering and judgment logic, including business-level retrieval requests and query requests, or atomic filtering instructions or scan control instructions issued within the distributed system; its receiving methods include network socket communication, inter-process communication, function call interface, instruction bus triggering, or hardware register writing.

[0104] 27. Underlying Cursor: Refers to the positioning information recorded and output by the execution unit during incremental scanning or atomic filtering of an ordered index structure, used to identify the current scanning progress; its underlying implementation can correspond to the numerical value of the identifier, the logical offset of the underlying index node, the physical storage positioning information, or the encapsulated representation of the above information; it is used to quickly restore the scanning context in subsequent pagination requests, and realize the logical truncation and continuation of the retrieval process.

[0105] Abbreviation Mapping Declaration: For the sake of brevity, in the descriptive text of the following embodiments, "space filling curve algorithm with geographic topology order preservation" is abbreviated as "space filling curve," "fixed-width binary integer adapted to processor register bit width" is abbreviated as "fixed-width integer," "spatial location coding domain" is abbreviated as "spatial domain," and "business feature coding domain" is abbreviated as "feature domain." The above abbreviations do not affect the complete meaning of the corresponding terms in the claims and specification.

[0106] Example 1: Spatial and Feature Coupled Coding Structure

[0107] like Figure 1As shown, this embodiment illustrates a space-priority mode coupled identifier structure, including a high-order spatial location encoding field 101 and a low-order business feature encoding field 102. This embodiment employs a coupled encoding structure that couples spatial location and business features into the same fixed-width binary sequence. The high-low order arrangement of the spatial location encoding field and the business feature encoding field corresponds to the retrieval priority: for proximity retrieval scenarios primarily based on spatial range filtering, a space-priority mode is used (the spatial location encoding field is located in the high-order bit segment); for wide-area retrieval scenarios primarily based on specific attribute filtering, a feature-priority mode is used (the business feature encoding field is located in the high-order bit segment). This bit weight allocation method allows the system to make fuller use of disk I / O and memory locality through adjustments to the underlying physical sorting. Both modes share the underlying branchless bitwise operation sequence logic, and mode switching is achieved by adjusting the mask coverage interval and shift parameters.

[0108] Spatial location coding generation steps: In a preferred embodiment of the present invention, the S2 geometric algorithm is used to generate spatial location coding, and the specific steps are as follows:

[0109] (1) Coordinate input: Obtain the geographic coordinates (longitude, latitude) of the data object;

[0110] (2) Spherical projection: Project latitude and longitude coordinates onto a spherical coordinate system and convert them into three-dimensional unit vectors (x, y, z);

[0111] (3) Cube projection: Project the spherical coordinates onto one of the six faces of the cube surrounding the sphere to generate a face ID (value range 0-5).

[0112] (4) Space filling curve mapping: On the selected cube surface, the two-dimensional planar coordinates are mapped to one-dimensional Hilbert distance values ​​through the Hilbert curve;

[0113] (5) Bit encoding generation: The face identifier and Hilbert distance value are combined into a spatial location code. The high 3 bits are the face identifier (Face ID), which is used to identify the 6 faces of the cube projection to maintain the uniqueness of the global geospatial coordinate mapping; the subsequent bits are the Hilbert path code within the face, which is used to identify the specific grid location within the face.

[0114] The spatial codes generated by the S2 geometric algorithm described above possess geographic topological order preservation within a single patch or local grid space: that is, within logically continuous coding intervals, spatial codes mapped from geographically adjacent coordinates exhibit proximity-ordered characteristics in numerical space. To address potential numerical discontinuities at surface boundaries or specific curve inflection points in the space-filling curve, this invention employs a cascaded decision-making mechanism (described later) to compensate for recall loss in cross-boundary scenarios at the system level, thereby improving retrieval completeness. Other space-filling curve algorithms with geographic topological order preservation (such as Hilbert curves, Peano curves, Moore curves, Z-Order curves, etc.) can be considered as alternative solutions.

[0115] Bit width configuration principle: such as Figure 2 As shown, the adaptation configurations of the 32-bit, 64-bit, and 128-bit coupled identifiers correspond to reference numerals 201, 202, and 203, respectively, illustrating the configuration relationship between the spatial location coding field and the business feature coding field under different total bit widths:

[0116] The above bit width allocation scheme can be dynamically configured by system administrators or users during the system initialization phase according to specific business accuracy requirements (such as tolerance for geographic location accuracy) and the number of feature dimensions to adapt to different application scenario needs.

[0117] Flexible bit-width allocation mechanism for feature subfields: Each feature subfield within the business feature encoding domain can adopt a flexible bit-width allocation strategy. The system dynamically calculates the minimum bit-width required for each feature dimension based on its cardinality and adaptively allocates it under the constraint of the total feature domain bit-width. For example: for Boolean features (such as "whether WiFi is provided", 1 bit), the minimum bit-width is allocated; for enumerated features (such as "merchant category", 5-6 bits), a larger bit-width is allocated; for continuous features that need to support range queries (such as "price"), the bit-width is determined according to the bucketing strategy.

[0118] 64-bit Coupled Identifier Bit-Level Structure Diagram (Preferred Embodiment):

[0119] Bit allocation for the 64-bit embodiment:

[0120] Comparison of bit weight allocation between the two modes (64-bit coupled identifier):

[0121] Note: Feature-first mode and space-first mode use the same bit width configuration (47 bits for space + 17 bits for features), only the high and low bit positions are interchanged. Both modes share the same branchless bitwise operation sequence execution engine, and mode switching is achieved by adjusting the bitmask coverage range and shift parameters.

[0122] Hardware word length alignment: The total bit width N of the coupled identifier is preferably 64 bits or 128 bits, aligned with the width of the general-purpose registers (64 bits) or vector registers (SIMD 128 / 256 / 512 bits) of mainstream processors, so as to facilitate the processing of the entire space and feature composite information through a single instruction.

[0123] Polymorphic mapping mechanism for business feature encoding: In this embodiment, the business feature encoding field (17 bits) can adopt a business type-oriented polymorphic semantic mapping architecture.

[0124] Specifically, the high-order 5-bit service type field (bits 16-12) not only serves as an industry classification identifier, but also as a "protocol decoder" for the subsequent 12-bit polymorphic service payload field (bits 11-0). When the 5-bit service type field takes different values, the physical division boundary and logical semantics of the subsequent 12 bits change dynamically.

[0125] This design of "unified total bit width and dynamic logical domain" enables the present invention to achieve refined feature representation of heterogeneous industry data while maintaining 64-bit hardware instruction alignment. During the filtering process, the filtering engine calls the feature bitmask matching the business type in the request in real time, completing the synchronous determination of spatial and polymorphic features in the same atomic bit operation stream.

[0126] Example table of polymorphic mappings (pre-defined mask lookup table LUT in the processor cache):

[0127] Example of dynamic semantics for polymorphic payloads (taking catering as an example): When business type = 00001 (catering), the 12-bit polymorphic payload is divided into: business level (bits 11-8, 4 bits), business status (bits 7-6, 2 bits), and tag bitmap (bits 5-0, 6 bits). Each subdomain defines the encoding semantics according to business requirements.

[0128] The hardware implementation mechanism of polymorphic mapping: The polymorphic mapping can be implemented through a lookup table (LUT) preset in a cache-friendly area of ​​the processor. The filtering engine extracts the service type identifier as an index, obtains the corresponding bitmask from the LUT, and performs polymorphic attribute parsing in conjunction with the instruction pipeline; under cache hit conditions, the lookup overhead can be controlled within a low range. The decoding of the polymorphic mapping can also be implemented through hard-coding of logic gates or non-jump assignment mechanisms such as conditional transfer instructions (CMOV).

[0129] Subdomain coding structure (example): The business feature coding domain can be divided into multiple subdomains with different bit weights. The logical relationship between the subdomains can take one of the following two basic forms:

[0130] (1) Hierarchical nested structure: The hierarchical feature encoding of "major category - subclass - attribute" is adopted. Taking the 17-bit feature domain as an example: the first level (major category) occupies the high 5 bits, the second level (subclass) occupies the middle 4 bits, and the third level (attribute) occupies the low 8 bits. This hierarchical encoding supports feature filtering of different granularities: coarse-grained filtering uses only the high 5 bits of the mask to achieve major category filtering, and fine-grained filtering uses the entire 17-bit mask to achieve precise attribute matching.

[0131] (2) Dimensional Tiled Structure: This structure employs feature encoding with multiple parallel dimensions, where there is no parent-child dependency between dimensions. Taking a 17-bit feature field as an example: the business type occupies the high 5 bits (supporting 32 types, serving as a polymorphic decoder), and the subsequent 12 bits are the polymorphic payload (dynamically defined based on the business type). This tiled structure supports independent or combined filtering of any dimension, with logical independence between each feature condition, resulting in greater flexibility in mask synthesis.

[0132] The two structures described above are illustrative examples. In practical applications, a suitable subdomain partitioning method can be selected based on business characteristics, or a composite structure combining nesting and tiling can be adopted.

[0133] Subdomain bit weighting based on change frequency (preferred configuration): As a preferred arrangement method, the multiple subdomains are arranged within the business feature coding domain according to the change frequency of the physical bit segments. Specifically, the system pre-evaluates the change frequency of each feature dimension, mapping feature dimensions with change frequencies below a preset threshold (static dimensions, such as merchant category, business scope, etc.) to the high bit segments of the business feature coding domain, and mapping feature dimensions with change frequencies above the preset threshold (dynamic dimensions, such as business status, real-time inventory, etc.) to the low bit segments of the business feature coding domain. This "high-bit static, low-bit dynamic" arrangement rule ensures that high-frequency data updates mainly cause low-bit fluctuations in the coupled identifier values, thereby maintaining good physical storage locality in the underlying ordered index structure, restricting the rebalancing operation of index nodes to within the leaf nodes, and reducing disk I / O overhead under high-frequency update load. When this configuration is combined with the "physical storage locality protection" mechanism described in Example 4, it can produce a synergistic effect in highly dynamic LBS data scenarios.

[0134] Bucketing Encoding for Continuous Numerical Features: For continuous numerical features such as prices and ratings, the system pre-performs bucketing and uses one-hot encoding for mapping, ensuring that each price tier has independent bits in the feature bit space. Taking price features as an example: 0-50 yuan, 50-100 yuan, 100-200 yuan, and above 200 yuan (closed upper limit range) are mapped to price tiers 0001, 0010, 0100, and 1000, respectively. For range queries of "prices between 50-200 yuan" (covering tier 1 and tier 2), the system synthesizes a composite feature bitmask 0110 through bitwise OR operations. During the filtering process, the processor can determine the target hit through a single bitwise AND operation. Due to the use of one-hot code mapping, the composite mask (0110) can only generate a non-zero association with gear 1 (0010) or gear 2 (0100) in physical logic, thereby reducing false hits on non-target range data such as gear 0 (0001) or gear 3 (1000), and realizing atomic, branchless filtering for continuous ranges aligned with preset bucket boundaries. For queries on arbitrary numerical ranges not strictly aligned with bucket boundaries (e.g., the requested range spans multiple preset gears), the branchless bitwise operation sequence performs highly efficient coarse-grained pruning, excluding most non-target gear data in a single instruction stream, and then removing a small number of false positive objects at the boundary through a subsequent precise verification step before the final result is output; this precise verification step can be completed in the storage layer, execution engine layer, or equivalent implementation.

[0135] Bucketing Coding Format Constraints: For feature dimensions requiring range filtering, the bucketing coding preferably employs bitmap coding or one-hot coding, ensuring no overlap in binary representation between any two different levels of coding, thereby reducing false hits of composite masks during range queries. Based on this, feature matching determination at the hardware execution level is equivalent to determining whether the extracted result is non-zero (range query) or equal to the target mask value (exact match), thus achieving parallel filtering while maintaining the branch-free characteristic.

[0136] Closed-end limit interval (unlimited bucket) configuration: As a preferred implementation, the bit corresponding to the highest tier in the bucketing encoding can be configured as a "closed-end limit interval" (also known as an "unlimited bucket"), used to carry all data objects whose values ​​exceed a preset maximum threshold. Taking price characteristics as an example: assuming the preset tier thresholds are 0-50 yuan, 50-100 yuan, and 100-200 yuan, then the fourth tier (above 200 yuan) corresponding to the highest bit (Bit 3) is configured as an unlimited interval, meaning all data objects with prices ≥ 200 yuan are mapped to this tier. This configuration facilitates the bucketing encoding to cover the entire numerical space, avoiding the problem of high-value data being unindexable due to exceeding the preset threshold. The specific threshold of the closed-end limit interval can be flexibly configured according to the business scenario to adapt to data objects with different numerical distributions.

[0137] Business Adaptation Notes on the Number of Buckets: It should be noted that the number of buckets for continuous numerical features can be configured as needed according to different business types; the aforementioned 4-level price buckets are only illustrative examples. In specific implementations, 3-level or other-level bucket codes can also be used, with the number of allocated bits corresponding to the number of buckets (for example, the hotel industry can use 3-level price tiers: economy / mid-range / high-end, corresponding to 3-bit unique hot code encoding).

[0138] The timing flexibility of mask synthesis is explained as follows: the synthesis process of the composite feature bitmask can occur either in the preprocessing stage (static mask pre-computation, caching the composite mask of high-frequency feature combination in the lookup table, and reading it directly during the query) or in the query instant generation stage (dynamic mask synthesis, performing bit operation synthesis in real time according to the feature conditions in the request); neither implementation method affects the execution of the core branchless bit operation filtering logic.

[0139] Feature processing of the time dimension: The business feature encoding domain is not limited to static attributes, but may also include time dimension encoding after discretization (such as time slice ID or time window encoding). Since time and space also have continuous characteristics, by incorporating the time dimension into the coupled encoding structure, this invention can natively support unified filtering for spatiotemporal joint queries.

[0140] Taking local life services as an example, 24 hours can be divided into 96 15-minute time slices, with the current time slice ID encoded using a 7-bit code. The system can dynamically map these 7 bits to specific fields in the polymorphic business payload subdomain (suitable for time-sensitive businesses) based on the business type, or use a 128-bit extended bit width for independent carrying. Through this configuration, the system can incorporate the time window as part of the business feature encoding into the dual determination of spatial correlation and business feature matching, thereby completing composite filtering including time dimension constraints within the same branchless bitwise operation sequence. This mechanism enables the single underlying index of this invention to, to a certain extent, replace the spatiotemporal composite index in traditional databases, reducing the expansion of multidimensional indexes while maintaining the technical characteristics of the branchless bitwise operation sequence and stable execution path of this invention.

[0141] The mathematical principle of high-order preservation: In the space priority mode, since the spatial location code occupies the high-order bits and the business feature code occupies the low-order bits, the spatial correlation determination (comparing whether the result of the high-order XOR is 0) is not affected by the change of the low-order feature bits.

[0142] The following is a general numerical model for the space-priority mode. Let the coupling identifier be C = S · 2^Nlow + R (plain text notation: C = S * 2^Nlow + R), where S is the high-order spatial location code, Nlow is the total bit width of all coding fields on the lower side of this spatial location coding field (including the bit width W of the business feature coding field and the bit width A of any possible additional coding fields), and R is the combined coding value of each coding field on the lower side. When performing spatial correlation determination, the processor executes a branchless instruction sequence (C1 ⊕ C2) >> Nlow == 0. This physical operation is equivalent to masking all differences in non-spatial bit segments on the lower side at the hardware level, thereby ensuring that high-order spatial determination and clustering based on high-order prefixes are not affected by fluctuations in low-order feature bits or additional information bits.

[0143] In feature-first mode, the business feature encoding field is in the high bit and the spatial location encoding field is in the low bit. At this time, it is necessary to first perform a bitwise AND operation on the XOR result through the spatial domain isolation mask to clear the difference in the high bit feature field, and then perform shift alignment and zeroing operations on the remaining pure spatial bit segments. The physical effect of its spatial correlation determination is equivalent to that of the space-first mode.

[0144] Uniqueness handling mechanism for coupled identifiers: When the spatial location encoding and business characteristic encoding of multiple data objects are exactly the same (e.g., multiple merchants of the same type within the same commercial complex), their coupled identifiers may conflict numerically. This invention provides the following optional conflict handling mechanisms:

[0145] (1) Sequence bit extension (preferably applicable to 128-bit or larger bit width embodiments): reserve k bits (such as 19 bits in the 128-bit embodiment) in the least significant bit of the coupled identifier as an auto-incrementing sequence number or hash collision bit to maintain the uniqueness of the same source object; the design of placing the sequence bit in the least significant bit can prevent it from interfering with the high-bit spatial sorting logic and from affecting the spatial correlation determination result of the spatial bit mask, thereby maintaining the geographical topology ordering of the coupled identifier; for bit width limited embodiments (such as 64-bit), the system preferably adopts the following multi-value mapping storage mechanism;

[0146] (2) Multi-value mapping storage: A one-to-many mapping structure is adopted in the storage layer, that is, one coupled identifier corresponds to one object identifier list, which is used to carry multiple object identifiers when encoding conflicts occur.

[0147] A complete solution for collision detection and secondary accurate verification:

[0148] When using the sequence bit extension scheme, the system performs conflict detection during the data writing phase: first, it checks whether there is an existing record that is identical to the target object's spatial location code and business feature code; if so, it assigns a sequence bit value of the current maximum sequence number + 1 to the new object to maintain the numerical uniqueness of the coupled identifier.

[0149] When using a multi-value mapping storage scheme, after a match is found, complete object information is obtained through association queries and a second-level exact match is performed before the final result is output. This second-level exact match only applies to a very small number of candidate objects that have undergone high-proportion pruning by the preceding atomic judgment. The impact on the overall filtering throughput of the system is within a preset controllable range, and it is significantly different from the post-filtering mode in traditional schemes that are designed for large-scale candidate sets.

[0150] The aforementioned conflict resolution mechanism maintains the uniqueness of the coupled identifier in the numerical space and does not affect the high-order space sorting logic.

[0151] Degradation Scenario Implementation and Instruction Compatibility: The bit-width dynamic allocation mechanism of this invention supports extreme degradation scenarios. When any coding domain is logically bypassed in the decision logic through the corresponding mask and shift parameter configuration (such as degrading to pure feature filtering or pure spatial retrieval), the system achieves logical bypass by pre-setting an all-zero spatial bit mask or an all-zero feature bit mask, maintaining the uniformity of the arithmetic logic unit execution path without modifying the core filtering instruction flow. In particular, in the pure feature filtering scenario where spatial correlation determination is achieved by configuring the spatial determination shift parameter to zero and cooperating with an all-zero spatial bit mask to achieve logical bypass, the system ensures that the spatial correlation determination is always logically true, thereby avoiding undefined or platform-related execution behaviors that may occur when the shift amount equals the register bit width without changing the core instruction flow (see the table below for details).

[0152] Example of fixed physical bit width and mask bypass configuration in a degradation scenario (taking a preferred embodiment of a 64-bit coupled identifier as an example):

[0153] This design enables the branchless bitwise operation sequence described in this invention to maintain instruction compatibility in degenerate scenarios, ensuring that the instruction sequence logic executed by the processor remains consistent. Logic bypass is achieved through an all-zero mask, eliminating the need to compile independent decision logic for different query modes, thereby achieving the technical effect of "one set of instructions, multiple modes reuse".

[0154] 128-bit Extended Implementation (For Enterprise-Level High-Precision Applications): In another implementation for enterprise-level high-precision geographic information, the coupling identifier uses a fixed 128-bit width to adapt to SIMD (Single Instruction Multiple Data) vectorized instruction sets (such as Intel AVX-512, ARM SVE, etc.). The 128-bit implementation maintains consistency with the 64-bit implementation in terms of the space-filling curve algorithm, one-hot code binning principle, and branchless bit operation sequence logic. Its differentiating features are: the spatial location coding field is extended to 69 bits (including a 3-bit face identifier and a 66-bit Hilbert path, improving accuracy to the millimeter level), the business feature coding field is extended to 40 bits, and an additional 19-bit coding field (preferably anti-collision sequence bits, as a specific implementation of the above-mentioned additional coding field) is added to support the unique representation of larger-scale data objects.

[0155] 128-bit coupled identifier bit-level structure diagram:

[0156] Bit allocation for the 128-bit embodiment:

[0157] The sequence bit, as a preferred implementation of the above-mentioned additional coding field, is located on the low side of the coupled identifier. During the filtering process, it is either masked by a bitmask or excluded as a low-level redundant bit from the scope of spatial correlation determination and business feature matching determination.

[0158] Regardless of whether a 64-bit or 128-bit configuration is used, the core branchless bitwise operation dual-decision architecture, word length alignment features, and bitmask determination logic of this invention remain unchanged. The core difference between the 128-bit and 64-bit embodiments is that the spatial domain is expanded to 69 bits (including 3-bit Face ID and 66-bit Hilbert path, with millimeter-level precision), the feature domain is expanded to 40 bits, and a new 16-bit independent tag bitmap and 19-bit additional coding field (anti-collision sequence bits) are added, which can be adapted to the SIMD vectorized instruction set to achieve higher throughput parallel filtering.

[0159] Explanation of the extensibility of the polymorphic payload: The 12 bits of the "polymorphic service payload" are not limited to the field combinations listed in this embodiment. They can be redefined according to business development as any discrete feature, continuous feature bucketing, or bitmap encoding based on the "service type" index. This "fixed shell, dynamic kernel" encoding concept utilizes the processor's word length alignment characteristics to achieve compatibility with heterogeneous services.

[0160] Description of the Open Architecture of Additional Encoding Fields: It should be noted that the coupled encoding structure and coupled identifiers described in this invention adopt an open design and are not limited to only including spatial location encoding fields and business feature encoding fields. In practical applications, the structure can flexibly introduce one or more additional encoding fields, such as the anti-collision sequence bits in the aforementioned extended bit-width implementation, or bit segments used to carry version identifiers, data verification, routing control, status identifiers, extended business category information, reserved extended information, and other additional control and extended information. The one or more additional encoding fields can be configured between the spatial location encoding field and the business feature encoding field, on the high outer edge of the overall arrangement of the spatial location encoding field and the business feature encoding field, on the low outer edge of the overall arrangement of the spatial location encoding field and the business feature encoding field, or a combination of the above positions.

[0161] When performing geographic data filtering, the system can adapt the additional coding fields according to the specific underlying physical implementation through bitmasking, bit segment selection and extraction, hardware bus interception, or other equivalent bypass and cooperative processing mechanisms. As long as the introduction of one or more additional coding fields does not change the logical relative bit weight relationship between the spatial location coding field and the business feature coding field in the target condition determination, and the target condition determination for the spatial location coding field and the business feature coding field can still be completed through the corresponding branchless bit operation sequence, it does not depart from the technical concept of this invention.

[0162] Example 2: Double screening and branchless bitwise operation sequence

[0163] This embodiment corresponds to the branchless dual screening and bitwise operation sequence scheme of the present invention.

[0164] like Figure 3 As shown, the dual screening process in this embodiment includes the following steps: loading of coupling identifier and query identifier 301, generation of displacement and bitmask parameters 302, spatial correlation determination 303, feature matching determination 304, logical AND hit determination 305, output of hit status signal 306, and generation of result bitmap 307.

[0165] Atomized Dual-Decision Execution Flow: The filtering engine sequentially executes the following branchless instruction sequence through the processor's Arithmetic Logic Unit (ALU): Spatial Associativity Determination: First, an XOR operation is performed to calculate the bit difference sequence between the pre-stored coupled identifier and the query identifier; then, a logical right shift instruction (SHR) is used to perform bit offset alignment, aligning the target space bit segment to the lower-order decision interval. In feature-first implementation mode, before performing the right shift operation, a bitwise AND operation is preferably performed on the XOR result using a space bit mask multiplexed as an isolation mask to mask the differences in the higher-order feature fields. Finally, spatial associativity is determined through zero-value determination.

[0166] Feature matching determination: A bitwise AND operation is performed on the pre-stored coupled identifier and query identifier using a feature bitmask to extract their respective feature segments; an equality comparison is then used to determine whether the two feature segments are consistent. The equality comparison shown in this embodiment corresponds to an exemplary implementation of exact matching; for composite feature filtering scenarios involving range queries or multiple selection conditions, feature matching determination can be configured as a non-zero check based on the extracted results or other branchless equivalent determination forms.

[0167] The overall hit output is achieved by performing a logical AND operation between the spatial correlation determination result and the feature matching determination result. If both are true, the target is determined to have been hit. This overall hit determination is implemented at the underlying physical execution level through a combination of conditional setting (SETcc), conditional transfer (CMOV), or bit-level logical instructions to avoid creating conditional jump paths that depend on the input data values.

[0168] In the feature-first implementation mode, the high-bit coding domain and the low-bit coding domain correspond to the business feature coding domain and the spatial location coding domain, respectively. The branchless bit operation sequence reuses the same set of high-bit coding domain determination and low-bit coding domain determination logic by adjusting the bit mask coverage interval and displacement parameters.

[0169] The technical principle of branchless bitwise operation sequences: This invention transforms traditional conditional filtering logic into branchless bitwise operation sequences. At the high-level language level, bitwise operators or other logical operators that can be mapped to non-jump execution mechanisms can be used to replace the traditional logical branching method. For example, during low-level physical execution, the processor can use a condition result writing mechanism (such as `sete`) to store the judgment result in a register, and then synthesize the final hit state through a logical AND instruction, thereby completing the dual judgment without changing the program counter (PC) value.

[0170] The underlying execution characteristics of traditional composite filtering logic with branch prediction risk are as follows: The processor first performs distance calculation. If calculateDistance(userPos, shopPos) ≤ radius is true, it enters the first-level conditional branch; otherwise, the processor executes a jump instruction to skip the current object. Inside the first-level branch, it further determines whether shop.type = targetType and shop.rating ≥ minRating are true at the same time. If they are true, the object is added to the result set; otherwise, the processor executes a jump instruction again to skip the current object.

[0171] The above logic contains multiple nested conditional jump instructions when executed at the lower level. The value of the program counter (PC) changes non-linearly with the judgment result of the input data. In scenarios where the candidate data distribution is highly discrete, it is easy to cause processor pipeline flushing, resulting in execution latency fluctuations.

[0172] This invention provides a schematic diagram of the branchless bitwise operation sequence logic (the following is a schematic diagram of the operator logic; at the underlying physical execution level, equivalent determination can be achieved through conditional setting, conditional passing, masked execution, or other non-jump conditional execution mechanisms):

[0173] Spatial correlation determination: Perform an XOR operation (⊕) on the pre-stored identifier and the query identifier to calculate the difference sequence, logically shift the result to the right by (>>) spatialShift bits and then check for zero; that is, spatialMatch = ((serverId ⊕queryId) >> spatialShift) == 0.

[0174] Feature matching determination: The feature bitmask is used to perform a bitwise AND operation (&) on the pre-stored identifier and the query identifier respectively to extract the feature bit segments, and then an equality comparison is performed; that is, featureMatch = (serverId & featureMask) == (queryId & featureMask).

[0175] Overall hit output: Perform a logical AND operation on the spatial correlation determination result and the feature matching determination result; that is, isHit = spatialMatch & featureMatch.

[0176] The technical features of the above branchless bitwise operation sequence are compared with those of the traditional branched screening scheme as follows:

[0177] Regarding the consistency of the query identifier and the pre-stored coupling identifier structure: The query identifier and the pre-stored coupling identifier maintain logical consistency in the weight allocation and partitioning boundaries of bit segments, regardless of their specific construction entities. As long as the pre-stored coupling identifier possesses the same structural features as the coupling coding structure described in this invention, the technical requirement of "structural consistency" can be met, thereby enabling the filtering method to be implemented independently of the construction method and adapting to multi-entity collaborative scenarios in distributed systems.

[0178] Explanation of the separation of control flow and decision flow: The "branchless" characteristic refers to the fact that the core execution path for filtering and determining each candidate coupled identifier does not contain conditional jump instructions that depend on input data. The counting branch used for loop control when traversing the candidate dataset belongs to the outer control flow and does not change the branchless technical feature emphasized by this invention for the dual decision path at the candidate object level.

[0179] Regarding the physical meaning of "synchronous completion within the same instruction stream": The "synchronous completion" described in this invention does not refer to concurrent execution within a single clock cycle (except for the pure hardware ASIC circuit configuration mentioned in the embodiments). Rather, it refers to the close scheduling and sequential passage of space-determination related instructions and feature-determination related instructions through the arithmetic logic unit (ALU) within the instruction pipeline of the same basic block of the processor. Between the start point (data loading) and the end point (output synthesis hit status) of this determination data stream, there is no control flow transfer that separates the two (such as short-circuit calculation branches that prematurely exit based on a certain determination result). This indivisibility in logical continuity and underlying hardware pipeline execution constitutes the "synchronous determination" described in this invention.

[0180] The physical basis for execution stability: In this embodiment, since conditional jump instructions are avoided, the decision logic is mapped by the compiler into an arithmetic logic sequence mainly based on basic bitwise operations such as XOR, SHR, AND, and CMP. Under the given hardware configuration and test conditions of the embodiment, the execution overhead of this type of instruction is generally low and relatively stable. Therefore, the fluctuation of the single decision time under different input data is relatively small, which helps to reduce the dispersion of response latency.

[0181] Compiler optimization and assembly instruction mapping example: The following example, using a "precise matching" scenario in 64-bit space-first mode, demonstrates the physical mapping of the branchless bitwise operation sequence logic described in this invention at the underlying hardware level. For range queries, feature-first, or other configuration modes, it can be mapped to an equivalent instruction sequence with the same branchless technique effect.

[0182] Exemplary decision logic (corresponding to bit offset alignment for spatial decision and mask extraction for feature decision):

[0183] Define the input parameters: the pre-stored coupling identifier is denoted as pre_stored_id, the query identifier is denoted as query_id, the spatial decision right shift displacement (calculated from the spatial bit prefix length L) is denoted as spatial_shift, and the feature bit mask is denoted as feature_mask.

[0184] One logical implementation of the core decision path is as follows:

[0185] (1) Spatial correlation determination: Perform an XOR operation (⊕) on pre_stored_id and query_id to calculate the bit difference sequence, logically shift the result to the right (>>) spatial_shift bits to align to the low-order boundary, and determine whether the result after shifting is zero; that is, spatial_match = ((pre_stored_id ⊕ query_id) >> spatial_shift) == 0;

[0186] (2) Feature matching determination: Use feature_mask to perform bitwise AND operation (&) on pre_stored_id and query_id respectively to extract feature segments, and determine whether the two feature segments are consistent by equality comparison; that is, feature_match = (pre_stored_id & feature_mask) == (query_id & feature_mask);

[0187] (3) Comprehensive hit output: Perform a logical AND operation on spatial_match and feature_match to output the final hit status; that is, is_hit = spatial_match & feature_match.

[0188] Among them, "⊕" represents bitwise XOR operation, ">>" represents logical right shift operation, and "&" represents bitwise AND operation.

[0189] An exemplary instruction sequence (based on x86-64 architecture) shows the following mapping between registers and the parameters mentioned above: rax / rdi carries pre_stored_id (pre-stored coupling identifier), rsi carries query_id (query identifier), cl carries spatial_shift (space decision right shift amount), and r8 carries feature_mask (feature bitmask). The specific steps of this instruction sequence are as follows:

[0190] (1) xor rax, rsi: Perform an XOR operation on the pre-stored coupled identifier and the query identifier, and store the bit difference sequence;

[0191] (2) shr rax, cl: Performs a logical right shift on the difference sequence, with a displacement of spatial_shift, to align the spatial segments;

[0192] (3) sete al: Set the spatial correlation determination state according to the zero flag bit. If the result after shifting is zero, then al is set to 1;

[0193] (4) and rdi, r8: Perform a bitwise AND operation on the pre-stored coupled identifier using the feature bitmask to extract its feature bit segments;

[0194] (5) and rsi, r8: Perform a bitwise AND operation on the query identifier using the feature bitmask to extract its feature bit segments;

[0195] (6) cmp rdi, rsi: Perform an equivalent comparison on the two extracted feature segments;

[0196] (7) sete dl: Set the feature matching judgment state according to the comparison result. If the two feature segments are equal, dl is set to 1;

[0197] (8) and al, dl: Perform a logical AND operation on the spatial determination state and the feature determination state to synthesize the final hit state.

[0198] The above instruction sequence does not include conditional jump instructions such as JMP, JZ, and JNZ. The value of the program counter (PC) increases linearly within the core decision path, which physically confirms the technical features of the branchless bitwise operation sequence described in this invention.

[0199] Key technology feature analysis:

[0200] (1) The above representative instruction sequence is composed of XOR, shift, bitwise AND, comparison and conditional set to form the core decision path. Among them, sete, cmov, csel or other non-jump conditional execution mechanisms can be used as equivalent implementations. As long as it does not cause the program counter (PC) to make a non-linear jump according to the input data decision result, they all belong to the branchless bit operation sequence described in this invention.

[0201] (2) The core decision path adopts basic bit operation instructions of fixed categories. Under a given hardware configuration, its execution overhead mainly depends on the operand bit width and instruction mapping method, and is basically decoupled from the specific value of the candidate object. Therefore, it is beneficial to reduce the pipeline recovery overhead caused by branch prediction mismatch in traditional branched schemes.

[0202] (3) On processors that support vector extension, the scalar decision logic can be further mapped to SIMD parallel implementation; in ASIC or FPGA implementation, the corresponding hardware execution path can be formed by input register interface, XOR logic gate array, barrel shifter, bitwise AND logic gate array, comparison logic circuit and output register interface to realize dual decision logic consistent with the implementation method of the present invention.

[0203] As an optional hardware implementation, the filtering and determination logic of this invention can be implemented by the data path circuit inside the chip. The input register interface is used to receive and temporarily store the coupling identifier, query identifier, spatial bit mask, feature bit mask, and displacement control signal. An XOR logic gate array performs a bitwise XOR operation on the coupling identifier and query identifier, outputting a difference bit sequence to a barrel shifter; the barrel shifter performs a shift operation on the difference bit sequence under the control of the displacement control signal to obtain an alignment result for the high-order coded domain determination. Simultaneously, a bitwise AND logic gate array combines the coupling identifier, query identifier, and the bit mask corresponding to the low-order coded domain to extract the low-order target bit segment, and sends the extraction result to the low-order coded domain equivalent comparison logic circuit. The high-order coded domain equivalent comparison logic circuit and the low-order coded domain equivalent comparison logic circuit output comparison results, which are then synthesized by an AND gate to output a hit status signal. A clock control unit is used to provide a synchronous clock signal to the above data path to drive the determination logic to complete execution.

[0204] In terms of functional correspondence, the input register interface and the general-purpose register group correspond to the input temporary storage stage in claim 30; the XOR logic gate array, the barrel shifter, and the high-order encoding field equivalent comparison logic circuit together correspond to the spatial correlation determination path of the high-order encoding field; the bitwise AND logic gate array and the low-order encoding field equivalent comparison logic circuit together correspond to the feature matching determination path of the low-order encoding field; the AND gate and the output register interface correspond to the synthesis of the dual determination results and the hit status output. For space-priority configuration and feature-priority configuration, the specific bit segment correspondence between the high-order encoding field and the low-order encoding field can be switched according to the input bitmask configuration, while the basic structure of the above hardware data path remains unchanged.

[0205] To facilitate understanding, a complete execution example of the core decision-making process described above is provided below, using the specific configuration of the 64-bit spatial priority mode. In this example, a 47-bit spatial location code and a 17-bit business feature code are used, and a 64-bit coupled identifier is formed through bit concatenation. During the query phase, the spatial bit prefix length is generated based on the spatial scale parameter, and the corresponding feature bit mask is generated based on the business type. The filtering engine determines the right shift displacement based on the spatial bit prefix length, and determines the combined feature bit mask based on the business type subdomain and the polymorphic business payload subdomain. Subsequently, spatial correlation is determined through XOR -> shift alignment -> zeroing, and feature matching is determined through bitwise AND -> equality comparison. Finally, logic is executed on the two results and the hit status is output. When using the feature priority mode, only the high and low bit arrangement of the business feature encoding field and the spatial location encoding field needs to be switched, and the mask coverage range and shift parameters are adjusted accordingly; its core dual decision-making logic still reuses the same branchless bit operation sequence.

[0206] Example 3: Distance Mapping and Neighborhood Expansion

[0207] This embodiment corresponds to the spatial bit prefix length adaptive mapping scheme and the adaptive neighborhood expansion filtering scheme based on bit feature prediction of the present invention.

[0208] like Figure 4 As shown in the figure, this embodiment illustrates the mapping relationship between the retrieval radius R and the spatial bit prefix length L. For example... Figure 5 As shown, when the target query coordinates are at the grid boundary, the neighborhood expansion mechanism avoids missing neighboring data.

[0209] Distance-Bit Prefix Mapping and Bit Truncation Logic: During spatial filtering, to adapt to the atomic shift operations of the underlying processor, the system needs to map the target retrieval radius R to a fixed spatial bit prefix length L. This embodiment constructs an adaptive empirical mapping formula based on the target scale, supporting arbitrary bit truncation of spatial position encoding with a fixed bit width, to achieve smooth spatial scale control.

[0210] L = Ns - ⌊log2(R / R0) × k⌋

[0211] The physical meanings of the parameters in the above formula are as follows: L is the spatial bit prefix length, used to determine the displacement amount of the displacement operation when the processor performs spatial correlation determination; Ns is the total bit width of the spatial position coding field (47 bits in this example); R is the target retrieval radius (meters); R0 is the preset reference grid cell side length (meters); k is the curve level mapping coefficient.

[0212] The spatial bit prefix length L output by the mapping formula follows the following bidirectional clamping constraint: the calculation result of the spatial bit prefix length L needs to be dynamically constrained within a preset effective value range [L_min, L_max]. Specifically, when the calculated value exceeds the upper limit of the range, the system clamps it to the upper limit Ns - S_suffix (where Ns is the total bit width of the spatial location coding field, and S_suffix is ​​the reserved suffix bit width); when the calculated value is lower than the preset lower limit of the range, it is clamped to the lower limit (e.g., 8 bits). This bidirectional clamping mechanism ensures that the displacement parameter when the processor performs a displacement operation is always within a preset stable and effective range, and maintains the stable execution of the spatial correlation determination logic under different retrieval scales.

[0213] Parameter calibration and mapping mechanism description: The above formula is the adaptive empirical mapping formula in the system of this invention. In actual deployment, its baseline parameters (R0 and k) are determined through conventional parameter calibration experiments in the field: by selecting POI sample data from representative geographical areas, the retrieval precision and recall are statistically analyzed within the target retrieval radius, and the values ​​of R0 and k are dynamically adjusted until the preset precision threshold is met.

[0214] When the underlying spatial encoding is preferably generated using the S2 geometric algorithm, the parameter calibration can be anchored with reference to the grid size range of each level in the official S2 Cell Statistics. For example, in an example configuration with a baseline grid side length R0 = 10 meters and a mapping coefficient k = 1.2 (in this configuration, changes in the R value can be smoothly converted into L-bit truncation, and are not limited to strict alignment with a specific discrete level), the typical mapping relationship between the retrieval radius R and the spatial bit prefix length L is shown in the table below:

[0215] Technical effects and physical implementation: Through the above mapping mechanism, the computing device can dynamically generate a determined prefix length L according to the retrieval requirements. This L value is directly mapped to the right shift operand in the processor's underlying instruction stream (e.g., the SHR instruction operand in the x86 architecture).

[0216] Based on the topological order preservation property of spatial filling curves such as Hilbert, even if the above L values ​​are not aligned to specific discrete level boundaries, the high-order prefixes retained after truncation usually form prefix clusters of corresponding local physically adjacent regions in numerical space. This truncation mechanism based on continuous displacement can filter out most irrelevant spatial objects, achieving a relatively efficient low-level coarse screening; combined with the adaptive neighborhood expansion mechanism in the system, the recall and accuracy of spatial retrieval can be further improved.

[0217] Range and constraints of L: In a preferred embodiment of the present invention, the range of values ​​for the spatial bit prefix length L follows the constraints:

[0218] (1) Minimum value constraint: The minimum value of L is not less than 8 bits, so that the truncated spatial coding prefix still has basic geographic topology order preservation and can distinguish different large-scale geographic regions.

[0219] (2) Maximum value constraint: The maximum value of L is Ns minus the reserved suffix bits S_suffix, where S_suffix is ​​2 to 8 bits, used to support the boundary determination trigger of the neighborhood expansion mechanism; this configuration retains sufficient geographic discrimination accuracy in the high-bit segment of spatial coding, while reserving a fixed reserved suffix bit segment for boundary awareness in the low-bit segment.

[0220] (3) Description of suffix bits: The reserved suffix bits are used to detect whether the spatial code in the query identifier is in the critical state of the grid boundary (such as the suffix bit sequence is all 0 or all 1). When the typical value is 4-6 bits, a good balance can be achieved between boundary detection accuracy and spatial code utilization.

[0221] Taking a 64-bit coupled identifier (spatial location coding field Ns=47 bits) as an example, the typical value range of L is 8 to 45 bits (47 bits minus 2 reserved suffixes), and the corresponding retrieval radius ranges from about 100 kilometers to 5 meters.

[0222] Calculation Example: Taking a 64-bit coupled identifier as an example, let the total bit width of the spatial location coding field Ns = 47, the bit width of the business feature coding field Nf = 17, the side length of the reference grid cell R0 = 10 meters, and the curve hierarchy coefficient k = 1.2. When the target retrieval radius R = 500 meters:

[0223] (1) Calculate the ratio: R / R0 = 500 / 10 = 50

[0224] (2) Calculate the logarithm: log2(50) ≈ 5.64

[0225] (3) Application coefficient: 5.64 × 1.2 ≈ 6.77

[0226] (4) Rounding operation: ⌊6.77⌋ = 6

[0227] (5) Calculate the prefix length: L = 47 - 6 = 41

[0228] Therefore, a 500-meter search radius corresponds to a 41-bit spatial prefix length. Due to the use of space-first mode (47 bits for the spatial domain, 17 bits for the feature domain, and a total bit width of 64 bits), when the processor performs spatial correlation determination, it needs to right-shift the XOR result by 23 bits (i.e., N - L = 64 - 41 = 23) and compare it with zero, thereby aligning the spatial prefix while automatically shifting the low-order feature differences out of the register.

[0229] Physical Implementation Explanation: The L value calculated by the above formula directly corresponds to the bit operand when the processor performs spatial determination. Specifically, when performing spatial correlation determination, the processor needs to right-shift the XOR result by (NL) bits (corresponding to the SHR instruction) to align the spatial bit segment to the low-order bits, and then perform a zero comparison. The larger the L value, the smaller the corresponding right shift operation displacement, and the more refined the spatial determination; the smaller the L value, the larger the corresponding right shift operation displacement, and the coarser the spatial determination. The specific right shift displacement depends on the encoding arrangement mode: in space-priority mode, the displacement is equal to the total bit width minus the current spatial bit prefix length L (i.e., N - L). This operation automatically shifts the low-order feature field difference out of the register while aligning the spatial prefix; in feature-priority mode, the displacement is equal to the total bit width of the spatial position encoding field minus the spatial bit prefix length L (i.e., Ns - L), but the high-order feature field needs to be cleared beforehand using the AND instruction to prevent shift pollution. This design, which transforms mathematical mapping into hardware configuration parameters, allows the L value to directly control the displacement operands of the processor's hardware shifter and align with the register bit width, producing a corresponding physical effect. That is, the execution delay of spatial determination mainly depends on the gate delay of the hardware shifter and ALU, and has a low correlation with the input retrieval radius value or geographical data distribution, thereby reducing pipeline flushing losses caused by software condition judgment.

[0230] The correspondence between the formula and the physical implementation: The space bit prefix length L is used to determine the shift amount of the bitwise operation when the processor performs bitwise operations. Taking a 64-bit space-first implementation (Ns=47, Nf=17) as an example, when L=30 is calculated, the filtering engine needs to right-shift the XOR result (SHR instruction) by 34 bits (i.e., the total bit width 64-30) before comparing it with zero; when L=32, it is right-shifted by 32 bits (i.e., 64-32). This mapping relationship allows changes in the search radius to be directly converted into operand adjustments in the underlying CPU instructions, without the need to redesign the algorithm logic or reconstruct the data structure.

[0231] Neighborhood expansion mechanism: Spatial filling curves such as S2 or GeoHash exhibit boundary effects of "geographical proximity and coding abrupt change" when mapping two-dimensional space to a one-dimensional sequence. This invention predicts critical states by detecting the suffix bit segment features of the spatial encoding in the query identifier.

[0232] (1) Boundary triggering condition: The suffix segment meets the preset boundary critical threshold (all 0 or all 1) or falls into the edge transition interval condition;

[0233] (2) Extension strategy: Directly generate adjacent grid codes through bit operations and perform cascaded batch retrieval.

[0234] The hierarchical definition of boundary critical threshold conditions: The boundary critical threshold conditions include the bit sequence of the reserved suffix bit segment presenting a logical extreme state of all 0s or all 1s, or its value falling into a preset edge transition interval that matches a specific curve algorithm. It should be understood that the boundary transition characteristics in the bit space differ for different types of space-filling curves, and this system supports configuring corresponding edge transition intervals as trigger signals.

[0235] As a preferred trigger criterion implementation, the boundary critical threshold condition is specifically defined as follows: For an embodiment using the S2 geometric algorithm, the typical value of the suffix segment length S_suffix is ​​4-6 bits. Let the suffix segment value be V_suffix, then the boundary critical threshold condition is defined as:

[0236] (1) All-zero critical state: V_suffix == 0, indicating that the target query coordinates are located at the origin of the encoding space of the current grid;

[0237] (2) All-1 critical state: V_suffix == (2^S_suffix - 1), indicating that the target query coordinates are located at the end of the encoding space of the current grid;

[0238] (3) Edge transition interval determination: V_suffix < T_edge or V_suffix > (2^S_suffix - 1 -T_edge), where T_edge = ⌈2^(S_suffix-2)⌉.

[0239] Specific numerical calculation examples: When the suffix field length S_suffix = 5 bits, T_edge = ⌈2^(5-2)⌉ = 8, and the edge transition interval is V_suffix < 8 or V_suffix > 23 (because 2^5-1-8=23); when S_suffix = 4 bits, T_edge = ⌈2^(4-2)⌉ = 4, and the edge transition interval is V_suffix < 4 or V_suffix > 11.

[0240] The boundary abrupt change characteristics of different space-filling curves differ: the boundary abrupt change of the S2 curve is concentrated at the surface boundary, the boundary abrupt change of the Hilbert curve is concentrated at the curve inflection point, and the boundary abrupt change of the Z-Order curve is concentrated at the quadrant boundary line. Those skilled in the art can determine the corresponding suffix segment length S_suffix and edge threshold T_edge by analyzing the boundary jump rules of its coding space based on the selected space-filling curve type.

[0241] Quadrant pruning optimization: Based on bit features, extract the corresponding quadrant positions of the target query coordinates within the current logical grid, and only query adjacent grids in the necessary directions, reducing the average number of query grids from 9 to approximately 2.5-4.

[0242] The specific implementation of quadrant pruning optimization: The system extracts the local spatial distribution features carried in the reserved suffix segments and retrieves their corresponding quadrant positions within the current logical grid through a preset binary neighborhood mapping table (lookup table). This "lookup table mapping" mechanism can directly generate specific adjacent grid prefixes bordering the corresponding quadrant in the bit space based on the encoding evolution state of the space-filling curve in the local region, thereby avoiding the complex overhead of recalculating and inverse mapping geographic coordinates. Taking a 5-bit suffix segment as an example, the system locates the bordering grid prefix of the target quadrant from the preset binary neighborhood mapping table based on the local position features corresponding to the suffix segment, and combines it with the segment corresponding to the business feature encoding field in the query identifier to generate a new query identifier in situ, so that the instruction flow still maintains a relatively stable execution path when neighborhood expansion is triggered.

[0243] Explanation of distance-bit prefix mapping adaptation in feature-first mode: When using a feature-first coupled coding structure to perform spatial correlation filtering, the calculation logic of the spatial bit prefix length L remains consistent with the above-described space-first mode, but the difference in bit segment arrangement needs to be adapted in the instruction execution sequence of the underlying ALU. Specifically:

[0244] (1) Hardware decision sequence adaptation (bit field protection mechanism): In feature priority mode, the service feature code occupies the high bit segment, and the spatial location code is located in the low bit segment. Since the logical right shift (SHR) operation will push the high bit data to the low bit, if the XOR result is directly right-shifted, the high bit feature difference will be mixed into the target spatial decision domain. Therefore, the processor must first use the spatial bit mask multiplexed as an isolation mask to perform a bitwise AND operation to accurately clear the difference sequence generated by the high bit feature domain, and then perform a right shift (SHR) operation on the remaining pure spatial bit segment to truncate the low bit suffix, and finally perform a zero comparison (CMP). The isolation function can be implemented at the hardware execution level by multiplexing or equivalently configuring the spatial bit mask output signal in the general-purpose register group of claim 30, without the need to set up an additional independent third mask input channel.

[0245] (2) Instruction flow compatibility: The core branchless instruction set (XOR, SHR, AND, CMP) remains consistent in both encoding modes, with only the execution order of instruction operands and the mask coverage bit field being adapted; this enables the determination engine of the present invention to utilize the hardware execution characteristics of the processor in both primary and secondary heterogeneous index modes, maintaining a relatively stable execution latency.

[0246] (3) Unified degradation scenario: When the feature matching determination is always true by implementing logical bypass through the corresponding feature bit mask configuration, the feature priority mode can be degraded into pure spatial retrieval. Its determination logic is completely equivalent to the degradation scenario of the spatial priority mode, and neither needs to introduce additional conditional jump control logic in the core hardware execution path.

[0247] Example 4: Dynamic Maintenance Mechanism for Coupled Identifiers Based on Bit-Segment Separation

[0248] This embodiment corresponds to a dynamic maintenance mechanism for coupled identifiers based on bit segment separation. This embodiment provides a dynamic maintenance mechanism for coupled identifiers based on bit operations, used to dynamically update coupled identifiers through incremental calculations when local attributes of data objects change, such as geographical displacement or changes in business characteristics.

[0249] Parameter Definitions and Logical Basis: To adapt to multi-dimensional composite structures including spatial location coding domains, business feature coding domains, and one or more additional coding domains, this mechanism is based on the logic of "bit segment isolation and in-situ embedding." The relevant input parameters are defined as follows:

[0250] Raw_Value (raw bit segment value): refers to the single-dimensional raw binary code that has not been shifted and aligned and conforms to the target bit width constraint.

[0251] Old coupling identifier: refers to the pre-update coupling identifier currently maintained in the ordered index structure.

[0252] Field_Mask (target bit field mask): refers to a binary sequence within a preset fixed bit width, where the corresponding bit field to be updated is "1" and the remaining bits are "0".

[0253] Preserve_Mask (Preserved Bitmask): Refers to the binary sequence generated by inverting the bits of Field_Mask within a preset fixed bit width, used to perform masking and preservation of non-changing bit fields during the update process.

[0254] Shift_Param (displacement parameter): refers to the starting offset of the target bit segment in the overall bit weight structure of the coupled identifier, that is, the bit number corresponding to the least significant bit of the bit segment.

[0255] Incremental update execution process: The system uses the processor's general-purpose registers to generate the updated coupling identifier (new coupling identifier) ​​through the following sequence of register-level bitwise operations executed consecutively during a single update: New coupling identifier = (old coupling identifier & Preserve_Mask) | ((Raw_Value << Shift_Param) & Field_Mask)

[0256] The specific physical execution steps include:

[0257] (1) Use Preserve_Mask to perform a bitwise AND operation on the old coupled identifier, effectively masking and preserving the non-changed dimension bit information while physically clearing the target bit segment range to be updated;

[0258] (2) Shift Raw_Value left by Shift_Param bits so that its physical position is aligned with the target bit segment weight range in the coupled identifier structure;

[0259] (3) Use bitwise OR operation to embed the aligned new value into the cleared bit segment range to complete the in-situ reassembly of the coupled identifier.

[0260] When using the feature-first mode, you only need to adjust the configuration of Field_Mask, Preserve_Mask and Shift_Param according to the corresponding bit field arrangement to achieve a local update equivalent to the space-first mode.

[0261] Related Updates and Uniqueness Guarantee: If the value of an additional encoded field (such as a version identifier, verification information, or status identifier) ​​in the coupled identifier depends on the updated spatial location segment or business feature segment, the system synchronously recalculates, increments, or changes the status of the corresponding additional encoded field during the execution of the above sequence to maintain the logical consistency between the encoded fields within the coupled identifier. If the newly generated coupled identifier conflicts numerically with the identifier of an existing data object, the system can invoke the additional sequence bit increment, version bit adjustment, or multi-value mapping storage mechanism described in Example 1 to ensure the uniqueness of the data object in the numerical space.

[0262] Specific implementation example: The following example uses a 64-bit space-first configuration (the high 47 bits are the spatial field, and the low 17 bits are the feature field) to demonstrate a specific implementation of the general update mechanism. Both `newFeatureRawValue` and `newSpatialRawValue` below represent the original bit field value without shift alignment.

[0263] The specific implementation of local bit-field updates (taking a 64-bit space-first configuration as an example, Ns=47, Nf=17):

[0264] Where SPATIAL_MASK is a bitmask with all 1s in the high 47 bits and all 0s in the low 17 bits, FEATURE_MASK is a bitmask with all 1s in the low 17 bits, and FEATURE_BITS = 17.

[0265] Local update of the feature domain: The spatial domain remains unchanged, and new feature values ​​are written. Its logical expression is: new coupling identifier = (old coupling identifier & SPATIAL_MASK) | new original feature value.

[0266] Spatial domain local update: The feature domain is preserved, and a new spatial value is written. Its logical expression is: new coupling identifier = (new original spatial value << FEATURE_BITS) | (old coupling identifier & FEATURE_MASK).

[0267] In configurations that include additional coding fields or intermediate bit segments, local updates of any target bit segment can be achieved by resetting Field_Mask, Preserve_Mask, and Shift_Param according to the aforementioned general update formula, without changing the values ​​of other unchanged bit segments.

[0268] Execution performance and storage layout characteristics: The incremental generation process of coupled identifiers is characterized by the execution of a fixed-length register-level instruction stream. Since it avoids the overhead of full recoding and object serialization, this stage has a definite constant-level (O(1)) computational complexity. After generating a new coupled identifier, the system synchronizes it to the ordered index structure according to the aforementioned dynamic maintenance mechanism. The execution performance of this synchronization process is affected by the underlying ordered structure maintenance strategy, physical storage medium characteristics, and concurrency control mechanisms.

[0269] Based on the bit weighting rules of coupled identifiers, when changes occur in low-weight bit segments (such as business feature coding fields or some low-weight additional coding fields), the new coupled identifier and the old coupled identifier usually have high proximity in numerical space. In the underlying ordered index, this numerical proximity increases the statistical probability that the new and old identifiers fall into the same physical storage unit or adjacent storage units, making index adjustments more likely to manifest as local intra-page modifications or migration adjustments between adjacent storage units. Compared to large-span geographical displacements that cause abrupt changes in high-weight bits, this mechanism helps alleviate the global index rebalancing overhead in scenarios with frequent business feature changes, thereby reducing the risk of write amplification. To intuitively demonstrate the technical advantages of the coupled identifiers described in this invention in terms of underlying index maintenance efficiency, the performance characteristics of traditional multidimensional index structures and the solution of this invention are compared in typical maintenance scenarios below:

[0270] Example 5: Dynamic Density Adaptive Mechanism for Computational Load Balancing

[0271] This embodiment corresponds to the dynamic density adaptive mechanism for computing load balancing of the present invention, and provides a dynamic load balancing mechanism for hardware cache topology optimization.

[0272] 1. Density adaptive core logic and stability control

[0273] The system uses a logical grid dynamically determined by the current spatial bit prefix length L as the statistical unit, and periodically monitors the scale of data objects falling within the grid. To prevent frequent changes in the retrieval path (i.e., "jitter") due to slight data fluctuations at the threshold edge, this embodiment introduces a stability control rule based on hysteresis. The dynamic adjustment strategy for the spatial bit prefix length L is as follows:

[0274] In the above adjustment strategy, the system presets a high-load threshold T_high=2048 and employs dual-threshold hysteresis control on the low-load side: the first low threshold T_low1=256 is used to trigger moderate grid expansion, and the second low threshold T_low2=128 is used to trigger further grid merging. When the object size continuously crosses higher load ranges, the adjustment can be further increased to +4 bits based on the +2 bit adjustment to cope with cache capacity overflow in extremely dense scenarios.

[0275] The second low threshold T_low2=128 can be determined based on the comprehensive calibration results of query fan-out overhead, cache utilization and scheduling benefits under low load scenarios.

[0276] Special note: The dynamic adjustment of the spatial bit prefix length L only affects the displacement parameters and real-time generation of the spatial bit mask during the retrieval phase. It does not change the fixed bit width configuration of the underlying stored data object coupled identifier, nor does it change the physical bit boundary between the spatial location encoding field and the business feature encoding field. This "logically dynamic, physically fixed" design helps to improve the execution efficiency of the arithmetic logic unit (ALU) without triggering the underlying index reconstruction.

[0277] 2. Hardware parameter calibration and cache affinity principle

[0278] The aforementioned high-load threshold T_high=2048 is a hardware alignment calibration result based on the processor's L1DCache capacity in one embodiment. Taking a typical 64-bit coupled identifier as an example, when the object size M=2048, the size of the data block to be processed is well matched with common L1 cache capacity constraints. By controlling the size of the candidate set executed in a single branchless bitwise operation sequence within a range that is compatible with the cache capacity, it is beneficial to improve the cache hit rate and reduce memory access wait overhead.

[0279] Example of specific parameter calibration steps:

[0280] (1) Sample selection: Select a sample dataset from a representative geographical region as the offline calibration environment;

[0281] (2) Constraint setting: Maintaining the processor's L1 cache hit rate as the core performance constraint;

[0282] (3) Multiple sets of experiments for comparison: Under different retrieval scales, the scale of data objects falling into a single logical grid under different T_high (e.g., 1024, 2048, 4096) was tested respectively;

[0283] (4) Determine the preferred value: Through statistics, it was found that when T_high is 2048, the amount of candidate set data scanned in a single branchless bit operation sequence is well matched with the common level 1 cache capacity constraint. Therefore, in this embodiment, T_high=2048, T_low1=256 and T_low2=128 are used as the preferred parameter combination.

[0284] This strategy is essentially a dynamic load balancing approach for hardware cache topologies: the system adaptively adjusts the spatial bit prefix length L to directly control the shift operands during bitwise operations performed by the processor, keeping the amount of data intercepted in each decision within a load range that matches the processor's cache capacity. Under the test conditions of the example implementation, this mechanism helps improve cache hit rate and maintain good cache affinity.

[0285] 3. Composite decision-making mechanism

[0286] As a preferred implementation, the dynamic density adaptive mechanism can combine "feature filtering intensity" to perform composite decision-making. When the data size M within the logical grid exceeds the high load threshold, but the feature bitmask coverage in the filtering request is narrow (i.e., the feature filtering intensity is high and the expected filtering rate is large), the system can choose to maintain the current L value without triggering a split, thereby balancing the management overhead and computational benefits brought about by grid splitting.

[0287] 4. Degradation Scenarios and Execution Constraints

[0288] The handling of encoding domain degradation scenarios follows the unified degradation mechanism described in Example 1: when any encoding domain is bypassed in the decision logic by setting the corresponding mask to zero and the displacement parameter to zero, the core decision instruction stream does not need to be modified. Regarding boundary jitter protection, the rewrite operation of L is only performed when the data size stably crosses the threshold for multiple consecutive statistical periods, or when the crossing range exceeds a preset offset (e.g., ±10%).

[0289] 5. Parameter isolation and consistency guarantee

[0290] The dynamic adjustment of the spatial bit prefix length L adopts a parameter snapshot mechanism, configuration version mechanism, or other equivalent consistency mechanism. When a mesh split or merge is triggered, causing a change in the L parameter, the newly generated displacement control signal and bit mask parameter only apply to subsequent filtering requests; the in-transit decision sequence that has entered the execution pipeline uses the parameter snapshot corresponding to its start time to ensure the consistency of the decision logic within a single filtering task.

[0291] Example 6: In-situ bitwise operation filtering and truncation mechanism at the computing device end

[0292] The "atomic execution unit" and "in-situ scanning process" described in this embodiment correspond to the in-situ bitwise operation filtering and truncation mechanism based on computational pushdown of the present invention; the deployment architecture and request-response logic described in this embodiment correspond to the geographic data filtering method deployed on the computing device side. For example... Figure 8 As shown, the execution flow on the computing device side includes receiving the filtering request 801, generating the query identifier and mapping the bitmask parameters 802, issuing the filtering instruction stream 803, executing the double filtering loop 804, accumulating the hit counter 805, truncating the instruction stream logic and recording it with the underlying cursor 806, extracting the hit result set and the underlying cursor 807, and returning the filtering result with the cursor 808.

[0293] Supplementary explanation of the physical implementation and deployment of the atomic execution unit: This invention pushes down and encapsulates the dual-determination bitmask operation logic into an atomic execution unit residing within the storage layer, realizing a near-data computation mode that "aligns computation to data". Specific implementations of the atomic execution unit include, but are not limited to, the following forms:

[0294] Software and middleware deployment forms: software execution modules, database extension units, filtering execution components, script execution environments, or other equivalent execution carriers residing in storage nodes or index nodes.

[0295] Hardware acceleration and near-data computing deployment forms: in-situ computing modules inside the storage engine, near-data computing (NDP) modules, programmable hardware acceleration devices, or other computing devices deployed on the storage side that can perform bitwise operations and determinations in-situ.

[0296] It should be noted that the specific names and terms mentioned above are only used to illustrate the feasible engineering implementation path of the present invention, and are not an exhaustive list of the physical forms of the execution carrier of the present invention, and should not be construed as limiting the scope of protection of the present invention.

[0297] In-situ scan execution process and hardware coordination mechanism: Cursor positioning: Utilizing the order-preserving property of coupled identifiers in the numerical space, the storage layer quickly locates the scan starting point by filtering the optional starting cursor carried in the request (this cursor is not required for homepage queries). Internally, the cursor can be represented by the coupled identifier value, the logical offset of the underlying index node, physical storage positioning information, or a combination thereof. This mechanism reduces the offset discarding overhead that grows O(N) with increasing page numbers in traditional database LIMIT / OFFSET paging.

[0298] During incremental scanning, because geographically proximate data objects exhibit localized clustering in the underlying storage medium, the execution unit can more easily trigger processor prefetching, reducing object deserialization and intermediate data transport overhead. For directly addressable data processing environments, the filtering engine can also directly perform judgments on the underlying binary bitstream to further reduce additional copy layers. When the hit counter reaches a preset threshold, the execution unit can trigger outer loop truncation and record the underlying cursor to stop subsequent candidate data judgment and I / O reading. This outer control flow does not change the branchless characteristic emphasized by the dual judgment path at the candidate object level in this invention.

[0299] In the optional enhanced scenario of the vectorized parallel filtering mode described in Example 8, if the cumulative number of hits produced by a single batch judgment exceeds the preset threshold, the execution unit extracts the low-bit hit objects that meet the remaining required number through the mask bitmap, and performs logical truncation and cursor recording after accurately aligning the hit number threshold to ensure the accuracy of the pagination results.

[0300] Degradation scenario handling: When the hit count threshold is configured to 0 (representing a full scan) or exceeds the current candidate set size, the truncation mechanism automatically bypasses the threshold. The system completes a full scan using the same branchless bitwise operation sequence, ensuring that the instruction execution path remains consistent under this configuration.

[0301] As a preferred implementation, the specific offline calibration steps for the preset value of the "hit count threshold" are as follows:

[0302] (1) Sample set selection: Select a representative sample dataset to simulate high-concurrency retrieval scenarios;

[0303] (2) Multi-indicator statistics: Under different paging requirements (threshold = 20, 50, 100), the end-to-end latency, main memory (RAM) bandwidth utilization and the reduction in CPU instruction cycles are statistically analyzed;

[0304] (3) Optimal Threshold Determination: Through calibration, it was found that in the mobile pagination display scenario, the hit count threshold of 20 can be taken as the preferred configuration in one embodiment. At this time, the end-to-end latency is reduced compared with the full return, the computing power occupation time is shortened, and the preset service quality constraints are met.

[0305] For extreme load scenarios involving a search radius of 50km, a candidate set of 100,000 entries, and a single page retrieval of 20 entries, the technical performance of the proposed solution is quantitatively compared with that of traditional solutions as follows:

[0306] Combining the hardware word length alignment feature described in Example 1, this mechanism achieves optimization effects across the entire link from instruction pipeline and cache to network transmission.

[0307] Example 7: Distributed Sharded Routing

[0308] This embodiment corresponds to the fragmented routing and adaptive adjustment mechanism of the present invention. For example... Figure 9 As shown, this invention utilizes the spatial location encoding field of coupled identifiers to achieve geographic proximity-aware data fragmentation storage and retrieval routing. Figure 9 The main focus is on demonstrating the correspondence between routing sharding key extraction 901, sharding mapping routing logic 902, and distributed storage units 903-906.

[0309] The fragmented route extraction mechanism achieves atomic sorting through native bitwise operation instructions of the processor. This extraction process is compatible with both space-first and feature-first encoding arrangement modes. The specific process is as follows:

[0310] (1) Space priority mode: Since the spatial location coding field is located in the high bit, the system uses the bit mask to extract the first K binary bits starting from the start bit, and then uses a logical right shift instruction (the right shift displacement is configured as the total bit width N of the coupling identifier minus K) to sink it to the low bit of the register as an integer routing fragment key.

[0311] (2) Feature Priority Mode: Since the spatial location coding field is located in the low bit, the system first uses the preset spatial field isolation mask to perform bitwise AND operation to isolate the pure spatial bit segment. Then, it directly uses a single logical right shift instruction (the right shift displacement is configured as the spatial bit width Ns minus K) to sink the target spatial prefix to the low bit of the register and directly extract it as the integer fragment key.

[0312] This instruction sequence of "mask isolation + shift alignment" ensures that the sharding logic maintains physical consistency across different encoding modes. The correspondence between the K value and the geographic scale is determined based on the hierarchical scaling ratio of the spatial curve (e.g., K=12 corresponds to approximately 100 kilometers, K=16 corresponds to approximately 25 kilometers), and its preferred range is configured to be 8 to 24 bits. For spatial filling curves with surface identifiers, such as S2 geometry, the K value preferably includes a Face ID bit segment to ensure that data within the same spherical patch is routed to the same storage node.

[0313] By establishing a mapping relationship between routing shard keys and distributed storage node identifiers, data objects are routed to target storage nodes during the data writing phase, thereby achieving localized merging of spatially related data objects at the storage shard level.

[0314] The system behavior of targeted retrieval is as follows: When receiving a filtering request, the computing device gateway synchronously performs the same shard key extraction operation on the query identifier as in the write phase. In non-boundary expansion scenarios, filtering instructions are typically distributed to the corresponding storage units, while in cross-boundary query scenarios, multi-path parallel distribution can be performed on adjacent target shards. This routing mechanism typically manifests at the system level as a specific filtering request generating inbound traffic only on the target shard node, rather than being broadcast across the entire cluster.

[0315] Elastic Reconfiguration and Degradation Scenarios: The system establishes a three-layer mapping model of "sharding key - routing mapping layer - physical node" to monitor the data load density or access frequency of each storage shard in real time. When the monitored value triggers a preset high load threshold (such as storage occupancy > 80% or access concurrency exceeding a preset water level), the sharding key length K is dynamically adjusted to perform shard splitting. When the load index of logical shards with the same high-bit spatial prefix (i.e., sibling shards sharing a common prefix) is continuously lower than the preset low load threshold, a shard merging operation is performed. The splitting or merging operation only involves adjusting the routing mapping relationship; the coupled identifiers associated with the data objects themselves remain encoded unchanged, thereby reducing deserialization and rehashing calculations. The cross-node data flow involved at the underlying level is manifested as sequential movement of data blocks based on continuous spatial prefixes in space-first mode, and as batch migration of one or more data intervals corresponding to the target spatial prefix in feature-first mode, rather than the row-by-row parsing and index reconstruction in traditional distributed systems. Elastic scaling can be achieved by rewriting the routing mapping table in memory and performing the corresponding data block or data range transfer; its end-to-end effective time is affected by specific deployment and network conditions, and overall it shows a relatively smooth system elastic reconstruction.

[0316] Extended Explanation of Physical Characteristic Parameters: The physical characteristic parameters (storage bit occupancy rate, addressing concurrency frequency, data channel bandwidth utilization rate) described in this invention are merely illustrative and do not constitute a closed limitation. Level signals, logical indicators, or hardware monitoring values ​​that can characterize the load state of storage units can all be categorized within the scope of the physical characteristic parameters described in this invention, including but not limited to: disk I / O latency, network connection pool saturation, cache hit rate, etc. This open-ended description allows the adaptive adjustment mechanism of this invention to adapt to heterogeneous distributed storage architectures and diverse load monitoring methods.

[0317] The technical essence of shard merging operation: Shard merging refers to utilizing the fixed-width characteristic of coupled identifiers to modify the correspondence between the routing mapping layer and physical nodes. Logically adjacent shards with the same high-order spatial prefix (i.e., sibling shards sharing a common prefix) are remapped to a single storage unit for unified addressing, thereby reducing system metadata overhead and the number of concurrent distributed addressing requests. Similar to shard splitting, merging only involves rewriting the routing mapping table; data objects maintain their original encoding characteristics, thus reducing the large-scale index reconstruction caused by resharding in traditional distributed systems. The underlying cross-node data flow manifests as sequential data block movement based on continuous spatial prefixes in space-priority mode, and as batch migration of one or more data intervals corresponding to the target spatial prefix in feature-priority mode, rather than row-by-row parsing and rehashing calculations. This automatic scaling mechanism enables the system to split and distribute data during peak periods and merge during off-peak periods to save energy, while reducing metadata bloat and query fan-out overhead caused by continuous fragmentation of logical shards.

[0318] In extreme degradation scenarios of distributed sharded routing, the specific processing logic of the system is as follows:

[0319] Scenario A (K=0 Degenerate): When K=0, the routing shard key degenerates into a global constant value, that is, all data objects are mapped to the same shard identifier, and the filtering command is downgraded to full broadcast probe mode.

[0320] Scenario B (K = Maximum value degradation): When the value of K reaches the total bit width Ns of the spatial location coding field, the routing key has the maximum distinguishability, and the filtering instruction converges to the minimum target fragment set according to the fragment mapping routing logic to perform the retrieval.

[0321] Scenario C (Query-side cross-shard boundary processing): In response to the boundary jump characteristics of the space filling curve, the gateway layer reuses the adaptive neighborhood expansion mechanism based on bit feature prediction described in Example 3 to generate candidate route shard keys for adjacent grids in the bit space, and concurrently distributes the query command to the corresponding target storage shard. Finally, the gateway layer merges the returned local result sets.

[0322] For the specific bit operation logic of the coding domain degradation (pure space / pure feature) involved in the above scenario, please refer to the unified processing mechanism in Example 1.

[0323] Maintaining structural consistency in multi-entity scenarios: In a typical distributed scenario of this invention, the index building module (entity A) is deployed on the data access gateway, responsible for executing steps S1-S3 and generating coupling identifiers that conform to the encoding rules of this invention; the filtering execution module (entity B) is deployed on each distributed storage shard node. When entity B receives the query identifier, it does not need to re-parse the original geographic coordinates, but directly executes an atomic, branchless bitwise operation sequence based on the consistent bit weight allocation rule between the query identifier and the pre-stored coupling identifier; the bit weight allocation rule includes a preset arrangement protocol for the correspondence between the high-bit encoding domain, low-bit encoding domain and spatial location encoding domain, and business feature encoding domain. This "preset structural consistency" ensures that even in a cross-entity, cross-network environment, the atomicity of the determination and the stable execution path characteristics still hold, thereby achieving the collaboration of geographic data construction and filtering.

[0324] Example 8: SIMD Vectorized Parallel Filtering

[0325] This embodiment corresponds to Article 22 (Vectorized Memory Model) of the SIMD Vectorized Parallel Filtering Scheme and Terminology Definition of the present invention. For example... Figure 7 As shown, the vector register loading instruction, the batch vectorized bit operation sequence, the parallel vector comparison logic, and the bitmap hit result extraction operation correspond to the attached figure labels 701, 702, 703, and 704, respectively.

[0326] Hierarchical relationship between scalar and vectorized modes: The branchless bitwise operation sequence described in this invention can be executed in scalar mode in a general-purpose processor ALU, forming the core implementation basis of the above-mentioned screening and determination path; the vectorized parallel screening executed using SIMD extended instruction sets (AVX-512, NEON, SVE, etc.) is an optional acceleration method and does not constitute a limitation on the technical features of the independent claims.

[0327] Hardware execution and memory alignment: Vectorized filtering logic is directly mapped to the physical gate operation sequence of the processor's Vector Execution Unit (VPU). To maximize throughput, the pre-stored coupling identifiers use a 64-byte physically aligned layout, allowing a single vector load instruction to load a complete cache line from the L1 cache into the vector register. The number of parallel filters is determined by the ratio of the vector register bit width to the coupling identifier bit width.

[0328] AVX-512 (512-bit) + 64-bit identifier: Determines 8 objects in a single instruction.

[0329] AVX-256 (256-bit) + 64-bit identifier: Determines 4 objects in a single instruction.

[0330] AVX-512 (512-bit) + 32-bit identifier: 16 objects can be determined in a single instruction.

[0331] Masking execution mechanism: In SIMD mode, the filtering logic adopts "mask-mask execution" instead of "conditional jump". The judgment result is directly mapped to the bit in the target mask register, so that the processor execution path remains definite and consistent.

[0332] The vectorized parallel filtering logic is as follows:

[0333] Step 1: Broadcasting Common Parameters – Scalar parameters such as query identifier, feature bitmask, and spatial domain isolation mask are broadcast to each vector channel via a broadcast instruction, serving as common operands for all parallel decisions. Specifically, this includes: broadcasting query_id to vector register v_query, broadcasting feature_mask to vector register v_feature_mask, and broadcasting isolation_mask to vector register v_isolation (where isolation_mask can be configured to all 1s in spatial priority mode to achieve logical bypass; in feature priority mode, it is used to clear the high-order feature domain differences before right shift to prevent shift contamination), and initializing the zero vector to v_zero.

[0334] Step 2: Process candidate coupling identifiers in batches according to hardware parallelism W. For each batch, perform the following sub-steps:

[0335] Step 2a (Batch Load): Load the W candidate coupled identifiers from aligned memory into the vector register v_ids.

[0336] Step 2b (Parallel determination of spatial correlation): Perform a vectorized XOR operation on v_ids and v_query to obtain v_xor; perform a vectorized bitwise AND operation on v_xor and v_isolation to isolate spatial domain differences to obtain v_isolated; perform a vectorized logical right shift (the shift amount is spatial_shift) on v_isolated and perform a vectorized equality comparison with v_zero to output the spatial matching mask spatial_mask.

[0337] Step 2c (Parallel determination of feature matching): Perform vectorized bitwise AND operation on v_ids and v_query and v_feature_mask respectively to extract feature segments, perform vectorized equal comparison on the two extraction results, and output the feature matching mask feature_match_mask.

[0338] Step 2d (mask-level parallel logic merging): Perform a logical AND operation on spatial_mask and feature_match_mask, and output the hit indicator bitmap hit_mask for this batch.

[0339] Step 2e (Accumulation and Truncation of Hit Count): Perform a bit-counting operation on hit_mask and accumulate it to hit_count; when hit_count reaches or exceeds the preset hit count threshold, terminate the traversal of subsequent batches and record the current underlying cursor.

[0340] Step 3: Tail-off unaligned data fallback – When there are fewer than W remaining candidate data items, the remaining data is processed using a mask loading mechanism: a tail mask tail_mask is generated corresponding to the remaining number of items, and a mask loading is performed to obtain the tail vector register; then, the same vectorized XOR, isolation, right shift, equal comparison, bitwise AND extraction, and logical AND merging operations as in steps 2b to 2d are performed to generate the tail hit indicator bitmap hit_mask_tail; finally, the tail hit count is accumulated to hit_count.

[0341] Step 4: Result Extraction - The hit indicator bitmap is converted into a hit index set through bitmap compression extraction instructions (such as trailing zero count, least significant bit clear, etc.).

[0342] The above steps demonstrate the core process of vectorized parallel filtering: common parameter broadcasting (step 1), batch loading and parallel dual judgment (step 2), tail masking processing (step 3), and hit bitmap output (step 4). Each vector operation corresponds to a vector extension instruction set for a specific hardware platform (such as AVX-512 under x86 architecture, SVE under ARM architecture, etc.), and its specific instruction name and parameter type depend on the compiler version and hardware architecture.

[0343] Taking the x86 AVX-512 architecture as an example, the broadcast operation in step 1 above corresponds to the `_mm512_set1_epi64` instruction, the batch load corresponds to the `_mm512_load_si512` instruction, the vectorized XOR corresponds to the `_mm512_xor_si512` instruction, the vectorized bitwise AND corresponds to the `_mm512_and_si512` instruction, the vectorized logical right shift corresponds to the `_mm512_srl_epi64` instruction, the vectorized equality comparison corresponds to the `_mm512_cmpeq_epi64_mask` instruction, and the bit-counting corresponds to the `POPCOUNT` operation. The instruction names above are merely examples; under different processor architectures, compiler versions, or vector extension instruction sets, they can be replaced with equivalent implementations that achieve the same technical effect, such as ARM NEON / SVE, RISC-V vector extensions, or GPU thread masking execution mechanisms.

[0344] Performance verification (test environment see Example 10): Under the test conditions of Example 10, the vectorized parallel filtering path shows a significant throughput improvement, a lower branch prediction failure rate, and better cache affinity compared to the traditional branched serial decision. Relevant quantitative comparison results are shown in the performance test table of Example 10.

[0345] Hit Bitmap Output and Post-processing Notes: The hit indicator bitmap is preferably output as a hit indicator bitmap or an index bitmask, rather than directly outputting the object identifier itself. For scenarios requiring the recovery of the target object array index, trailing zero counting, least significant bit clearing, or equivalent bitmap extraction instructions can be further utilized to perform fast parsing of the hit bitmap, maintaining the efficiency of the overall result extraction path.

[0346] Hardware alternative implementation description: GPU's Thread Masking mechanism, ARM NEON / SVE vector extension, hardware bit test instruction (vtest) to replace the "XOR + bitwise AND" combination, etc., can all be used as corresponding implementation forms of the vectorization acceleration concept of this invention.

[0347] In conjunction with the vectorized overflow handling of pagination truncation in Embodiment 6: In the pagination filtering task based on the hit count threshold described in Embodiment 6, if the number of hits in the result mask of a single vectorized batch judgment exceeds the remaining quota required for the current page, the execution unit uses a mask masking instruction or a bit segment truncation instruction to extract a target subset to achieve accurate alignment with the hit count threshold, and updates the underlying cursor accordingly.

[0348] Example 9: Multi-mode heterogeneous index routing

[0349] This embodiment corresponds to the multi-mode heterogeneous index routing scheme of the present invention.

[0350] To adapt to the needs of geographic data retrieval at different scales, this invention constructs a heterogeneous architecture that includes a spatially prioritized primary index and a feature-priority secondary index, the specific configuration of which is as follows:

[0351] (1) Spatial priority main index: The high segment of the coupled identifier is configured as the spatial location encoding field, and the low segment is configured as the business feature encoding field; geographically adjacent data objects form physical clusters in the underlying storage, supporting sequential scanning for specific geographical areas, which is suitable for nearby range retrieval scenarios.

[0352] (2) Feature-first auxiliary index: The high-order segment of the coupled identifier is configured as the business feature encoding field, and the low-order segment is configured as the spatial location encoding field; data objects with the same business features form physical clusters in the underlying storage, supporting sequential scanning of specific feature clusters in a wide range of retrieval scenarios.

[0353] Regarding the maintenance method of the feature-first auxiliary index, the present invention provides, but is not limited to, the following polymorphic implementation methods:

[0354] (1) Pre-construction of the entire dataset: During the system initialization phase, a complete auxiliary index is constructed based on the entire dataset and stored persistently;

[0355] (2) On-demand incremental construction: Based on the statistical results of query popularity, auxiliary index shards are dynamically constructed only for the feature categories of high-frequency access;

[0356] (3) Asynchronous delayed construction based on hot spot features: When the system detects that a specific business feature is frequently searched in a wide area, the corresponding auxiliary index shards are asynchronously constructed in the background and reside in memory or cache layer for reuse by subsequent requests for the same or similar features.

[0357] All of the above-mentioned maintenance methods can be used to implement the additional maintenance feature priority auxiliary index described in this invention.

[0358] The system employs the following strategy for dynamic route scheduling based on spatial scale parameters, feature filtering intensity, and preset route threshold rules:

[0359] The feature filtering strength (i.e., the ratio of the length of the business feature coding field bit segment covered by the feature filtering conditions to the total bit width of the business feature coding field, typically ranging from 0.1 to 1.0) serves as the primary decision factor for routing determination. In a preferred embodiment, the system first maps the spatial scale parameter to a normalized spatial breadth value in the [0,1] interval, then assigns corresponding weights to it and the feature filtering strength, and performs a linear weighted summation. When the weighted result is less than or equal to a preset routing threshold, routing is performed to the spatial priority primary index; otherwise, routing is performed to the feature priority secondary index. This rule is beneficial for automatically switching to a more suitable feature-priority mode when the retrieval range is large or the feature filtering requirement is strong. Before executing the routing determination, the computing device parses the feature filtering strength in the request in real time to preload the corresponding bitmask parameters in the execution path.

[0360] The aforementioned space-priority primary index and feature-priority secondary index share the same bitmask-based atomic decision engine. Based on the current indexing mode, the decision engine dynamically adjusts the coverage segments and offsets of the space bitmask and feature bitmask through a preset parameter mapping table. At the instruction execution level, this manifests as atomic overloading of operands for integer bitwise operations, eliminating the need for conditional jumps in the algorithm logic and achieving in-situ optimization for different search dimensions.

[0361] In feature-first mode, the decision engine ensures accuracy by implementing a bit isolation protection mechanism. When switching to feature-first auxiliary index mode, the system loads a specific spatial domain isolation mask to pre-clear the XOR differences generated by the high-order service feature coding segments before performing the shift operation. Specifically, when performing spatial decision-making in feature-first mode, the processor first performs a bitwise AND operation between the XOR result and the spatial domain isolation mask, retaining only the difference information of the low-order spatial domain, and then performs a right shift operation. This isolation mask is obtained by the system from a preset parameter mapping table according to the current index mode, and its bit width is aligned with the spatial position coding field, with all bits corresponding to the high-order feature fields set to zero.

[0362] To visually demonstrate the performance of multi-modal heterogeneous index routing in real-world application scenarios, the table below lists performance metrics for typical retrieval scenarios:

[0363] Note: The above example time metrics are exemplary results measured in the test environment of the embodiment. The "Nearby Restaurants" row corresponds to the core decision time, and the "Michelin Restaurants Nationwide" row corresponds to the end-to-end execution time including storage I / O. The core decision latency (excluding network and storage I / O) is on the order of microseconds in this test environment. The feature-first auxiliary index achieves physical clustering through high-bit feature encoding, so that data with similar features are arranged continuously on the storage medium, thereby keeping the scanning overhead of Michelin restaurants nationwide (approximately 300-500) at a low level.

[0364] For extreme degradation scenarios during the index routing process, the corresponding processing logic of the present invention is as follows:

[0365] Scenario A (Missing Secondary Index): If the feature-priority secondary index is not pre-built due to storage resource limitations, the routing module automatically downgrades and directs all requests to the space-priority primary index. In this case, the system directly reuses the aforementioned branchless bitwise operation judgment instruction stream to perform the scan, ensuring result consistency without modifying the underlying judgment logic.

[0366] Scenario B (Boundary Jitter Protection): When the spatial scale parameter of the retrieval request is within a preset edge range (e.g., ±5%) of the routing threshold, the routing module uses an execution cost predictor to evaluate the computational cost in order to select the optimal index path and avoid drastic performance fluctuations at the boundary caused by a single threshold. The execution cost predictor calculates the expected execution cycle of two indexing modes based on the feature filtering strength of the current query, the estimated candidate set size, and index statistics, and selects the superior one. The estimated candidate set size can be obtained by reading the high-order prefix statistical histogram, sampling statistical structure, or approximate cardinality estimation structure maintained by the underlying index.

[0367] The preferred value of the routing threshold described in this invention is determined based on the following parameter calibration process:

[0368] (1) Select a sample dataset of representative geographical regions (such as megacities, suburbs, and provinces);

[0369] (2) Under different retrieval scales, the I / O addressing overhead and instruction execution cycle of space priority mode and feature priority mode are statistically analyzed respectively;

[0370] (3) The intersection of the performance curves of the two modes was selected as the routing threshold. Experimental results showed that when the radius exceeded 5 kilometers, the convergence of the spatial prefix decreased, leading to a surge in invalid candidate sets. At this point, switching to the feature-first mode could achieve a better filtering ratio.

[0371] Example 10: Performance Testing

[0372] To verify the technical performance of the present invention, the test environment configuration set in this embodiment is as follows:

[0373] (1) Hardware environment: Intel Xeon Gold 5218 CPU (dual-socket 32-core), 256GB DDR4 memory, NVMe SSD;

[0374] (2) Software environment: CentOS 7.9, Redis 6.0.10 cluster mode, GCC 11.2 compiler (with -O3 optimization enabled);

[0375] (3) Test data: 100 million active geographic data objects, with spatial distribution conforming to the typical urban POI density characteristics;

[0376] (4) Supplementary explanation: The test environment is only used for performance comparison and verification. The judgment logic described in this invention has no specific dependence on the hardware platform.

[0377] To verify the performance of the present invention in a real-world business scenario, the 100 million geographic data objects used in the test specifically cover the following data types and characteristics:

[0378] (1) Data types: including food delivery merchants (approximately 40 million records), ride-hailing vehicle real-time locations (approximately 35 million records), local life service merchants (approximately 15 million records), and logistics delivery points (approximately 10 million records).

[0379] (2) Geographical distribution: Covering major cities across the country (first-tier, new first-tier, and second-tier cities), with data density positively correlated with urban population density;

[0380] (3) Business characteristic dimensions: type (16 categories), price tiers (8 tiers), rating levels (8 levels), business status (4 types), and tag bitmap (7 types of tags);

[0381] (4) Data dynamism: It includes both high-frequency location update objects and low-frequency attribute update objects, covering the data change patterns in typical LBS applications.

[0382] Based on the above testing environment and data, the verification results of the present invention under different testing scenarios are as follows:

[0383] In test scenario 1 (core algorithm performance), micro-benchmark tests were performed on the core screening method described in this invention and the branchless bitwise operation sequence (where the vectorized mode corresponds to the SIMD parallel screening scheme). The performance comparison results are shown in the table below:

[0384] Note: To avoid confusion between different statistical standards, this scenario uses a single composite query request with a fixed small candidate set size as the statistical unit to compare the underlying execution overhead of different decision paths. It is not directly equivalent to the end-to-end retrieval latency in a large-scale candidate set scanning scenario. In this scenario, the core composite decision bit operation logic of a single object is on the order of a low clock cycle under the test conditions of the example, while the "microsecond-level response latency" in the table corresponds to the typical value of the complete execution process, including candidate object addressing, core decision and result extraction.

[0385] Based on the above test data, the performance stability and hardware compatibility analysis of the present invention are as follows: Through extensive random sample testing, the single-decision latency of the present invention exhibits high stability, and the latency fluctuation range of its core execution path is small. Under the test conditions of Example 10, the single-core throughput of the vectorized mode shows a significant improvement compared to the scalar mode. All of the above data collectively demonstrate that after transforming the composite filtering logic into a pure data stream instruction sequence, the present invention exhibits good latency stability and hardware compatibility at the hardware execution level.

[0386] In test scenario 2 (wide-range retrieval bandwidth optimization), bandwidth optimization tests were performed on the in-situ bitwise operation filtering and truncation mechanism described in this invention. The retrieval conditions and performance comparison results are as follows:

[0387] The specific search conditions for this scenario are set as follows: search radius 50km, spatial bit prefix length L=33 bits (example value calculated according to the mapping formula described in Example 3), candidate dataset of 100,000 records, and hit count threshold preset to 20 records (Note: This scenario adopts the basic scalar mode to verify the independent optimization effect of the in-situ truncation mechanism on network and I / O overhead).

[0388] During the test, once the atomic execution unit detects that the cumulative number of hits has reached or exceeded the preset threshold (e.g., 20), the system immediately executes instruction flow logic truncation and records the current underlying cursor, stopping the judgment of the remaining candidate data and I / O reading.

[0389] In test scenario 3 (branch prediction failure comparison), a practical test comparison was performed on the hardware affinity of the branchless bitwise operation sequence described in this invention, and the results are shown in the table below:

[0390] It should be noted that this invention avoids conditional jump instructions in the core execution path that are sensitive to input data values ​​by using a branchless bitwise operation sequence. Multiple tests using Intel VTune Profiler and Linux perf tools, after comprehensive screening of a large amount of randomly distributed geographic data, showed that the branch mismatch statistics of its core execution path remained at a low level. This metric is used to illustrate the stability of the hardware execution path. The jump direction of the loop control branch used to traverse the dataset is determined by a preset number of iterations and is not within the scope of the pipeline flushing addressed in this invention.

[0391] Example 11: Multi-scale spatial aggregation and heatmap generation based on feature selection

[0392] This embodiment mainly corresponds to the feature-based multi-scale spatial aggregation scheme of the present invention, and also serves as a positive implementation of the feature-based multi-scale aggregation and in-situ multi-scale spatial aggregation schemes in a feature-based scenario.

[0393] The technical principle of this invention, which utilizes the binary structure characteristics of coupled identifiers to achieve integrated feature filtering and spatial aggregation, is as follows:

[0394] (1) Generate a feature bitmask based on business characteristic conditions;

[0395] (2) Perform feature matching determination using feature bitmasks;

[0396] (3) For data objects that meet the target business characteristics, extract the corresponding logical grid cells by dynamically adjusting their spatial bit prefix length in order to perform spatial aggregation statistics;

[0397] (4) Generate corresponding multi-scale spatial distribution views based on the aggregated statistical results of different precision levels.

[0398] To address the limitations of traditional Geographic Information Systems (GIS) in supporting multi-scale visualization, the background for technological improvements is described below: Traditional GIS systems typically employ a "pyramid index" architecture, requiring the pre-computation and storage of independent data copies for each scaling level. This often results in 5-10 times data redundancy, and data updates require simultaneous updates to all levels, leading to high ETL latency. This embodiment, together with Embodiment 12 below, demonstrates how the present invention eliminates the aforementioned redundancy through in-situ truncation.

[0399] To visually demonstrate the technical advantages of the spatial aggregation scheme described in this invention, the following table compares the performance characteristics of the embodiments of this invention with those of traditional pre-aggregation schemes:

[0400] In one specific implementation of a relational database, taking the query "heat map of high-end / mid-range commercial segments of hot pot restaurants" as an example, the aggregation execution logic is described as follows:

[0401] (1) Spatial cell identifier extraction: After performing a logical right shift of the coupled identifier (coupled_id) by 48 bits, perform a bitwise AND operation with the mask 0xFFFF to extract the spatial prefix as the spatial cell identifier spatial_cell;

[0402] (2) Business type filtering: The 5-bit business type mask 0x1F000 (corresponding to bits 16-12) is used to perform a bitwise AND operation on the coupling identifier, and then compared with the target business type code 0x2000 (the 5-bit code 00010 for hot pot class shifted left by 12 bits) to filter the data objects of the target business type;

[0403] (3) Business tier range filtering: Use the business tier mask 0x0C00 (binary 1100 0000 0000, corresponding to bit 11 representing high-end and bit 10 representing mid-end) to perform a bitwise AND operation on the coupled identifier, and filter the data objects of high-end or mid-end tiers by non-zero judgment (this mask can match high-end objects with bit 11 set and mid-end objects with bit 10 set at the same time).

[0404] (4) Group counting aggregation: For data objects that meet the above business type and commercial grade conditions, perform group counting according to the spatial cell identifier spatial_cell, and output the data density value in each spatial cell.

[0405] In the physical implementation of relational databases, the coupled_id is preferably mapped to an unsigned integer (such as UNSIGNED BIGINT) to avoid interference from sign bit extension during bit shift operations and bitmask calculations. For storage systems that do not support native unsigned 64-bit integers, aggregation bias caused by sign bit extension can be avoided through logical shift padding, explicit mask clearing, or function encapsulation.

[0406] In the execution layer of the database or storage engine, the above spatial prefix extraction and feature filtering process can be performed as a combination of bitwise shift operators, bitwise AND operators and counting aggregation operators, thereby avoiding geographic coordinate inverse solution, coordinate projection transformation or complex spatial relationship determination.

[0407] When spatial aggregation is performed using the feature-first mode, since the spatial location coding field is located in the low bit, the extraction logic of the target spatial prefix is ​​adapted as follows: preferably, the clean spatial bit segment is extracted first using the spatial field isolation mask, then the result is shifted right by (Ns - L) bits to align the target spatial prefix to the low bit, and irrelevant bits are cleared by combining the preset low bit mask, thereby obtaining the spatial unit identifier used for aggregation grouping.

[0408] To meet different spatial scale requirements, the present invention supports multi-scale precision mapping by adjusting the prefix length, and the typical correspondence is shown in the table below:

[0409] At the hardware execution level, this invention achieves significant optimization by simplifying geospatial aggregation determination to integer truncation and equality comparison operations in the processor. Spatial unit extraction corresponds to only one right shift instruction (SHR), and group statistics are transformed into pure integer equality determination. Compared to traditional aggregation schemes based on R-trees or spatial geometry operations (involving floating-point comparisons and polygon boundary calculations), this scheme demonstrates a significant reduction in execution cycle under the test conditions of the embodiment. When the map zoom level changes, only the displacement operands need to be adjusted to quickly switch the aggregation granularity.

[0410] To further verify the spatial aggregation efficiency of this solution, the measured comparison results of the present invention and the traditional solution under the test environment described in Example 10 are shown in the table below:

[0411] Note: The above results are test values ​​obtained under the test environment described in Example 10. Actual performance varies with data distribution, hardware configuration and deployment form.

[0412] The spatial aggregation scheme described in this embodiment also supports handling degradation scenarios for different business needs: when the feature matching determination is always logically true when configured with a full-coverage bypass value through a feature bitmask, this embodiment degenerates into a pure spatial aggregation mode. In this case, it is only necessary to extract the spatial prefix based on the spatial bit prefix length corresponding to the target precision level and perform group counting; when the spatial correlation determination is always logically true when configured with an all-zero spatial bitmask and bypassed with corresponding displacement parameters, the system degenerates into a pure feature filtering aggregation mode. In the above degradation scenarios, the core branchless bit operation instruction sequence maintains logical consistency and can be adapted without modifying the determination path.

[0413] Example 12: In-situ multi-scale spatial aggregation based on bitstream truncation (zero-copy and extraction-free transformation, feature matching) (Scenarios where the compatibility determination always holds true)

[0414] This embodiment is used to further illustrate the implementation of the "in-situ multi-scale spatial aggregation based on bitstream truncation" technology in this invention in a scenario where the feature matching determination is always true. In this case, the feature bitmask can be configured to be all zeros or bypass values, so that the feature matching determination is logically always true, and the system only performs bit truncation, spatial prefix extraction, and in-situ counting aggregation for the spatial location coding domain.

[0415] In this embodiment, "extraction-free conversion" means that spatial prefix extraction and aggregation statistics are performed directly on a fixed-width bitstream without restoring the coupled identifier to its original coordinates or re-performing projection or mesh coding. "Zero copy" preferably means that bit truncation and aggregation are performed directly in the storage layer or memory-mapped region to reduce the overhead of intermediate object reorganization and format conversion.

[0416] When using the space-first mode, the target spatial prefix can be directly extracted through bit truncation. When using the feature-first mode, a clean spatial bit segment can be extracted first using a spatial domain isolation mask, and then right-shifted by (Ns - L) bits to complete the prefix alignment. For boundary-sensitive scenarios, the adaptive neighborhood expansion mechanism described in Example 3 can be used to mitigate the statistical bias caused by boundary jumps. Compared with the traditional pyramid-style pre-aggregation scheme, this embodiment helps reduce the overhead of multi-copy storage and hierarchical ETL reconstruction, and makes multi-scale view switching more of an adjustment of displacement parameters and truncation length.

[0417] Example 13: Bitmap Pre-screening of Ultra-Large-Scale Data

[0418] This embodiment provides an optional bitmap pre-screening mechanism for entry-level coarse screening of spatial prefix requests that clearly fall into the spatial domain in ultra-large-scale data scenarios. The bitmap layer and the core branchless dual-decision method described in this invention are at different execution levels: the former is used to determine whether to trigger the underlying ordered index access, while the latter is used for fine-grained determination after the candidate set enters the fine screening. Therefore, the introduction of the bitmap layer does not change the branchless characteristic of the core determination path.

[0419] In a preferred implementation, the system constructs an existence bitmap based on the length L_bitmap of the coarse-grained spatial prefix. During the write phase, bit truncation is performed on the coupled identifier and the corresponding bitmap position is set. During the query phase, the query coverage is first mapped to one or more coarse prefixes and bit tests are performed. If all corresponding bitmap bits are 0, the request is directly intercepted at the entry layer or routing layer. If a hit is found, the corresponding target fragment or candidate interval is accessed and subsequent atomic fine screening is performed.

[0420] As a relatively complete enhanced implementation, the bitmap pre-screening may include the following steps: performing fixed-bit truncation on the spatial location encoding field to generate a coarse prefix; performing atomic bit setting or equivalent existence registration in the bitmap based on the coarse prefix; performing bit testing on the set of coarse prefixes to be covered during querying; triggering subsequent ordered index access and branchless dual judgment only for the fragments corresponding to the prefixes that hit the bitmap. The bitmap layer preferably adopts a continuous bit array, compressed bitmap, or hierarchical bitmap structure adapted to the processor word length to reduce the cost of ingress layer probing.

[0421] This mechanism is suitable for scenarios with many empty prefixes and high costs associated with route null probing, helping to reduce invalid I / O, invalid remote calls, and the load on fine-tuning entry points. In an example scenario, when the spatial distribution is highly discrete and the request coverage area is large, the bitmap layer can first filter out coarse prefixes that obviously do not contain data, and then hand over the remaining target intervals to the lower layer for fine-tuning, thereby reducing the proportion of invalid addressing. Ordinary bitmaps, compressed bitmaps, multi-level prefix bitmaps, fragmented local bitmaps, and their equivalent implementations can all be used as alternative solutions.

[0422] When the query coverage area is highly concentrated, the bitmap's interception benefit for null prefixes is low, or the deployment environment is not suitable for maintaining additional bitmap structures, the L_bitmap and logical bypass bitmap can be dynamically reduced, or the system can be directly rolled back to the fine screening mode based on ordered indexes to ensure functional integrity and deployment flexibility.

[0423] Example 14: Polar coordinate sector region fine screening based on coupled coding coarse screening

[0424] This embodiment provides a supplementary fine-tuning scheme for directional sector region retrieval scenarios. After completing the coarse screening using core coupling encoding, the system can convert the relative positions of candidate objects and the query center into distance and angle components, and then perform synchronous judgment based on the distance and angle masks to further narrow down the result set.

[0425] In a preferred implementation, the supplementary screening may include two stages: the first stage is to generate distance and angle representations based on the relative positions of candidate objects and query centers. The generation process can be completed by a lookup table, a fixed-round shift addition sequence, a dedicated hardware coordinate transformation unit, or an equivalent mechanism thereof; the second stage is to generate distance and angle masks based on the user's orientation angle, angular range, and distance threshold, and output the sector hit result through distance determination AND angle determination.

[0426] The distance encoding segment and angle encoding segment can be configured with asymmetric bit widths based on the measurement range, angular resolution, and processor word length. Preferably, the distance encoding segment assumes range constraints, and the angle encoding segment assumes directional domain constraints, thus allowing the sector region determination to still be completed within the framework of integer, bitwise operations, and table lookup. This supplementary fine screening still preferably uses a fixed-length execution sequence to reduce data-related control flow overhead and does not replace the core dual-determination mechanism described in this invention.

[0427] When the angle is configured as 360°, angle determination can be bypassed and degenerate into a circular range search; when only coarse direction determination is needed, the angle encoding segment can use a shorter bit width configuration; when the coarse screening result is empty, the fine screening unit is directly bypassed. Cartesian coordinate system bit descriptors, asymmetric bit width allocation, lookup table approximation, multi-sector union or circular intersection, etc., can all be used as equivalent implementations.

[0428] Supplementary Explanation of Implementation Methods

[0429] To facilitate understanding of the engineering implementation of the various embodiments of the present invention, the following supplementary explanations are provided: The coupled coding structure is preferably represented by a fixed-width integer field and an ordered storage structure with the field as the sorting key; the branchless bitwise operation sequence is preferably represented by a core execution path mainly based on bitwise shifts, XOR, bitwise AND, and comparisons, and avoids conditional jumps dependent on input data; the distributed sharding routing is preferably represented by queries with the same spatial prefix being stably routed to the same storage node; the multi-scale spatial aggregation is preferably represented by directly performing group statistics after extracting the spatial prefix through bitwise operations; and the bitmap pre-screening is preferably represented by intercepting the entry layer for requests with empty prefixes.

[0430] Index construction and filtering can also be implemented collaboratively across different servers, cloud service providers, or different geographical locations. As long as the relevant parties jointly utilize the spatial and feature coupling coding structure and branchless bit operation sequence described in this invention, it still falls under the consistent implementation form of the technical concept of this invention.

[0431] Description of alternative implementation methods

[0432] To facilitate understanding of the implementation boundaries of this invention, the following supplementary explanations are provided: The high and low bit arrangement of the spatial location coding field and the business feature coding field is not limited to the specific bit width allocation ratio in the aforementioned embodiments. Those skilled in the art can adapt and adjust it according to actual spatial accuracy requirements, business feature dimension capacity, and additional coding field configuration requirements. As long as the logical relative bit weight relationship between the spatial location coding field and the business feature coding field in target condition determination is maintained, as well as the corresponding continuous bit segment boundaries and mask decidability, it does not depart from the technical concept of this invention. Bit concatenation is not limited to shifting and bitwise OR; hardware bit segment insertion, arithmetic addition, lookup table mapping, and other equivalent bit operations can also be used.

[0433] Dynamic density adaptation, in-situ bit operation filtering and truncation, coupled identifier local update, adaptive neighborhood expansion, multi-scale spatial aggregation, and bitmap pre-filtering can all be implemented using equivalent methods to the technical solutions described in this invention. Aggregation statistics methods may include counting, summation, averaging, extreme values, and deduplication counting.

[0434] The method described in this invention can be deployed on cloud servers, edge computing nodes, terminal devices, embedded systems, vehicle-mounted computing units, or distributed clusters; its underlying storage carrier may include in-memory databases, relational databases, NoSQL storage systems, search engines, distributed storage systems, or intelligent storage devices with built-in computing units; bitwise operations and vectorization acceleration logic can be adapted to hardware platforms such as x86, ARM, RISC-V, and GPU, and can be implemented in the form of software programs, firmware code, FPGA configuration files, ASIC gate-level netlists, or chip IP cores.

[0435] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the protection scope of the claims and specification of the present invention.

Claims

1. A method for constructing a geographic data index, characterized in that, Includes the following steps: Step S1: Construct a spatial and feature coupled coding structure including a spatial location coding domain and a business feature coding domain. The position weight of the spatial location coding domain is higher than that of the business feature coding domain. The spatial location coding domain is used to carry the spatial location code generated based on a spatial filling curve algorithm with geographic topology order preservation. The spatial and feature coupled coding structure limits the bit segment division and position weight configuration of the coupled identifier. Step S2: Map the coordinates and business features of the data object to spatial codes and feature codes, and combine them into a coupling identifier by bit concatenation; the coupling identifier is a fixed-width binary integer that conforms to the spatial and feature coupling coding structure and is adapted to the bit width of the processor register, and its sorting order in the numerical space is jointly determined by the bit weight configuration of the spatial position coding field and the business feature coding field; Step S3: Using the coupling identifier as the index sorting key, construct an ordered index structure for the data object, maintain the coupling identifier in the storage unit, and output the construction result of the ordered index structure.

2. A method for constructing a geographic data index, characterized in that, Includes the following steps: Step S1: Construct a feature-priority coupled coding structure including a business feature coding domain and a spatial location coding domain. The position weight of the business feature coding domain is higher than that of the spatial location coding domain. The spatial location coding domain is used to carry the spatial location code generated based on a spatial filling curve algorithm with geographic topology order preservation. The feature-priority coupling coding structure defines the bit segment division and bit weight configuration of the coupling identifier; Step S2: Map the business features and coordinates of the data object into feature codes and spatial codes, and combine them into a coupling identifier by bit concatenation; the coupling identifier is a fixed-width binary integer that conforms to the feature-first coupling coding structure and is adapted to the bit width of the processor register, and its sorting order in the numerical space is jointly determined by the bit weight configuration of the business feature coding field and the spatial location coding field; Step S3: Using the coupling identifier as the index sorting key, construct an ordered index structure for the data object, maintain the coupling identifier in the storage unit, and output the construction result of the ordered index structure.

3. The method according to claim 1 or 2, characterized in that, The coupled coding structure has the following configuration that supports the execution of branchless bitwise operation sequences: A binary integer with a fixed bit width of N is adapted to the width of the processor's registers and is loaded and executed in the processor's data channel, where N is a positive integer; The bit width boundaries of the spatial location coding field and the business feature coding field are asymmetrically divided according to the geospatial accuracy requirements and the business feature dimension capacity, and remain fixed within the same ordered index structure after the division. In the decision logic, any of the encoding fields can be bypassed by configuring the corresponding bitmask.

4. The method according to claim 1 or 2, characterized in that, The business feature coding domain includes multiple subdomains with different bit weights; the multiple subdomains respectively carry different dimensions or different levels of business features, wherein the multiple subdomains are distributed in bit segments with different bit weights in the business feature coding domain.

5. The method according to claim 4, characterized in that, The service feature encoding domain includes a service type subdomain and a polymorphic service payload subdomain, wherein the bit division boundary of the polymorphic service payload subdomain is dynamically determined by the value of the service type subdomain.

6. The method according to claim 1 or 2, characterized in that, The spatial and feature coupled coding structure and the coupled identifier, in addition to the spatial location coding field and the business feature coding field, also include one or more additional coding fields; The one or more additional coding fields are set between the spatial location coding field and the business feature coding field, on the high outer side of the overall arrangement of the spatial location coding field and the business feature coding field, on the low outer side of the overall arrangement of the spatial location coding field and the business feature coding field, or a combination of the above positions. The one or more additional coding fields are used to carry version identifiers, verification information, routing control information, status identifiers, anti-collision sequence bits, or reserved extension bits; The configuration of the one or more additional coding fields does not change the logical relative positional relationship between the spatial location coding field and the business feature coding field in the target condition determination.

7. The method according to claim 1 or 2, characterized in that, It also includes a dynamic maintenance mechanism for coupled identifiers based on bit-field separation: When the data object undergoes spatial displacement or business characteristic change, the original coupled identifier is updated by performing local field bit operations using the bitmask corresponding to the changed dimension. Bitwise operations are used to embed the modified new coding segment into the corresponding bit segment range of the original coupled identifier, and a masking and retention operation is performed on the bit segments of the unchanged dimensions to generate the updated coupled identifier and synchronize it to the ordered index structure.

8. The method according to claim 1 or 2, characterized in that, It also includes a fragmented routing mechanism: The routing fragmentation key is determined based on the bit segment attribute of the spatial location coding field in the coupling identifier. The routing fragmentation key is a fixed-width integer extracted from the spatial location coding field and used to map to the storage unit identifier. The data object is stored in the corresponding storage unit of the storage system using the routing sharding key, and the spatially related data objects are mapped to the same physical storage address range or logical sharding identifier according to the routing sharding key.

9. The method according to claim 8, characterized in that, It also includes a mechanism for adaptive adjustment of sharding parameters: Obtain physical characteristic parameters that characterize the state of each storage unit, including storage bit occupancy rate, addressing concurrency frequency, or data channel bandwidth utilization rate; When the monitored value exceeds the preset high load threshold, the sharding level parameters are dynamically adjusted, and a sharding splitting operation is performed to split the data in a single overloaded storage unit into multiple sub-shards and redirect them to available storage units. When the monitored value is continuously lower than the preset low load threshold, a sharding and merging operation is performed.

10. The method according to claim 9, characterized in that, The fragment splitting or merging operation only involves adjusting the routing mapping relationship between the routing fragment key and the storage unit; the coupling identifier associated with the data object itself remains unchanged in encoding. The cross-fragment flow of the underlying data is manifested as the sequential movement of data blocks based on continuous spatial prefixes in the arrangement mode where the spatial location encoding field has a higher weight than the business feature encoding field; and as the batch migration of one or more data intervals corresponding to the target spatial prefix in the arrangement mode where the business feature encoding field has a higher weight than the spatial location encoding field.

11. A method for filtering geographic data, characterized in that, Includes the following steps: Step S4: Obtain the query identifier; The query identifier is a fixed-width binary integer, which includes a spatial location encoding field and a business feature encoding field. The bit weight of the spatial location encoding field is higher than that of the business feature encoding field. The query identifier is formed by bit concatenation of the spatial code generated by the spatial location in the filtering request based on the spatial filling curve algorithm with geographic topology order preservation and the feature code mapped by the target feature conditions. Step S5: Determine the spatial bit prefix length based on the spatial scale parameters and generate the spatial bit mask; determine the feature bit mask based on the target feature conditions. Step S6: Perform a branchless bitwise operation sequence on the pre-stored coupling identifier and the query identifier. Based on the bitwise operation results, determine the spatial correlation through a spatial bitmask and the feature matching through a feature bitmask. The coupling identifier is a fixed-width binary integer, which includes a spatial location encoding field and a business feature encoding field corresponding to the query identifier. The branchless bitwise operation sequence is executed in the form of a continuously executed instruction stream. The dual-determination execution path for each candidate data object does not contain conditional jump instructions that depend on the determination result of the input data, and the logical operation result of the bitwise operation sequence is output as the hit status.

12. The method according to claim 11, characterized in that, In step S4, the structure of the query identifier is consistent with the structure of the pre-stored coupling identifier; in step S6, the pre-stored coupling identifier has the same structural features as the coupling identifier in the ordered index structure. Furthermore, the query identifier and the coupling identifier have the same encoding structure bit weight allocation rules.

13. A method for filtering geographic data, characterized in that, Includes the following steps: Step S4: Obtain the query identifier; the query identifier is a fixed-width binary integer, which includes a business feature encoding field and a spatial location encoding field. The bit weight of the business feature encoding field is higher than that of the spatial location encoding field. The query identifier is formed by bit concatenation of the feature code mapped by the target feature conditions and the spatial code generated by the spatial location in the filtering request based on the spatial filling curve algorithm with geographic topology order preservation. Step S5: Determine the target feature bit prefix length and generate the feature bit mask based on the dimension or level precision of the target feature conditions; and determine the spatial bit prefix length and generate the spatial bit mask based on the spatial scale parameter; Step S6: Perform a branchless bitwise operation sequence on the pre-stored coupling identifier and the query identifier. Based on the bitwise operation results, determine the feature matching through the feature bit mask, and at the same time determine the spatial correlation using the spatial bit mask. The coupling identifier is a fixed-width binary integer, which includes a business feature encoding field and a spatial location encoding field corresponding to the query identifier. The branchless bitwise operation sequence is executed in the form of a continuously executed instruction stream. The dual-decision execution path for each candidate data object does not contain conditional jump instructions that depend on the determination result of the input data, and the logical operation result of the bitwise operation sequence is output as the hit status.

14. The method according to claim 13, characterized in that, In step S4, the structure of the query identifier is consistent with the structure of the pre-stored coupling identifier; in step S6, the pre-stored coupling identifier has the same structural features as the coupling identifier in the ordered index structure. Furthermore, the query identifier and the coupling identifier have the same encoding structure bit weight allocation rules.

15. The method according to claim 11 or 13, characterized in that, Step S6 includes: Perform an XOR operation on the coupling identifier and the query identifier to calculate the bit difference sequence; When performing the determination of the coding field located on the high-order side, the bit difference sequence is bit offset aligned according to the bit prefix length corresponding to the coding field on the high-order side, and the high-order difference bit segment is determined by combining the bit mask corresponding to the coding field on the high-order side. When performing the determination of the low-side coding field, the target bit segment is extracted by performing a bitwise AND operation on the coupling identifier and the query identifier using the bit mask corresponding to the low-side coding field, and the target bit segment is determined by comparing whether the extracted target bit segments are equal. The high-order encoding field determination and the low-order encoding field determination are executed synchronously in the same branchless bit operation sequence.

16. The method according to claim 11 or 13, characterized in that, The steps for generating the feature bitmask include: Based on the service type in the filtering request, the corresponding feature bit mask is obtained from the preset mask lookup table, and the bit coverage of the feature bit mask matches the bit division boundary of the polymorphic service payload subdomain corresponding to the service type. For multiple discrete feature conditions spanning different feature dimensions or levels, an initial feature bit mask is generated for each discrete feature condition corresponding to a subdomain. A single composite feature bit mask is synthesized by bitwise OR operation. The bit coverage of the composite feature bit mask is the union of the multiple discrete feature conditions corresponding to the subdomains. Among them, the bit coverage of the initial feature bit mask corresponding to the coarse-grained feature condition only covers the high-bit segment subdomain of the business feature coding domain, while the bit coverage of the composite feature bit mask corresponding to the fine-grained or composite feature condition covers the combination of discrete subdomains across levels. The business feature code of the query identifier is formed by combining and concatenating the subdomain code values ​​of the multiple discrete feature condition mappings; When performing feature matching determination, the single composite feature bitmask is used to perform bitwise AND operation on the coupled identifier and the query identifier to extract feature bit segments, and a single equal comparison instruction is used to determine whether the multiple discrete feature conditions are simultaneously satisfied.

17. The method according to claim 11 or 13, characterized in that, The specific steps in step S5 for determining the spatial bit prefix length based on the spatial scale parameter include: Perform adaptive mapping operation: Based on the ratio of the target spatial scale parameter to the preset benchmark grid scale corresponding to the target geographic accuracy requirement, calculate the corresponding spatial bit prefix length; Based on the total bit width of the spatial location coding field, the length of the spatial bit prefix, and the bit segment arrangement of the spatial location coding field in the coupling identifier, the shift amount of the shift operation when the processor performs spatial correlation determination is determined. The effective number of bits of the spatial bit prefix length is configured to decrease as the target spatial scale parameter increases; The spatial bit prefix length is used to determine the shift operands when the processor performs spatial correlation determination, and is used to generate a spatial bit mask corresponding to the spatial correlation determination; The range of the spatial bit prefix length is dynamically constrained to a preset minimum value within the interval from the total bit width of the spatial location encoding field minus the reserved suffix bits, wherein the subtracted reserved suffix bits constitute the boundary feature bit segment representing the relative coordinates inside the current grid.

18. The method according to claim 11 or 13, characterized in that, It also includes an adaptive neighborhood expansion filtering mechanism based on bit feature prediction: Extract the reserved suffix segment located on the low side of the spatial bit prefix length in the spatial position encoding field of the query identifier; If the value of the reserved suffix field satisfies the preset boundary critical threshold condition that represents the spatial location corresponding to the request as being at the physical boundary position in the current logical grid, then it is determined that the spatial location corresponding to the request is in the physical boundary region of the current logical grid, and the neighborhood expansion operation sequence is executed. The boundary critical threshold condition includes the reserved suffix bit sequence presenting a logical extreme state of all 0s or all 1s, or its value falling into a preset edge transition range defined by the bit width; In the neighborhood expansion process, based on the bit feature parsing request of the reserved suffix bit segment, the corresponding spatial position of the request is located in the corresponding quadrant position within the current logical grid. Spatial quadrant pruning is then performed, and spatial position prefixes of specific adjacent grids that border the corresponding quadrant position are directly generated in the bit space. These prefixes are then combined with the bit segment in the query identifier that corresponds to the business feature encoding field, and used as a new query identifier to perform cascaded batch branchless filtering.

19. The method according to claim 11 or 13, characterized in that, It also includes a dynamic density adaptive mechanism for compute load balancing: Using the logical grid determined by the current spatial bit prefix length as the statistical unit, the scale of data objects falling into the logical grid is periodically monitored; When the size of the data object is detected to exceed a preset high-density computing threshold that matches the processor cache capacity, the effective number of bits of the spatial bit prefix length is increased, and the coverage of a single logical grid is reduced. When the data object size is continuously monitored to meet the preset low-density idle threshold, the effective number of bits of the spatial bit prefix length is reduced to expand the coverage of a single logical grid.

20. The method according to claim 11 or 13, characterized in that, It also includes in-situ bitwise operation filtering and truncation mechanisms based on computational pushdown: The bitmask operation logic of the dual determination is pushed down to the data physical storage node of the ordered index structure, and the filtering instruction is executed on the data physical storage node by the original bit operation filtering execution unit. The in-situ bitwise operation filtering execution unit performs incremental scanning and the branchless bitwise operation sequence on the candidate dataset in numerical order; During the in-situ scanning determination process, when the cumulative number of hits that simultaneously satisfy spatial correlation and feature matching reaches a preset hit number threshold, the execution of the traversal scanning instruction stream is terminated, the current bottom-level cursor is recorded, and the hit result set and the bottom-level cursor are output.

21. The method according to claim 11 or 13, characterized in that, The branchless bitwise operation sequence consists of native bitwise operation instructions from the processor and a non-jump conditional execution mechanism. The non-jump conditional execution mechanism includes conditional transfer instructions, conditional selection instructions, conditional set instructions, mask execution mechanisms, or equivalent mechanisms. The bitwise operation instructions include XOR, bitwise AND, and bit shift instructions. The dual-decision execution path for each candidate data object in the branchless bitwise operation sequence is arranged as a linear instruction flow under the compiler's mapping and does not contain conditional jump instructions that change the control flow based on the determination result of the input data.

22. The method according to claim 11 or 13, characterized in that, The branchless bitwise operation sequence further utilizes the processor's Single Instruction Multiple Data (SIMD) extended instruction set to perform one-to-many batch parallel dual decision-making: The query identifier, the spatial bitmask, and the feature bitmask are pre-defined as common constant scalars and filled into the common parameter channel of the vectorized memory model via broadcast instructions. Multiple candidate coupled identifiers of a predetermined batch size are merged and loaded into the candidate data channel of the vectorized memory model; In a single vectorized batch decision sequence, the data in the common parameter channel and the candidate data channel are processed by channel-isolated batch vector XOR and vector bitwise AND operation instructions, and the final hit status vector across all data channels is generated by parallel equal comparison instructions. The hit state vector is converted into a hit indicator bitmap or index bitmask by a result compression extraction instruction.

23. The method according to claim 11 or 13, characterized in that, It also includes a multi-mode heterogeneous index routing mechanism: A space-priority index using the coupled coding structure described in claim 1 is pre-constructed as the main index, and a feature-priority auxiliary index is additionally maintained; The feature-first auxiliary index adopts the feature-first coupled coding structure described in claim 2, and uses the coupled identifier as the index sorting key; After receiving a filtering request, the spatial scale parameter and feature filtering intensity in the request are parsed. Based on the logical judgment result of the spatial scale parameter, the feature filtering intensity and the preset routing threshold rule, the filtering request is directed to the range retrieval mode based on spatial priority index or the feature clustering scanning mode based on feature priority auxiliary index. Both the feature-priority auxiliary index and the primary index support the reuse of the branchless bitwise operation sequence described in step S6; When performing data filtering, the bitmask coverage segments are adjusted to adapt to the bit weight arrangement of the coding field corresponding to the switched index mode, and the mask judgment of the corresponding high-bit coding field and the bit segment comparison of the low-bit coding field are performed synchronously in the same branchless bit operation sequence.

24. The method according to claim 11 or 13, characterized in that, It also includes a multi-scale spatial aggregation step based on feature selection: Feature matching is performed using the feature bitmask corresponding to the target business feature conditions, and the target spatial prefix is ​​extracted by combining the spatial bit prefix length corresponding to the target precision level. Data objects with the same target space prefix are identified as the same logical grid cell in the underlying index, and counting aggregation is performed on each logical grid cell.

25. The method according to claim 11 or 13, characterized in that, It also includes in-situ multi-scale spatial aggregation steps based on bitstream truncation and feature selection: At the truncation position dynamically determined by the target view accuracy level, a bit truncation operation is performed on the coupling identifier using a bit mask, and the target space prefix is ​​extracted; Data objects with the same spatial prefix are identified as the same logical grid cell in the underlying index, and in-situ counting aggregation is performed on the logical grid cell as a unit. The aggregation and statistical process is configured to be performed in-situ while the underlying storage data physical structure remains unchanged. The in-situ counting aggregation combined with feature filtering is performed as follows: using the feature bitmask corresponding to the target business feature conditions, feature matching determination is performed on the coupled identifier; and only for the coupled identifier that meets the feature matching conditions, the bit truncation operation, target space prefix extraction and aggregation statistics are performed.

26. A geographic data filtering system, characterized in that, It includes a coupling coding module, a communication module, a storage module, and a bitmask filtering engine: The coupled coding module includes a spatial coding subunit, a feature coding subunit, and a bit concatenation unit, configured to construct a spatial and feature coupled coding structure. The high and low bit arrangement of its spatial position coding field and business feature coding field is configured to correspond to the retrieval priority. The spatial coordinates of the data object are mapped to spatial position codes, and the business feature information is mapped to business feature codes. The two codes are then combined into a coupled identifier of a fixed-width binary integer through bit concatenation operations. The order of the coupled identifier is determined by the bit weight configuration of the spatial position codes and the business feature codes. The communication module is configured to receive geographic data filtering requests and output the filtering results; The storage module is configured to maintain an ordered index structure corresponding to the data object using the coupling identifier as the index sorting key. The bitmask filtering engine is configured to determine the spatial bitmask and feature bitmask based on the geographic data filtering request, and obtain the query identifier corresponding to the filtering request. Execute a branchless bitwise operation sequence, wherein the bitwise operation sequence contains spatial correlation determination and business feature matching determination in the same instruction stream, and outputs the target hit result; the bitwise operation sequence does not contain conditional jump logic that depends on the input data.

27. The system according to claim 26, characterized in that, The system also includes at least one of the following extended modules: The multi-mode heterogeneous routing module, located in the request entry gateway layer, is configured to parse spatial scale parameters, feature filtering strength, and routing thresholds, and perform dynamic instruction distribution between the space-priority main index storage area where the position weight of the spatial location coding domain is higher than that of the business feature coding domain, and the feature-priority auxiliary index storage area where the position weight of the business feature coding domain is higher than that of the spatial location coding domain. The precision mapping unit, located within the bitmask filtering engine, is configured to perform adaptive mapping between spatial scale parameters and spatial bit prefix length, and to convert the mapping result into shift parameters for bitwise operations. The density adaptive unit, belonging to the bitmask filtering engine, is configured to monitor the object distribution density within the logical grid and dynamically rewrite the bit prefix length output by the precision mapping unit. The neighborhood expansion unit, located within the home bit mask filtering engine, is configured to perform adaptive neighborhood expansion based on bit criticality determination, directly generating candidate prefix sequences of adjacent grids within the bit space and performing cascaded batch retrieval. The in-situ bitwise operation filtering and truncation unit belongs to the storage module and is configured to encapsulate the bitmask operation logic into an in-situ bitwise operation filtering execution unit residing in the storage node kernel. When the hit count threshold is met, the logic truncation of the traversal scan is executed. The distributed sharding routing unit, belonging to the storage module, is configured to calculate the storage shard identifier based on the spatial bit prefix corresponding to the spatial location encoding field in the coupling identifier, and write the data object to the corresponding sharding storage unit or route the retrieval request to the corresponding sharding storage unit based on the storage shard identifier.

28. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it performs the method of any one of claims 1-25.

29. A geographic data filtering device, characterized in that, Includes processor, memory, and communication interface: The communication interface is configured to receive geographic data filtering requests and output filtering results. The memory is configured to store coupled identifiers corresponding to computer programs and data objects; the coupled identifier is a fixed-width binary integer, and its encoding structure supports flexible configuration of the high and low bits of the spatial location encoding field and the business feature encoding field. The processor is configured to execute the computer program to perform the following steps: parsing the geographic data filtering request, generating a query identifier corresponding to the coupled identifier structure, and determining a spatial bitmask and a feature bitmask based on the filtering request; Execute the branchless bitwise operation sequence corresponding to the coupling identifier and query identifier, perform synchronous dual determination on spatial correlation and business feature matching, and output the hit status.

30. A processor chip for geographic data filtering, characterized in that, The chip integrates a bitmask filtering engine, an input register interface, an output register interface, and a clock control unit. The input register interface is configured to receive and temporarily store externally input coupling identifiers, query identifiers, spatial bitmasks, feature bitmasks, and shift control signals. Specifically, one of the spatial bitmasks and the feature bitmasks is configured as a bitmask corresponding to the high-order coding domain, and the other is configured as a bitmask corresponding to the low-order coding domain. In a space-priority configuration, the high-order coding domain corresponds to the spatial location coding domain, and the low-order coding domain corresponds to the service feature coding domain. In a feature-priority configuration, the high-order coding domain corresponds to the service feature coding domain, and the low-order coding domain corresponds to the spatial location coding domain. The bitmask filtering engine includes an XOR logic gate array, a barrel shifter, a general-purpose register group, a bitwise AND logic gate array, a high-order encoding field equivalent comparison logic circuit, and a low-order encoding field equivalent comparison logic circuit at the hardware circuit layer. The general-purpose register group is configured to temporarily store the coupling identifier, query identifier, space bitmask, feature bitmask, and displacement control signal; The input of the XOR logic gate array is connected to the output of the coupled identifier and the query identifier in the general-purpose register group, and the output is connected to the input of the barrel shifter. The displacement control terminal of the barrel displacement device is connected to the displacement control signal, and the output terminal and the output terminal of the bit mask corresponding to the high-order encoding field in the general-purpose register group are connected together to the input terminal of the high-order encoding field equivalent comparison logic circuit. The input terminals of the bitwise AND logic gate array are respectively connected to the output terminals of the coupled identifier, query identifier and the bit mask corresponding to the low-order encoding field in the general-purpose register group, and the output terminals are connected to the input terminals of the low-order encoding field equal comparison logic circuit. The outputs of the high-order encoding field equivalent comparison logic circuit and the low-order encoding field equivalent comparison logic circuit are connected to the input of the AND gate, and the output of the AND gate is connected to the output register interface. The clock control unit is configured to provide a synchronous clock signal to the bitmask filtering engine. The logic circuit of the bitmask filtering engine completes the calculation and outputs a hit status signal under a given clock configuration and input interface conditions. The hardware execution path does not include conditional jump control logic circuits that depend on input data.

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