Display device and global dimming control method thereof

Abstract

Disclosed are a display device and a global dimming control method thereof. The display device includes: a display panel including a first display area having first pixels and a second display area having second pixels, each pixel including a light-emitting element; a data driver circuit configured to output a data voltage of an image to the first and second pixels; a gate driver configured to output a scan signal to the first and second pixels; and a power supply configured to generate a low-level power supply voltage, which is applied to the light-emitting element included in each pixel, the low-level power supply voltage switching between a first level enabling the light-emitting element to emit light and a second level disabling the light-emitting element from emitting light. A frame period of the display device includes an addressing period, and during the addressing period, the low-level power supply voltage switches from the second level to the first level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0174334, filed on December 8, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device and a global dimming control method thereof. Background Art

[0004] According to the material of the light-emitting layer, electroluminescent display devices are divided into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include organic light-emitting diodes (hereinafter referred to as "OLEDs") that emit light by themselves (e.g., self-luminous) and have the advantages of fast response speed, high luminous efficiency, high brightness and wide viewing angle. In an organic light-emitting display device, an OLED is formed in each pixel. The organic light-emitting display device not only has a faster response speed and excellent luminous efficiency, brightness and viewing angle, but also has excellent contrast and color reproducibility because it can represent black grayscale in full black.

[0005] The pixel circuit of an organic light-emitting display device includes a light-emitting element, a driving element for driving the light-emitting element, and one or more switching elements. The pixel circuit may further include an EM switching element that is turned on / off according to a light-emitting control pulse. The EM switching element can adjust the lighting duration and off duration of the OLED by switching the current path between the driving element and the OLED. In an organic light-emitting display device, a global dimming control method can control the brightness of the entire screen by controlling the EM switching elements of all pixels by PWM (pulse width modulation) during a vertical blank period when pixel data of an input image is not input. However, since the global dimming control method can control the duty cycle of the EM switching element within a very short vertical blank period, the range in which the duty cycle can be adjusted is limited, and therefore the brightness of the screen cannot change linearly over a wide range.

[0006] Because the EM switching element is subjected to a large amount of stress due to a longer driving period than other switching elements in the pixel circuit, the EM switching element degrades faster than other switching elements. When the EM switching element is implemented by an oxide transistor, the reliability of the EM switching element is reduced. Summary of the Invention

[0007] The present disclosure is intended to address the above-mentioned needs and / or shortcomings.

[0008] The present disclosure provides a display device and a global dimming control method thereof that are capable of expanding a duty cycle adjustment range for performing global dimming and adjusting screen brightness without an EM switching element.

[0009] In one embodiment, a display device includes: a display panel, the display panel including a first display area and a second display area, the first display area including a plurality of first pixels, the second display area including a plurality of second pixels, each of the plurality of first pixels and the plurality of second pixels including a corresponding light-emitting element; a data driver circuit, the data driver circuit being configured to output a plurality of data voltages of an image to the plurality of first pixels and the plurality of second pixels; a gate driver, the gate driver being configured to output a plurality of scan signals to the plurality of first pixels and the plurality of second pixels; and a power supply, the power supply being configured to generate a low-level power supply voltage, the low-level power supply voltage being applied to the corresponding light-emitting element included in each of the plurality of first pixels and the plurality of second pixels, the low-level power supply voltage being switched between a first level enabling the light-emitting element in each pixel to emit light and a second level preventing the light-emitting element in each pixel from emitting light, wherein The frame period of the display device includes an address period and a blank period, during which the multiple data voltages and the multiple scan signals of the image are output to the multiple first pixels and the multiple second pixels, and during the blank period, the multiple data voltages and the multiple scan signals are not output to the multiple first pixels and the multiple second pixels, wherein, during a first part of the address period, the low-level power supply voltage is at the second level, so that none of the multiple first pixels in the first display area emits light and none of the multiple second pixels in the second display area emits light, and during a second part of the address period after the first part, the low-level power supply voltage is at the first level, so that the multiple first pixels in the first display area emit light to display the first part of the image, and at least a part of the multiple second pixels in the second display area emit light to display at least a part of the second part of the image.

[0010] In one embodiment, a display device includes: a display panel, the display panel including a first display area and a second display area, the first display area including a plurality of first pixels, the second display area including a plurality of second pixels, each of the plurality of first pixels and the plurality of second pixels including a corresponding light-emitting element; a data driver circuit, the data driver circuit being configured to output a plurality of data voltages of an image to the plurality of first pixels and the plurality of second pixels; a gate driver, the gate driver being configured to output a plurality of scan signals to the plurality of first pixels and the plurality of second pixels; and a power supply, the power supply being configured to generate a low-level power supply voltage, the low-level power supply voltage is applied to the corresponding light-emitting element included in each pixel of the plurality of first pixels and the plurality of second pixels, and the low-level power supply voltage switches between a first level that enables the light-emitting element in each pixel to emit light and a second level that is greater than the first level and does not enable the light-emitting element in each pixel to emit light, wherein the frame period of the display device includes an addressing period, during which the plurality of data voltages and the plurality of scan signals of the image are output to the plurality of first pixels and the plurality of second pixels, and during the addressing period, the low-level power supply voltage switches from the second level to the first level, so that the light-emitting element in each pixel can emit light to display the image.

[0011] In one embodiment, a display device includes: a display panel, the display panel including a first display area and a second display area, the first display area including a plurality of first pixels, the second display area including a plurality of second pixels, each of the plurality of first pixels and the plurality of second pixels including a corresponding light-emitting element; a data driver circuit, the data driver circuit being configured to output a plurality of data voltages of an image to the plurality of first pixels and the plurality of second pixels; a gate driver, the gate driver being configured to output a plurality of scan signals to the plurality of first pixels and the plurality of second pixels; and a power supply, the power supply being configured to generate a low-level power supply voltage, the low-level power supply voltage being applied to the corresponding light-emitting element included in each of the plurality of first pixels and the plurality of second pixels. light elements, the low-level power supply voltage switches between a first level that enables the light-emitting elements in each pixel to emit light and a second level that is greater than the first level and does not enable the light-emitting elements in each pixel to emit light, wherein the frame period of the display device includes an addressing period, during which the multiple data voltages of the image and the multiple scan signals are output to the multiple first pixels and the multiple second pixels, and during the addressing period, the low-level power supply voltage switches from the second level to the first level, wherein the display device is configured to operate in one of a plurality of modes, in which each mode has a corresponding duty ratio of the first level of the low-level power supply voltage and the second level of the low-level power supply voltage from a plurality of different duty ratios.

[0012] Problems to be solved by the present disclosure are not limited to the above-mentioned problems, and those skilled in the art will clearly understand other unmentioned problems through the following description.

[0013] According to the present disclosure, global dimming can be initiated on the display panel screen during the addressing period of a frame period. Therefore, the global dimming control method of the present disclosure can ensure a sufficiently long global dimming period within each frame period, thereby linearly controlling the global dimming duty cycle over a wide range.

[0014] According to the present disclosure, by setting an address skip period within an address period and switching a low potential power supply voltage within the address skip period, it is possible to prevent a gate-source voltage of a driving element from being changed due to switching of the low potential power supply voltage.

[0015] According to the present disclosure, by adjusting the duty cycle during global dimming, the brightness of the pixel can be adjusted while the data voltage is fixed to a predetermined voltage or above. The method of changing the duty cycle of the pixel on and off can provide a color spot improvement effect at low brightness.

[0016] According to the present disclosure, the global dimming duty cycle can be adaptively changed according to the use environment or driving mode of the display device, thereby providing image quality optimized for the use environment and reducing power consumption. In addition, according to the present disclosure, based on the results of analyzing the input image, power consumption can be further reduced without reducing image quality.

[0017] According to the present disclosure, the global dimming duty cycle can be varied within a wide variable range according to the brightness of the surrounding environment or the driving mode of the display device, thereby reducing power consumption without degrading image quality.

[0018] According to the present disclosure, when the average brightness of an input image is low, low grayscale representation in a darker image can be improved by reducing the global dimming duty cycle and extending the data voltage range.

[0019] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be apparently understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0021] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0022] Figure 2 It shows Figure 1 A cross-sectional view of the cross-sectional structure of the display panel shown;

[0023] Figure 3 is a circuit diagram showing a pixel circuit according to one embodiment of the present disclosure;

[0024] Figure 4 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure;

[0025] Figure 5 is shown applied to Figure 4 The waveform diagram of the gate signal of the pixel circuit shown;

[0026] Figure 6 is a diagram showing one frame period of a display device;

[0027] Figure 7 is a diagram illustrating an address period, a lighting period, and a light-off period of a display device according to an embodiment of the present disclosure;

[0028] Figure 8is a waveform diagram showing an example of a change in the gate-source voltage of a driving element when the low-potential power supply voltage changes;

[0029] Figure 9 is a view showing an example in which an address skip period is set between a first address period and a second address period;

[0030] Figure 10 is a waveform diagram showing an example in which no scan pulse is generated during an address skip period;

[0031] Figure 11 is a diagram illustrating an example of global dimming according to one embodiment of the present disclosure;

[0032] Figure 12 is a waveform diagram showing an example in which a low-potential power supply voltage is changed and a data voltage is maintained during an address skip period;

[0033] 13A to 13E is a view showing an example of sequentially performing data addressing, address skipping, and light emission along a scanning direction of a display panel;

[0034] 14A to 14C is a diagram showing a global dimming duty ratio applied differently according to a driving mode of a display device;

[0035] Figure 15 is a view showing an example of reducing screen brightness in a moving image;

[0036] Figure 16 is a view comparing the global dimming duty cycle for still and moving images; and

[0037] Figure 17 and Figure 18 is a diagram showing an example in which a global dimming duty ratio is varied based on an average picture level (APL). DETAILED DESCRIPTION

[0038] The advantages and features of the present disclosure and their implementation methods will be more clearly understood through the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various forms. On the contrary, these embodiments will complete the disclosure of the present disclosure and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is defined only within the scope of the appended claims.

[0039] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0040] Terms such as “including,” “comprising,” “having,” and “consisting of…” used herein generally intend to enable the addition of other components unless these terms are used with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0041] Even if not explicitly stated, the components are interpreted as including ordinary error ranges.

[0042] When terms such as "on", "over", "under", and "beside" are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used together with the terms "immediately" or "directly".

[0043] The terms “first”, “second”, etc. may be used to distinguish components from each other, but the function or structure of the components is not limited by the ordinal numbers preceding the components or the names of the components.

[0044] The following embodiments may be partially or completely combined or combined with each other, and may be technically associated and operated in various ways. The embodiments may be performed independently or in association with each other.

[0045] Each pixel may include multiple sub-pixels with different colors to reproduce the colors of the image on the screen of the display panel. Each sub-pixel includes a transistor that serves as a switching element or driving element. Such a transistor can be implemented as a TFT (thin film transistor).

[0046] The display device's driver circuit writes pixel data of an input image into pixels on a display panel. To this end, the display device's driver circuit may include a data driver circuit configured to supply data signals to data lines and a gate driver circuit configured to supply gate signals to gate lines.

[0047] In the display device of the present disclosure, the pixel circuit and the gate driver circuit may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, and the like. In the embodiments, the description is given based on an example in which the transistors of the pixel circuit and the gate driver circuit are implemented as n-channel oxide TFTs, but the present disclosure is not limited thereto.

[0048] Typically, a transistor is a three-electrode component consisting of a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current flow direction from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0049] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0050] The transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate-high voltage and the gate-off voltage may be a gate-low voltage.

[0051] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described with focus on an organic light emitting display device, but the present disclosure is not limited thereto.

[0052] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described with focus on an organic light-emitting display device, but the present disclosure is not limited thereto. In addition, the scope of the present disclosure is not limited by the names of components or signals in the following embodiments and claims.

[0053] refer to Figure 1 and Figure 2 , a display device according to an embodiment of the present disclosure includes a display panel 100 and a display panel driver for writing pixel data into pixels of the display panel 100 .

[0054] The display panel 100 may be a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array may be divided into a first pixel region A and a second pixel region A', where an address period is separated based on a transition time of the low potential power supply voltage ELVSS.

[0055] The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix. The display panel 100 may further include power lines commonly connected to the pixels. The power lines supply the voltage required to drive the pixels 101 to the pixels 101. For example, the display panel 100 may include a VDD line to which a pixel drive voltage ELVDD is applied and a VSS line to which a low potential power supply voltage ELVSS is applied. The power lines may further include a reference (REF) line and an initialization (INIT) line, wherein a reference voltage Vref is applied via the REF line and an initialization voltage Vinit is applied via the INIT line.

[0056] like Figure 2 As shown, according to one embodiment, the cross-sectional structure of the display panel 100 may include a circuit layer 12 , a light emitting element layer 14 , and an encapsulation layer 16 stacked on a substrate 10 .

[0057] Circuit layer 12 may include a TFT array (the TFT array includes pixel circuits connected to wiring such as data lines, gate lines, and power lines), a demultiplexer array 112, a gate driver 120, and the like. The wiring and circuit elements of circuit layer 12 may include: multiple insulating layers; two or more metal layers separated by insulating layers therebetween; and an active layer comprising a semiconductor material. All transistors formed in circuit layer 12 may be implemented as n-channel oxide TFTs, but the present disclosure is not limited thereto.

[0058] The light-emitting element layer 14 may include a light-emitting element EL driven by a pixel circuit. The light-emitting element EL may include a red (R) light-emitting element, a green (G) light-emitting element, and a blue (B) light-emitting element. In another embodiment, the light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting element EL of the light-emitting element layer 14 may be covered by a multi-layer passivation layer including an organic film and an inorganic film.

[0059] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 can have a multilayer insulating structure with alternating organic and inorganic films. The inorganic films prevent the penetration of moisture and oxygen. The organic films flatten the surface of the inorganic films. When the organic and inorganic films are stacked in multiple layers, the migration path of moisture or oxygen becomes longer compared to a single layer, thereby effectively blocking or at least reducing the penetration of moisture and oxygen that could affect light-emitting element layer 14.

[0060] A touch sensor layer (not shown) may be formed on the encapsulation layer 16, and a polarizer or color filter layer may be disposed on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor that senses touch input based on a change in capacitance before and after a touch input. The touch sensor layer may include a metal wiring pattern and an insulating film that form the touch sensor's capacitance. The insulating film may insulate the intersection of the metal wiring patterns and flatten the surface of the touch sensor layer. The polarizer may improve visibility and contrast by converting the polarization of external light reflected by the metal in the touch sensor layer and circuit layer. The polarizer may be implemented as a circular polarizer or as a combination of a linear polarizer and a phase retarder film. The encapsulation glass may be adhered to the polarizer. The color filter layer may include a red filter, a green filter, and a blue filter. The color filter layer may further include a black matrix pattern. The color filter layer may replace the polarizer by absorbing a portion of the wavelength of light reflected from the circuit layer and touch sensor layer, thereby improving the color purity of the image reproduced in the pixel array.

[0061] The pixel array includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel row share the same gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of pixel rows L1 to Ln.

[0062] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device that displays an image on a screen while allowing the actual background to be seen. The display panel 100 can be manufactured as a flexible display panel.

[0063] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color realization. Each pixel can further include a white sub-pixel. Each sub-pixel includes a pixel circuit. Hereinafter, a pixel can be interpreted as having the same meaning as a sub-pixel. Each pixel circuit is connected to a data line, a gate line, and a power line.

[0064] Pixels can be configured as true color pixels and pentile pixels. A true color pixel includes a red subpixel, a green subpixel, and a blue subpixel. Pentile pixels can achieve higher resolution than true color pixels by driving two subpixels of different colors as a single pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm can use the color of light emitted from adjacent pixels to compensate for insufficient color representation in each pixel.

[0065] Under the control of the timing controller 130, the display panel driver writes pixel data of an input image into the pixels of the display panel 100. During a first address period, the display panel driver maintains the low-potential power supply voltage ELVSS at an extinguishing voltage. During the first address period, pixel data is sequentially written into pixels in the first pixel region A, one pixel row at a time. During a second address period, the display panel driver maintains the low-potential power supply voltage ELVSS at an on-voltage. During the second address period, pixel data is sequentially written into pixels in the second pixel region A', one pixel row at a time. Between the first and second address periods, the display panel driver converts the low-potential power supply voltage ELVSS from an extinguishing voltage to a on-voltage. When the low-potential power supply voltage ELVSS is at the extinguishing voltage, the pixels can emit light.

[0066] The display panel driver includes a data driver 110, a gate driver 120, a power supply 140, and a timing controller 130. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

[0067] The power supply 140 uses a DC-DC converter to generate the direct current (DC) power required to drive the pixel array and display panel driver of the display panel 100. The DC-DC converter may include a charge pump, a voltage regulator, a buck converter, a boost converter, etc. The power supply 140 can adjust the level of the DC input voltage applied from the host system (not shown) and generate voltages such as the gamma reference voltage VGMA, the gate-on voltage, the gate-off voltage, the pixel drive voltage ELVDD, the low potential power supply voltage ELVSS, the initialization voltage Vinit, and the reference voltage Vref. The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltage and the gate-off voltage are supplied to the gate driver 120. Voltages such as the pixel drive voltage ELVDD, the low potential power supply voltage ELVSS, the initialization voltage Vinit, and the reference voltage Vref are supplied to the pixels 101 via power lines commonly connected to the pixels 101.

[0068] The power supply 140 can change the output voltage under the control of the timing controller 130. For example, the power supply 140 can generate a preset lighting voltage during the lighting period to suppress the pixel from emitting light, and can generate a lighting voltage higher than the lighting voltage during the lighting period to enable the pixel to emit light.

[0069] The demultiplexer array 112 sequentially supplies data voltages output from the channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers DEMUX. Each demultiplexer may include a plurality of switching elements provided on the display panel 100. When the demultiplexer is provided between the output terminal of the data driver 110 and the data lines 102, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 may be omitted.

[0070] The display panel driver may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver can be integrated into one driver integrated circuit (IC). In a mobile device or wearable device, the timing controller 130, the power supply 140, the data driver 110, etc. can be integrated into one driver IC.

[0071] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. The low-speed drive mode can be set to reduce the power consumption of the display device when the input image does not change during a preset number of frames as a result of analyzing the input image. In the low-speed drive mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel driver and the display panel 100 can be reduced by reducing the refresh rate (i.e., the frame rate of the pixel). The low-speed drive mode is not limited to the case where a still image is input. For example, when the display device is operating in standby mode, or when a user command or input image is not input to the display panel driver for a predetermined time or longer, the display panel driver can operate in a low-speed drive mode.

[0072] The data driver 110 receives pixel data of an input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 generates a data voltage Vdata by converting the pixel data of the input image into a gamma compensation voltage during each frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided into gamma compensation voltages for each grayscale by a voltage divider circuit. The gamma compensation voltages for each grayscale are supplied to the DAC in the data driver 110. The data voltage Vdata is output from each channel of the data driver 110 through an output buffer.

[0073] The gate driver 120 can be implemented as a gate-in-panel (GIP) circuit formed in the circuit layer 12 on the display panel 100 together with the TFT array and wiring of the pixel array. The gate driver 120 can be set on the bezel BZ (the bezel BZ is a non-display area of ​​the display panel 100), or can be dispersed in the pixel array that reproduces the input image. The gate driver 120 outputs the gate signal to the gate line 103 in sequence under the control of the timing controller 130. The gate driver 120 can supply the gate signal to the gate line 103 in sequence by shifting the gate signal using a shift register. The gate signal may include various gate pulses such as a scan pulse, an initialization pulse, a sensing pulse, etc.

[0074] The timing controller 130 receives digital video data DATA of an input image and timing signals synchronized with the digital video data from the host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, and a data enable signal DE. Since the vertical and horizontal periods can be determined by calculating the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0075] The host system may be a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, or a vehicle system. The host system may scale the image signal from the video source to match the resolution of the display panel 100 and transmit it to the timing controller 130 along with the timing signal.

[0076] The host system can adjust the overall brightness of the image reproduced on the display panel by determining the brightness of the surrounding environment based on the output signal of the brightness sensor. The host system can change the global dimming duty cycle based on the brightness value (such as the display brightness value (DBV) or peak brightness control (PLC)), and the brightness value can be changed according to the user-specified screen brightness. The host system can classify the normal driving mode of the display device into outdoor mode, standard mode, night mode, energy-saving mode, etc., and can change the global dimming duty cycle for each mode.

[0077] The host system or timing controller 130 may change the global dimming duty based on the average picture level (APL) of the input image, or may change the global dimming duty between still and moving images by detecting movement of an object in the input image to determine whether there is movement.

[0078] The timing controller 130 can multiply the input frame frequency by i (i is a natural number) in the normal driving mode, so that it can control the operation timing of the display panel driver at a frame frequency of input frame frequency × i Hz. In the National Television Standards Committee (NTSC) system, the input frame frequency is 60 Hz, and in the Phase Alternating Line (PAL) system, the input frame frequency is 50 Hz. For example, the display panel driver can address pixel data to the pixel 101 at a frame frequency of more than 120 Hz under the control of the timing controller 130. In order to reduce the refresh rate of the pixel in the low-speed driving mode, the timing controller 130 can reduce the driving frequency of the display panel driver by reducing the frame frequency to a frequency between 1 Hz and 30 Hz.

[0079] The timing controller 130 generates data timing control signals for controlling the operation timing of the data driver 110 based on the timing signals Vsync, Hsync, and DE received from the host system, generates control signals for controlling the operation timing of the demultiplexer array 112, and generates gate timing control signals for controlling the operation timing of the gate driver 120. The timing controller 130 synchronizes the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120 by controlling the operation timing of the display panel driver.

[0080] The gate timing control signal generated from the timing controller 130 can be input to the shift register of the gate driver 120 through a level shifter (not shown). The level shifter can receive the gate timing control signal, generate a start pulse and a shift clock, and provide them to the shift register of the gate driver 120.

[0081] The timing controller 130 can change the global dimming duty cycle for each frame by changing the duty cycle of the low-voltage power supply voltage ELVSS commonly applied to the pixels 101. The timing controller 130 controls the duty cycle, which is the ratio of the duration of the on voltage to the duration of the off voltage in the low-voltage power supply voltage ELVSS, according to the global dimming duty cycle. The duty cycle of the low-voltage power supply voltage ELVSS is substantially the same as the global dimming duty cycle.

[0082] When the duty cycle of the low potential power supply voltage ELVSS changes, the boundary position of the first pixel region A and the second pixel region A' on the screen of the display panel 100 changes. For example, when the duty cycle of the low potential power supply voltage ELVSS is less than a predetermined threshold value, the size of the second pixel region A' on the screen of the display panel 100 is reduced, so that the boundary between the first pixel region A and the second pixel region A' can move down on the screen (for example, closer to the bottom of the screen). On the other hand, when the duty cycle of the low potential power supply voltage ELVSS is greater than a predetermined threshold value, the size of the second pixel region A' on the screen of the display panel 100 is increased, so that the boundary between the first pixel region A and the second pixel region A' can move up on the screen (for example, closer to the top of the screen).

[0083] Due to device characteristic deviations and process deviations caused in the manufacturing process of the display panel 100, there may be differences in the electrical characteristics of the driving elements between pixels, and this difference may increase as the driving time of the pixels passes. In order to compensate for the changes in the electrical characteristics of the driving elements between pixels, an internal compensation circuit can be embedded in the pixel circuit, or an external compensation circuit can be connected to the pixel circuit. The internal compensation circuit uses an internal compensation circuit implemented in each pixel circuit to sample the electrical characteristics of the driving element of each sub-pixel and compensates the gate-source voltage Vgs of the driving element based on the electrical characteristics. The external compensation circuit compensates for the changes in the electrical characteristics of the driving element by generating a compensation value based on the result of sensing the electrical characteristics of the driving element using an external compensation circuit connected to the pixel circuit. The external compensation circuit includes a REF line (or sensing line) connected to the pixel circuit and an analog-to-digital converter (ADC) that converts the sensing voltage stored in the REF line into digital data. The sensing voltage may include the electrical characteristics of the driving element DT, for example, a threshold voltage and / or mobility. An integrator can be connected to the input terminal of the ADC. The timing controller 130 using an external compensation circuit can generate a compensation value for compensating for variations in the electrical characteristics of the driving element DT based on sensing data input from the ADC, and can compensate for variations in the electrical characteristics of the driving element DT by adding or multiplying the compensation value with pixel data of an input image. The ADC can be embedded in the data driver 110.

[0084] The pixel circuit of the present disclosure may include an internal compensation circuit or may be connected to an external compensation circuit without an EM switch element. The pixel circuit may include an internal compensation circuit or may be connected to an external compensation circuit without an EM switch element.

[0085] Figure 3 is a circuit diagram illustrating a pixel circuit according to one embodiment of the present disclosure.

[0086] refer to Figure 3The pixel circuit includes a light emitting element EL, a driving element DT for driving the light emitting element EL, a capacitor Cst connected between a second node DRG and a third node DRS, and a plurality of switching elements M01 and M02. In the pixel circuit, the driving element DT and the switching elements M01 and M02 can be implemented as n-channel oxide TFTs.

[0087] Voltages such as a pixel driving voltage ELVDD, a low potential power supply voltage ELVSS, and a reference voltage Vref are applied to the pixel circuit. The pixel driving voltage ELVDD is higher than the low potential power supply voltage ELVSS. The gate-on voltage can be set to a voltage higher than the pixel driving voltage ELVDD. The reference voltage Vref can be set to a voltage lower than the low potential power supply voltage ELVSS. The gate-off voltage can be set to a voltage lower than the reference voltage Vref.

[0088] The low-potential power supply voltage ELVSS can be generated as an alternating current (AC) voltage that swings between a lighting voltage and an extinguishing voltage. When the low-potential power supply voltage ELVSS rises to the extinguishing voltage, the voltage difference between the anode and cathode of the light-emitting element EL becomes lower than the threshold voltage of the light-emitting element EL, so that the light-emitting element EL cannot emit light.

[0089] The gate driver 120 may include a first shift register that sequentially outputs the scan pulse SCAN. The gate driver 120 may further include a second shift register that sequentially outputs the sense pulse SENSE.

[0090] The light-emitting element EL can be implemented as an OLED including an anode, a cathode, and an organic compound layer connected between these electrodes. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When voltage is applied to the anode and the cathode, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the light-emitting layer EML to form excitons. At this time, visible light can be emitted from the light-emitting layer EML. The OLED used as the light-emitting element EL can have a series structure in which multiple light-emitting layers are stacked. The OLED of the series structure can improve the brightness and life of the pixel.

[0091] The anode of the light emitting element EL may be connected to the third node DRS, and the cathode of the light emitting element EL may be connected to the VSS line to which the low potential power supply voltage ELVSS is applied. The light emitting element EL includes a capacitor CEL formed between the anode and the cathode.

[0092] The driving element DT generates a current for driving the light-emitting element EL based on a gate-source voltage Vgs. The driving element DT includes a gate connected to a second node DRG, a first electrode connected to a first node DRD to which a pixel driving voltage ELVDD is applied, and a second electrode connected to a third node DRS. A capacitor Cst is connected between the second node DRG and the third node DRS. The gate-source voltage Vgs of the driving element DT is charged into the capacitor Cst.

[0093] The first switching element M01 is turned on according to the gate-on voltage of the scan pulse SCAN to supply the data voltage Vdata to the second node DRG. The first switching element M01 includes a gate connected to the first gate line to which the scan pulse SCAN is applied, a first electrode connected to the data line to which the data voltage Vdata is applied, and a second electrode connected to the second node DRG.

[0094] The second switching element M02 is turned on according to the gate-on voltage of the scan pulse SCAN or the sensing pulse SENSE to apply the reference voltage Vref to the third node DRS. The second switching element M02 includes a gate connected to the second gate line to which the scan pulse SCAN or the sensing pulse SENSE is applied, a first electrode connected to the third node DRS, and a second electrode connected to the REF line to which the reference voltage Vref is applied.

[0095] The REF line can be connected to an external compensation circuit. In this case, the voltage of the third node DRS is stored in a capacitor on the REF line, the electrical characteristics of the driving element DT are stored in the REF line, and the voltage of the REF line is converted into digital data by the ADC. The electrical characteristics of the driving element DT may include threshold voltage and mobility.

[0096] Figure 4 is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure.

[0097] refer to Figure 4 The pixel circuit includes a light emitting element EL, a driving element DT for supplying current to the light emitting element EL, a capacitor Cst connected between a second node DRG and a third node DRS, and a plurality of switching elements M11, M12, and M13. In this pixel circuit, the driving element DT and the switching elements M11, M12, and M13 can be implemented as n-channel oxide TFTs.

[0098] Voltages such as a pixel driving voltage ELVDD, a low potential power supply voltage ELVSS, a reference voltage Vref, and an initialization voltage Vinit are applied to the pixel circuit. The pixel driving voltage ELVDD is higher than the low potential power supply voltage ELVSS. The gate-on voltage can be set to a voltage higher than the pixel driving voltage ELVDD. The gate-off voltage can be set to a voltage lower than the low potential power supply voltage ELVSS. The reference voltage Vref can be set to a voltage lower than the low potential power supply voltage ELVSS and higher than the gate-off voltage. The initialization voltage Vinit is set to a voltage that turns on the driving element DT, which is lower than the pixel driving voltage ELVDD and equal to or greater than the half-grayscale data voltage Vdata.

[0099] The low potential power supply voltage ELVSS can be generated as an AC voltage that swings between a lighting voltage and an extinguishing voltage. When the low potential power supply voltage ELVSS rises to the extinguishing voltage, the voltage difference between the anode and cathode of the light-emitting element EL becomes lower than the threshold voltage of the light-emitting element EL, so that the light-emitting element EL cannot emit light.

[0100] The gate driver 120 may include a first shift register sequentially outputting a first scan pulse SCAN1 , a second shift register sequentially outputting a second scan pulse SCAN2 , and a third shift register sequentially outputting a third scan pulse SCAN3 .

[0101] The light-emitting element EL may be implemented as an OLED including an anode, a cathode, and an organic compound layer connected between these electrodes. The anode of the light-emitting element EL may be connected to a third node DRS, and the cathode of the light-emitting element EL may be connected to a VSS line to which a low-potential power supply voltage ELVSS is applied. The light-emitting element EL includes a capacitor CEL formed between the anode and the cathode.

[0102] The driving element DT generates a current for driving the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate connected to a second node DRG, a first electrode connected to a first node DRD to which a pixel driving voltage ELVDD is applied, and a second electrode connected to a third node DRS. A capacitor Cst is connected between the second node DRG and the third node DRS.

[0103] The first switching element M11 is turned on according to the gate-on voltage of the scan pulse SCAN1 to supply the data voltage Vdata to the second node DRG. The first switching element M11 includes a gate connected to the first gate line to which the first scan pulse SCAN1 is applied, a first electrode connected to the data line DL to which the data voltage Vdata is applied, and a second electrode connected to the second node DRG.

[0104] The second switching element M12 is turned on according to the gate-on voltage of the second scan pulse SCAN2 to supply the reference voltage Vref to the third node DRS. The second switching element M12 includes a gate connected to the second gate line to which the second scan pulse SCAN2 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the REF line RL to which the reference voltage Vref is applied.

[0105] The third switching element M13 is turned on according to the gate-on voltage of the scan pulse SCAN3 to supply the initialization voltage Vinit to the second node DRG. The third switching element M13 includes a gate connected to the third gate line to which the third scan pulse SCAN3 is applied, a first electrode connected to the INIT line to which the initialization voltage Vinit is applied, and a second electrode connected to the second node DRG.

[0106] Figure 5 The gate signal shown can be input to Figure 4 The pixel circuit shown.

[0107] refer to Figure 5 , the driving period of the pixel circuit can be divided into an initialization step INIT, a sensing step SEN, an addressing step WR, a boosting step BOOST, and an emission step EMIS. In the initialization step INIT, the driving element DT is turned on. In the sensing step SEN, when the voltage of the third node DRS increases and the gate-source voltage Vgs of the driving element DT becomes lower than the threshold voltage Vth of the driving element DT, the driving element DT is turned off. When the driving element DT is turned off in the sensing step SEN, the threshold voltage Vth of the driving element DT is sampled and stored in the capacitor Cst. In the holding period HO between the sensing step SEN and the addressing step WR, all gate signals SCAN1, SCAN2, and SCAN3 are at the gate-off voltage VGL. In the holding period HO, the second node DRG and the third node DRS float to maintain their previous voltages.

[0108] When the data voltage Vdata is applied to the second node DRG in the addressing step WR, the data voltage Vdata compensated by the threshold voltage Vth is applied to the gate of the driving element DT. After the capacitor CEL of the light-emitting element EL is charged as the voltages of the second node DRG and the third node DRS, which are floated in the boosting step BOOST, increase, the light-emitting element EL can be illuminated by a current generated by the gate-source voltage Vgs compensated by the threshold voltage Vth of the driving element DT in the light-emitting step EMIS. In the light-emitting step EMIS, the low-potential power supply voltage ELVSS is generated at the lighting voltage Von.

[0109] During the initialization step INIT and the sensing step SENSE, a third scan pulse SCAN3 is generated at a gate-on voltage VGH. The third scan pulse SCAN3 is at a gate-off voltage VGL during the hold period HO, the addressing step WR, the boosting step BOOST, and the light-emitting step EMIS. The first scan pulse SCAN1 is synchronized with the data voltage Vdata of the pixel data and is generated at a gate-on voltage VGH during the addressing step WR. The first scan pulse SCAN1 is at a gate-off voltage VGL during the hold period HO, the initialization step INIT, the sensing step SENSE, the boosting step BOOST, and the light-emitting step EMIS. During the initialization step INIT, a second scan pulse SCAN2 is generated at a gate-on voltage VGH. The second scan pulse SCAN2 is at a gate-off voltage VGL during the sensing step SENSE, the hold period HO, the addressing step WR, the boosting step BOOST, and the light-emitting step EMIS.

[0110] Figure 6 is a view showing one frame period of a display device.

[0111] refer to Figure 6 , one frame period (one frame) is divided into an address period AT in which pixel data of an input image is written into pixels and a vertical blank period VB in which pixel data of no input image is written into pixels. In one embodiment, the vertical blank period VB includes a front porch FP portion, a vertical synchronization VS portion, and a back porch (BP) portion.

[0112] The vertical synchronization signal Vsync defines one frame period. One pulse cycle of the horizontal synchronization signal Hsync and the data enable signal DE constitutes one horizontal period (1H). During the address period AT, the display panel driver sequentially writes pixel data corresponding to one frame into the pixels of the display panel 100, one pixel row at a time. The data voltage Vdata of the pixel data is synchronized with the scan pulse and is simultaneously charged into the pixels in one pixel row within one horizontal period (1H).

[0113] like Figure 7As shown, the address period AT of one frame period may include a first address period AT1 and a second address period AT2, and the first address period AT1 and the second address period AT2 are divided at a time point between the first address period AT1 and the second address period AT2 at which the low potential power supply voltage ELVSS is converted. Therefore, the first address period AT1 and the second address period AT2 do not overlap. The timing controller 130 may divide the address period AT of one frame period into the first address period AT1 and the second address period AT2, transfer the pixel data to be written in the pixels in the first pixel area A to the data driver 110 during the first address period, and then transfer the pixel data to be written in the pixels in the second pixel area A' to the data driver 110 during the second address period. As will be referred to below, Figure 9 As further described, the timing controller 130 may control the power supply 140 to temporarily stop the transmission of pixel data during an address skip period provided between the first address period AT1 and the second address period AT2 .

[0114] The data enable signal DE defines a valid data period including pixel data to be written into pixels within one horizontal period 1 H. A pulse of the data enable signal DE is synchronized with pixel data of one pixel row.

[0115] During the vertical blank period VB, no new pixel data is written to the pixel. The subpixel maintains the voltage charged from the previous frame during the vertical blank period VB. The low-potential power supply voltage ELVSS can remain at the lighting voltage for at least a portion of the vertical blank period VB. Before the start of the next frame period, the low-potential power supply voltage ELVSS can be switched to the extinguishing voltage during the vertical blank period VB.

[0116] The horizontal blank period HB is a period without pixel data in one horizontal period. There is a horizontal blank period HB between a row of data to be written into sub-pixels in the i-th (i is a positive integer) pixel row and a row of data to be written into sub-pixels in the i+1-th pixel row.

[0117] In the display device of the present disclosure, Figure 1 and Figure 7As shown, the low-potential power supply voltage ELVSS is reduced to the lighting voltage Von during the address period AT in which pixel data is written sequentially in a pixel row, causing the pixel to start emitting light. Therefore, in the present disclosure, global dimming can be started during the address period AT and can be performed until the vertical blank period VB. Therefore, since the global dimming period is generated during the address period AT rather than during the vertical blank period VB, the global dimming control method of the present disclosure can ensure a sufficiently long global dimming period for each frame period, thereby linearly controlling the global dimming duty cycle within a wider range. Therefore, the brightness of the first pixel area A and the second pixel area A' can change non-linearly within a wider range of the duty cycle.

[0118] refer to Figure 1 and Figure 7 , the screen of the display panel 100 may include a first pixel region A and a second pixel region A'. The address period of one frame period (N-1th frame to N+1th frame) may be divided into a first address period AT1 in which pixel data is sequentially written into pixels in the first pixel region A and a second address period AT2 in which pixel data is sequentially written into pixels in the second pixel region A'. Figure 7 In the figure, “N-1th frame” indicates the N-1th frame period, “Nth frame” indicates the Nth frame period, and “N+1th frame” indicates the N+1th frame period.

[0119] During the first address period AT1 for scanning the pixels in the first pixel region A, the low-potential power supply voltage ELVSS is generated at the extinguishing voltage Voff, so that the pixels in the first pixel region A do not emit light. During the second address period AT2 for scanning the pixels in the second pixel region A', the low-potential power supply voltage ELVSS is converted to the lighting voltage Von. As a result, the pixels in the first pixel region A and the second pixel region A' begin to emit light from the start of the second address period for scanning the second pixel region A'.

[0120] The first pixel region A may include two or more pixel rows from the first pixel row to the (I-1)-th pixel row, where I is a positive integer equal to or greater than 2. The second pixel region A' may include two or more pixel rows from the (I)-th pixel row to the (n)-th pixel row, where n is a positive integer greater than 2 and greater than 1. The low potential power supply voltage ELVSS is supplied to all pixels in the first pixel region A and the second pixel region A' through a VSS line formed as a common electrode in the screen of the display panel. Therefore, when the voltage level of the low potential power supply voltage ELVSS changes, the voltage levels of the low potential power supply voltage ELVSS applied to all pixels change simultaneously.

[0121] During the first address period AT1, the data voltage Vdata of the pixel data is sequentially charged one pixel row at a time from the first pixel row to the (I-1)th pixel row included in the first pixel region A along the shift direction of the scan pulse. During the first address period AT1, the low-potential power supply voltage ELVSS maintains the extinguishing voltage Voff. Therefore, all pixels included in the first pixel region A and the second pixel region A' do not emit light during the first address period AT1.

[0122] When pixel data begins to be written to the pixels in the first pixel row, the second address period AT2 begins. During the second address period AT2, the data voltage Vdata of the pixel data is sequentially charged, one pixel row at a time, from the first pixel row to the nth pixel row contained in the second pixel area A' along the shift direction of the scan pulse. When the second address period AT2 begins, the low-potential power supply voltage ELVSS is converted to the lighting voltage Von, and during the second address period AT2, the low-potential power supply voltage ELVSS is generated at the lighting voltage Von. Therefore, since the low-potential power supply voltage ELVSS maintains the lighting voltage Von during the second address period AT2, the pixels contained in the first pixel area A and the second pixel area A' can emit light at the target brightness corresponding to the grayscale of the pixel data during the second address period.

[0123] From the start of the second address period to the end of the vertical blank period VB, the low potential power supply voltage ELVSS can be generated as the lighting voltage Von. Therefore, the maximum lighting duration of the pixel is the duration from the start of the second address period AT2 to the end of the vertical blank period VB. The timing controller 130 can change the global dimming duty cycle according to the driving mode or the analysis result of the input image. When the global dimming duty cycle is high, the time point at which the low potential power supply voltage ELVSS is converted to the lighting voltage Von is advanced, so that the position of the first pixel row starting from the second address period AT2 is changed to the position of the pixel row with an earlier scanning time point. On the contrary, when the global dimming duty cycle is low, the time point at which the low potential power supply voltage ELVSS is converted to the lighting voltage Von is delayed, so that the position of the first pixel row starting from the second address period AT2 is changed to the position of the pixel row with a later scanning time point.

[0124] Meanwhile, when the low potential power supply voltage ELVSS is switched, the gate-source voltage Vgs of the driving element DT may be changed, as shown in FIG. Figure 8 shown.

[0125] refer to Figure 8, when the low potential power supply voltage ELVSS changes within the address period AT, the voltage of the third node DRS coupled to the VSS line through the capacitor CEL (i.e., the source voltage of the driving element DT) changes to the low potential power supply voltage ELVSS. At this time, the third node DRS is changed based on the ΔELVSS×CAP ratio. ΔELVSS is the amount of change in the low potential power supply voltage ELVSS, and the CAP ratio is the ratio of the capacitor Cst and CEL connected to the third node DRS. In this case, the gate-source voltage Vgs of the driving element DT changes in the pixel row where the low potential power supply voltage ELVSS is converted, and thus the brightness at the pixel in the corresponding pixel row changes, so that dark lines may be visually recognized on the screen. In order to prevent or at least reduce this problem, the present disclosure may set an address skip period, such as Figure 9 and Figure 10 As shown, when the low potential power supply voltage ELVSS switches, addressing is temporarily stopped.

[0126] The address skip period may be set between the first address period AT1 and the second address period AT2 within the address period AT of a frame period. During the address skip period between the first address period AT1 and the second address period AT2, the low-potential power supply voltage ELVSS may be changed from the extinguishing voltage Voff to the lighting voltage Von. Furthermore, the address skip period may be set within the vertical blank period VB before entering the next frame period. During the address skip period within the vertical blank period VB, the low-potential power supply voltage ELVSS may be changed from the lighting voltage Von to the extinguishing voltage Voff.

[0127] Figure 9 1 is a diagram showing an example in which an address skip period SK (eg, an intermediate period) is set between the first address period AT1 and the second address period AT2. Figure 10 is a waveform diagram showing an example in which no scan pulse is generated in the address skip period SK.

[0128] refer to Figure 9 and Figure 10 Under the control of the timing controller 130, the gate driver 120 sequentially outputs gate signals to the first pixel row to the (I-1)-th pixel row during the first address period AT1, and supplies the gate signals to the gate lines of the pixel rows. After the first address period AT1, the gate driver 120 does not output (e.g., limits output) gate signals (specifically, scan pulses) during the address skip period SK, and maintains the voltage of the gate line at the gate-off voltage during the address skip period SK. Therefore, during the address skip period SK, since the scan pulse is not applied to all pixels in the first pixel row and the screen, the data voltage Vdata of the pixel data is not applied to the second node DRG of the pixel circuit.

[0129] The timing controller 130 uses a row memory or a delay circuit to delay the pixel data of the input image during the address skip period SK, and then transmits the pixel data of the first pixel row to the data driver 110 when the second address period AT2 begins. The timing controller 130 may temporarily stop driving the output buffer between the output terminal of the data driver 110 and the data line or turn off the output switching element during the address skip period SK, thereby separating the output terminal of the data driver 110 from the data line. In another embodiment, the timing controller 130 may turn off the switching element of the demultiplexer array 112 provided between the output terminal of the data driver 110 and the data line, thereby electrically separating the output terminal of the data driver 110 from the data line during the address skip period SK.

[0130] The gate driver 120, under the control of the timing controller 130, sequentially supplies gate signals to the gate lines of pixel rows from the 1st pixel row to the nth pixel row in response to the second address period AT2 starting after the address skip period SK.

[0131] Figure 11 is a view illustrating an example of global dimming according to one embodiment of the present disclosure.

[0132] refer to Figure 11 The timing controller 130 can adjust the brightness of the image reproduced on the screen of the display panel by changing the global dimming duty cycle. In other words, the global duty cycle is adjustable. For example, the timing controller 130 can adjust the brightness on the screen by changing the global dimming duty cycle to 25%, 50%, 75%, etc. The position of the pixel row on the screen synchronized with the address skip period can be changed according to the global dimming duty cycle.

[0133] Figure 12 is a waveform diagram showing an example in which the low-potential power supply voltage changes and the data voltage is maintained during the address skip period.

[0134] refer to Figure 12 , the input image may be a vertical gradient image in which the grayscale value gradually decreases from the first pixel row to the nth pixel row. In this case, for each pixel row, the grayscale value of the data voltage Vdata of the pixel data gradually decreases. The scan pulse SCAN may be in the first address period AT1 (for example, Figure 12 During the "addressing only" ("addressing only") period, the data voltage Vdata is synchronized with the data voltage and applied to the pixel rows in sequence.

[0135] The low potential power voltage ELVSS maintains the off voltage Voff during the first address period AT1. Therefore, only data addressing is performed without emitting light during the first address period AT1, so that the pixels in the first pixel area A do not emit light and are charged with the data voltage Vdata.

[0136] During the address skip period SK (eg, Figure 12 During the "address skip" period (in the address skip period), the voltage of the data line maintains the previous data voltage, and the scan pulse is maintained at the gate-off voltage VGL (data hold), so that data addressing is not performed. During the address skip period SK, the low potential power supply voltage ELVSS changes from the extinguishing voltage Voff to the lighting voltage Von.

[0137] When the second address period AT2 (eg, Figure 12 At the beginning of the "addressing+light emission" in the first address period, the data voltage Vdata of the pixel data is generated with the grayscale voltage of the pixel data to be written into the pixels in the first pixel row. During the second address period AT2 starting after the address skip period SK, the scan pulse SCAN can be synchronized with the data voltage Vdata and sequentially applied to the pixel rows. Therefore, when the second address period AT2 begins, the data driver 110 resumes outputting the data voltage Vdata, and the gate driver 120 resumes outputting the scan pulse SCAN.

[0138] The low-potential power supply voltage ELVSS maintains the lighting voltage Von during the second address period AT2 and the vertical blank period VB. Therefore, during the second address period AT2, data addressing is performed on the pixels in the second pixel region A', while the pixels in the first pixel region A and the second pixel region A' can emit light according to the global dimming duty cycle. In this case, the pixels in the first pixel region A emit light at a target brightness corresponding to the grayscale of the pixel data written during the first address period of the current frame, and the pixels in the second pixel region A' emit light while performing data addressing to update the pixel data written in the previous frame to the pixel data of the current frame.

[0139] 13A to 13E 1 is a diagram showing an example of sequentially performing data addressing, address skipping, and light emission along a scanning direction of a display panel. 13A to 13E In the upper drawing showing the screen of the display panel, a black screen indicates pixels that do not emit light.

[0140] During the first address period AT1, if Figure 13A As shown, data addressing is performed, and pixel data is written into the pixels in the first pixel region A. During the first address period AT1 , the pixels in the first pixel region A and the second pixel region A′ do not emit light.

[0141] During the address skip period SK, if Figure 13B As shown, the low potential power voltage ELVSS changes from the extinguishing voltage Voff to the lighting voltage Von. At this time, scanning is stopped for the first pixel region A and the second pixel region A', so that the pixels maintain the previous data voltage and do not emit light.

[0142] After the address skip period SK, the second address period AT2 begins. During the second address period AT2, the low potential power supply voltage ELVSS is generated at the lighting voltage Von. Figure 13C As shown, the second address period AT2 begins when the data voltage Vdata of the pixel data to be written in the first pixel row is output from the data driver 110 and the scan pulse SCAN synchronized with the data voltage Vdata is output from the gate driver 120. After the data voltage Vdata of the pixel data is charged into the pixels in the first pixel row, the pixels in the first pixel area A and the second pixel area A' begin to emit light.

[0143] During the second address period AT2, as shown in FIG. Figure 13D As shown, data addressing is performed on the pixels in the I+J-th pixel row. Here, each of I and J is a positive integer, and "I+J" is a positive integer less than n. During the second address period AT2, since the low potential power supply voltage ELVSS is the lighting voltage Von, the pixel rows in the first pixel region A and the second pixel region A' can emit light.

[0144] As the execution time of the second address period AT2 increases, the luminous screen area expands. When data addressing is completed for the nth pixel row to which the last scan pulse is applied, as shown in FIG. Figure 13E As shown, all pixels of the screen emit light (full light).

[0145] According to the present disclosure, by adjusting the duty cycle when performing global dimming, the brightness of the pixel can be adjusted while the data voltage is fixed to a predetermined voltage or above. The method of changing the duty cycle of turning on and off the pixel can provide a color spot improvement effect at low brightness.

[0146] Since the required brightness on the screen varies depending on the usage environment, the global dimming duty cycle can be adaptively applied according to the brightness of the surrounding environment. For example, the duty cycle of the low potential power supply voltage ELVSS can be changed in proportion to the brightness of the surrounding environment of the display device.

[0147] In the case of outdoor mode, since high brightness is required on the screen, the pixels may be driven at a maximum duty cycle (ie, a duty cycle of 100%), as shown in FIG. Figure 14AWhen the duty ratio of the low potential power supply voltage ELVSS changes from the standard mode, the energy saving mode, or the night mode to the outdoor mode, the duty ratio of the low potential power supply voltage ELVSS becomes higher.

[0148] In the case of standard mode, a global dimming duty cycle can be applied according to the brightness specified by the user, and as Figure 14B As shown, a duty cycle of 50% may be applied as a default value.

[0149] In case of energy saving mode or night mode, because the pixels are driven at low brightness, the global dimming duty cycle can be reduced to a duty cycle below 20%, such as Figure 14C As shown in the figure, when the drive mode changes to energy-saving mode or night mode, the duty cycle of the low-voltage power supply voltage ELVSS decreases. Energy-saving mode can be entered when the remaining battery charge is less than a preset value. Because color spots on the display are more sensitive in nighttime environments, global dimming can be applied to enhance image quality.

[0150] As described above, the present disclosure can provide image quality optimized for the usage environment and reduce power consumption by adaptively changing the global dimming duty cycle according to the usage environment or driving mode. In addition, according to the present disclosure, based on the results of analyzing the input image, power consumption can be further reduced without reducing image quality. For example, Figure 15 As shown in the figure, when the input image is a moving image, the power consumption of the moving image can be reduced by lowering the brightness of the moving image compared to a still image. Compared to still images, moving images have greater complexity, such as many edges and a lot of movement of objects, so users are less sensitive to increases or decreases in brightness. Therefore, even if the screen brightness is reduced for moving images, the image quality that users can perceive is lower.

[0151] like Figure 16 As shown, the timing controller 130 can analyze the input image and change the duty cycle of the low potential power supply voltage ELVSS to make the global dimming duty cycle of the moving image lower than the global dimming duty cycle of the still image, thereby reducing the brightness of the screen reproducing the moving image and reducing power consumption. Figure 16 An example is shown in which the global dimming duty cycle for a still image is 100% and the global dimming duty cycle for a video is reduced to 30%. The global dimming duty cycle is substantially the same as the duty cycle of the low-potential power supply voltage ELVSS. The timing controller 130 can reduce the global dimming duty cycle when the input image changes from a still image to a moving image, and can increase the global dimming duty cycle when the input image changes from a moving image to a still image. The timing controller can enter a low-speed drive mode for still images and reduce the frame frequency, thereby reducing power consumption even in still images.

[0152] The duty cycle of the low potential power supply voltage ELVSS can be changed in proportion to the average brightness of a frame of image, such as Figure 17 and Figure 18 shown.

[0153] Figure 17 and Figure 18 is a diagram showing an example in which a global dimming duty ratio is varied based on an average picture level (APL).

[0154] refer to Figure 17 and Figure 18 , the average picture level APL is a value representing the average brightness of a frame of image, and is calculated as the average value of the cumulative distribution value of each grayscale level of a frame of image. An image with a higher average picture level (APL) is a brighter image, and an image with a lower average picture level (APL) is a darker image. The timing controller 130 can change the global dimming duty cycle in proportion to the average picture level (APL) of a frame of image calculated for each frame. The timing controller 130 increases the global dimming duty cycle by increasing the duty cycle of the low potential power supply voltage ELVSS under brighter images with higher average picture levels (APL) to increase the brightness of the screen. The timing controller 130 can reduce the global dimming duty cycle by reducing the duty cycle of the low potential power supply voltage ELVSS under darker images with lower average picture levels (APL) to reduce the brightness of the screen. Furthermore, the timing controller may increase a voltage range between a maximum voltage and a minimum voltage of the data voltage Vdata in a darker image having a lower average picture level (APL), ie, expand the data voltage range to improve low grayscale representation in the darker image.

[0155] In one embodiment, a display device includes: a display panel, the display panel including a first display area and a second display area, the first display area including a plurality of first pixels, the second display area including a plurality of second pixels, each of the plurality of first pixels and the plurality of second pixels including a corresponding light-emitting element; a data driver circuit, the data driver circuit being configured to output a plurality of data voltages of an image to the plurality of first pixels and the plurality of second pixels; a gate driver, the gate driver being configured to output a plurality of scan signals to the plurality of first pixels and the plurality of second pixels; and a power supply, the power supply being configured to generate a low-level power supply voltage, the low-level power supply voltage being applied to the corresponding light-emitting element included in each of the plurality of first pixels and the plurality of second pixels, the low-level power supply voltage being switched between a first level enabling the light-emitting element in each pixel to emit light and a second level preventing the light-emitting element in each pixel from emitting light, wherein The frame period of the display device includes an address period and a blank period, during which the multiple data voltages and the multiple scan signals of the image are output to the multiple first pixels and the multiple second pixels, and during the blank period, the multiple data voltages and the multiple scan signals are not output to the multiple first pixels and the multiple second pixels, wherein, during a first part of the address period, the low-level power supply voltage is at the second level, so that none of the multiple first pixels in the first display area emits light and none of the multiple second pixels in the second display area emits light, and during a second part of the address period after the first part, the low-level power supply voltage is at the first level, so that the multiple first pixels in the first display area emit light to display the first part of the image, and at least a part of the multiple second pixels in the second display area emit light to display at least a part of the second part of the image.

[0156] In one embodiment, each of the plurality of first pixels and the plurality of second pixels includes: a driving element, including a first electrode of the driving element, a gate of the driving element, and a second electrode of the driving element, the first electrode of the driving element being connected to a first node, a first power line applying a pixel driving voltage to the first node, the gate of the driving element being connected to a second node, and the second electrode of the driving element being connected to a third node; a light-emitting element, including an anode and a cathode, the anode being connected to the third node, and the low-level power supply voltage being applied to the cathode; a capacitor between the second node and the third node; and a first switching element, including a first electrode of the first switching element, a gate of the first switching element, and a second electrode of the first switching element, the first electrode of the first switching element being connected to a data line, a data voltage from the plurality of data voltages being applied to the data line, a scan signal from the plurality of scan signals being applied to the gate of the first switching element, and the second electrode of the first switching element being connected to the second node.

[0157] In one embodiment, during the first portion of the address period, while the low-level power supply voltage is at the second level, a first data voltage from the plurality of data voltages is written into the plurality of first pixels in the first display area via a first switching element included in the plurality of first pixels, while a second data voltage from the plurality of data voltages is not written into the plurality of second pixels in the second display area, and during the second portion of the address period, while the low-level power supply voltage is at the first level, the light-emitting elements included in the plurality of first pixels in the first display area emit light corresponding to the first data voltage to display the first portion of the image, and at least a portion of the second data voltage from the plurality of data voltages is output via a first switching element included in the plurality of first pixels. The first switching elements in the plurality of second pixels are written to a portion of the plurality of second pixels in the second display area, and the light-emitting elements included in the portion of the plurality of second pixels emit light corresponding to the portion of the second data voltage to display the portion of the second part of the image, wherein the plurality of first pixels are arranged as a plurality of first pixel rows in the first display area, and the plurality of second pixels are arranged as a plurality of second pixel rows in the second display area, wherein during the second portion of the addressing period, the plurality of first pixel rows display the first portion of the image substantially simultaneously, and as the corresponding second data voltage is written to each second pixel row, the plurality of second pixel rows substantially display corresponding portions of the second portion of the image in the second display area.

[0158] In one embodiment, the address period further includes an intermediate period between the first portion of the address period and the second portion of the address period, and the low-level power supply voltage is switched from the second level to the first level during the intermediate period.

[0159] In one embodiment, the gate driver suppresses outputting the plurality of scan signals during the intermediate period.

[0160] In one embodiment, during the addressing period, a duty cycle of the low-level power supply voltage at the first level and the low-level power supply voltage at the second level can be adjusted between one of a plurality of duty cycles, wherein a brightness of an image displayed by the display device is based on a duty cycle selected from the plurality of duty cycles.

[0161] In one embodiment, as the duty cycle increases, the brightness of the image increases, and as the duty cycle decreases, the brightness of the image decreases.

[0162] In one embodiment, the duty cycle is selected from the plurality of duty cycles based on whether the image is a still image or a moving image.

[0163] In one embodiment, a first duty cycle of the plurality of duty cycles for the still image is associated with a greater brightness than a second duty cycle of the plurality of duty cycles for the moving image.

[0164] In one embodiment, each of the plurality of duty cycles is associated with a corresponding average brightness, and the duty cycle of the frame period is selected from the plurality of duty cycles based on the average brightness of an image to be displayed during the frame period.

[0165] In one embodiment, the size of the first display area and the size of the second display area are based on a duty cycle selected from the plurality of duty cycles.

[0166] In one embodiment, as the duty cycle increases, the size of the first display area decreases and the size of the second display area increases; as the duty cycle decreases, the size of the first display area increases and the size of the second display area decreases.

[0167] In one embodiment, a display device includes: a display panel, the display panel including a first display area and a second display area, the first display area including a plurality of first pixels, the second display area including a plurality of second pixels, each of the plurality of first pixels and the plurality of second pixels including a corresponding light-emitting element; a data driver circuit, the data driver circuit being configured to output a plurality of data voltages of an image to the plurality of first pixels and the plurality of second pixels; a gate driver, the gate driver being configured to output a plurality of scan signals to the plurality of first pixels and the plurality of second pixels; and a power supply, the power supply being configured to generate a low-level power supply voltage, the low-level power supply voltage is applied to the corresponding light-emitting element included in each pixel of the plurality of first pixels and the plurality of second pixels, and the low-level power supply voltage switches between a first level that enables the light-emitting element in each pixel to emit light and a second level that is greater than the first level and does not enable the light-emitting element in each pixel to emit light, wherein the frame period of the display device includes an addressing period, during which the plurality of data voltages and the plurality of scan signals of the image are output to the plurality of first pixels and the plurality of second pixels, and during the addressing period, the low-level power supply voltage switches from the second level to the first level, so that the light-emitting element in each pixel can emit light to display the image.

[0168] In one embodiment, the low-level power supply voltage is applied to a cathode of each of the corresponding light emitting elements.

[0169] In one embodiment, during the address period, a duty ratio of the low-level power supply voltage at the first level and the low-level power supply voltage at the second level can be adjusted between one of a plurality of duty ratios.

[0170] In one embodiment, during a first portion of the addressing period, the low-level power supply voltage is at the second level, so that none of the multiple first pixels in the first display area emits light and none of the multiple second pixels in the second display area emits light, and during a second portion of the addressing period after the first portion, the low-level power supply voltage is at the first level, so that the multiple first pixels in the first display area emit light to display a first portion of an image in the first display area, and at least a portion of the multiple second pixels in the second display area emit light to display at least a portion of a second portion of an image in the second display area.

[0171] In one embodiment, a display device includes: a display panel, the display panel including a first display area and a second display area, the first display area including a plurality of first pixels, the second display area including a plurality of second pixels, each of the plurality of first pixels and the plurality of second pixels including a corresponding light-emitting element; a data driver circuit, the data driver circuit being configured to output a plurality of data voltages of an image to the plurality of first pixels and the plurality of second pixels; a gate driver, the gate driver being configured to output a plurality of scan signals to the plurality of first pixels and the plurality of second pixels; and a power supply, the power supply being configured to generate a low-level power supply voltage, the low-level power supply voltage being applied to the corresponding light-emitting element included in each of the plurality of first pixels and the plurality of second pixels. light elements, the low-level power supply voltage switches between a first level that enables the light-emitting elements in each pixel to emit light and a second level that is greater than the first level and does not enable the light-emitting elements in each pixel to emit light, wherein the frame period of the display device includes an addressing period, during which the multiple data voltages of the image and the multiple scan signals are output to the multiple first pixels and the multiple second pixels, and during the addressing period, the low-level power supply voltage switches from the second level to the first level, wherein the display device is configured to operate in one of a plurality of modes, in which each mode has a corresponding duty ratio of the first level of the low-level power supply voltage and the second level of the low-level power supply voltage from a plurality of different duty ratios.

[0172] In one embodiment, the multiple modes include an outdoor mode having a first duty cycle of the low-level power supply voltage, a normal mode having a second duty cycle of the low-level power supply voltage, and an energy-saving mode having a third duty cycle of the low-level power supply voltage, wherein the second duty cycle is smaller than the first duty cycle of the outdoor mode, and the third duty cycle is smaller than the second duty cycle.

[0173] In one embodiment, the multiple modes include a still image mode and a moving image mode, during the still image mode, the image displayed in the frame period is a still image, and during the moving image mode, the image displayed in the frame period is a moving image, wherein the duty cycle of the still image mode is greater than the duty cycle of the moving image mode.

[0174] In one embodiment, during a first portion of the addressing period, the low-level power supply voltage is at the second level, so that none of the multiple first pixels in the first display area emits light and none of the multiple second pixels in the second display area emits light, and during a second portion of the addressing period after the first portion, the low-level power supply voltage is at the first level, so that the multiple first pixels in the first display area emit light to display a first portion of an image in the first display area, and at least a portion of the multiple second pixels in the second display area emit light to display at least a portion of a second portion of an image in the second display area.

[0175] The objects to be achieved by the present disclosure, the means for achieving the objects, and the effects of the present disclosure described above do not specifically describe the essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0176] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the following claims, and all technical concepts within their equivalent scope should be interpreted as belonging to the scope of the present disclosure.

Claims

1. A display device, comprising: A display panel, the display panel comprising a first display area and a second display area, the first display area comprising a plurality of first pixels, the second display area comprising a plurality of second pixels, each of the plurality of first pixels and the plurality of second pixels comprising a corresponding light-emitting element; a data driver circuit configured to output a plurality of data voltages of an image to the plurality of first pixels and the plurality of second pixels; a gate driver configured to output a plurality of scan signals to the plurality of first pixels and the plurality of second pixels; as well as a power supply configured to generate a low-level power supply voltage, the low-level power supply voltage being applied to a corresponding light-emitting element included in each of the plurality of first pixels and the plurality of second pixels, the low-level power supply voltage being switched between a first level enabling the light-emitting element in each pixel to emit light and a second level disabling the light-emitting element in each pixel from emitting light, The frame period of the display device includes an address period and a blank period. During the address period, the plurality of data voltages and the plurality of scan signals of the image are output to the plurality of first pixels and the plurality of second pixels. During the blank period, the plurality of data voltages and the plurality of scan signals are not output to the plurality of first pixels and the plurality of second pixels. wherein, during a first portion of the address period, the low-level power supply voltage is at the second level such that none of the plurality of first pixels in the first display area emits light and none of the plurality of second pixels in the second display area emits light, and during a second portion of the address period following the first portion, the low-level power supply voltage is at the first level such that the plurality of first pixels in the first display area emit light to display a first portion of the image and at least a portion of the plurality of second pixels in the second display area emit light to display at least a portion of a second portion of the image, wherein the plurality of first pixels are arranged as a plurality of first pixel rows in the first display area, and the plurality of second pixels are arranged as a plurality of second pixel rows in the second display area, and During the first part of the addressing period, the data voltage is sequentially charged into the multiple first pixel rows one pixel row along the shift direction of the scan pulse, and during the second part of the addressing period, the data voltage is sequentially charged into the multiple second pixel rows one pixel row along the shift direction of the scan pulse.

2. The display device according to claim 1, wherein Each of the plurality of first pixels and the plurality of second pixels includes: a driving element comprising a first electrode of the driving element, a gate of the driving element, and a second electrode of the driving element, wherein the first electrode of the driving element is connected to a first node, a first power line applies a pixel driving voltage to the first node, the gate of the driving element is connected to a second node, and the second electrode of the driving element is connected to a third node; a light emitting element including an anode and a cathode, the anode being connected to the third node, the low-level power supply voltage being applied to the cathode; a capacitor between the second node and the third node; and a first switching element, the first switching element including a first electrode of the first switching element, a gate of the first switching element, and a second electrode of the first switching element, the first electrode of the first switching element being connected to a data line, a data voltage from the plurality of data voltages being applied to the data line, a scan signal from the plurality of scan signals being applied to the gate of the first switching element, and the second electrode of the first switching element being connected to the second node.

3. The display device according to claim 2, wherein: During the first portion of the address period, while the low-level power supply voltage is at the second level, a first data voltage from the plurality of data voltages is written to the plurality of first pixels in the first display area via a first switching element included in the plurality of first pixels, and a second data voltage from the plurality of data voltages is not written to the plurality of second pixels in the second display area, and During the second portion of the address period, while the low-level power supply voltage is at the first level, the light emitting elements included in the plurality of first pixels in the first display area emit light corresponding to the first data voltage to display the first portion of the image, at least a portion of the second data voltage from the plurality of data voltages is written into a portion of the plurality of second pixels in the second display area via the first switching elements included in the plurality of second pixels, and the light emitting elements included in the portion of the plurality of second pixels emit light corresponding to the portion of the second data voltage to display the portion of the second portion of the image, wherein, during the second portion of the addressing period, the plurality of first pixel rows display the first portion of the image substantially simultaneously, and as a corresponding second data voltage is written to each second pixel row, the plurality of second pixel rows substantially display corresponding portions of the second portion of the image in the second display area.

4. The display device according to claim 1, wherein The address period further includes an intermediate period between the first portion of the address period and the second portion of the address period, and the low-level power supply voltage is switched from the second level to the first level during the intermediate period.

5. The display device according to claim 4, wherein The gate driver suppresses outputting the plurality of scan signals during the intermediate period. The display device according to claim 1 , wherein: During the address period, a duty ratio of the low-level power supply voltage at the first level and the low-level power supply voltage at the second level is adjustable between one of a plurality of duty ratios, The brightness of the image displayed by the display device is based on a duty cycle selected from the plurality of duty cycles.

7. The display device according to claim 6, wherein: As the duty cycle increases, the brightness of the image increases, and as the duty cycle decreases, the brightness of the image decreases.

8. The display device according to claim 7, wherein: A duty ratio is selected from the plurality of duty ratios based on whether the image is a still image or a moving image.

9. The display device according to claim 8, wherein A first duty cycle among the plurality of duty cycles for the still image is associated with a greater brightness than a second duty cycle among the plurality of duty cycles for the moving image.

10. The display device according to claim 6, wherein Each of the plurality of duty ratios is associated with a corresponding average brightness, and the duty ratio of the frame period is selected from the plurality of duty ratios based on the average brightness of an image to be displayed during the frame period.

11. The display device according to claim 6, wherein The size of the first display area and the size of the second display area are based on a duty ratio selected from the plurality of duty ratios.

12. The display device according to claim 11, wherein As the duty cycle increases, the size of the first display area decreases and the size of the second display area increases. As the duty cycle decreases, the size of the first display area increases and the size of the second display area decreases.

13. A display device comprising: A display panel, the display panel comprising a first display area and a second display area, the first display area comprising a plurality of first pixels, the second display area comprising a plurality of second pixels, each of the plurality of first pixels and the plurality of second pixels comprising a corresponding light-emitting element; a data driver circuit configured to output a plurality of data voltages of an image to the plurality of first pixels and the plurality of second pixels; a gate driver configured to output a plurality of scan signals to the plurality of first pixels and the plurality of second pixels; as well as a power supply configured to generate a low-level power supply voltage, the low-level power supply voltage being applied to a corresponding light-emitting element included in each of the plurality of first pixels and the plurality of second pixels, the low-level power supply voltage being switched between a first level enabling the light-emitting element in each pixel to emit light and a second level greater than the first level and disabling the light-emitting element in each pixel to emit light, wherein the frame period of the display device includes an address period, during which the plurality of data voltages of the image and the plurality of scan signals are output to the plurality of first pixels and the plurality of second pixels, and during which the low-level power supply voltage is switched from the second level to the first level, so that the light-emitting elements in the respective pixels can emit light to display the image, wherein the plurality of first pixels are arranged as a plurality of first pixel rows in the first display area, and the plurality of second pixels are arranged as a plurality of second pixel rows in the second display area, wherein, during a first portion of the address period, the low-level power supply voltage is at the second level such that none of the plurality of first pixels in the first display area emits light and none of the plurality of second pixels in the second display area emits light, and during a second portion of the address period following the first portion, the low-level power supply voltage is at the first level such that the plurality of first pixels in the first display area emit light to display a first portion of an image in the first display area, and at least a portion of the plurality of second pixels in the second display area emit light to display at least a portion of a second portion of an image in the second display area, and During the first part of the addressing period, the data voltage is sequentially charged into the multiple first pixel rows one pixel row along the shift direction of the scan pulse, and during the second part of the addressing period, the data voltage is sequentially charged into the multiple second pixel rows one pixel row along the shift direction of the scan pulse.

14. The display device according to claim 13, wherein: The low-level power supply voltage is applied to the cathode of each of the corresponding light emitting elements.

15. The display device according to claim 13, wherein During the address period, a duty ratio of the low-level power supply voltage at the first level and the low-level power supply voltage at the second level can be adjusted between one of a plurality of duty ratios.

16. A display device comprising: A display panel, the display panel comprising a first display area and a second display area, the first display area comprising a plurality of first pixels, the second display area comprising a plurality of second pixels, each of the plurality of first pixels and the plurality of second pixels comprising a corresponding light-emitting element; a data driver circuit configured to output a plurality of data voltages of an image to the plurality of first pixels and the plurality of second pixels; a gate driver configured to output a plurality of scan signals to the plurality of first pixels and the plurality of second pixels; as well as a power supply configured to generate a low-level power supply voltage, the low-level power supply voltage being applied to a corresponding light-emitting element included in each of the plurality of first pixels and the plurality of second pixels, the low-level power supply voltage being switched between a first level enabling the light-emitting element in each pixel to emit light and a second level greater than the first level and disabling the light-emitting element in each pixel to emit light, wherein the frame period of the display device includes an address period, during which the plurality of data voltages of the image and the plurality of scan signals are output to the plurality of first pixels and the plurality of second pixels, and during which the low-level power supply voltage is switched from the second level to the first level, wherein the display device is configured to operate in one of a plurality of modes, each of the plurality of modes having a corresponding duty cycle of the first level of the low-level power supply voltage and the second level of the low-level power supply voltage from a plurality of different duty cycles, wherein the plurality of first pixels are arranged as a plurality of first pixel rows in the first display area, and the plurality of second pixels are arranged as a plurality of second pixel rows in the second display area, wherein, during a first portion of the address period, the low-level power supply voltage is at the second level such that none of the plurality of first pixels in the first display area emits light and none of the plurality of second pixels in the second display area emits light, and during a second portion of the address period following the first portion, the low-level power supply voltage is at the first level such that the plurality of first pixels in the first display area emit light to display a first portion of an image in the first display area, and at least a portion of the plurality of second pixels in the second display area emit light to display at least a portion of a second portion of an image in the second display area, and During the first part of the addressing period, the data voltage is sequentially charged into the multiple first pixel rows one pixel row along the shift direction of the scan pulse, and during the second part of the addressing period, the data voltage is sequentially charged into the multiple second pixel rows one pixel row along the shift direction of the scan pulse.

17. The display device according to claim 16, wherein: The multiple modes include an outdoor mode having a first duty cycle of the low-level power supply voltage, a normal mode having a second duty cycle of the low-level power supply voltage, and an energy-saving mode having a third duty cycle of the low-level power supply voltage, wherein the second duty cycle is smaller than the first duty cycle of the outdoor mode, and the third duty cycle is smaller than the second duty cycle.

18. The display device according to claim 16, wherein: The multiple modes include a still image mode and a moving image mode, during the still image mode, the image displayed in the frame period is a still image, and during the moving image mode, the image displayed in the frame period is a moving image, wherein the duty cycle of the still image mode is greater than the duty cycle of the moving image mode.

Images