Word line driver circuitry including shared driver gates and related methods, devices, and systems

Abstract

Word line driver circuitry including shared driver gates, and related methods, devices, and systems are disclosed. A device can include a number of word line drivers, where each word line driver of the number of word line drivers includes a first transistor and a second transistor. The device can also include a number of first driver gates, where the first transistor of each word line driver has a gate coupled to a dedicated first driver gate of the number of driver gates. Further, the device can include a second driver gate coupled to a gate of each second transistor of each of the number of word line drivers.

Description

[0001] Priority Claim

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 544,219, filed December 7, 2021, entitled “WORD LINE DRIVER CIRCUITRY INCLUDING SHAREDGATES, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS,” the disclosure of which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to word line drivers. More specifically, various embodiments relate to word line driver circuit systems, word line driver layouts, and related methods, apparatus, and systems that include a shared driver gate. Background Technology

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. Many different types of memory exist, including, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low-power double data rate memory (LPDDR), phase-change memory (PCM), and flash memory.

[0005] Memory devices typically contain a number of memory cells capable of holding charges representing data bits. These memory cells are typically arranged in a memory array. Data can be written to or retrieved from memory cells by selectively activating the memory cells via associated word line drivers. Summary of the Invention

[0006] Various embodiments of this disclosure may include an apparatus comprising a plurality of word line drivers, wherein each of the plurality of word line drivers includes a first transistor and a second transistor. The apparatus may also include a plurality of first driver gates, wherein the first transistor of each word line driver includes a gate coupled to a dedicated first driver gate of the plurality of driver gates. Furthermore, the apparatus may include a second driver gate coupled to the gate of each second transistor of each of the plurality of word line drivers.

[0007] According to other embodiments of this disclosure, the apparatus may include a plurality of word lines and a word line driver chain. Each word line driver in the word line driver chain may be coupled to an associated word line among the plurality of word lines. Each word line driver in the word line driver chain may be configured to couple the associated word line to an associated main word line via a first transistor. Furthermore, each word line driver in the word line driver chain may be configured to couple the associated word line to at least one other word line among the plurality of word lines and a common negative word line voltage source via a second transistor.

[0008] One or more other embodiments of this disclosure include a method of operating a memory device. The method may include, during a first mode, transmitting a first driver signal via a first driver gate to a word line driver among a plurality of word line drivers. The method may further include, during a second mode, transmitting a second driver signal via a second driver gate to each of the plurality of word line drivers. Furthermore, the method may include, in response to the second driver signal, coupling a plurality of word lines associated with the plurality of word line drivers together and to a common voltage source.

[0009] Additional embodiments of this disclosure include an electronic system. The electronic system may include at least one input device, at least one output device, and at least one processor device operatively coupled to the input device and the output device. The electronic system may also include at least one memory device operatively coupled to the at least one processor device and including a sub-word line driver circuitry. The sub-word line driver circuitry may include a plurality of sub-word line drivers. Each sub-word line driver may include a pull-up transistor for coupling an associated word line to a main word line and a pull-down transistor for coupling the associated word line to a negative word line voltage. The sub-word line driver circuitry may further include a plurality of first driver gates, wherein each sub-word line driver is coupled to a dedicated first driver gate of the plurality of driver gates. Furthermore, the sub-word line driver circuitry may include a plurality of second driver gates, wherein more than one of the plurality of sub-word line drivers is coupled to a second driver gate of the plurality of second driver gates.

[0010] According to other embodiments, the apparatus may include a first word line driver configured to drive a first word line and a second word line driver configured to drive a second word line. The apparatus may also include a first driver gate coupled to the first word line driver and configured to transmit a first driver signal to couple the first word line to a first master word line. The apparatus may further include a second driver gate coupled to the second word line driver and configured to transmit a second driver signal to couple the second word line to a second master word line. Additionally, the apparatus may include a third driver gate coupled to each of the first and second word line drivers and configured to transmit a third driver signal to couple each of the first and second word lines to a common voltage source. Attached Figure Description

[0011] Figure 1 This is a block diagram of an example memory device according to various embodiments of the present disclosure.

[0012] Figure 2 This is another more specific block diagram of an example memory device according to various embodiments of the present disclosure.

[0013] Figure 3 Describe the word line driver layout of a conventional memory device.

[0014] Figure 4 A word line driver layout according to various embodiments of the present disclosure is depicted.

[0015] Figure 5 Examples of relationships between several word lines and driver gates according to various embodiments of the present disclosure are described.

[0016] Figure 6 Example word line driver circuit systems according to various embodiments of the present disclosure are described.

[0017] Figure 7A The circuits according to various embodiments of this disclosure are described.

[0018] Figure 7B The word line driver gaps, including even-numbered word lines and odd-numbered word lines, are depicted according to various embodiments of the present disclosure.

[0019] Figure 7C A graph depicting several signals associated with a word line driver according to various embodiments of the present disclosure.

[0020] Figure 8A Describe a conventional subword line driver array.

[0021] Figure 8B A word line driver array according to various embodiments of the present disclosure is depicted.

[0022] Figure 9 This describes a portion of a memory device including a word line driver circuitry according to various embodiments of the present disclosure.

[0023] Figure 10A Describe the word line driver layout of a conventional memory device.

[0024] Figure 10B An example layout of a word line driver according to various embodiments of the present disclosure is depicted.

[0025] Figure 11 Another example layout of a word line driver according to various embodiments of this disclosure is depicted.

[0026] Figure 12 Example word line driver circuit systems according to various embodiments of the present disclosure are described.

[0027] Figure 13 This is a flowchart of an example method for operating a memory device according to various embodiments of the present disclosure.

[0028] Figure 14 This is a simplified block diagram of a memory device according to various embodiments of the present disclosure.

[0029] Figure 15 This is a simplified block diagram of an electronic system according to various embodiments of the present disclosure. Detailed Implementation

[0030] Memory typically comprises numerous memory cells arranged in a two-dimensional array of intersecting rows and columns. Data is selectively written to or retrieved from memory cells by applying activation voltages to word lines (i.e., access lines) and bit lines (i.e., data lines). Generally, word lines activate memory cells, and bit lines provide data to or retrieve data from activated memory cells.

[0031] When memory access is needed, an activation voltage can be applied to the word line via the word line driver to enable the desired function (e.g., read or write). More specifically, when an activation voltage (e.g., a high voltage) is applied via the word line, the circuitry in the memory cell (e.g., a pass-gate transistor) allows the bit line to write data to or retrieve data from the active memory cell. When memory access is not needed, the word line driver can apply a deactivation voltage (e.g., a low voltage or ground).

[0032] In some conventional devices, a back-to-back N-channel metal-oxide-semiconductor (NMOS) subword line driver (SWD) layout requires sixteen (16) driver gates (e.g., polysilicon gates) that include individual “holding” gates (also referred to herein as “FXF gates” or “FXF holding gates”) that short each word line to a negative word line voltage (VNWL).

[0033] In the various embodiments described herein, the gate count (e.g., the number of polysilicon gates) contained in a word line driver layout (e.g., a sub-word line driver layout) can be reduced compared to conventional devices. More specifically, for example, in at least some embodiments, the various embodiments disclosed herein may contain a word line driver layout containing thirteen (13) driver gates, compared to a conventional back-to-back NMOS sub-word line driver (SWD) layout that requires sixteen (16) driver gates (e.g., polysilicon gates). More specifically, at least some “holding” gates may be shared by several word line drivers of the layout (e.g., reducing the holding gate count of the layout from eight (8) to five (5), and reducing the total gate count of the layout from sixteen (16) to thirteen (13)). In these embodiments, the holding gates may be configured to short at least some inactive word lines to each other (e.g., at a negative word line voltage VNWL). Thus, by downloading adjacent word lines, adjacent word line coupling can be reduced and may be prevented. Furthermore, according to some embodiments, the negative word line voltage (VNWL) may be supplied at the end of the word line driver group (e.g., the negative word line voltage VNWL may be coupled to the last sub-word line driver in the sub-word line driver group). In some embodiments, the negative word line voltage VNWL may be supplied in or near a layout area (e.g., a small gap) between the sub-word line driver and the sense amplifier.

[0034] More specifically, according to the various embodiments disclosed herein, a word line driver circuit (e.g., a sub-word line driver circuit (also referred to as a "local word line driver circuit")) may include a plurality of word line drivers (e.g., a plurality of sub-word line drivers (also referred to as "local word line drivers")), wherein each of the plurality of word line drivers includes a first transistor and a second transistor. Furthermore, the word line driver circuit may include a plurality of first driver gates, wherein the first transistor of each word line driver is coupled to a dedicated first driver gate of the plurality of first driver gates. Furthermore, the word line driver circuit may include a second driver gate coupled to a second transistor of each of the plurality of word line drivers. Additionally, according to some embodiments, a method of operating a memory device may include transmitting a first driver signal to a word line driver among the plurality of word line drivers via a first driver gate during a first mode (e.g., an active mode). Furthermore, the method may include transmitting a second driver signal via a second driver gate to each of a plurality of word line drivers during a second mode (e.g., an inactive mode), such that the plurality of word lines associated with the plurality of word line drivers are coupled together and coupled to a common voltage source (e.g., a negative word line voltage VNWL).

[0035] Furthermore, in at least some embodiments described more fully below, the various embodiments disclosed herein may contain, for example, seven (7) driver gates (i.e., four (4) phase gates and four (4) phase bar gates, wherein one (1) phase bar gate is shared by multiple word line drivers) compared to SWDs (e.g., even- or odd-gap NMOSSWDs) that may contain, for example, eight (8) driver gates (i.e., four (4) phase gates and four (4) phase bar gates). In these and other embodiments, the apparatus may include a first word line driver configured to drive a first word line and a second word line driver configured to drive a second word line. The apparatus may also include a first driver gate coupled to the first word line driver and configured to transmit a first driver signal to couple the first word line to a first main word line. The apparatus may further include a second driver gate coupled to the second word line driver and configured to transmit a second driver signal to couple the second word line to a second main word line. In addition, the device may include a third driver gate coupled to each of the first word line driver and the second word line driver, and configured to transmit a third driver signal to couple each of the first word line and the second word line to a common voltage source.

[0036] Although various embodiments are described herein with reference to memory devices, this disclosure is not limited thereto, and the embodiments are generally applicable to microelectronic devices that may or may not include semiconductor devices and / or memory devices. Embodiments of this disclosure will now be explained with reference to the accompanying drawings.

[0037] Figure 1 This block diagram includes examples of memory devices 100 according to various embodiments of the present disclosure. Memory device 100 may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), dual data rate DRAM (DDR SDRAM), such as DDR4 SDRAM, or synchronous graphics random access memory (SGRAM). Memory device 100, which can be integrated on a semiconductor chip, may include a memory cell array 102.

[0038] exist Figure 1 In this embodiment, the memory cell array 102 is shown to include eight memory groups BANK0-7. More or fewer groups may be included in the memory cell array 102 of other embodiments. Each memory group includes several access lines (word lines WL), several data lines (bit lines BL) and / BL, and several memory cells MC arranged at the intersections of the several word lines WL and the several bit lines BL and / BL. The selection of word lines WL may be performed by the row decoder 104, and the selection of bit lines BL and / BL may be performed by the column decoder 106. Figure 1 In one embodiment, row decoder 104 may include a corresponding row decoder for each memory group BANK0-7, and column decoder 106 may include a corresponding column decoder for each memory group BANK0-7.

[0039] Bit lines BL and / BL are coupled to the corresponding sense amplifiers SAMP. Read data from bit lines BL or / BL can be amplified by the sense amplifiers SAMP and transmitted to the read / write amplifier 160 via the complementary local data line (LIOT / B), the transmission gate (TG), and the complementary master data line (MIOT / B). Conversely, write data output from the read / write amplifier 160 can be transmitted to the sense amplifier SAMP via the complementary master data line MIOT / B, the transmission gate TG, and the complementary local data line LIOT / B, and written to the memory cell MC coupled to bit lines BL or / BL.

[0040] The memory device 100 may typically be configured to receive various inputs via various terminals (e.g., address terminal 110, command terminal 112, clock terminal 114, data terminal 116, and data mask terminal 118) (e.g., from an external controller). The memory device 100 may include additional terminals, such as power supply terminals 120 and 122.

[0041] During expected operation, one or more command signals COM received via command terminal 112 can be transmitted to command decoder 150 via command input circuitry 152. Command decoder 150 may include circuitry configured to generate various internal commands by decoding one or more command signals COM. Examples of internal commands include the active command ACT and the read / write signal R / W.

[0042] Furthermore, one or more address signals ADD received via address terminal 110 can be transmitted to address decoder 130 via address input circuit 132. Address decoder 130 can be configured to supply row address XADD to row decoder 104 and column address YADD to column decoder 106.

[0043] The activity command ACT may include a pulse signal activated in response to a command signal COM (e.g., an activity command) indicating row access. In response to the activity signal ACT, the row decoder 104 specifying the group address can be activated. Therefore, the word line WL specified by the row address XADD can be selected and activated.

[0044] The read / write signal R / W may include a pulse signal activated in response to a command signal COM (e.g., a read command or a write command) indicating column access. In response to the read / write signal R / W, the column decoder 106 may be activated, and the bit line BL specified by the column address YADD may be selected.

[0045] In response to the activity command ACT, the read signal, the row address XADD, and the column address YADD, data can be read from the memory cell MC specified by the row address XADD and the column address YADD. The read data can be output via the sense amplifier SAMP, the transmission gate TG, the read / write amplifier 160, the input / output circuit 162, and the data terminal 116. Furthermore, in response to the activity command ACT, the write signal, the row address XADD, and the column address YADD, write data can be supplied to the memory cell array 102 via the data terminal 116, the input / output circuit 162, the read / write amplifier 160, the transmission gate TG, and the sense amplifier SAMP. The write data can be written to the memory cell MC specified by the row address XADD and the column address YADD.

[0046] Clock signals CK and ICK can be received via clock terminal 114. Clock input circuit 170 can generate an internal clock signal ICLK based on clock signals CK and ICK. The internal clock signal ICLK can be transmitted to various components of memory device 100, such as command decoder 150 and internal clock generator 172. Internal clock generator 172 can generate an internal clock signal LCLK, which can be transmitted to input / output circuit 162 (e.g., for controlling the operating timing of input / output circuit 162). Furthermore, data mask terminal 118 can receive one or more data mask signals DM. When a data mask signal DM is activated, overwriting of the corresponding data can be disabled.

[0047] Figure 2 A further more specific block diagram depicts an example memory device 200 according to various embodiments of the present disclosure. The memory device 200 (which may be...) Figure 1 A portion of the memory device 100 includes a memory cell array 202 having memory cells 203 arranged side by side (e.g., Figure 1 The memory cell array 102), the row decoder 204 (e.g., Figure 1 The row decoder 104) and column decoder 206 (e.g., Figure 1 (Column decoder 106). The memory device 200 further includes a word line driver circuitry, which includes a word line driver 208 and a driver control circuitry 210. The memory device 200 also includes a bit line driver 212. The memory device 200 further includes row and column arranged word lines 214 and bit lines 216 adjacent to the memory cells 203.

[0048] It should be understood that memory arrays (e.g., Figure 2 The memory cell array 202 in the memory typically contains several memory cells arranged in rows and columns; however, for simplicity, Figure 2 Only two such memory cells are shown (i.e., memory cell 203_1 and memory cell 203_2). Similarly, it should be understood that a memory device (e.g., memory device 200) may generally contain any number of word line drivers, any number of word lines, and any number of bit lines; however, for simplicity, Figure 2 Only two word line drivers (e.g., word line driver 208_1 and word line driver 208_2), two word lines (i.e., word line 214_1 and word line 214_2), and one bit line (i.e., bit line 216) are shown.

[0049] As will be understood, each memory cell 203 includes a pass-gate transistor 218, the gate of which is connected to an associated word line 214, the drain of which is connected to a bit line 216, and the source of which is connected to an associated capacitor 220. Each word line 214 is driven by an associated word line driver 208, and each bit line 216 is driven by a bit line driver 212.

[0050] Row decoder 204 and column decoder 206 can be configured to decode address signals on address lines 222 to access memory cell 203. Data can be provided to memory cell 203 via data input path 224 and retrieved from memory cell 203 via data output path 226. Data transmitted between data input path 224 and data output path 226 can be carried on data line 228.

[0051] Each word line driver 208 may be controlled by a driver control circuitry 210, which may (e.g., from the line decoder 204) receive signals indicating which word line drivers 208 should apply an activation voltage to word line 214 and which word line drivers 208 should apply a deactivation voltage to word line 214.

[0052] According to some embodiments, in an active mode (e.g., also referred to herein as "row active mode," "active phase," or "active cycle"), driver control circuitry 210 transmits a high (e.g., logic high state) signal to word line driver 208_1, and word line driver 208_1 can apply an activation voltage to word line 214_1 (and any other word lines positively driven by word line driver 208_1). The activation voltage (e.g., supply voltage Vccp) can be provided by a voltage source 230 (also referred to herein as a "high voltage source") coupled to word line driver 208_1. The activation voltage can be applied to word line 214_1 to perform memory access functions (e.g., read or write functions) on associated memory cell 203_1. More specifically, for example, the activation voltage can activate pass-gate transistor 218_1 to enable data transfer between memory cell 203_1 and data paths 224 and 226.

[0053] In an inactive mode (also referred to herein as "standby phase," "precharge mode," or "precharge phase") (e.g., when no memory access functions are being performed), word line driver 208_1 may apply a deactivation voltage to word line 214_1. The deactivation voltage (e.g., ground voltage or a negative voltage) may be provided by a voltage source 232 (also referred to herein as a "low voltage source") coupled to word line driver 208_1. The application of the deactivation voltage causes the pass-gate transistor 218_1 to turn off, thereby preventing any memory access functions from being performed on memory cell 203_1.

[0054] Alternatively, in some embodiments, the driver control circuitry 210 may cause the word line driver 208_1 to apply an activation voltage (i.e., provided by voltage source 232) to word line 214_1. Thus, the activation voltage (e.g., ground voltage, low positive voltage, or negative voltage) activates the pass-gate transistor 218_1 (e.g., a PMOS transistor) to enable data transfer between memory cell 203_1 and data paths 224 and 226. Additionally, in some embodiments, the driver control circuitry 210 may cause the word line driver 208_1 to apply a deactivation voltage (i.e., provided by voltage source 230) to word line 214_1. Thus, the deactivation voltage (e.g., voltage Vccp) turns off the pass-gate transistor 218_1, thereby preventing any memory access functions from being performed on memory cell 203.

[0055] Figure 3 A sub-word line driver (SWD) layout 300 of a conventional memory device is depicted. Layout 300 includes back-to-back SWD layouts 302 and 304 for driving even-numbered and odd-numbered word lines. Each SWD layout 302 / 304 includes eight (8) driver gates, and SWD layout 302 includes fourteen (14) word lines (i.e., even-numbered word lines WL0, WL2, WL4, ..., WL26), and SWD layout 304 includes fourteen (14) word lines (i.e., odd-numbered word lines WL1, WL3, WL5, ..., WL27). Layout 300 also includes several main word lines (i.e., MWL0-MWL2) and several regions 306 for supplying the negative word line voltage VNWL. Furthermore, Figure 3 The driver gates FXF and FXT (i.e., eight (8) FXF driver gates and eight (8) FXT driver gates) are depicted, which can be used to transmit driver signals to the transistors of layout 300.

[0056] As will be understood, in a conventional device, two driver gates (i.e., FXF and FXT driver gates) are required to drive the word line in each gap of layout 300 (i.e., the area located between the two arrays MAT). More specifically, dedicated FXF and FXT driver gates are used to drive a single word line. However, more specifically, to turn the word line on (i.e., to drive the word line "high"), the dedicated driver gate FXT is used to pass the driver signal to the gate of the first transistor (i.e., the pull-up transistor) of the associated word line driver to couple the word line to a high voltage source. Furthermore, to turn the word line off (i.e., to drive the word line low), the dedicated driver gate FXF (also referred to herein as the "holding gate") is used to pass the driver signal to the gate of the second transistor (i.e., the pull-down transistor) of the associated word line driver to couple the word line to a low voltage source (i.e., the negative word line voltage VNWL).

[0057] Compared to conventional devices, according to various embodiments of this disclosure, a single FXF driver gate (i.e., a single hold gate) can be shared by multiple word line drivers. In other words, at least some gates (e.g., "hold gates") of a word line driver layout can be shared by multiple word line drivers (e.g., a word line driver chain (also referred to herein as a "word line driver group"). Furthermore, in these embodiments, one end of a word line driver chain (i.e., containing multiple word line drivers) can be coupled to a low voltage source (e.g., a negative word line voltage VNWL), and in response to a driver signal (i.e., transmitted via the FXF driver gate), several word lines associated with the word line driver chain can be coupled together and coupled to a common voltage source (e.g., a negative word line voltage VNWL). Therefore, the number of gates (e.g., the number of polysilicon gates) can be reduced (e.g., from sixteen (16) driver gates to thirteen (13) driver gates) compared to a conventional word line driver layout.

[0058] Figure 4 Layout 400 depicts a word line driver circuit system (e.g., a sub-word line driver (SWD) circuit system) comprising a plurality of word lines according to various embodiments of the present disclosure. Layout 400 (which may be a memory device (e.g., Figure 1 A portion of the memory device 100 includes region 402 containing fourteen (14) word lines (i.e., even-numbered word lines WL0, WL2, WL4, ..., WL26), and region 404 contains fourteen (14) word lines (i.e., odd-numbered word lines WL1, WL3, WL5, ..., WL27). Furthermore, layout 400 includes several master word lines (also referred to herein as “global word lines”) (i.e., MWL0-MWL2). Layout 400 further depicts driver gates FXF and FXT (e.g., polysilicon gates) that can be used to transmit driver signals to the word line drivers of layout 400.

[0059] and Figure 3Compared to layout 300 which includes sixteen (16) driver gates (i.e., eight (8) FXT driver gates and eight (8) FXF driver gates), layout 400 includes thirteen (13) driver gates (i.e., eight (8) FXT driver gates and five (5) FXF driver gates). More specifically, region 402 includes three FXF gates (i.e., FXFE, FXFC, and FXFA) and four FXT gates (i.e., FXT4, FXT6, FXT2, and FXT0), and region 404 includes three FXF gates (i.e., FXFB, FXFD, and FXFA) and four FXT gates (i.e., FXT1, FXT3, FXT7, and FXT5). It should be noted that gate FXFA is shared by regions 402 and 404. In other words, the driver signal transmitted via gate FXFA can be received by the word line drivers of region 402 and the word line drivers of region 404. Thus, compared to layout 300, layout 400 includes a reduced number of driver gates and thus the size of the associated memory device can be reduced.

[0060] In Figure 4 the embodiment illustrated, driver gate FXFE can be coupled to a word line driver circuit system (e.g., a pull-down NMOS transistor) for each of word line WL<4>, word line WL<12>, and word line WL<20>. Thus, in this instance, word line WL<4>, word line WL<12>, and word line WL<20> can be part of a word line driver chain, as indicated by arrow 410. According to various embodiments, at least one word line driver associated with the chain can be configured to (e.g., during an inactive mode) couple the word line chain to a voltage source (e.g., a negative word line voltage VNWL). For example, the voltage source (e.g., the negative word line voltage VNWL) can be located at at least one end of the word line driver chain that includes word line WL<4>, word line WL<12>, and word line WL<20>.

[0061] In addition, driver gate FXFC can be coupled to a word line driver circuit system (e.g., a pull-down NMOS transistor) for each of word line WL<2>, word line WL<6>, word line WL<10>, word line WL<14>, word line WL<18>, word line WL<22>, and word line WL<26>. Thus, in this instance, word line WL<2>, word line WL<6>, word line WL<10>, word line WL<14>, word line WL<18>, word line WL<22>, and word line WL<26> can be part of a word line driver chain, as indicated by arrow 412. According to various embodiments, the last word line driver in the chain can be coupled to a source voltage (e.g., the unshaded arrow 412 extending from WL<2> and near the bottom of Figure 4 can indicate the connection to the source voltage (e.g., the negative word line voltage VNWL)).

[0062] In addition, the driver gate FXFA can be coupled to a word line driver circuit system (e.g., a pull-down NMOS transistor) for each of word lines WL<0>, word lines WL<5>, word lines WL<8>, word lines WL<13>, word lines WL<16>, word lines WL<21>, and word lines WL<24>. Thus, in this example, word lines WL<0>, word lines WL<5>, word lines WL<8>, word lines WL<13>, word lines WL<16>, word lines WL<21>, and word lines WL<24> can be part of a word line driver chain, as indicated by arrow 414. According to various embodiments, the last word line driver in the chain can be coupled to a source voltage (e.g., a connection to a source voltage (e.g., negative word line voltage VNWL) as indicated by the unshaded arrow 414 extending near the bottom of WL<0> and at Figure 4 ).

[0063] In addition, the driver gate FXFD can be coupled to a word line driver circuit system (e.g., a pull-down NMOS transistor) for each of word lines WL<3>, word lines WL<7>, word lines WL<11>, word lines WL<15>, word lines WL<19>, word lines WL<23>, and word lines WL<27>. Thus, in this example, word lines WL<3>, word lines WL<7>, word lines WL<11>, word lines WL<15>, word lines WL<19>, word lines WL<23>, and word lines WL<27> can be part of a word line driver chain, as indicated by arrow 416. According to various embodiments, the last word line driver in the chain can be coupled to a source voltage (e.g., a connection to a source voltage (e.g., VNWL) as indicated by the unshaded arrow 416 extending near the bottom of WL<3> and at Figure 4 ).

[0064] Additionally, the driver gate FXFB can be coupled to a word line driver circuit system (e.g., a pull-down NMOS transistor) for each of word lines WL<1>, word lines WL<9>, word lines WL<17>, and word lines WL<25>. Thus, in this example, word lines WL<1>, word lines WL<9>, word lines WL<17>, and word lines WL<25> can be part of a word line driver chain, as indicated by arrow 418. According to various embodiments, at least one word line driver associated with the chain can be configured to couple the word line chain to a source voltage (e.g., negative word line voltage VNWL). For example, a voltage source (e.g., negative word line voltage VNWL) can be located at at least one end of the word line driver chain that includes word lines WL<1>, word lines WL<9>, word lines WL<17>, and word lines WL<25>.

[0065] According to some embodiments, during the intended operation of layout 400, each of the driver gates FXFA, FXFB, FXFC, FXFD, and FXFE can be high (e.g., at voltage VCC), except when the adjacent FXT gate is high (e.g., at voltage VCCP2). This ensures that, at least in some cases, each word line is shunted to each other. Furthermore, according to at least some embodiments, with Figure 3 Compared to layout 300, layout 400 may not include the edges of layout 400. Figure 4 The negative word line voltage VNWL is connected at the left and right vertical edges (in the layout), and therefore, the active area at one or more of the edges may not be needed in layout 400. Therefore, the size of layout 400 can be smaller than that of conventional layouts such as layout 300.

[0066] It should be noted that, although Figure 4 The word line driver chains shown herein contain a specific number of word line drivers, but this disclosure is not limited thereto, and each word line driver chain of the layout may contain any number of word line drivers. Furthermore, according to some embodiments, layout 400 may include one or more active regions adjacent to the word line driver chains (e.g., below the word line driver chains (i.e., into the page)). More specifically, for example, the active regions may be located adjacent to one or more ends of one or more of the arrows (e.g., arrows 410, 412, 414, 416, and / or 418) of the word line driver chains (e.g., below the ends (i.e., into the page)).

[0067] Figure 5 Figure 500 illustrates an example relationship between a word line (depicted as an embedded word line (BWL) (e.g., as part of an array)) and an FXF driver gate. Figure 5 As shown, the embedded word lines BWL0, BWL8, BWL16, and BWL24 are associated with the driver gate FXFA (i.e., BWL0, BWL8, BWL16, and BWL24 span...). Figure 5The page in the code is aligned with the driver gate FXFA. Therefore, in this example, embedded word lines BWL0, BWL8, BWL16, and BWL24 are part of the word line driver chain, and each of the embedded word lines BWL0, BWL8, BWL16, and BWL24 can be coupled together and coupled to a common source voltage in response to a high signal transmitted via the driver gate FXFA. Furthermore, embedded word lines BWL1, BWL9, BWL17, and BWL25 are associated with the driver gate FXFB (i.e., BWL1, BWL9, BWL17, and BWL25 are aligned with the driver gate FXFB across the page in the X direction). Therefore, in this example, the embedded word lines BWL1, BWL9, BWL17, and BWL25 are part of the word line driver chain, and each of the embedded word lines BWL1, BWL9, BWL17, and BWL25 can be coupled together and coupled to a common source voltage in response to a high signal transmitted via the driver gate FXFB.

[0068] Furthermore, the embedded word lines BWL2, BWL6, BWL10, BWL14, BWL18, BWL22, and BWL26 are associated with the driver gate FXFC (i.e., BWL2, BWL6, BWL10, BWL14, BWL18, BWL22, and BWL26 are aligned with the driver gate FXFC across the page in the X direction). Therefore, in this example, the embedded word lines BWL2, BWL6, BWL10, BWL14, BWL18, BWL22, and BWL26 are part of the word line driver chain, and each of the embedded word lines BWL2, BWL6, BWL10, BWL14, BWL18, BWL22, and BWL26 can be coupled together and coupled to a common source voltage in response to a high signal transmitted via the driver gate FXFC. Furthermore, the embedded word lines BWL3, BWL7, BWL11, BWL15, BWL19, BWL23, and BWL27 are associated with the driver gate FXFD (i.e., BWL3, BWL7, BWL11, BWL15, BWL19, BWL23, and BWL27 are aligned with the driver gate FXFD across the page in the X direction). Therefore, in this example, the embedded word lines BWL3, BWL7, BWL11, BWL15, BWL19, BWL23, and BWL27 are part of the word line driver chain, and each of the embedded word lines BWL3, BWL7, BWL11, BWL15, BWL19, BWL23, and BWL27 can be coupled together and coupled to a common source voltage in response to a high signal transmitted via the driver gate FXFD.

[0069] Additionally, embedded word lines BWL4, BWL12, and BWL20 are associated with the driver signal FXFE (i.e., BWL4, BWL12, and BWL20 are aligned with the driver signal FXFE across the page in the X direction). Therefore, in this example, embedded word lines BWL4, BWL12, and BWL20 are part of the word line driver chain, and each of the embedded word lines BWL4, BWL12, and BWL20 can be coupled together and coupled to a common source voltage in response to a high signal transmitted via the driver gate FXFE.

[0070] Figure 500 further depicts the signal combination for each word line (i.e., according to the signal combination in...). Figure 5 (Alignment in the Y direction). More specifically, for example, the embedded word line BWL0 is configured to be coupled to the main word line MWL0 via a pull-up NMOS transistor (i.e., the gate of the pull-up NMOS transistor is coupled to the gate FXT0); and coupled to VNWL via a pull-down NMOS transistor (i.e., the gate of the pull-down NMOS transistor is coupled to the gate FXFA). As another example, the embedded word line BWL9 is configured to be coupled to the main word line MWL1 via a pull-up NMOS transistor (i.e., the gate of the pull-up NMOS transistor is coupled to the gate FXT1); and coupled to VNWL via a pull-down NMOS transistor (i.e., the gate of the pull-down NMOS transistor is coupled to the gate FXFB). As another example, the embedded word line BWL19 is configured to be coupled to the main word line MWL2 via a pull-up NMOS transistor (i.e., the gate of the pull-up NMOS transistor is coupled to the gate FXT3); and coupled to VNWL via a pull-down NMOS transistor (i.e., the gate of the pull-down NMOS transistor is coupled to the gate FXFD). As another example, the embedded word line BWL25 is configured to be coupled to the main word line MWL3 via a pull-up NMOS transistor (i.e., the gate of the pull-up NMOS transistor is coupled to the gate FXT1); and coupled to VNWL via a pull-down NMOS transistor (i.e., the gate of the pull-down NMOS transistor is coupled to the gate FXFB).

[0071] In some conventional devices, sixteen (16) sub-word line drivers are required for sixteen (16) interleaved word lines, comprising sixteen (16) PMOS pull-up transistors, sixteen (16) NMOS pull-down transistors, and eight (8) NMOS word line-to-word line holders. In some other conventional devices, sixteen (16) sub-word line drivers are required for sixteen (16) “spaced” word lines, comprising sixteen (16) NMOS pull-up transistors and sixteen (16) NMOS pull-down transistors. In contrast, according to various embodiments of this disclosure, sixteen (16) sub-word line drivers comprising sixteen (16) NMOS pull-up transistors and eight (8) NMOS pull-down transistors can be used for sixteen (16) “spaced” word lines.

[0072] Figure 6 A word line driver circuit system 600 according to various embodiments of the present disclosure is depicted. The word line driver circuit system 600, which may include an SWD circuit system, comprises a plurality of transistors (i.e., transistors M1-M16), each of which may include, for example, an NMOS transistor. Furthermore, Figure 6 Depicting letter lines WL, main letter lines MWL (e.g., MWL0, MWL1, MWL2, or MWL3 (see also...) Figure 5 ), driver gate FXF and FXT and negative word line voltage (VNWL).

[0073] like Figure 6 As shown, in portion 602 of the SWD circuit system 600, the first terminal (e.g., source or drain) of transistor M1 is coupled to the main word line MWL, and the gate of transistor M1 is coupled to the driver gate FXT. <4> And the second terminal (e.g., source or drain) of transistor M1 is coupled to word line WL <4> Furthermore, the first terminal (e.g., source or drain) of transistor M2 is coupled to word line WL. <4> The gate of transistor M2 is coupled to the driver gate FXFE, and the second terminal of transistor M2 (e.g., source or drain) is coupled to the negative word line voltage VNWL. As will be understood, in order to make the word line WL... <4> On (i.e., high), driver gate FXT <4> When the word line WL is high (e.g., at Vccp+Vt), the driver gate FXFE is low (e.g., at VNWL), and the main word line MWL is high (e.g., at Vccp). Furthermore, to make the word line WL... <4> Disconnected (i.e., low), driver gate FXT <4> The driver gate FXFE is low (e.g., at zero volts and / or VNWL), the main word line MWL is high (e.g., at 1 volt), and the main word line MWL may be at, for example, Vccp or low.

[0074] In another part 604 of the SWD circuit system 600, the first terminal (e.g., source or drain) of transistor M3 is coupled to the main word line MWL, and the gate of transistor M3 is coupled to the driver gate FXT. <6> And the second terminal (e.g., source or drain) of transistor M3 is coupled to word line WL <6> Furthermore, the first terminal (e.g., source or drain) of transistor M4 is coupled to word line WL. <6> The gate of transistor M4 is coupled to the driver gate FXFC, and the second terminal (e.g., source or drain) of transistor M4 is coupled to the word line WL. <2> Furthermore, the first terminal of transistor M5 (e.g., source or drain) is coupled to the main word line MWL, and the gate of transistor M5 is coupled to the driver gate FXT. <2> And the second terminal (e.g., source or drain) of transistor M5 is coupled to word line WL <2> Furthermore, the first terminal (e.g., source or drain) of transistor M6 is coupled to word line WL. <2> The gate of transistor M6 is coupled to the driver gate FXFC, and the second terminal of transistor M6 (e.g., the source or drain) is coupled to the negative word line voltage VNWL.

[0075] In another part 606 of the SWD circuit system 600, the first terminal (e.g., source or drain) of transistor M7 is coupled to the main word line MWL, and the gate of transistor M7 is coupled to the driver gate FXT. <5> And the second terminal (e.g., source or drain) of transistor M5 is coupled to word line WL <5> Furthermore, the first terminal (e.g., source or drain) of transistor M8 is coupled to word line WL. <5> The gate of transistor M8 is coupled to the driver gate FXFA, and the second terminal of transistor M8 (e.g., source or drain) is coupled to the word line WL. <0> Furthermore, the first terminal of transistor M9 (e.g., source or drain) is coupled to the main word line MWL, and the gate of transistor M9 is coupled to the driver gate FXT. <0> And the second terminal (e.g., source or drain) of transistor M9 is coupled to word line WL <0> Furthermore, the first terminal (e.g., source or drain) of transistor M10 is coupled to word line WL. <0> The gate of transistor M10 is coupled to the driver gate FXFA, and the second terminal of transistor M10 (e.g., the source or drain) is coupled to the negative word line voltage VNWL.

[0076] In another part 608 of the SWD circuit system 600, the first terminal (e.g., source or drain) of transistor M11 is coupled to the main word line MWL, and the gate of transistor M11 is coupled to the driver gate FXT. <7> And the second terminal (e.g., source or drain) of transistor M11 is coupled to word line WL <7> Furthermore, the first terminal (e.g., source or drain) of transistor M12 is coupled to word line WL. <7> The gate of transistor M12 is coupled to the driver gate FXFD, and the second terminal of transistor M12 (e.g., source or drain) is coupled to the word line WL. <3> Furthermore, the first terminal of transistor M13 (e.g., source or drain) is coupled to the main word line MWL, and the gate of transistor M13 is coupled to the driver gate FXT. <3> And the second terminal (e.g., source or drain) of transistor M13 is coupled to word line WL <3> Furthermore, the first terminal (e.g., source or drain) of transistor M14 is coupled to word line WL. <3> The gate of transistor M14 is coupled to the driver gate FXFD, and the second terminal of transistor M14 (e.g., the source or drain) is coupled to the negative word line voltage VNWL.

[0077] Additionally, in another part 610 of the SWD circuit system 600, the first terminal (e.g., source or drain) of transistor M15 is coupled to the main word line MWL, and the gate of transistor M15 is coupled to the driver gate FXT. <1> And the second terminal (e.g., source or drain) of transistor M15 is coupled to word line WL <1> Furthermore, the first terminal (e.g., source or drain) of transistor M16 is coupled to word line WL. <1> The gate of transistor M16 is coupled to the driver gate FXFB, and the second terminal of transistor M16 (e.g., source or drain) is coupled to the negative word line voltage VNWL.

[0078] According to an expected operation, if the driver gate FXT <2> If the value is high, then the driver gate FXFC can be low, and the word line WL <2> It can be coupled to its associated main word line MWL. Furthermore, if the driver gate FXT <2> and FXT <6> If the value is low, then the driver gate FXFC can be high, and the word line WL <2> The character line <6> They can be coupled together and coupled to the negative word line voltage VNWL. Similarly, as another example, if the driver gate FXT <7> If the value is high, then the driver gate FXFD can be low, and the word line WL can be high. <7> It can be coupled to its associated main word line MWL. Furthermore, if the driver gate FXT <7> and FXT <3> If the value is low, then the driver gate FXFD can be high, and the word line WL can be low. <7> The character line <3> They can be coupled together and coupled to the negative word line voltage VNWL.

[0079] Figure 7AThis describes a circuit 700 according to various embodiments of the present disclosure. Circuit 700 includes a plurality of transistors, a plurality of word lines 0-15, driver gates FXT and FXF, and main word lines MWLO and MWL1. Similar to... Figure 4 In the embodiments shown, the word line driver circuitry (i.e., pull-down transistors) associated with each of word lines 4 and 12 shares an FXF gate (i.e., driver gate FXFE in this example). Furthermore, the word line driver circuitry (i.e., pull-down transistors) associated with each of word lines 2, 6, 10, and 14 shares an FXF gate (i.e., driver gate FXFC in this example). Additionally, the word line driver circuitry (i.e., pull-down transistors) associated with each of word lines 0, 5, 8, and 13 shares an FXF gate (i.e., driver gate FXFA in this example). Furthermore, the word line driver circuitry (i.e., pull-down transistors) associated with each of word lines 3, 7, 11, and 15 shares an FXF gate (i.e., driver gate FXFD in this example). Additionally, the word line driver circuitry (i.e., pull-down transistors) associated with each of word lines 1 and 19 shares an FXF gate (i.e., driver gate FXFB in this example).

[0080] Figure 7B The word line driver (e.g., sub-word line driver) gap 700 is described according to various embodiments, comprising both even-numbered word lines (WL0-WL14) and odd-numbered word lines (WL1-WL15). Furthermore, Figure 7C A graph 780 depicts several signals associated with a word line driver according to various embodiments of the present disclosure. Specifically, graph 780 depicts the driver gate FXT, driver gate FXF, and main word line signal MWL. Figure 7C Table 790 further illustrates the voltage states of the driver gate FXT, driver gate FXF, main word line signal MWL, and word line WL.

[0081] As shown in graph 780 and table 790, in order to turn on the word line, the associated driver gate FXT (i.e., the gate coupled to the associated pull-up transistor) can be switched from low (e.g., 0 volts) to high (e.g., voltage Vccp2 (e.g., 4.2 volts)), the associated driver gate FXF (i.e., the gate coupled to the associated pull-down transistor) can be switched from high (e.g., medium voltage VEQ (e.g., 1 volt)) to low (e.g., 0 volts), and the associated main word line signal MWL can be switched from low (e.g., 0 volts) to high (e.g., voltage VCCP (e.g., 3.2 volts)). To disconnect the word line, the associated driver gate FXT (i.e., the gate coupled to the associated pull-up transistor) can be switched from high (e.g., voltage Vccp2 (e.g., 4.2 volts)) to low (e.g., 0 volts), the associated driver gate FXF (i.e., the gate coupled to the associated pull-down transistor) can be switched from low (e.g., 0 volts) to high (e.g., medium voltage VEQ (e.g., 1 volt)), and the associated main word line signal MWL can be switched from high (e.g., voltage VCCP (e.g., 3.2 volts)) to low (e.g., 0 volts).

[0082] Furthermore, in a non-limiting example shown in Table 790, if for the associated word line driver, the main word line signal MWL and the driver signal FXT are low (e.g., at 0 volts) and the driver gate FXF is high (e.g., at 1 volt), then the associated word line WL can be at a negative word line voltage VNWL (e.g., 0.2 volts). Additionally, if for the associated word line driver, the main word line signal MWL and the driver gate FXF are low (e.g., at 0 volts) and the driver gate FXT is high (e.g., at 4.2 volts), then the associated word line WL can be low (e.g., at 0 volts). Furthermore, if for the associated word line driver, the main word line signal MWL is at 3.2 volts, the driver gate FXT is at 4.2 volts, and the driver gate FXF is at 0 volts, then the associated word line WL can be at 3.2 volts. Additionally, if for the associated word line driver, the main word line signal MWL is at 3.2 volts, the driver gate FXT is at 0 volts, and the driver gate FXF is at 1 volt, then the associated word line WL can be at 0.2 volts.

[0083] Figure 8A A conventional interleaved SWD array 802 comprising several cores is depicted, wherein each gap 803 between the cores comprises an even number of SWD drivers 810 or an odd number of SWD drivers 812. Figure 8B A pitched word line driver array (e.g., SWD) array 804 comprising a plurality of cores is depicted according to various embodiments of the present disclosure. In the pitched array 804, each gap 805 of the cores comprises an even number of drivers 810 and an odd number of drivers 812. Therefore, compared to an interleaved SWD array 802, in Figure 8BIn the embodiment shown, even-number lines and odd-number lines can be driven by a single gap 805, and thus the number of memory bits driven via a single gap can be increased.

[0084] Figure 9 This describes a portion 900 of a memory device including an interface region 902 and a sub-word line driver circuitry 904, according to various embodiments of the present disclosure. For example... Figure 9 As depicted, the gap 805 of the core 908 may contain a portion 900 of the memory device, wherein the sub-word line driver circuitry 904 is configured such that even and odd number lines can be driven by a single gap 805. According to various embodiments, dimension D1 (e.g., width) may be substantially 0.808 micrometers, dimension D2 (e.g., width) may be substantially 2.3 micrometers, and dimension D3 (e.g., width) may be substantially 0.808 micrometers. In contrast, the dimension D2 (i.e., between BWL interfaces) of some conventional memory devices (i.e., containing sixteen (16) gate NMOS SWDs) may be substantially 3.01 micrometers.

[0085] Figure 10A A SWD layout 1000 of a conventional memory device is depicted. Layout 1000 includes driver gates (e.g., polysilicon gates) arranged horizontally. In contrast, Figure 10B The SWD layout 1050 depicted, which may be an NMOS SWD, may include an active region rotated relative to the active region of the SWD layout 1000, and thus the driver gates (e.g., polysilicon gates) of the layout 1050 (i.e., driver gates FXF0, FXT0, FXF2, FXT2, FXF4, FXT4, FXF6, and FXT6) are vertically configured. The layout 1050 further includes a voltage source (e.g., a negative word line voltage VNWL), word lines WL, and main word lines MWL (i.e., main word lines MWL0 and MWL1). As will be understood, the SWD layout 1050 is in an even-odd configuration (i.e., even-numbered word lines are positioned in one SWD gap, and odd-numbered word lines are positioned in another different SWD gap) (e.g., for driving 1k word lines).

[0086] As will be understood, the size of an NMOS SWD can be reduced relative to an SWD containing a PMOS device. Furthermore, as mentioned above at least regarding... Figures 4 to 9 As described, the size of the SWD can be further reduced by using a shared driver gate.

[0087] As will be understood, due to the current-pitch cell process, the area of ​​the memory device's supporting circuitry does not shrink at the same rate as the array area shrinks. In other words, the memory device array area and supporting circuitry are scaled asymmetrically, which negatively impacts array efficiency (i.e., a metric typically used to evaluate at least some memory devices, such as DRAM devices).

[0088] According to various embodiments of this disclosure, the size of SWD can be reduced by removing the driver gate and the active region node of the negative word line voltage VNWL (e.g., with...). Figure 10B Compared to the SWD layout 1050). Figure 11 Example layout 1100 depicts a word line driver circuit system (e.g., an SWD circuit system) comprising several word lines according to various embodiments of the present disclosure. Layout 1100 (which may be a memory device (e.g., Figure 1 A portion of the memory device 100 includes driver gates FXF and FXT (e.g., polysilicon gates). More specifically, layout 1100 includes driver gates FXT0, FXT2, FXT4, FXT6, FXFA, FXFC, and FXFE. Layout 1100 further includes voltage sources (e.g., negative word line voltage VNWL), word lines WL, and master word lines MWL (i.e., master word lines MWL0 and MWL1). As will be understood, SWD layout 1100 is an even / odd configuration (i.e., even-numbered lines are positioned in one SWD gap, and odd-numbered lines are positioned in another different SWD gap). In other words, according to... Figure 11 The layout of the embodiments described herein can be configured to drive even-number lines and odd-number lines in separate SWD gaps (e.g., for driving 1k word lines), wherein Figure 4 The layout 400 can drive both even and odd number lines in a single SWD gap (e.g., for driving 2k word lines).

[0089] exist Figure 11 In the embodiment shown, a single FXF driver gate (i.e., driver gate FXFC) is at least partially located between the two FXT driver gates and is shared by word lines of internal phase. More specifically, with Figure 10BCompared to layout 1050, where each phase includes a dedicated phase bar (i.e., driver gate FXT0 is associated with dedicated driver gate FXF0, driver gate FXT2 with dedicated driver gate FXF2, driver gate FXT4 with dedicated driver gate FXF4, and driver gate FXT6 with dedicated driver gate FXF6), driver gate FXFC is at least partially located between driver gate FXT0 and driver gate FXT4, and driver gate FXFC is shared by word lines associated with driver gates FXT0 and FXT4. Furthermore, in these embodiments, active regions adjacent to driver gate FXFC (e.g., one active region on each side of driver gate FXFC (e.g., left and right sides)) are staggered, such that word lines, for example, coupled to inner phases, can be connected in a chain (e.g., a serpentine chain) 1102 in response to a driver signal transmitted via driver gate FXFC. According to some embodiments, each word line in chain 1102 can be coupled to a common voltage source (e.g., a negative word line voltage VNWL) in response to a driver signal transmitted via driver gate FXFC. More specifically, for example, in response to a driver signal transmitted via the driver gate FXFC, each word line in chain 1102 (i.e., word line WL0, word line WL4, word line WL8, word line WL12, word line WL16, etc.) may be coupled to the negative word line voltage VNWL node at a first end (e.g., at the top) of the SWD gap, and coupled to the negative word line voltage VNWL node at a second end (e.g., at the bottom) of the SWD gap. Figure 10B Compared to layout 1050, which contains eight (8) driver gates, layout 1100 contains seven (7) driver gates.

[0090] Figure 12 A word line driver circuit system 1200 according to various embodiments of the present disclosure is depicted. The word line driver circuit system 1200, which may include an SWD circuit system, comprises a plurality of transistors (i.e., transistors M21-M28), each of which may include, for example, an NMOS transistor. Furthermore, Figure 12 Depicting the letter line WL, main letter line MWL (e.g., Figure 11 The word line driver circuitry includes MWL0 or MWL1, driver gates FXF and FXT, and a voltage source (e.g., negative word line voltage VNWL). For example, the word line driver circuitry 1200 may be... Figure 11 The circuit layout of 1100 is shown in the diagram.

[0091] like Figure 12As shown, in portion 1202 of the SWD circuit system 1200, the first terminal (e.g., source or drain) of transistor M21 is coupled to the main word line MWL, and the gate of transistor M21 is coupled to the driver gate FXT. <2> And the second terminal (e.g., source or drain) of transistor M21 is coupled to word line WL <2> Furthermore, the first terminal (e.g., source or drain) of transistor M22 is coupled to word line WL. <2> The gate of transistor M22 is coupled to the driver gate FXFA, and the second terminal of transistor M22 (e.g., source or drain) is coupled to the negative word line voltage VNWL. As will be understood, in order to make the word line WL... <2> On (i.e., high), driver gate FXT <2> When the word line WL is high (e.g., at Vccp+Vt), the driver gate FXFA is low (e.g., at or below VNWL), and the main word line MWL is high (e.g., at Vccp). Furthermore, to make the word line WL... <2> Disconnected (i.e., low), driver gate FXT <2> When the voltage is low (e.g., at zero volts and / or at or below VNWL), the driver gate FXFA is high (e.g., about 2 volts), and the main word line MWL may be at, for example, Vccp or low.

[0092] In another part 1204 of the SWD circuit system 1200, the first terminal (e.g., source or drain) of transistor M23 is coupled to the main word line MWL, and the gate of transistor M23 is coupled to the driver gate FXT. <4> And the second terminal (e.g., source or drain) of transistor M23 is coupled to word line WL <4> Furthermore, the first terminal (e.g., source or drain) of transistor M24 is coupled to word line WL. <4> The gate of transistor M24 is coupled to the driver gate FXFC, and the second terminal of transistor M24 (e.g., source or drain) is coupled to the word line WL. <0> Furthermore, the first terminal of transistor M25 (e.g., source or drain) is coupled to the main word line MWL, and the gate of transistor M25 is coupled to the driver gate FXT. <0> And the second terminal (e.g., source or drain) of transistor M25 is coupled to word line WL <0> Furthermore, the first terminal (e.g., source or drain) of transistor M26 is coupled to word line WL. <0> The gate of transistor M26 is coupled to the driver gate FXFC, and the second terminal of transistor M26 (e.g., source or drain) is coupled to the negative word line voltage VNWL.

[0093] In another part 1206 of the SWD circuit system 1200, the first terminal (e.g., source or drain) of transistor M27 is coupled to the main word line MWL, and the gate of transistor M27 is coupled to the driver gate FXT. <6> And the second terminal (e.g., source or drain) of transistor M25 is coupled to word line WL <6> Furthermore, the first terminal (e.g., source or drain) of transistor M28 is coupled to word line WL. <6> The gate of transistor M28 is coupled to the driver gate FXFE, and the second terminal of transistor M28 (e.g., the source or drain) is coupled to the negative word line voltage VNWL.

[0094] refer to Figure 11 and / or Figure 12 According to various embodiments, if the driver gate FXFC is on (i.e., when the word lines in chain 1102 are not activated), then the word lines coupled in chain 1102 can be coupled to the negative word line voltage VNWL at, for example, the top and bottom of the associated SWD gap. Word lines near the center of the SWD gap can be considered the worst-case scenario (i.e., because word lines near the center of the SWD gap are located furthest from the VNWL node). However, all word lines coupled in chain 1102 can benefit from an RC load (e.g., a relatively large RC load), which can mitigate undesirable coupling (e.g., even in the worst-case scenario).

[0095] In at least some embodiments, if the driver gate FXFC is disconnected (i.e., when a word line in chain 1102 is activated), then other word lines coupled in chain 1102 can float. Based on the word line coupling method, the floating word lines can be shielded by several (e.g., three (3)) word lines connected to the node of the strong negative word line voltage VWNL.

[0096] Furthermore, according to some embodiments, the driver gate FXFC can be switched when either of the two internal phases (i.e., driver gate FXT4 and driver gate FXT0) is active. In at least these embodiments, the number of FXF signals can be reduced (e.g., by one (1) signal at a time), and the number of FXF drivers in the associated row decoder can be reduced (e.g., by one (1) driver at a time).

[0097] Figure 13 This is a flowchart of an example method 1300 for operating a memory device according to various embodiments of the present disclosure. Method 1300 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 1300 may be performed by a circuit, device, or system, for example... Figure 1 Memory device 100 Figure 2 Memory device 200, Figure 4 Sub-word line driver circuit system layout 400 Figure 6Sub-word line driver circuit system 600 Figure 7A 700 circuit system Figure 8B Sub-word line driver array 804, Figure 9 Part 900 of the memory device Figure 11 Layout 1100 Figure 12 Word line driver circuit system 1200 Figure 14 The memory device 1400 and / or Figure 15 The electronic system 1500 or another device or system. Although described as discrete blocks, the individual blocks may be divided into additional blocks, combined into fewer blocks, or excluded, depending on the desired implementation.

[0098] Method 1300 may begin at block 1302, wherein during a first mode, a first driver signal may be transmitted via a first driver gate to a word line driver among a plurality of word line drivers, and method 1300 may proceed to block 1304. For example, during an active mode, a high signal may be transmitted via an FXT driver gate to the gate of a pull-up transistor of a word line driver (i.e., coupling the associated word line to the main word line).

[0099] At block 1304, during the second mode, a second driver signal can be transmitted via the second driver gate to each of the plurality of word line drivers, and method 1300 can proceed to block 1306. For example, during the inactive mode, a second driver signal can be transmitted via the FXF driver gate (e.g., Figure 4 , Figure 5 , Figure 6 , Figure 11 and / or Figure 12 The FXFA, FXFB, FXFC, FXFD, or FXFE in the code transmits the high driver signal to the gate of the pull-down transistor in each of the several word line drivers.

[0100] At block 1306, in response to a second driver signal, several word lines associated with several word line drivers can be coupled together and coupled to a common voltage source. For example, refer to... Figure 4 In response to a high signal transmitted via the driver gate FXF, word lines WLO, WL5, WL8, WL13, WL16, WL21, and WL24 can be coupled together and coupled to the negative word line voltage VNWL. As another example, see reference... Figure 11 In response to a high signal transmitted via the driver gate FXFC, word lines WL0, WL4, WL8, WL12 and WL16 can be coupled together and coupled to the negative word line voltage VNWL.

[0101] Modifications, additions, or omissions may be made to method 1300 without departing from the scope of this disclosure. For example, the operations of method 1300 may be performed in a different order. Furthermore, the operations and actions outlined are provided only as examples, and some of these operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions without departing from the essence of the disclosed embodiments.

[0102] A memory device is also disclosed. According to various embodiments, the memory device may include one or more memory cell arrays, such as memory cell array 102 (see...). Figure 1 An array of one or more memory cells may contain several memory cells.

[0103] Figure 14 This is a simplified block diagram of a memory device 1400 implemented according to one or more embodiments described herein. The memory device 1400, which may include, for example, semiconductor devices, includes a memory array 1402 and a controller 1404. The memory array 1402, which may include several memory groups, may include several memory cells.

[0104] Controller 1404 may be operably coupled to memory array 1402 to read, write, or refresh any or all memory cells within memory array 1402. Controller 1404 may be configured to perform one or more embodiments disclosed herein. For example, in some embodiments, controller 1404 may include at least a portion of the following, such as: Figure 2 The driver control circuit system 210 Figure 2 Word line driver 208 Figure 4 Word line driver circuit system layout 400 Figure 6 Word line driver circuit system 600 Figure 7A 700 circuit system Figure 8B 804 word line driver array Figure 11 Layout 1100 and / or Figure 12 The word line driver circuit system 1200.

[0105] A system is also disclosed. According to various embodiments, the system may include a memory device comprising a plurality of memory banks, each memory bank having an array of memory cells. Each memory cell may include an access transistor and a memory element operatively coupled to the access transistor.

[0106] Figure 15This is a simplified block diagram of an electronic system 1500 implemented according to one or more embodiments described herein. The electronic system 1500 includes at least one input device 1502, which may include, for example, a keyboard, mouse, or touchscreen. The electronic system 1500 further includes at least one output device 1504, such as a monitor, touchscreen, or speaker. The input device 1502 and the output device 1504 are not necessarily separable from each other. The electronic system 1500 further includes a storage device 1506. The input device 1502, output device 1504, and storage device 1506 may be coupled to a processor 1508. The electronic system 1500 further includes a memory device 1510 coupled to the processor 1508. [The last sentence appears to be incomplete and possibly refers to a different component.] Figure 14 The memory device 1510 of the memory device 1400 may include an array of memory cells. The electronic system 1500 may include, for example, computing, processing, industrial, or consumer products. For example, without limitation, the electronic system 1500 may include a personal computer or computer hardware component, a server or other networking hardware component, a database engine, an intrusion prevention system, a handheld device, a tablet computer, an e-notebook, a camera, a telephone, a music player, a wireless device, a display, a chipset, a game, a vehicle, or other known systems.

[0107] Various embodiments of this disclosure may include an apparatus comprising a plurality of word line drivers, wherein each of the plurality of word line drivers includes a first transistor and a second transistor. The apparatus may also include a plurality of first driver gates, wherein the first transistor of each word line driver includes a gate coupled to a dedicated first driver gate of the plurality of driver gates. Furthermore, the apparatus may include a second driver gate coupled to the gate of each second transistor of each of the plurality of word line drivers.

[0108] According to other embodiments of this disclosure, the apparatus may include a plurality of word lines and a word line driver chain. Each word line driver in the word line driver chain may be coupled to an associated word line among the plurality of word lines. Each word line driver in the word line driver chain may be configured to couple the associated word line to an associated main word line via a first transistor. Furthermore, each word line driver in the word line driver chain may be configured to couple the associated word line to at least one other word line among the plurality of word lines and a common negative word line voltage source via a second transistor.

[0109] One or more other embodiments of this disclosure include a method of operating a memory device. The method may include, during a first mode, transmitting a first driver signal via a first driver gate to a word line driver among a plurality of word line drivers. The method may further include, during a second mode, transmitting a second driver signal via a second driver gate to each of the plurality of word line drivers. Furthermore, the method may include, in response to the second driver signal, coupling a plurality of word lines associated with the plurality of word line drivers together and to a common voltage source.

[0110] Additional embodiments of this disclosure include an electronic system. The electronic system may include at least one input device, at least one output device, and at least one processor device operatively coupled to the input device and the output device. The electronic system may also include at least one memory device operatively coupled to the at least one processor device and including a sub-word line driver circuitry. The sub-word line driver circuitry may include a plurality of sub-word line drivers. Each sub-word line driver may include a pull-up transistor for coupling an associated word line to a main word line and a pull-down transistor for coupling the associated word line to a negative word line voltage. The sub-word line driver circuitry may further include a plurality of first driver gates, wherein each sub-word line driver is coupled to a dedicated first driver gate of the plurality of driver gates. Furthermore, the sub-word line driver circuitry may include a plurality of second driver gates, wherein more than one of the plurality of sub-word line drivers is coupled to a second driver gate of the plurality of second driver gates.

[0111] According to other embodiments, the apparatus may include a first word line driver configured to drive a first word line and a second word line driver configured to drive a second word line. The apparatus may also include a first driver gate coupled to the first word line driver and configured to transmit a first driver signal to couple the first word line to a first master word line. The apparatus may further include a second driver gate coupled to the second word line driver and configured to transmit a second driver signal to couple the second word line to a second master word line. Additionally, the apparatus may include a third driver gate coupled to each of the first and second word line drivers and configured to transmit a third driver signal to couple each of the first and second word lines to a common voltage source.

[0112] As is customary, the various features illustrated in the drawings may not be drawn to scale. The descriptions presented in this disclosure are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations for describing various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Additionally, some figures may be simplified for clarity. Thus, the figures may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0113] As used herein, the terms "apparatus" or "memory device" may include, but are not limited to, devices having only memory. For example, an apparatus or memory device may include memory, a processor, and / or other components or functions. For instance, an apparatus or memory device may include a system-on-a-chip (SoC).

[0114] The terms used herein, and especially in the appended claims (e.g., the body of the appended claims), are generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0115] Furthermore, if the intention is to use a specific number of introduced claim statements, then such an intention will be explicitly stated in the claims, and where no such statement exists, such an intention does not exist. For example, to aid understanding, the appended claims may contain the use of introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing claim statements with the indefinite article “a / an” limits any particular claim containing such introduced claim statements to embodiments containing only one such statement, even when the same claim contains the introductory phrases “one or more” or “at least one” and an indefinite article such as “a” (e.g., “a” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles to introduce claim statements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0116] Furthermore, even when a specific number of the introduced claims are explicitly stated, it should be understood that such statements should generally be interpreted as meaning at least the number of statements (e.g., a simple statement of "two statements" without other modifiers means at least two statements, or two or more statements). Moreover, in cases where conventions such as "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." are used, such structures are generally intended to include only A, only B, only C, A and B, A and C, B and C, or A, B, and C, etc. For example, the use of the term "and / or" is intended to be interpreted in this manner.

[0117] Furthermore, it should be understood that any transitional word or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, is intended to include the possibility of including one, any, or both of the stated terms. For example, the phrase "A or B" will be understood to include the possibility of including "A" or "B" or "A and B".

[0118] Furthermore, the use of terms such as "first," "second," and "third" in this document does not necessarily imply a specific order or number of elements. Generally, the terms "first," "second," and "third" are used as general identifiers to distinguish different elements. Where there is no indication that the terms "first," "second," and "third" imply a specific order, these terms should not be construed as implying a specific order. Similarly, where there is no indication that the terms "first," "second," and "third" imply a specific number of elements, these terms should not be construed as implying a specific number of elements.

[0119] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes, to a certain extent, what a person skilled in the art would understand as a given parameter, property, or condition being satisfied with a small degree of variation, such as within acceptable manufacturing tolerances. For example, depending on the particular parameter, property, or condition that is substantially satisfied, it may be satisfied with at least 90%, at least 95%, or even at least 99%.

[0120] The embodiments described above and illustrated in the accompanying drawings do not limit the scope of this disclosure, which is covered by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, various modifications to this disclosure will become apparent to those skilled in the art from the description, in addition to the alternative applicable combinations of elements shown and described herein. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. An apparatus comprising: Two or more word line drivers, each of the two or more word line drivers including a first transistor and a second transistor; A plurality of first driver gates, wherein the first transistor of each word line driver has a gate coupled to a dedicated first driver gate of the plurality of first driver gates; and A second driver gate, which is coupled to the gate of each of the second transistors in each of the two or more word line drivers. The second transistor of one of the two or more word line drivers has a first end coupled to an associated word line and a second end coupled to a word line associated with another word line driver of the two or more word line drivers.

2. The apparatus of claim 1, wherein each word line driver is configured to couple an associated word line to an associated main word line in response to receiving a signal via the dedicated first driver gate.

3. The apparatus of claim 1, wherein the two or more word line drivers are configured such that, in response to receiving a signal via the second driver gate, a plurality of word lines associated with the two or more word line drivers are coupled together.

4. The apparatus of claim 1, wherein the second transistor of each of the two or more word line drivers is configured to couple the associated word line to a common negative word line voltage in response to receiving a signal via the second driver gate.

5. The apparatus of claim 1, wherein the two or more word line drivers are configured such that, in response to receiving a signal via the second driver gate, two or more word lines associated with the two or more word line drivers are coupled together and coupled to a common voltage source.

6. The apparatus of claim 1, wherein for each word line driver: The first terminal of the first transistor is coupled to the associated main word line; The second terminal of the first transistor is coupled to the associated word line; The first terminal of the second transistor is coupled to the associated word line; and The second terminal of the second transistor is coupled to a word line associated with another word line driver or negative word line voltage source.

7. An apparatus comprising: Two or more letter lines; and A word line driver chain, wherein each word line driver in the word line driver chain is coupled to an associated word line among the two or more word lines, and each word line driver in the word line driver chain is configured to: The associated word line is coupled to the associated main word line via a first transistor; and The associated word line is coupled to a common negative word line voltage source via a second transistor. The second transistor of one word line driver in the word line driver chain is configured to couple the associated word line to a word line associated with another word line driver in the word line driver chain.

8. The apparatus of claim 7, wherein the second transistor of each word line driver in the word line driver chain is configured to couple the associated word line to at least one of the common negative word line voltage source or a word line associated with another word line driver in the word line driver chain.

9. The apparatus according to claim 7, further comprising: A plurality of first driver gates, wherein the gate of the first transistor of each word line driver is coupled to a plurality of dedicated first driver gates for driver signals; and The second driver gate, wherein the gate of the second transistor of each word line driver is coupled to the second driver gate.

10. The apparatus of claim 7, further comprising: The second or more word lines; and A second word line driver chain, wherein each word line driver in the second word line driver chain is coupled to an associated word line in the second two or more word lines, and each word line driver in the second word line driver chain is configured to: The associated word line is coupled to the associated main word line via a first transistor; and The associated word line is coupled to a second common negative word line voltage source via a second transistor, the voltage at the common negative word line voltage source being substantially equal to the voltage at the second common negative word line voltage source.

11. The apparatus of claim 7, wherein the word line driver chain comprises at least one word line driver configured to drive even-numbered word lines and at least one word line driver configured to drive odd-numbered word lines.

12. A method of operating a memory device, comprising: During the first mode, the first driver signal is transmitted via the first driver gate to the word line driver in two or more word line drivers; During the second mode, a second driver signal is transmitted via the second driver gate to each of the two or more word line drivers; and In response to the second driver signal, two or more word lines associated with the two or more word line drivers are coupled together and coupled to a common voltage source. During the second mode, coupling the two or more word lines together and to the common voltage source includes coupling one word line of the two or more word lines and another word line of the two or more word lines together via a pull-down transistor during the inactive mode.

13. The method of claim 12, further comprising coupling a word line associated with the word line driver to an associated main word line during the first mode and in response to the first driver signal.

14. The method of claim 13, wherein coupling the word line to the associated main word line during the first mode includes coupling the word line to the associated main word line via a pull-up transistor during the active mode.

15. The method of claim 12, wherein during the second mode, coupling the two or more word lines together and to the common voltage source comprises coupling the two or more word lines together and to the common voltage source via a plurality of pull-down transistors during the inactive mode.

16. The method of claim 12, wherein during the second mode, coupling the two or more word lines together and to the common voltage source includes, during the inactive mode, coupling the two or more word lines together and to the negative word line voltage.

17. A system comprising: At least one input device; At least one output device; At least one processor device is operatively coupled to the input device and the output device; and At least one memory device operatively coupled to the at least one processor device and including a sub-word line driver circuitry, the sub-word line driver circuitry comprising: Two or more subword line drivers, wherein each subword line driver contains: Pull-up transistors are used to couple associated word lines to the main word line; and A pull-down transistor is used to couple the associated word line to a negative word line voltage; A plurality of first driver gates, wherein each sub-word line driver is coupled to a dedicated first driver gate of the plurality of first driver gates; and A plurality of second driver gates, wherein more than one sub-word line driver of two or more sub-word line drivers is coupled to the plurality of second driver gates. In response to a signal from a second driver gate via the plurality of second driver gates, an associated word line is coupled to another word line via the pull-down transistor.

18. The system of claim 17, wherein each of the pull-up transistor and the pull-down transistor comprises an NMOS transistor.

19. The system of claim 17, wherein the two or more sub-word line drivers are configured such that each associated word line is coupled to the negative word line voltage in response to a signal via the second driver gate.

20. The system of claim 17, wherein an associated word line is coupled to a main word line in response to a signal via the dedicated first driver gate.

21. An apparatus comprising: First word line driver, which is configured to drive the first word line; Second word line driver, which is configured to drive the second word line; A first driver gate is coupled to the first word line driver and configured to transmit a first driver signal to couple the first word line to the first main word line; A second driver gate, coupled to the second word line driver, and configured to transmit a second driver signal to couple the second word line to the second main word line; and A third driver gate is coupled to each of the first word line driver and the second word line driver, and is configured to transmit a third driver signal to couple each of the first word line and the second word line to a common voltage source.

22. The apparatus of claim 21, wherein the third driver gate is coupled to: The gate of the pull-down transistor of the first word line driver; and The gate of the pull-down transistor of the second word line driver.

23. The apparatus of claim 21, wherein the first driver gate is coupled to the gate of the pull-up transistor of the first word line driver, and the second driver gate is coupled to the gate of the pull-up transistor of the second word line driver.

24. The apparatus of claim 21, wherein each of the first word line driver and the second word line driver comprises a plurality of NMOS transistors.

25. The apparatus of claim 21, wherein, in response to the third driver signal, each of the first word line and the second word line is coupled to the common voltage source at a first node at a first end of the word line driver gap and at a second node at a second opposite end of the word line driver gap.

26. The apparatus of claim 21, wherein the third driver gate is at least partially located between the first driver gate and the second driver gate.

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