Fabrication method of silicon nitride waveguide based on SOI wafer

Abstract

This invention provides a method for fabricating a silicon nitride waveguide based on an SOI wafer, comprising the following steps: 1) depositing an isolation dielectric layer on a first main surface of the SOI wafer; 2) forming a first silicon nitride layer and a second silicon nitride layer on the deposited isolation dielectric layer and a second main surface of the SOI wafer, respectively, using a low-pressure chemical vapor deposition process; 3) etching the second silicon nitride layer to remove at least a portion of its thickness; 4) depositing a high-stress silicon nitride layer on the second main surface of the SOI wafer using a plasma-enhanced chemical vapor deposition process; 5) etching the first silicon nitride layer to form a silicon nitride waveguide. The high-stress silicon nitride layer is used to achieve stress balance in the silicon nitride waveguide during its formation. This invention not only solves the problem of stress imbalance in silicon nitride waveguides but also protects devices on the front side of the wafer, and can be widely applied in silicon photonics technology.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronics, and in particular relates to a method for fabricating silicon nitride waveguides based on SOI wafers. Background Technology

[0002] Microelectronics technology has been developing rapidly according to Moore's Law for over fifty years. However, with the feature size of devices shrinking to below a dozen nanometers, the ability of the microelectronics industry to continue advancing according to Moore's Law faces challenges. Device speed, power consumption, and heat dissipation have become bottlenecks restricting the development of microelectronics technology. On the other hand, information technology based on computer and communication networks also demands faster processing speeds, larger data storage capacities, and higher transmission rates for its functional devices and systems. Silicon integrated circuit technology, which only uses electrons as information carriers, is no longer sufficient to meet these requirements. Therefore, applying "silicon-based optoelectronics technology," combining microelectronics and optoelectronics on a silicon-based platform, fully leveraging the advanced and mature process technology of microelectronics, the low cost brought by large-scale integration, and the unique advantages of photonic devices and systems such as extremely high bandwidth, ultra-fast transmission rates, and high anti-interference capabilities, has become an inevitable trend in the development of information technology and a common consensus in the industry.

[0003] In some silicon optoelectronic technologies, silicon nitride (SIN) waveguides need to be formed. However, stress imbalance problems are encountered in the process of forming silicon nitride waveguides. If not properly resolved, subsequent processes will be difficult to proceed. Moreover, the stress problem is more prominent for silicon nitride waveguides of different thicknesses and multilayers.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating silicon nitride waveguides based on SOI wafers, which solves the problem of reduced silicon nitride waveguide quality due to stress imbalance in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a silicon nitride waveguide based on an SOI wafer. The method includes: 1) providing an SOI wafer, the SOI wafer including a first main surface and a second main surface opposite to each other, and depositing an isolation dielectric layer on the first main surface of the SOI wafer; 2) forming a first silicon nitride layer and a second silicon nitride layer on the deposited isolation dielectric layer and the second main surface of the SOI wafer respectively using a low-pressure chemical vapor deposition process; 3) etching the second silicon nitride layer to remove at least a portion of the thickness of the second silicon nitride layer; 4) depositing a high-stress silicon nitride layer on the second main surface of the SOI wafer using a plasma-enhanced chemical vapor deposition process; 5) etching the first silicon nitride layer to form a silicon nitride waveguide, wherein the high-stress silicon nitride layer is used to achieve stress balance in the silicon nitride waveguide during its formation.

[0007] Optionally, the method further includes the following steps: 6) forming an isolation dielectric layer on the silicon nitride waveguide, and depositing a third silicon nitride layer and a fourth silicon nitride layer on the isolation dielectric layer and the high-stress silicon nitride layer respectively using a low-pressure chemical vapor deposition process; 7) etching the fourth silicon nitride layer and the high-stress silicon nitride layer to remove at least a portion of the thickness of the stack formed by the fourth silicon nitride layer and the high-stress silicon nitride layer; 8) depositing a high-stress silicon nitride layer on the second main surface of the SOI wafer using a plasma-enhanced chemical vapor deposition process; 9) etching the third silicon nitride layer to form a silicon nitride waveguide; 10) repeating steps 6 to 9) to form a multilayer silicon nitride waveguide with stacked layers.

[0008] Optionally, the insulating dielectric layer includes one of silicon dioxide, polycrystalline silicon, and amorphous silicon.

[0009] Optionally, in step 2), the thickness of the first silicon nitride layer deposited on the isolation dielectric layer is 400 nm to 1000 nm.

[0010] Optionally, step 3) etching the second silicon nitride layer includes either dry etching or wet etching.

[0011] Optionally, step 3) involves etching the second silicon nitride layer to remove a portion or all of its thickness, wherein the portion is 50% to 100% of the total thickness of the second silicon nitride layer.

[0012] Optionally, the deposition thickness of the high-stress silicon nitride layer is positively correlated with the thickness of the high-stress silicon nitride layer to be etched and the thickness of the first silicon nitride layer.

[0013] Optionally, the deposition thickness of the high-stress silicon nitride layer in step 4) is 50% to 100% of the thickness of the first silicon nitride layer.

[0014] Optionally, the temperature for depositing the silicon nitride layer using a low-pressure chemical vapor deposition process is 650–800°C, including the following reaction: 3SiH2Cl2+4NH3→Si3N4+6HCl+6H2, or the temperature for depositing the silicon nitride layer using a low-pressure chemical vapor deposition process is 700–900°C, including the following reaction: 3SiH4+4NH3→Si3N4+12H2.

[0015] Optionally, the high-stress silicon nitride layer is deposited at a temperature of 200–400 °C using plasma-enhanced chemical vapor deposition, including the following reaction: 3SiH4 + 4NH3 → Si3N4 + 12H2.

[0016] As described above, the method for fabricating silicon nitride waveguides based on SOI wafers of the present invention has the following beneficial effects:

[0017] 1) A back-side pretreatment method is employed. First, a portion of the thickness of the second silicon nitride layer deposited on the back side of the SOI wafer using low-pressure chemical vapor deposition (LPCVD) is removed. Then, a high-stress silicon nitride layer is deposited on the back side of the SOI wafer using plasma-enhanced chemical vapor deposition (PECVD). This ensures stress balance in the silicon nitride waveguide during etching on the front side of the SOI wafer. This invention not only solves the problem of stress imbalance in silicon nitride waveguides but also protects devices on the front side of the wafer, making it widely applicable in silicon photonics technology.

[0018] 2) This invention can be extended to the process or research and development of multilayer silicon nitride waveguides and waveguides of different thicknesses, and greatly improves the quality of multilayer silicon nitride waveguides. Attached Figure Description

[0019] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0020] Figures 1-12 The diagram shows the structural schematics of each step in the fabrication method of silicon nitride waveguide based on SOI wafer according to an embodiment of the present invention.

[0021] Component designation explanation

[0022] 101 substrate silicon

[0023] 102 Insulation layer

[0024] 103 Top-layer silicon

[0025] 104 Isolation Medium Layer

[0026] 105 First silicon nitride layer

[0027] 106 Second silicon nitride layer

[0028] 107 High-stress silicon nitride layer

[0029] 108 silicon nitride waveguide

[0030] 109 Isolation Medium Layer

[0031] 110 Third silicon nitride layer

[0032] 111 Fourth silicon nitride layer

[0033] 112 High-stress silicon nitride layer

[0034] 113 Silicon nitride waveguide

[0035] 114 Isolation Medium Layer Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0038] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0039] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0040] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0041] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] like Figures 1-12 As shown, this embodiment provides a method for fabricating a silicon nitride waveguide based on an SOI wafer. The fabrication method includes:

[0044] like Figures 1-2 As shown, step 1) is performed first, providing an SOI wafer, the SOI wafer including a first main surface and a second main surface opposite to each other, and depositing an isolation dielectric layer 104 on the first main surface of the SOI wafer.

[0045] like Figure 1 As shown, the SOI wafer includes a substrate silicon 101, an insulating layer 102, and a top silicon 103 stacked sequentially from bottom to top.

[0046] In one embodiment, the isolation dielectric layer 104 may be, for example, silicon dioxide, and the isolation dielectric layer may be formed on the surface of the top silicon 103 of the SOI wafer by means of a process such as plasma-enhanced chemical vapor deposition.

[0047] In other embodiments, the isolation dielectric layer 104 may also be polycrystalline silicon or amorphous silicon, which may be formed on the surface of the top silicon 103 of the SOI wafer by methods such as vapor phase epitaxy.

[0048] like Figure 3As shown, then step 2) is performed, in which a first silicon nitride layer 105 and a second silicon nitride layer 106 are formed on the deposition isolation medium layer 104 and the second main surface of the SOI wafer, respectively, using a low-pressure chemical vapor deposition process.

[0049] In one embodiment, the low-pressure chemical vapor deposition (LPCVD) process operates at a pressure of 10–1000 Pa. Due to the varying relative speeds of gas transport and chemical reaction during LPCVD deposition, the film quality, chemical composition, and stoichiometry of the first silicon nitride layer 105 and the second silicon nitride layer 106 in this embodiment can be well controlled. Under normal pressure, the ratio of gas reaction rate to gas transport rate is close to 1 or on the same order of magnitude, leading to insufficient gas reaction and a slow reaction rate. This results in a non-standard stoichiometry film containing numerous NH / Si-H bonds, along with byproduct gases, creating numerous pores. Consequently, the entire film is dense yet porous, with an uneven surface and poor film quality. Therefore, this embodiment uses LPCVD to deposit a silicon nitride layer, reducing the gas pressure and slowing down the gas transmission and diffusion rate, making it much lower than the gas reaction rate. Taking a low pressure of 100 Pa as an example, the gas diffusion rate can be slowed down by about 1000 compared to room temperature. This allows the gas sufficient time to react and produce a Si3N4 thin film with a standard stoichiometric ratio. The entire film has high purity, high density, and uniform surface.

[0050] In one embodiment, the silicon nitride layer is deposited using a low-pressure chemical vapor deposition process at a temperature of 650–800°C, comprising the following reaction: 3SiH₂Cl₂ + 4NH₃ → Si₃N₄ + 6HCl + 6H₂. The products of this reaction are HCl and hydrogen gas, which can be removed by a simple cleaning process to obtain a high-quality silicon nitride layer.

[0051] In another embodiment, the silicon nitride layer is deposited using a low-pressure chemical vapor deposition process at a temperature of 700–900°C, comprising the following reaction: 3SiH4 + 4NH3 → Si3N4 + 12H2. The product of this reaction is hydrogen gas, which ensures that the silicon nitride layer is free of excess impurities.

[0052] In one embodiment, the thickness of the first silicon nitride layer 105 deposited on the isolation dielectric layer 104 in step 2) is 400 nm to 1000 nm. For example, the thickness of the first silicon nitride layer 105 can be 400 nm or 800 nm, etc. The thickness of the first silicon nitride layer 105 can be set according to different waveguide requirements and is not limited to the examples listed herein.

[0053] like Figure 4As shown, then step 3) is performed to etch the second silicon nitride layer 106 to remove at least a portion of the thickness of the second silicon nitride layer 106.

[0054] In one embodiment, step 3) etching the second silicon nitride layer 106 includes either dry etching or wet etching.

[0055] In one embodiment, step 3) involves etching the second silicon nitride layer 106 to remove a portion or all of the thickness of the second silicon nitride layer 106, wherein the portion thickness is 50% to 100% of the total thickness of the second silicon nitride layer 106. For example, in this embodiment, the entire thickness of the second silicon nitride layer 106 is removed.

[0056] like Figure 5 As shown, then step 4) is performed, in which a high-stress silicon nitride layer 107 is deposited on the second main surface of the SOI wafer using a plasma-enhanced chemical vapor deposition process.

[0057] In one embodiment, the deposition temperature of the plasma-enhanced chemical vapor deposition process is 200–400°C.

[0058] The plasma-enhanced chemical vapor deposition (PECVD) process in this embodiment increases gas activity by ionizing the gas with an external electric field (e.g., applying a mixed-frequency RF), rather than by increasing the ambient temperature. This allows chemical deposition to be achieved even at lower ambient temperatures, and the deposition rate can be altered by controlling the intensity of the external electric field. Because the deposition temperature of PECVD is relatively low, higher stress can be retained in the formed silicon nitride layer, resulting in a high-stress silicon nitride layer 107. This high-stress layer 107 is used to achieve stress balance in the silicon nitride waveguide during its formation. In this embodiment, the high-stress silicon nitride layer 107 is deposited at a temperature of 200–400°C using PECVD, comprising the following reaction: 3SiH4 + 4NH3 → Si3N4 + 12H2.

[0059] In one embodiment, the deposition thickness of the high-stress silicon nitride layer 107 is positively correlated with the thickness of the high-stress silicon nitride layer 107 to be etched and the thickness of the first silicon nitride layer 105.

[0060] In one implementation, the deposition thickness of the high-stress silicon nitride layer 107 in step 4) is 50% to 100% of the thickness of the first silicon nitride layer 105, so as to ultimately achieve the effect of stress balance.

[0061] like Figure 6As shown, step 5) is then performed, etching the first silicon nitride layer 105 to form a silicon nitride waveguide 108. The high-stress silicon nitride layer 107 is used to achieve stress balance in the silicon nitride waveguide 108 during the formation of the silicon nitride waveguide.

[0062] like Figures 7-8 As shown, then step 6) is performed, forming an isolation dielectric layer 109 on the silicon nitride waveguide 108, and depositing a third silicon nitride layer 110 and a fourth silicon nitride layer 111 on the deposited isolation dielectric layer 109 and the high-stress silicon nitride layer, respectively, using a low-pressure chemical vapor deposition process.

[0063] like Figure 9 As shown, then step 7) is performed to etch the fourth silicon nitride layer 111 and the high-stress silicon nitride layer 108 to remove at least a portion of the thickness of the stack formed by the fourth silicon nitride layer 111 and the high-stress silicon nitride layer 108.

[0064] Since the high-stress silicon nitride layer in step 4) has undergone steps such as the high-temperature low-pressure chemical vapor deposition process in step 6), some stress may be released. Therefore, this step can remove part of the thickness of the stack composed of the fourth silicon nitride layer 111 and the high-stress silicon nitride layer 108, and then re-deposit a high-stress silicon nitride layer on the second main surface of the SOI wafer using plasma-enhanced chemical vapor deposition to further ensure stress balance. For example, this step can remove only the fourth silicon nitride layer 111, or remove the fourth silicon nitride layer 111 and part of the high-stress silicon nitride layer 108, or remove both the fourth silicon nitride layer 111 and the high-stress silicon nitride layer 108.

[0065] like Figure 10 The process then proceeds to step 8), where a high-stress silicon nitride layer 112 is deposited on the second main surface of the SOI wafer using a plasma-enhanced chemical vapor deposition process.

[0066] The thickness of the high-stress silicon nitride layer 112 is positively correlated with the thickness of the third silicon nitride layer 110. For example, the thickness of the high-stress silicon nitride layer 112 can be 50% to 100% of the thickness of the third silicon nitride layer 110.

[0067] like Figures 11-12 As shown, step 9) is then performed, etching the third silicon nitride layer 110 to form a silicon nitride waveguide 113, and then forming an isolation dielectric layer 114 on the silicon nitride waveguide.

[0068] Finally, steps 6 to 9 can be repeated under the same or similar conditions as those described above to form a multilayer silicon nitride waveguide with stacked arrangement.

[0069] As described above, the method for fabricating silicon nitride waveguides based on SOI wafers of the present invention has the following beneficial effects:

[0070] 1) A back-side pretreatment method is employed. First, a portion of the thickness of the second silicon nitride layer deposited on the back side of the SOI wafer using low-pressure chemical vapor deposition (LPCVD) is removed. Then, a high-stress silicon nitride layer is deposited on the back side of the SOI wafer using plasma-enhanced chemical vapor deposition (PECVD). This ensures stress balance in the silicon nitride waveguide during etching on the front side of the SOI wafer. This invention not only solves the problem of stress imbalance in silicon nitride waveguides but also protects devices on the front side of the wafer, making it widely applicable in silicon photonics technology.

[0071] 2) This invention can be extended to the process or research and development of multilayer silicon nitride waveguides and waveguides of different thicknesses, and greatly improves the quality of multilayer silicon nitride waveguides.

[0072] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating silicon nitride waveguides based on SOI wafers, characterized in that, The preparation method includes: 1) Provide an SOI wafer, the SOI wafer including opposing first and second main surfaces, and deposit an isolation dielectric layer on the first main surface of the SOI wafer; 2) A first silicon nitride layer and a second silicon nitride layer are formed on the deposition isolation medium layer and the second main surface of the SOI wafer, respectively, using a low-pressure chemical vapor deposition process; 3) Etch the second silicon nitride layer to remove at least a portion of the thickness of the second silicon nitride layer; 4) A high-stress silicon nitride layer is deposited on the second main surface of the SOI wafer using plasma-enhanced chemical vapor deposition (PECVD). 5) Etch the first silicon nitride layer to form a silicon nitride waveguide, wherein the high-stress silicon nitride layer is used to achieve stress balance in the silicon nitride waveguide during its formation.

2. The method for fabricating silicon nitride waveguides based on SOI wafers according to claim 1, characterized in that: It also includes the following steps: 6) An isolation dielectric layer is formed on the silicon nitride waveguide, and a third silicon nitride layer and a fourth silicon nitride layer are deposited on the isolation dielectric layer and the high-stress silicon nitride layer respectively using a low-pressure chemical vapor deposition process; 7) Etch the fourth silicon nitride layer and the high-stress silicon nitride layer to remove at least a portion of the thickness of the stack formed by the fourth silicon nitride layer and the high-stress silicon nitride layer; 8) A high-stress silicon nitride layer is deposited on the second main surface of the SOI wafer using plasma-enhanced chemical vapor deposition (PECVD). 9) Etch the third silicon nitride layer to form a silicon nitride waveguide; 10) Repeat steps 6 to 9) to form a multilayer silicon nitride waveguide with stacked arrangement.

3. The method for fabricating silicon nitride waveguides based on SOI wafers according to claim 1, characterized in that: The isolation dielectric layer includes one of silicon dioxide, polycrystalline silicon, and amorphous silicon.

4. The method for fabricating silicon nitride waveguides based on SOI wafers according to claim 1, characterized in that: Step 2) The thickness of the first silicon nitride layer deposited on the isolation dielectric layer is 400 nm to 1000 nm.

5. The method for fabricating silicon nitride waveguides based on SOI wafers according to claim 1, characterized in that: Step 3) Etching the second silicon nitride layer includes either dry etching or wet etching.

6. The method for fabricating silicon nitride waveguides based on SOI wafers according to claim 1, characterized in that: Step 3) Etch the second silicon nitride layer to remove a portion or all of the thickness of the second silicon nitride layer, wherein the portion thickness is 50% to 100% of the total thickness of the second silicon nitride layer.

7. The method for fabricating silicon nitride waveguides based on SOI wafers according to claim 1 or 2, characterized in that: The deposition thickness of the high-stress silicon nitride layer is positively correlated with the thickness of the high-stress silicon nitride layer to be etched and the thickness of the first silicon nitride layer.

8. The method for fabricating silicon nitride waveguides based on SOI wafers according to claim 1, characterized in that: The deposition thickness of the high-stress silicon nitride layer in step 4) is 50% to 100% of the thickness of the first silicon nitride layer.

9. The method for fabricating a silicon nitride waveguide based on an SOI wafer according to claim 1 or 2, characterized in that, The temperature for depositing silicon nitride layers using low-pressure chemical vapor deposition (LPCVD) is 650–800℃, including the following reaction: 3SiH₂Cl₂ + 4NH₃ → Si₃N₄ + 6HCl + 6H₂. Alternatively, the temperature for depositing silicon nitride layers using LCVD is 700–900℃, including the following reaction: 3SiH₄ + 4NH₃ → Si₃N₄ + 12H₂.

10. The method for fabricating a silicon nitride waveguide based on an SOI wafer according to claim 1 or 2, characterized in that, The high-stress silicon nitride layer is deposited at a temperature of 200–400 °C using plasma-enhanced chemical vapor deposition, which includes the following reaction: 3SiH4 + 4NH3 → Si3N4 + 12H2.

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