Communication device, communication system and communication method

Abstract

[PROBLEM] To efficiently implement serial communication. [SOLUTION] A communication device includes: a controller that determines a time stamp to be used as a starting point and a unit period of the time stamp from the starting point; a wrapper that samples a general purpose input / output (GPIO) signal from a host device in synchronization with the time stamp at a set sampling period or a sampling period corresponding to a frequency of a logical change of the GPIO signal, and generates a predetermined communication protocol packet including the sampled data; and a LINK (link layer) that transmits the packet to a communication counterpart device.

Description

Technical Field

[0001] This disclosure relates to communication equipment, communication systems, and communication methods. Background Technology

[0002] In the case of data communication between a master device and a slave device, a technique is proposed for implementing serial communication between a SerDes (hereinafter referred to as M_SerDes) for the master device and a SerDes (hereinafter referred to as S_SerDes) for the slave device. Serial communication between the two SerDes is implemented through packet switching based on a predetermined communication protocol.

[0003] At the same time, GPIO (General Purpose Input / Output) communication is implemented, for example, between the master device and M_SerDes and between the slave device and S_SerDes.

[0004] Reference List

[0005] Patent documents

[0006] PTL 1

[0007] Japanese Patent Application Publication No. 2011-239011 Summary of the Invention

[0008] Technical issues

[0009] The M_SerDes, which receives data from the master device via GPIO communication, samples the received data, converts the sampled data into packets according to a predetermined communication protocol, and sends the packets to the S_SerDes. However, when the amount of data received via GPIO communication is extremely large, sampling at a fixed period leads to an increase in the amount of sampled data.

[0010] The signal logic of data received via GPIO communication may change very little. However, as long as such data is sampled at a fixed period, the amount of sampled data cannot be reduced. Consequently, the total number of packets sent / received between M_SerDes and S_SerDes will also increase.

[0011] Therefore, this disclosure provides a communication device, communication system, and communication method that can efficiently implement serial communication.

[0012] Solutions to the problem

[0013] To address the problems described above, this disclosure provides a communication device comprising: a controller that determines a timestamp to be used as a starting point and a unit period of the timestamp starting from the starting point; a package that generates a first GPIO (General Purpose Input / Output) packet, the first GPIO packet comprising all sampled data items obtained by sampling a GPIO signal of an autonomous device at a fixed sampling period starting from the starting point in sync with the timestamp, or by sampling at a sampling interval corresponding to a logically changing frequency of the GPIO signal and information about the sampling location; a LINK (link layer) that generates an uplink packet including the first GPIO packet; and a PHY (physical layer) that transmits a transmission signal including the uplink packet and conforming to a predetermined communication protocol to a corresponding communication device.

[0014] The controller can receive GPIO configuration information from the master device, including the sampling period, timestamp, and sampling mode information to specify a first mode or a second mode. In the first mode, the wrapper can generate a first GPIO packet including all sampled data items obtained by sampling the first GPIO signal of the receiving autonomous device according to the sampling period starting from the starting point. In the second mode, when the value of the sampled data item sampled at the first sampling timing is not equal to the value of the sampled data item sampled at the second sampling timing, which is later than the first sampling timing, the wrapper can generate a first GPIO packet including the sampled data item sampled at the second sampling timing and first time information indicating the second sampling timing.

[0015] The communication device may further include a decapsulator that reproduces the second GPIO signal and sends it to the master device. The PHY can receive transmission signals following a predetermined communication protocol from the corresponding communication device. The LINK can separate the second GPIO packet from the transmission signal. The decapsulator can reproduce the second GPIO signal based on mode information, start point, sampling period, and the second GPIO packet.

[0016] In the first mode, one or more sampled data items are included in the second GPIO group. The decapsulator can reproduce the second GPIO signal by assigning the sampled data items included in the second GPIO group to the corresponding sampled data items sampled each time a sampling period elapses from the start point. In the second mode, one or more sampled data items are included in the second GPIO group in association with second time information indicating the corresponding sampling timing. The decapsulator can reproduce the second GPIO signal by repeating the following process: assigning sampled data items corresponding to the second time information at the sampling timing indicated by the second time information, and then assigning the same sampled data items during the sampling period until the next sampling timing indicated by the second time information included in the second GPIO group.

[0017] The communication device may include a second timer that outputs timing information synchronized with a first timer included in the master device. The decapsulator may include a memory storing a second GPIO signal. The second GPIO packet may include timestamp information regarding the timing of the second GPIO signal output. When the timestamp information is set to a first value, the decapsulator may send the second GPIO signal to the master device without storing it in memory; when the timestamp information is set to a second value, the decapsulator may store the second GPIO signal in memory, and when the second timer timing information matches the timing information inserted after the timestamp information in the second GPIO packet, the second GPIO signal is read from memory and sent to the master device via the second GPIO channel.

[0018] Before GPIO communication with the master device begins, the controller can control the wrapper to generate packets based on GPIO configuration information sent from the master device through a different communication method than GPIO communication.

[0019] GPIO configuration information may include at least one of the following: information about the sampling frequency of the GPIO signal, GPIO pin configuration information, GPIO configuration information, or information about the data length of the sampled data item.

[0020] The wrapper can generate a first GPIO packet that includes header information, which includes at least one of the following: sampling mode information, sampling frequency information, GPIO pin setting information, GPIO configuration information, or data length information.

[0021] GPIO configuration information may include the number of pins for implementing GPIO communication, GPIO pin settings, and time slots for storing GPIO communication information.

[0022] Before the packet containing the sampled data items is sent to the corresponding communication device, the wrapper can generate a first GPIO packet that does not include the sampled data items but includes header information.

[0023] The wrapper can generate at least one of the following: a first GPIO packet that does not include the sampled data items but includes header information, a first GPIO packet that includes both header information and the sampled data items, or a first GPIO packet that does not include header information but includes the sampled data items.

[0024] The wrapper can add at least one of timestamp information or error detection information to the first GPIO group.

[0025] The communication protocol may include the communication protocol of the TDD (Time Division Duplex) communication method, and the unit period may be equal to one frame period of the TDD communication method.

[0026] This disclosure provides a communication device, comprising: a PHY (physical layer) for receiving transmission signals following a predetermined communication protocol from a communication counterpart; a LINK (link layer) for separating a first GPIO packet including a timing control command from the transmission signal; a controller for determining a start point based on the timing control command; and a decapsulator for determining whether sampling mode information in the header information included in the first GPIO packet is set to a first mode or a second mode, converting the first GPIO packet into a first GPIO signal, and sending the first GPIO signal to a slave device, wherein the first mode indicates that it includes all sampled data items obtained by sampling the GPIO (general purpose input / output) signal of the transmitting slave device at a fixed sampling period, and the second mode indicates that it includes sampled data items obtained by sampling the GPIO signal at a sampling interval corresponding to a logically changing frequency of the GPIO signal and information about the sampling position.

[0027] In the first mode, one or more sampled data items are included in the first GPIO group. The decapsulator can reproduce the first GPIO signal by assigning the sampled data items included in the first GPIO group to the corresponding sampled data items sampled each time a sampling period elapses from the start point. In the second mode, one or more sampled data items are included in the first GPIO group in association with first time information indicating the corresponding sampling timing. The decapsulator can reproduce the first GPIO signal by repeating the following process: assigning sampled data items corresponding to the first time information at the sampling timing indicated by the first time information, and then assigning the same sampled data items during the sampling period until the next sampling timing indicated by the first time information included in the first GPIO group.

[0028] The communication device may include a second timer that outputs timing information synchronized with a first timer included in the master device. The decapsulator may include a memory storing a first GPIO signal. The first GPIO packet may include timestamp information regarding the timing of the output of the first GPIO signal. When the timestamp information is set to a first value, the decapsulator may send the first GPIO signal to the slave device without storing it in memory; when the timestamp information is set to a second value, the decapsulator may store the first GPIO signal in memory, and when the second timer timing information matches the timing information inserted after the timestamp information in the first GPIO packet, the first GPIO signal is read from memory and the first GPIO channel is sent to the slave device.

[0029] The communication device may include an encapsulator for generating a second GPIO packet, the second GPIO packet including sampled data items and information about the sampling position obtained by sampling a second GPIO signal provided by the device from a starting point at a fixed sampling period or at a sampling interval corresponding to the frequency of logical changes in the GPIO signal.

[0030] In the first mode, the wrapper can generate a second GPIO packet including all sampled data items obtained by sampling the second GPIO signal received from the device according to the sampling period starting from the starting point. In the second mode, when the value of the sampled data item obtained by sampling at the first sampling timing is not equal to the value of the sampled data item obtained by sampling at the second sampling timing, which is later than the first sampling timing, the wrapper can generate a second GPIO packet including the sampled data item obtained by sampling at the second sampling timing and time information indicating the second sampling timing.

[0031] Before communication with the slave device begins, the controller can control the input / output of the GPIO pins based on the GPIO pin configuration information sent from the master device via the corresponding communication device.

[0032] The header information may include at least one of the following: sampling frequency information, GPIO pin setting information, GPIO configuration information, or information about the data length of the sampled data item.

[0033] The communication protocol may include a communication protocol for the TDD (Time Division Duplex) communication method.

[0034] This disclosure provides a communication system including a master SerDes and slave SerDes, wherein serial communication is implemented between the master SerDes and slave SerDes via a predetermined communication protocol. The master SerDes includes: a first controller that determines a timestamp to be used as a start point and a unit period of the timestamp starting from the start point; a first wrapper that generates a first GPIO (General Purpose Input / Output) packet, the first GPIO packet including all sampled data items obtained by sampling a GPIO signal of an autonomous device at a fixed sampling period starting from the start point in sync with the timestamp, or by sampling at a sampling interval corresponding to a logically changing frequency of the GPIO signal and information about the sampling position; a first LINK (link layer) that generates an uplink packet including the first GPIO packet; and a first PHY (physical layer) that transmits a transmission signal including the uplink packet and conforming to the predetermined communication protocol to a corresponding communication device. The slave SerDes includes: a second PHY (physical layer) that receives transmission signals following a predetermined communication protocol from the corresponding communication device; a second LINK (link layer) that separates second GPIO packets including timing control commands from the transmission signals; a second controller that determines the start point based on the timing control commands; and a first decapsulator that determines whether the sampling mode information in the header information included in the second GPIO packet is set to a first mode or a second mode, converts the second GPIO packet into a second GPIO signal, and sends the second GPIO signal to the slave device, wherein the first mode indicates that it includes all sampled data items obtained by sampling the second GPIO signal of the transmitting slave device at a fixed sampling period, and the second mode indicates that it includes sampled data items obtained by sampling the second GPIO signal at a sampling interval corresponding to the frequency of the logical change of the GPIO signal and information about the sampling position.

[0035] This disclosure provides a communication method for implementing serial communication between a master SerDes and a slave SerDes via a predetermined communication protocol. The master SerDes: determines a timestamp to be used as a start point and a unit period of that timestamp starting from that start point; generates a first GPIO packet comprising all sampled data items obtained by sampling GPIO signals of an autonomous device at a fixed sampling period starting from the start point in sync with the timestamp, or by sampling at a sampling interval corresponding to a logically changing frequency of the GPIO signals, and information about the sampling position; generates an uplink packet including the first GPIO packet; and transmits a transmission signal including the uplink packet and conforming to the predetermined communication protocol to the slave SerDes. Slave SerDes: Receives transmission signals following a predetermined communication protocol from the corresponding communication device; separates a second GPIO packet including a timing control command from the transmission signal; a second controller determines a start point based on the timing control command; and determines whether the sampling mode information in the header information included in the second GPIO packet is set to a first mode or a second mode, converts the second GPIO packet into a second GPIO signal, and sends the second GPIO signal to the slave device, wherein the first mode indicates that it includes all sampled data items obtained by sampling the second GPIO signal of the autonomous device according to a fixed sampling period, and the second mode indicates that it includes sampled data items obtained by sampling the second GPIO signal at a sampling interval corresponding to the frequency of the logical change of the GPIO signal and information about the sampling position. Attached Figure Description

[0036] Figure 1 It is a block diagram depicting a schematic configuration of a communication system including a communication device according to one embodiment.

[0037] Figure 2A This is a block diagram depicting the internal configuration of the wrapper 150 of M_SerDes 100.

[0038] Figure 2B This is a block diagram depicting the internal configuration of the decapsulator 160 of M_SerDes 100.

[0039] Figure 3 It is a block diagram depicting a schematic configuration of a communication system comprising multiple M_SerDes and multiple S_SerDes.

[0040] Figure 4 This is a diagram depicting the relationship between the TDD cycle and the sampling period of Enc in M_SerDes.

[0041] Figure 5This is a diagram used to explain the details of full sampling.

[0042] Figure 6 This is a diagram used to explain the details of edge sampling.

[0043] Figure 7 It is a diagram that depicts an example of the sampling period in terms of absolute or relative time within a unit period.

[0044] Figure 8 This is a diagram illustrating an example of GPIO header information.

[0045] Figure 9A It is a data configuration diagram that only includes GPIO header information.

[0046] Figure 9B It is a data configuration diagram that only includes the grouped sampled data.

[0047] Figure 9C It is a data configuration diagram that only includes GPIO header information and sampled data in groups.

[0048] Figure 10 It is a diagram depicting the details of the GPIO header information and data under the condition of full sampling.

[0049] Figure 11 It is a diagram depicting the details of the GPIO header information and data when edge sampling is implemented.

[0050] Figure 12 This is a diagram used to explain the details of pin placement.

[0051] Figure 13 The illustration is obtained by adding signal transmission procedures (1) to (10) to a block diagram depicting the internal configuration of M_SerDes.

[0052] Figure 14 It is a diagram depicting the sampled waveforms, GPIO packets, and uplink (downlink) packets of M_SerDes obtained during full sampling.

[0053] Figure 15 It is a diagram depicting the sampled waveforms, GPIO packets, and uplink (downlink) packets of M_SerDes 100 obtained when edge sampling is implemented.

[0054] Figure 16 The illustration is obtained by adding signal transmission procedures (1) to (11) to a block diagram depicting the internal configuration of S_SerDes.

[0055] Figure 17It is a diagram depicting the uplink (downlink) packets sent / received by S_SerDes during full sampling.

[0056] Figure 18 It is a diagram depicting the uplink (downlink) packets sent / received by S_SerDes during edge sampling.

[0057] Figure 19 It is a diagram depicting the data configuration of the packets input to the decapsulator 260.

[0058] Figure 20 It is a diagram depicting the procedures (1) to (6) for achieving time synchronization between the timer of the master device, the timer of M_SerDes and the timer of S_SerDes.

[0059] Figure 21 It is a diagram depicting the procedures (7) to (12) for achieving time synchronization between the timer of the master device, the timer of M_SerDes and the timer of S_SerDes. Detailed Implementation

[0060] Embodiments of the communication devices, communication systems, and communication methods will be explained below with reference to the accompanying drawings. The explanations will primarily focus on the essential parts of the communication devices, communication systems, and communication methods; however, these devices, systems, and methods may include any other components or functions not depicted or explained. The following explanations are not intended to exclude any other components or functions not depicted or explained.

[0061] Figure 1 This is a block diagram depicting a schematic configuration of a communication system including a communication device according to one embodiment. For example, Figure 1 The communication system in the system is a camera image recognition system, which is one of the ADAS (Advanced Driver Assistance Systems).

[0062] Figure 1 The communication system 1 includes a master device 10, a master SerDes (M_SerDes) 100, a slave device 20, and a subordinate SerDes (S_SerDes) 200. M_SerDes 100 and / or S_SerDes 200 are communication devices according to one embodiment of this disclosure.

[0063] M_SerDes 100 and S_SerDes 200 are communicatively connected to each other according to a predetermined communication standard (hereinafter referred to as "communication standard X"). Examples of predetermined communication standard X include FPD-Link III, A-phy, and ASA. Predetermined communication standard X is not limited to any particular standard. M_SerDes 100 and S_SerDes 200 respectively correspond to the communication device according to this embodiment. This specification will mainly explain an example of M_SerDes 100 and S_SerDes 200 implementing serial signal transmission via the TDD method.

[0064] Master device 10 and M_SerDes 100 can exchange serial signals at least via GPIO (General Purpose Input / Output) communication. It should be noted that master device 10 and M_SerDes 100 can also exchange serial signals via I2C (Inter-Integrated Circuit) communication or SPI (Serial Peripheral Interface) communication, in addition to GPIO communication.

[0065] exist Figure 1 In the transmission path (cable) 6, the signal path that sends information from S_SerDes 200 to M_SerDes 100 via serial signal is called the downlink, and the signal path that sends information from M_SerDes 100 to S_SerDes 200 via serial signal is called the uplink.

[0066] Figure 1 The master device 10 includes a controller 11, a timer 12, and input / output buffers 13 and 14 for GPIO communication. Figure 1 Only blocks related to GPIO communication in master device 10 are shown. Master device 10 may have any functions other than those for GPIO communication, but such functions are not included in the definition of GPIO communication. Figure 1 The text is omitted. Controller 11 generates GPIO signals to be sent to M_SerDes 100 and implements control to send / receive GPIO signals through input / output buffers 13 and 14. Timer 12 is used for time synchronization with M_SerDes 100, slave device 20, and S_SerDes 200, as will be explained later.

[0067] M_SerDes 100 includes a controller 101, an encapsulator (Enc) 150, a link layer block (hereinafter referred to as DLL or in some cases LINK) 120, a PHY layer block (PHY) 110, a decapsulator (DeEnc) 160, a timer 102, and input / output buffers 103 and 104.

[0068] Controller 101 determines the timestamp to be used as the starting point and the unit period of that timestamp from the starting point based on the time information provided by timer 102. Furthermore, controller 101 controls Enc 150 to generate uplink packets and controls DeEnc 160 to retrieve downlink packets. Additionally, controller 101 obtains GPIO setting information, the unit period, and the setting value for the sampling period from master device 10 via I2C communication. That is, controller 101 has the function of controlling I2C communication with master device 10. Furthermore, based on the header information in the GPIO packets extracted from the downlink packets received from S_SerDes 200, controller 101 determines whether the data in the received GPIO packets includes all sampled data items sampled at a fixed sampling period or sampled data items sampled at sampling intervals corresponding to logical changes in the GPIO signal and sampling positions.

[0069] Here, the unit period refers to the time interval of timestamps. As configuration information, the unit period can be pre-defined for M_SerDes 100 and S_SerDes 200. Alternatively, the master device 10 can send information about the unit period to the controller 101 of M_SerDes 100 and the controller 201 of S_SerDes 200 via I2C communication.

[0070] Encapsulator 150 generates predetermined communication protocol packets, including all sampled data items obtained by sampling the GPIO signals of the autonomous device 10 at a fixed sampling period synchronized with a timestamp in each unit cycle specified by controller 101, or including sampled data items obtained by sampling at sampling intervals corresponding to logical changes and sampling positions of the GPIO signals. In full sampling mode (first mode), encapsulator 150 generates a first GPIO packet, including all sampled data items obtained by sampling the first GPIO signals of the receiving autonomous device at a sampling period starting from the start point. In edge sampling mode (second mode), when the value of a sampled data item sampled at the first sampling timing is not equal to the value of a sampled data item sampled at the second sampling timing, which is later than the first sampling timing, encapsulator 150 generates a first GPIO packet, including the sampled data item sampled at the second sampling timing and first time information indicating the second sampling timing.

[0071] DLL 120 generates uplink packets by combining packets generated by Enc (also known as GPIO packets) with any other transmit packets. Additionally, DLL 120 receives downlink packets transmitted from S_SerDes 200 via the downlink, extracts GPIO packets from the downlink packets, and sends the GPIO packets to decapsulator 160.

[0072] PHY 110 outputs uplink packets from DLL 120 to the transmission path according to the uplink output timing of TDD. Additionally, PHY 110 receives downlink packets sent from S_SerDes 200 and sends the downlink packets to DLL 120.

[0073] Under the control of controller 101, decapsulator 160 receives GPIO packets extracted from downlink packets by DLL 120 and converts the GPIO packets into GPIO signals. Decapsulator 160 sends the GPIO signals obtained through the conversion to master device 10 via input / output buffers. Decapsulator 160 reconstructs the second GPIO signal based on mode information, start point, sampling period, and the second GPIO packet. More specifically, decapsulator 160 reconstructs the second GPIO signal based on mode information, start point, sampling period, and the second GPIO packet. More specifically, in full sampling mode (first mode), one or more sampled data items are included in the second GPIO packet, and decapsulator 160 reconstructs the second GPIO signal by assigning the sampled data items included in the second GPIO packet to the corresponding sampled data items sampled each time a sampling period elapses from the start point. In edge sampling mode (second mode), one or more sampled data items are included in a second GPIO group in association with second time information indicating the corresponding sampling timing, and the decapsulator 160 reproduces the second GPIO signal by repeating the following process: allocating sampled data items corresponding to the second time information at the sampling timing indicated by the second time information, and then allocating the same sampled data items during the sampling period until the next sampling timing indicated by the second time information in the second GPIO group.

[0074] Timer 102 outputs time information. The time information output by Timer 102 is input to Controller 101, Encapsulator 150, and Decapsulator 160. Encapsulator 150 adds timestamp information or time information to GPIO packets based on the time information provided from Timer 102, as will be explained later.

[0075] Slave device 20 includes a controller 21, a timer 22, and input / output buffers 23 and 24. Figure 1Only the blocks related to GPIO communication in slave device 20 are shown. Slave device 20 may have any other functions not related to GPIO communication, but... Figure 1 Such functionality is omitted. Controller 21 implements control to exchange GPIO signals with S_SerDes 200 via input / output buffers 23 and 24. Timer 22 can be synchronized with the time of S_SerDes 200, master device 10, and M_SerDes 100, as will be explained later.

[0076] S_SerDes 200 includes a controller 201, an encapsulator (Enc) 250, a link layer block (DLL) 220, a physical layer block (PHY) 210, a decapsulator (DeEnc) 260, a timer 202, input / output buffers 203 and 204, and an I2C controller 270.

[0077] Based on the header information of the GPIO packets extracted from the uplink packets received from M_SerDes 100, controller 201 determines whether the data in the received GPIO packets includes all sampled data items sampled at a fixed sampling period, or sampled data items sampled at sampling intervals corresponding to logical changes in the GPIO channel and sampling positions. Furthermore, controller 201 controls Enc 250 to generate packets and controls DeEnc 260 to extract GPIO signals from the packets. Controller 201 has the function of implementing I2C communication with slave device 20 via I2C controller 270. The functionality of I2C controller 270 can be included in controller 201.

[0078] Enc 250 generates a predetermined communication protocol packet (GPIO packet), which includes all sampled data items obtained by sampling the GPIO signal provided by device 20 at a fixed sampling period, synchronized with the timestamp in each unit cycle, or includes sampled data items obtained by sampling at the sampling interval corresponding to the logical change of the GPIO signal and the sampling position.

[0079] DLL 220 generates downlink packets by combining GPIO packets generated by Enc 250 with other transmit packets. Furthermore, DLL 220 extracts GPIO packets from uplink packets received from M_SerDes 100 via the uplink and sends the GPIO packets to DeEnc 260.

[0080] PHY 210 outputs downlink packets from DLL 220 to the transmission path according to the downlink output timing of TDD. Additionally, PHY 210 receives uplink packets sent by M_SerDes 100 and sends the uplink packets to DLL 220.

[0081] Under the control of controller 201, DeEnc 260 receives GPIO packets extracted from uplink packets by DLL 220 and converts the GPIO packets into GPIO signals. DeEnc 260 then sends the GPIO signals obtained through the conversion to slave device 20 via input / output buffers 203 and 204.

[0082] Timer 202 outputs time information. The time information output from Timer 202 is input to the controller, Enc 250, and DeEnc 260. Enc 250 adds a timestamp to the GPIO group based on the time information provided by Timer 202, as will be explained later.

[0083] Figure 2A This is a block diagram depicting the internal configuration of the wrapper 150 of M_SerDes 100. It should be noted that Enc 250 of S_SerDes 200 has a similar... Figure 2A The internal configuration within. For example... Figure 2A As depicted, the encapsulator 150 includes a sampler 53, an encoder 52, and an Enc core 51.

[0084] Sampler 53 samples the GPIO signal of the transmitting autonomous device 10 according to a fixed sampling period and transmits all sampled data items, or transmits sampled data items sampled at the sampling interval corresponding to the logic change and sampling position of the GPIO signal. In this specification, sampling the GPIO signal according to a fixed sampling period is called full sampling, and sampling the GPIO signal at the sampling interval corresponding to the logic change of the GPIO signal is called edge sampling, as will be explained later. More specifically, in full sampling, the GPIO signal is sampled in every sampling period, and all sampled data items are transmitted. In edge sampling, the GPIO signal is sampled according to the sampling period, and the set of sampled data items sampled at the sampling interval and sampling position where the logic change of the GPIO signal occurs is transmitted.

[0085] Encoder 52 encodes the data items sampled by sampler 53. Enc core 51 generates GPIO packets by adding header information or timestamps to the encoded data obtained by encoder 52. The GPIO packets generated by Enc core 51 are sent to DLL 120.

[0086] Figure 2B This is a block diagram depicting the internal configuration of the decapsulator 160 of M_SerDes 100. It should be noted that the DeEnc 260 of S_SerDes 200 has a similar... Figure 2B The internal configuration within. For example... Figure 2B As described in the document, the decapsulator 160 includes a DeEnc core 61, a decoder 62, a memory (mem) 63, and a selector (sel) 64.

[0087] The DeEnc core 61 separates the GPIO packets extracted by the DLL from the downlink packets received from S_SerDes 200 via the transmission path and outputs the encoded data. The decoder 62 decodes the encoded data output by the DeEnc core 61 to recover the sampled data used before encoding and temporarily stores the sampled data in memory 63. The selector 64 recovers the original GPIO signal based on the sampled data stored in memory 63 and the sampled data decoded by the decoder 62. The GPIO signal output from the selector 64 is sent to the master device 10 through input / output buffers 103 and 104.

[0088] Figure 1 An example is depicted where a master device 10 communicates via GPIO with one M_SerDes 100 and a slave device 20 communicates via GPIO with one S_SerDes 200. However, it can also be assumed that the master device 10 communicates via GPIO with multiple M_SerDes 100s and multiple slave devices 20 communicate via GPIO with multiple S_SerDes 200s. That is, a master device 10 can transmit serial signals to multiple slave devices 20 through multiple M_SerDes 100s and multiple S_SerDes 200s.

[0089] Figure 3 This is a block diagram depicting a schematic configuration of a communication system 1, which includes multiple M_SerDes 100 and 400 that implement GPIO communication with a master device 10, and multiple S_SerDes 200 and 500 that implement GPIO communication with multiple slave devices 20 and 90. The M_SerDes 100 and 400, the S_SerDes 200 and 500, and the slave devices 20 and 90 have similar... Figure 1The internal configuration is as follows: Master device 10 communicates with at least one of the multiple M_SerDes 100 and 400 via GPIO. The multiple M_SerDes 100 and 400 transmit serial signals with one of the multiple S_SerDes 200 and 500 via, for example, TDD method. Multiple slave devices 20 and 90 communicate with at least one of the multiple S_SerDes 200 and 500 via GPIO.

[0090] Figure 4 This is a diagram illustrating the relationship between the TDD cycle and the sampling period of the wrapper 150 of M_SerDes 100. It should be noted that the sampling period of Enc 250 of S_SerDes 200 is similar to that of the wrapper 150 of M_SerDes 100.

[0091] The controller 101 of M_SerDes 100 sets a timestamp based on the time information provided by the self-timer 102 to be used as the start point for sampling GPIO signals. In addition, the controller 101 sets a timestamp for each TDD cycle (unit interval) of the TDD method. Figure 4 Three timestamps are depicted as an example. The time intervals between these timestamps are matched with the TDD cycle.

[0092] The sampler 53 of the package 150 samples the GPIO signals synchronously with a timestamp set by the controller 101. As explained previously, the M_SerDes 100 selects to perform full sampling or edge sampling based on the GPIO configuration information provided by the autonomous device 10. More specifically, the controller 101 acquires the GPIO configuration information sent from the master device 10 via I2C communication and provides the M_SerDes 100 with instructions to perform full sampling or edge sampling based on the acquired GPIO configuration information. The GPIO configuration information includes at least one of the following: GPIO signal sampling frequency information, GPIO pin configuration information, GPIO configuration information, or information about the data length of the sampled data item. The GPIO configuration information includes the number of pins for implementing GPIO communication, GPIO pin configuration information, and the time slot for storing GPIO communication information.

[0093] When full sampling is implemented in M_SerDes 100, sampler 53 of package 150 begins sampling in sync with a timestamp, and then samples the GPIO signal at fixed intervals. More specifically, in the case of full sampling, sampler 53 samples the GPIO signal in sync with the rising or falling edge of a clock (not shown) that is synchronized with a timestamp.

[0094] Furthermore, in the case of edge sampling, as in the case of full sampling, sampler 53 begins sampling synchronously with the timestamp and then performs sampling according to the sampling period. However, in edge sampling, sampler 53 sends the sampled data item along with its sampling position when a logic change of the GPIO signal occurs. Therefore, if the logic of the GPIO signal does not change during a TDD cycle, such as Figure 4 As described in the latter half of the cycle, no sampled data items are sent. Accordingly, the amount of sampled data can be reduced.

[0095] By using GPIO configuration information, master device 10 specifies whether M_SerDes 100 and S_SerDes 200 perform full sampling or edge sampling of the GPIO signals. The GPIO configuration information includes GPIO mode information, as explained later. If the GPIO mode information is set to full sampling mode, M_SerDes 100 and S_SerDes 200 perform full sampling. If the GPIO mode information is set to edge sampling mode, M_SerDes 100 and S_SerDes 200 perform edge sampling.

[0096] Figure 5 This is a diagram used to explain the details of full sampling. When the full sampling mode is specified by the master device 10, M_SerDes 100 and S_SerDes 200 implement full sampling. In full sampling, the GPIO signal is sampled at fixed time intervals during the time period between two adjacent timestamps. When M_SerDes 100 and S_SerDes 200 implement serial signal transmission via the TDD method, the interval between two adjacent timestamps is equal to one TDD cycle. Sampler 53 begins sampling the GPIO signal synchronously with the timestamp that serves as the starting point.

[0097] exist Figure 5 In the example, sampling begins synchronously with the top timestamp and a sampled data item, data0, is obtained. A sampled data item is a 1-bit data set to either 0 or 1. Subsequently, 500 samples are performed, for example, within a TDD loop. The 500 sampled data items, data0, data10… and data4990, are placed sequentially to generate a packet containing 500 bits of serial data. Besides… Figure 5 In addition to the serial data items depicted, header information and timestamps are added to the actual packets, as will be explained later.

[0098] The sampling frequency of sampler 53 is specified by master device 10 based on GPIO configuration information, as will be explained later. A higher sampling frequency allows for high-precision sampling of GPIO signals, but increases the amount of sampled data. Correspondingly, the number of packets exchanged between M_SerDes 100 and S_SerDes 200 increases. Master device 10 specifies the optimal sampling frequency suitable for the GPIO signals.

[0099] It should be noted that, in Figure 5 In the example, groups are generated by sequentially placing 500 sampled data items. Alternatively, groups can be generated that include the sampled data items and information about their positions. Furthermore, sampler 53 can sample the GPIO signal at the rising edge of the clock or at the falling edge of the clock.

[0100] Figure 6 This is a diagram used to explain the details of edge sampling. With the master device 10 specifying the edge sampling mode, M_SerDes 100 and S_SerDes 200 perform edge sampling. In edge sampling, the sampled data item, along with its sampling position, obtained by timing the logical change of the GPIO signal, is sent over a time period between two adjacent timestamps. More specifically, sampling begins synchronously with timestamp (a) as the starting point, and the sampled data item data0 is obtained. Subsequently, sampling is performed according to a fixed sampling period, but the set of sampled data items and their sampling positions is only sent when the logic of the GPIO signal changes ((b), (c), (d), and (e)). Figure 6 In the example, the time interval between two adjacent timestamps equals one TDD cycle. Within a TDD cycle, sampling periods are provided at fixed intervals. Of the multiple sampled data items, the sampled data item acquired at the sampling timing immediately following the timing of the logic change of the GPIO signal, along with its sampling position, is sent. Figure 6 In the diagram, the sampling timing when a logic change of a GPIO signal occurs is indicated by a solid arrow, while the sampling timing when no logic change of a GPIO signal occurs is indicated by a dashed arrow. GPIO signals can be sampled at either the rising edge or the falling edge of the clock cycle.

[0101] Figure 6This illustrates an example of generating serial data by placing separate sets, each including a sampling position and a sampled data item. At the sampling position synchronized with the top timestamp, the sampled data item is sent regardless of any logical change in the GPIO signal. That is, the set of sampling position pos0 and sampled data item data0 is sent. Subsequently, only at timings POS2, POS4… and POS499, where a logical change in the GPIO signal occurs, are the separate sets, each including the sampling position and sampled data item, sent, generating serial data. Timestamp information and header information are added. Figure 6 The serial data in the data is used to generate GPIO packets.

[0102] It should be noted that instead of the set of sampling locations and sampled data items, a set of time information regarding sampling timing and sampled data items can be formed to generate groups. Absolute time is not necessary for the time information regarding sampling timing. For this purpose, relative time elapsed from the sampling start time can be used.

[0103] Figure 7 This is a diagram illustrating an example of sampling location in terms of absolute or relative time within a unit period. Figure 7 Two types of data formats are depicted. The upper data format shows an example of using 16 bits of absolute time as time information. The lower data format shows an example of using 8 bits of relative time as time information. Relative time is the difference in time relative to the start time of sampling. Alternatively, relative time can be the low-order part of the bit string representing absolute time. When using relative time to represent time information, the amount of serial data in the packet can be significantly reduced.

[0104] As explained above, except in Figures 5 to 7 In addition to the serial data in the data format described, the packets exchanged between M_SerDes 100 and S_SerDes 200 via the transmission path include timestamp information and GPIO header information. Figure 8 This is a diagram illustrating an example of GPIO header information. Figure 8 The GPIO header information varies depending on whether full sampling or edge sampling is implemented, as will be explained later. Figure 8 In this context, the information items included in the GPIO header information are uniformly indicated for both full sampling and edge sampling.

[0105] like Figure 8 As described in the document, the GPIO header information includes GPIO mode (GPIO mode(T)), GPIO pin information (GPIO pin information(U) or(R)) and data placement information (data placement(W)).

[0106] The timestamp information t_s tamp(S) is 1 bit. A timestamp information t_s tamp(S) set to 0 indicates that there is no timestamp. A timestamp information t_s tamp(S) set to 1 indicates that new timestamp information is inserted immediately after the timestamp information t_stamp(S).

[0107] GPIO mode (T) is, for example, a 3-bit information. A GPIO mode (T) with the highest bit set to 0 indicates full sampling. A GPIO mode (T) with the highest bit set to 1 indicates edge sampling. In a 3-bit GPIO mode (T), setting the lower two bits to 00 indicates that the GPIO header includes GPIO configuration information (configuration) and data information. Setting the lower two bits to 01 indicates that the GPIO header includes GPIO configuration information but does not include data information. Setting the lower two bits to 10 indicates that the GPIO header includes data information but does not include GPIO configuration information. Setting the lower two bits to 11 indicates that the GPIO header includes user-defined information (user-defined).

[0108] GPIO pin information (U) or (R) includes the pin number. The pin number is represented, for example, by four bits starting from the fourth bit to the seventh bit of the GPIO header information. Additionally, the lower two bits of the GPIO header information indicate whether the pin is disabled, or whether it is an input signal, an input signal in a high-impedance state, or an output signal.

[0109] The data placement information (W) is a two-bit information. A data placement information (W) set to 00 indicates that serial data is transmitted using 8 time slots for one pin. A data placement information (W) set to 01 indicates that serial data is transmitted using up to two pins using 4 time slots for each pin. A data placement information (W) set to 10 indicates that serial data is transmitted using up to four pins using two time slots for each pin. A data placement information (W) set to 11 indicates that serial data is transmitted using up to 16 pins using 1 time slot for each pin. Figure 12 The text describes a specific example of data placement information (W), as will be explained later.

[0110] When performing full sampling, Figure 8 Among the information items described, the GPIO header information includes Figure 8 The (T) and (U) in the header. When performing edge sampling, the GPIO header information includes... Figure 8 (T) and (R) in the text.

[0111] Figure 9A , Figure 9B and Figure 9CThese are diagrams depicting the data structure of packets sent by M_SerDes 100 or S_SerDes 200, respectively.

[0112] Figure 9A This describes the scenario where a packet consisting only of GPIO header information is sent. In this example, the packet includes timestamp information, header information, and a CRC as an error detection signal. Figure 9A The groupings in the data do not include data.

[0113] Figure 9B Describe the case where packets containing only sampled data are sent. In this example, the packets include timestamp information, fully sampled or edge-sampled data, and CRC. Figure 9B Excluding GPIO header information.

[0114] Figure 9C This describes the transmission of packets containing GPIO header information and sampled data. In this example, the packets include timestamp information, GPIO header information, full-sampled or edge-sampled data, and CRC. In this way, Figure 9C The packets in the packet structure are used to combine and send GPIO header information and data.

[0115] Figure 9B and 9C The groups in the data include serial data in which multiple sampled data items are sequentially placed in full sampling, and serial data in which multiple sets including sampling position information and sampled data items are sequentially placed in edge sampling. Figure 9A , 9B The grouping in 9C is an example where the timestamp information t_stamp(S) is 0. When the timestamp information t_stamp(S) is set to 1, the time information... Figure 9A The time information is inserted between the timestamp information t_s tamp(S) and the GPIO header information in the group. Figure 9B The time information is inserted between the timestamp information t_stamp(S) and the sampling information in the grouping, or the time information is in Figure 9C The data is inserted between the timestamp information t_s tamp(S) and the GPIO header information in the group.

[0116] Figure 10 and 11 These are illustrations depicting the GPIO header information included in the GPIO packets generated by the wrapper 150 of M_SerDes 100 or the Enc 250 of S_SerDes 200, respectively.

[0117] (GPIO header information in full sampling)

[0118] Figure 10 Describe the GPIO header information used for full sampling. Figure 11 Describe the GPIO header information used for edge sampling. Figure 10 and Figure 11 The comparison shows a difference in a portion of the GPIO header information between GPIO packets to be sent via the uplink and those to be sent via the downlink. Furthermore, the GPIO header information varies depending on whether full sampling or edge sampling is implemented.

[0119] The header information in the GPIO packet generated by the wrapper 150 of M_SerDes 100 is 8 bytes. Figure 10 The middle is indicated by the uplink. Figure 10 The header information in the uplink GPIO packet is an example of selecting two time slots, as will be explained later. When two time slots are selected, up to four pins (Pin1 to Pin4) are used, each pin simultaneously transmitting one bit in parallel, thus transmitting one byte of data using both time slots. It should be noted that the time slot indicates the number of sampled data items of the GPIO signal that can be transmitted simultaneously.

[0120] Figure 10 The first byte of the header information of the uplink GPIO packet in the packet indicates the GPIO mode (T) and uses bits [7] and [1:0]. Bit [7] set to 0 indicates full sampling, and bit [7] set to 1 indicates edge sampling. Bits [1:0] set to 00 indicate that GPIO configuration information and data information are included in the second and subsequent bytes. Bits [1:0] set to 01 indicate that only GPIO configuration information is included in the second and subsequent bytes. Bits [1:0] set to 10 indicate that only data information is included in the second and subsequent bytes. Bits [1:0] set to 11 indicate that user-defined information is included in the second and subsequent bytes.

[0121] The second byte indicates the GPIO pin information (U). Bits [1:0] are for Pin 1. Bits [3:2] are for Pin 2. Bits [5:4] are for Pin 3. Bits [7:6] are for Pin 4. The pin information for each of Pins 1 through 4 is represented by two bits. A pin setting of 00 indicates a disabled state. A pin setting of 01 indicates an input signal. A pin setting of 10 indicates an input signal in a high-impedance state. A pin setting of 11 indicates an output signal.

[0122] When two time slots are selected, up to four pins can be used for input or output signals. Figure 10In the example, Pin1 to Pin3 are used for input signals, and Pin4 is used for output signals. That is, Pin1 to Pin3 are used for the uplink, and Pin4 is used for the downlink.

[0123] The third byte indicates the sampling frequency (V) as part of the pin configuration information. For example, 0x01 in the third byte indicates a sampling frequency of 250 MHz (sampling period of 4 nsec), and 0xFA in the third byte indicates a sampling frequency of 1 MHz (sampling period of 1 μsec).

[0124] The fourth byte indicates the pin placement (pin pattern) as part of the pin configuration information (W). For example, 0x00, 0x01, 0x02, 0x03, and 0x04 in the fourth byte indicate 8 time slots, 4 time slots, 2 time slots, 1 time slot, and half a time slot, respectively. Figure 10 The example in the text depicts 0x02, which indicates two time slots.

[0125] Figure 12 This diagram illustrates the details of pin placement. When the fourth byte of the header indicates 8 time slots, one pin is used for 1-bit sequential serial signal transmission. Accordingly, 8 time slots are needed to transmit 1 byte of data. When the fourth byte of the header indicates 4 time slots, two pins are used for 1-bit sequential serial signal transmission, respectively. Accordingly, 4 time slots are needed to transmit 1 byte of data. When the fourth byte of the header indicates 2 time slots, 4 pins are used for 1-bit sequential serial signal transmission, respectively. Accordingly, 2 time slots are needed to transmit 1 byte of data. When the fourth byte of the header indicates 1 time slot, 8 pins are used for 1-bit sequential serial signal transmission, respectively. Accordingly, 1 time slot is needed to transmit 1 byte of data. When the fourth byte of the header indicates half a time slot, 16 pins are used for 1-bit sequential serial signal transmission, respectively. Accordingly, half a time slot is needed to transmit two bytes of data.

[0126] Without changing the logic of the data in the group, it is sufficient to fix the potential of each pin corresponding to the selected time slot to a high or low potential.

[0127] Refer again Figure 10 The description states that bytes 5 through 7 (X) and (Y) of the header information for uplink GPIO packets contain data information. The fifth byte indicates the data length. Figure 10 In the example, 0x02 indicates a data length of two bytes. The sixth and seventh bytes indicate the data placement on the pins for the data to be sent via the uplink. Figure 10The example shows four types of data, Data0 to Data3, being sent in parallel via Pin1 to Pin3. Specifically, in this example, 1 bit of Data0 is sent from Pin1 to Pin3, 1 bit of Data1 is sent from Pin1 to Pin3, then 1 bit of Data2 is sent from Pin1 to Pin3, and finally 1 bit of Data3 is sent from Pin1 to Pin3.

[0128] The eighth byte (Q) of the uplink GPIO packet is error detection information (CRC). By using the CRC added to the received packet, the packet receiver can detect whether a bit error is included in the received packet.

[0129] Figure 10 The first byte of the header information for the downlink GPIO packet indicates the GPIO mode, which is the same as the GPIO mode in the uplink GPIO packet. The second byte indicates the GPIO pin information, which is the same as the GPIO pin information in the uplink GPIO packet. Figure 10 In the example, Pin4 is assigned for the downlink. The third and fourth bytes indicate pin configuration information. Figure 10 In the example, the fourth byte is 0x00 representing 8 time slots. The fifth byte indicates the data length. The sixth byte indicates the data information. Figure 10 The example shows how to send four types of data (Data0 to Data3) sequentially using Pin4. The seventh byte indicates the CRC.

[0130] (GPIO header information in edge sampling)

[0131] Figure 11 Describe the GPIO header information of GPIO packets when edge sampling is implemented. Figure 11 The first byte of the header information of the uplink GPIO packet in the packet indicates the GPIO mode (T), which is different from the GPIO mode (T) in the packet. Figure 10 The GPIO mode in the header information is the same.

[0132] The second byte indicates GPIO pin information (R). Bit [7] set to 0 indicates continued packet transmission, and bit [7] set to 1 indicates abandoned packet transmission. Bits [5:4] set to 00 indicate disabled state. Bits [5:4] set to 01 indicate input signal and input signal in high impedance state. Bits [5:4] set to 11 indicate output signal. Bits [3:0] in the second byte indicate pin number. 0x01, indicated as pin number, indicates Pin1.

[0133] In addition, the second byte can also specify the sampling frequency information (V). The sampling frequency information is related to... Figure 10 The third byte is similar. The third byte indicates that it is similar to... Figure 10 Similar data length in the fifth byte.

[0134] Bytes three through seven represent data information (X) and (Z). No time slot is selected in edge sampling. This is because in edge sampling, only the logical change point of each signal is transmitted, so the number of data items to be transmitted does not represent the elapsed time of the data. Therefore, timing information about the logical change point of each signal is transmitted.

[0135] exist Figure 11 In the example, Pin1 and Pin2 are assigned for the uplink, and Pin4 is assigned for the downlink. Pin3 is set to be ignored. Figure 11 In the above, bytes four through seven of the uplink indicate information about Pin1. More specifically, bytes four and five describe information about the first logical change point in Pin1, and bytes six and seven describe information about the second logical change point in Pin1.

[0136] Figure 11 The eighth to eleventh bytes of the uplink in the code provide information about Pin2. Figure 11 In the example, Pin1 has two logical change points, and Pin2 has one logical change point. Therefore, regarding Pin2, information about the first logical change point is described in bytes nine and eleven. Byte twelfth (Q) indicates the CRC information.

[0137] exist Figure 11 In the downlink configuration, the first byte indicates GPIO mode information, and the second byte indicates GPIO pin information. 0x04, representing GPIO pin information, indicates the pin number of Pin 4. The fourth and fifth bytes indicate information about the logic change point in Pin 4. The sixth byte indicates CRC information.

[0138] (Operation of M_SerDes 100 in full sampling)

[0139] The operation of M_SerDes 100 in full sampling will be explained next. Figure 13 It is a diagram illustrating the addition of signal transmission procedures (1) to (10) to depict the internal configuration of M_SerDes 100. Figure 14 It is a diagram depicting the sampled waveforms, GPIO packets, and uplink (downlink) packets of M_SerDes 100 obtained when full sampling is performed.

[0140] The master device 10 has the function of sending GPIO header information ((R), (T), (U), (V), and (W)), time control commands for timer 102, and GPIO setting information to the controller 101 of M_SerDes 100 using protocols such as I2C. For example, as GPIO header information or time control commands, the master device 10 writes a new setting time for timer 102 into the appropriate register in the controller 101 via the I2C protocol. When the new setting time is written, the controller 101 causes timer 102 to reflect the new setting time, thereby achieving time synchronization between timer 12 of the master device 10 and timer 102 of M_SerDes 100. Similarly, when the master device 10 writes GPIO setting information (U) or (R) into the appropriate register in the controller 101 via the I2C protocol, the controller 101 implements the GPIO setting.

[0141] M_SerDes 100 includes a controller 101, a timer 102, input / output buffers 103 and 104, a wrapper 150, a dewrapper 160, a link 120, and a PHY 110.

[0142] Controller 101 controls timer 102, input / output buffers 103 and 104, encapsulator 150 and decapsulator 160.

[0143] The encapsulator 150 has the following functions: it samples (2) the GPIO signal (1) provided by the master device 10 according to the time information input from the timer 102 and the GPIO header information ((T) to (X)) sent from the controller 101 at a specified sampling period (V); it converts the sampled GPIO signal into a sampled data item (Y) by implementing (3) encoding in a specified GPIO mode (T); it encapsulates the GPIO header information ((T) to (X)) related to the time information sent from the controller 101 and the timestamp information t_s tamp (S) into the sampled data item (Y); it adds CRC (Q) to the obtained data; and it sends the packet (4) to LINK 120. The timestamp information t_s tamp (S) is a 1-bit information set to 0 or 1, as explained previously.

[0144] Encapsulator 150 generates GPIO packets containing data about time control commands sent from master device 10 via I2C communication and sends the GPIO packets to S_SerDes200. Upon receiving the GPIO packets, S_SerDes200 recovers the time control commands from the GPIO packets and sets the time control commands for timer 202, thereby enabling master device 10, M_SerDes 100, and S_SerDes 200 to synchronize with each other.

[0145] The decapsulator 160 extracts the sampled data item (Y) by decapsulating (6) the input signal (5) input from LINK 120 according to the GPIO header information ((T) to (W)) sent from the controller 101, recovers (8) the original GPIO signal from the grouping of the sampled data item (Y), and writes the original GPIO signal into the memory 63 when necessary.

[0146] When the timestamp information t_s tamp(S) in the received GPIO packet is set to 0, the decapsulator 160 determines the output timing of the GPIO signal based on the timing information input from the timer 102. In this case, the recovered GPIO signal is sent to the selector 64 instead of being written to the memory 63.

[0147] On the other hand, when the timestamp information t_stamp(S) in the received GPIO packet is set to 1, the decapsulator 160 determines the output timing of the GPIO signal based on the timing information immediately following it. In this case, the decapsulator 160 has the following functions (10): writing the recovered GPIO signal into the memory 63, reading the GPIO signal from the memory 63 at a timing when the timing information of the input self-timer 102 matches the timing information immediately following the timestamp information t_stamp(S), and sending the GPIO signal to the master device 10 through the selector 64.

[0148] In this manner, if the timestamp information t_s tamp(S) is set to 1, a GPIO signal can be sent to the master device 10 at the timing corresponding to the time information set by the slave device 20. Furthermore, when multiple slave devices 20, multiple M_SerDes 100, and multiple S_SerDes 200 are provided, as will be explained later, a GPIO signal can be sent to the master device 10 at the timing corresponding to the time information set by each slave device 20.

[0149] Furthermore, when setting new GPIO header information ((T) to (W)) after decapsulation (6), the decapsulator 160 has the function of sending the new GPIO header information to the controller 101.

[0150] It should be noted that the GPIO header information sent from the controller 101 includes the GPIO mode (T) indicating the data format of the data to be sent / received, the GPIO pin information (U) about the pin used, the sampling period information (V), the data placement information (W), and the data length (X).

[0151] When the timestamp information t_stamp(S) in the GPIO packet is set to 0 after decapsulation (6), the decapsulator 160 causes the recovered GPIO signal to pass through path (7) according to the selection signal for selector 64 provided by controller 101, and sends the GPIO signal (10) to master device 10 without delay.

[0152] (The operation of M_SerDes 100 in edge sampling)

[0153] Figure 15 It is a diagram depicting the sampling waveforms, GPIO packets, and uplink (downlink) packets of M_SerDes 100 obtained when edge sampling is implemented.

[0154] The master device 10 has the function of sending GPIO header information ((R) and (T) to (W)), time control commands for timer 102 and GPIO setting information to the controller 101 of M_SerDes 100 using protocols such as I2C.

[0155] The controller 101 of M_SerDes 100 controls timer 102, input / output buffers 103 and 104, encapsulator 150 and decapsulator 160.

[0156] The encapsulator 150 has the following functions: it samples (2) the GPIO signal (1) provided by the master device 10 according to the time information input from the timer 102 and the GPIO header information ((R), (T), (V) and (X)) sent by the controller 101 according to the specified sampling period; it converts the GPIO signal into a sampled data item (Z) by implementing (3) encoding in the specified GPIO mode (T); it encapsulates the GPIO header information ((R), (T), (V) and (X)) and the timestamp information t_s tamp (S) related to the time information sent from the controller 101 into the sampled data item (Z); it adds CRC (Q) to the obtained data; and it sends the packet (4) to LINK 120.

[0157] The decapsulator 160 decapsulates (6) the input signal (5) provided from LINK 120 according to the GPIO header information ((R), (T), and (V)) sent by the controller 101, extracts (6) the sampled data item (Z), recovers (8) the original GPIO signal from the group of sampled data item (Z), and writes the GPIO signal into memory 63. In addition, the decapsulator 160 has the functions of reading (9) the data item written into memory 63 and sending (10) the data item to master device 10 after the time information input from timer 102 is matched with the time information immediately following the timestamp information t_s tamp (S), recovering (8) the original GPIO signal from the group of sampled data item (Z) and sending (10) the GPIO signal to master device 10, and sending new GPIO header information to controller 101 if new GPIO header information ((R), (T), and (V)) is set in the decapsulation (6).

[0158] It should be noted that the GPIO header information sent by the controller 101 includes the GPIO mode (T) indicating the data format of the data to be sent / received, the pin number and configuration information (R) of the GPIO pin used, the sampling period information (V), and the data length (X).

[0159] After decapsulation (6), if the timestamp information t_s tamp(S) is 0 and the input data does not include time information, the decapsulator 160 causes the GPIO signal to pass through path (7) and selector 64 according to the selection signal provided from controller 101, and sends the GPIO signal (10) to master device 10 without delay.

[0160] (Operation of S_SerDes 200 in full sampling)

[0161] Figure 16 The illustration is obtained by adding signal transmission procedures (1) to (11) to a block diagram depicting the internal configuration of S_SerDes200. Figure 17 This is a diagram depicting uplink (downlink) packets sent / received by S_SerDes 200 in full sampling.

[0162] S_SerDes 200 includes an I2C controller 270, a controller 201, a timer 202, input / output buffers 203 and 204, a decapsulator 260, and a capsulator 250.

[0163] I2C controller 270 communicates with controller 21 of slave device 20 using protocols such as I2C.

[0164] The controller 201 has the function of controlling LINK 220 and PHY 210, which implement transmission / reception via communication protocol X, as well as timer 202, Enc 250, DeEnc 260, and I2C controller 270 as internal blocks. Before GPIO communication with slave device 20 begins, controller 201 controls the input / output of GPIO pins based on GPIO pin setting information sent from master device 10 via the corresponding communication device.

[0165] The decapsulator 260 has the function of recovering the original GPIO signal or GPIO header information by decapsulating the packets (5) of the communication protocol X. The decapsulator 260 determines whether the sampling mode information in the header information included in the first GPIO packet is set to full sampling mode (first mode) or edge sampling mode (second mode), converts the first GPIO packet into a first GPIO signal, and sends the first GPIO signal to the slave device. The full sampling mode indicates that it includes all sampled data items obtained by sampling the GPIO signal of the transmitting slave device according to a fixed sampling period. The edge sampling mode indicates that it includes sampled data items sampled at the sampling interval corresponding to the frequency of logical change of the GPIO signal and information about the sampling position. More specifically, in the full sampling mode, one or more sampled data items are included in the first GPIO packet. The decapsulator 260 reproduces the first GPIO signal by assigning the sampled data items included in the first GPIO packet to the corresponding sampled data items sampled every time a sampling period elapses from the starting point. In edge sampling mode, one or more sampled data items are included in a first GPIO group in association with first time information indicating that the corresponding sampled data item is sampled. The decapsulator 260 reproduces the first GPIO signal by repeating the following process: allocating sampled data items corresponding to the first time information at the sampling timing indicated by the first time information, and then allocating the same sampled data items during the sampling period until the next sampling timing indicated by the first time information in the first GPIO group.

[0166] Encapsulator 250 samples and encapsulates the GPIO signals provided by device 20 and sends the packets (4) to M_SerDes 100. Encapsulator 250 has the following functions: it samples (2) the GPIO signals (1) provided by device 20 according to the time information input from timer 202 and the GPIO header information ((T) to (X)) sent by controller 201 according to a specified sampling period (V); it converts the GPIO signals into sampled data items (Y) by implementing (3) encoding in a specified GPIO mode (T); it encapsulates the GPIO header information ((T) to (X)) sent by controller 201 and the timestamp information t_s tamp (S) or time information into the sampled data items (Y); it adds CRC (Q) to the obtained data; and it sends the packets (4) to LINK 220. The package 250 generates a second GPIO packet, which includes sampled data obtained by sampling the second GPIO signal provided from the device 20 at a fixed sampling period or at a sampling interval corresponding to the frequency of a logical change in the GPIO signal, starting from the starting point, and information about the sampling position. More specifically, in full sampling mode, the package generates a second GPIO packet including all sampled data items obtained by sampling the second GPIO signal received from the device at the sampling period, starting from the starting point. In edge sampling mode, when the value of a sampled data item sampled at the first sampling timing is not equal to the value of a sampled data item sampled at the second sampling timing, which is a sampling period later than the first sampling timing, the package 250 generates a second GPIO packet including the sampled data item sampled at the second sampling timing and time information indicating the second sampling timing.

[0167] The decapsulator 260 decapsulates the input signal (5) from LINK 220 according to the GPIO header information ((T) to (W)) sent by the controller 201, extracts the sampled data item (Y) (6), recovers the original GPIO signal (8) from the grouping of the sampled data item (Y), and writes the GPIO signal into the memory 63 when needed.

[0168] When the timestamp information t_s tamp(S) included in the received GPIO packet is set to 0, the decapsulator 260 determines the output timing of the GPIO signal based on the timing information input from the timer 202. In this case, the recovered GPIO signal is sent to the selector 64 instead of being written to the memory 63.

[0169] On the other hand, when the timestamp information t_s tamp(S) included in the received GPIO packet is set to 1, the decapsulator 260 determines the output timing of the GPIO signal based on the timing information immediately following it. In this case, the decapsulator 260 has the following functions (10): writing the recovered GPIO signal into the memory 63, reading the GPIO signal from the memory 63 at a timing when the timing information of the input self-timer 202 matches the timing information immediately following the timestamp information t_s tamp(S), and sending the GPIO signal to the slave device 20 through the selector 64.

[0170] Therefore, the decapsulator 260 has the following function (10): when the timestamp information t_s tamp(S) is set to 1, after the time information of the input self timer 202 is matched with the time information immediately following the timestamp information t_s tamp(S), the data written in the memory 63 is read (9) and the data is sent to the slave device 20.

[0171] Accordingly, if the timestamp information t_s tamp(S) is set to 1, the GPIO signal can be sent to the slave device 20 at the time corresponding to the time information set by the master device 10. Furthermore, when multiple slave devices 20, multiple M_SerDes100, and multiple S_SerDes 200 are provided, as will be explained later, the GPIO signal can be sent simultaneously to each slave device 20 at the time corresponding to the time information set by the master device 10.

[0172] Furthermore, if the decapsulation (6) includes setting information (U) about input / output buffers 203 and 204, the decapsulator 260 has the function of setting input / output buffers 203 and 204 according to the setting information (U), and if the decapsulation (6) includes new GPIO header information ((T) to (W)), the decapsulator 260 has the function of sending the new GPIO header information to the controller 201.

[0173] When the received GPIO packet includes a time control command for timer 202, controller 201 causes timer 202 to reflect the newly set time included in the time control command, thereby enabling timer 12 to synchronize with timer 202.

[0174] (The operation of S_SerDes 200 in edge sampling)

[0175] Figure 18This is a diagram depicting the uplink (downlink) packets sent / received by S_SerDes 200 during edge sampling. The wrapper 250 of S_SerDes 200 has the following functions: sampling (2) the GPIO signal (1) provided by the device 20 according to the time information input from the timer 202 and the GPIO header information ((R), (T), (V) and (X)) sent by the controller 201 at a specified sampling period (V); converting the GPIO signal into a sampled data item (Y) by implementing (3) encoding in a specified GPIO mode (T); adding the GPIO header information ((R), (T), (V) and (X)), the time information and timestamp information t_s tamp (S) sent by the controller 201 to the sampled data item (Y) to encapsulate the sampled data item; adding CRC (Q) to the obtained data; and sending the packet (4) to LINK 220.

[0176] The decapsulator 260 decapsulates the input signal (5) provided from LINK 220 according to the GPIO header information ((R), (T), and (V)) sent from the controller 201, extracts the sampled data item (Y), recovers the original GPIO signal from the group of sampled data items (Y), and writes the GPIO signal into memory 63. In addition, the decapsulator 260 has the function (10) to read (9) the data written into memory 63 and send the data to slave device 20 after the time information input from timer 202 is matched with the time information immediately following the timestamp information t_stamp(S), set the input / output buffers 203 and 204 according to the setting information (U) when the setting information (U) about the pins connected to input / output buffers 203 and 204 is included in the decapsulation (6), and send new GPIO header information to controller 201 when new GPIO header information ((R), (T), and (V)) is included in the decapsulation (6).

[0177] (GPIO control at point 260 of S_SerDes 200 decapsulation)

[0178] The decapsulator 260 decapsulates the packet (5) provided from LINK 220 according to the GPIO header information ((T) to (X) or (R), (T) and (V)) sent by the controller 201, extracts the sampled data item (Y) (6), recovers the original GPIO signal (8) from the sampled data item (Y) packet, and writes the GPIO signal into the memory 63.

[0179] Figure 19This is a diagram depicting the data structure of the packets input to the decapsulator 260. The decapsulator 260 has the function (10) to read (9) the data written to the memory 63 and send the data to the slave device 20 when the time information input from the timer 202 matches the time information immediately following the timestamp information t_stamp(S). In addition, the decapsulator 260 has the function to set the input / output buffers 203 and 204 according to the setting information (U) when the setting information (U) about the pins connected to the input / output buffers 203 and 204 is included in the decapsulation (6), and to send the new GPIO header information to the controller 201 when the new GPIO header information ((T) to (X) or (R), (T) and (V)) is included in the decapsulation (6).

[0180] Decapsulator 260 decapsulates group (5). If configuration information (U) or (R) about the pins connected to input / output buffers 203 and 204 is included in the group, decapsulator 260 confirms the configuration information (U) or (R) about the pins and implements GPIO configuration.

[0181] For example, if the setting information (U) or (R) for input / output buffer 203 indicates IN, then GPIO settings for GPIO are implemented so that the output from slave device 20 is input. If the setting information (U) or (R) for input / output buffer 204 indicates OUT, then GPIO settings for GPIO are implemented so that the signal input to slave device 20 is output. When pull-up or pull-down settings are implemented externally to input / output buffers 203 and 204, the GPIO setting information (U) or (R) is set to IN_float (pull-up / pull-down).

[0182] It should be noted that the controller 101 of M_SerDes 100 can also configure the input / output buffers 103 and 104.

[0183] (System time synchronization 1 / 2)

[0184] Figure 20 The diagrams depict the procedures (1) to (6) for achieving time synchronization between timer 12 of master device 10, timer 102 of M_SerDes 100 and timer 202 of S_SerDes 200.

[0185] (1) The master device 10 sends a time control command to the controller 101 via I2C to synchronize the time of the master device 10's timer 12 and the timer 102 of M_SerDes100.

[0186] (2) According to the received command, M_SerDes 100 sets the timer 102 so that the time of the timer 102 coincides with the time of the timer 12 of the master device 10.

[0187] (3) Master device 10 causes the wrapper 150 of M_SerDes 100 to encapsulate the time control command for synchronizing the time of timer 12 of master device 10 and timer 202 of S_SerDes 200 in the protocol X format.

[0188] (4) Encapsulated time control commands in Protocol X format are sent to S_SerDes 200.

[0189] (5) The time control command is recovered by decapsulation at decapsulation 260 of S_SerDes 200 and sent to controller 201 of S_SerDes 200.

[0190] (6) According to the received command, the controller 201 sets the timer 202 so that the time of the timer 202 coincides with the time of the timer 12 of the master device 10.

[0191] As described above, time synchronization between timers (12, 102, and 202) can be achieved.

[0192] (System time synchronization 2 / 2)

[0193] Figure 21 It is a diagram depicting the procedures (7) to (12) for achieving time synchronization between timer 12 of master device 10, timers 102 and 402 of M_SerDes 100 and 400 and timers 202 and 502 of S_SerDes 200 and 500.

[0194] (7) The master device 10 sends a time control command to the controllers 101 and 401 to synchronize the time of the master device 10's timer 12 and the timers 102 and 402 of M_SerDes 100 and 400.

[0195] (8) According to the received command, M_SerDes 100 and 400 set timers 102 and 402 so that the time of timers 102 and 402 coincides with the time of timer 12 of master device 10.

[0196] (9) Master device 10 causes the wrappers 150 and 450 of M_SerDes 100 and 400 to encapsulate the time control commands for synchronizing the time of Master device 10's timer 12 and the timers 202 and 502 of S_SerDes 200 and 500 in the Protocol X format.

[0197] (10) Encapsulated time control commands in Protocol X format are sent to S_SerDes 200 and 500.

[0198] (11) The time control command is recovered by decapsulation at ...

[0199] (12) Controllers 201 and 501 set timer 502 according to the received command, so that the time of timer 502 coincides with the time of timer 12 of master device 10.

[0200] As described above, time synchronization can be achieved between timers 12, 402, and 502. Accordingly, as a result of the time synchronization achieved between timers 12, 102, 202, 402, and 502, time synchronization can be achieved throughout the entire system, thereby synchronizing the start time of the commands provided by autonomous device 10 across multiple devices in the system.

[0201] (The effects provided in this embodiment)

[0202] According to this embodiment, M_SerDes 100 and S_SerDes 200 can sample the GPIO signals of the autonomous device 10 or slave device 20 by full sampling or edge sampling when needed. For example, full sampling is selected when the toggle rate of the GPIO signal is high, thereby preventing the GPIO signal from being missed. Edge sampling is selected when the toggle rate of the GPIO signal is low, thereby obtaining only information about the start point and logical change point of the GPIO signal, thereby reducing the amount of data and achieving efficient data transmission.

[0203] According to this embodiment, M_SerDes 100 communicates with the master device 10 via GPIO, and S_SerDes 200 communicates with the slave device 20 via GPIO. Serial signal transmission can be performed between M_SerDes 100 and S_SerDes 200 via a predetermined communication protocol X. The predetermined communication protocol X is, for example, a half-duplex communication TDD method, and GPIO communication is implemented via a full-duplex communication method. Therefore, M_SerDes 100 and S_SerDes 200 can implement high-speed serial communication by converting full-duplex communication signals into half-duplex communication packets.

[0204] Furthermore, before communication with S_SerDes 200 begins, M_SerDes 100 can generate packets to be sent to S_SerDes 200 based on GPIO configuration information sent from master device 10 via a communication method different from GPIO communication. Since the GPIO configuration information can be included in the GPIO header information of the packets, it can be easily obtained at S_SerDes 200. Therefore, based on the GPIO configuration information provided by master device 10, S_SerDes 200 can extract GPIO signals from the packets and convert the GPIO signals provided by slave device 20 into packets.

[0205] It should be noted that the technology of the present invention can have the following configuration.

[0206] (1) A communication device, comprising:

[0207] The controller determines the timestamp that will be used as the starting point and the unit period of that timestamp starting from that starting point;

[0208] The wrapper generates a first GPIO (General Purpose Input / Output) packet, which includes all sampled data items obtained by sampling the GPIO signal of the autonomous device from the starting point in sync with the timestamp at a fixed sampling period, or by sampling at a sampling interval corresponding to the frequency of a logical change in the GPIO signal and information about the sampling position.

[0209] LINK (link layer), generates uplink packets including the first GPIO packet; and

[0210] The PHY (Physical Layer) transmits signals, including uplink packets and following a predetermined communication protocol, to the corresponding communication device.

[0211] (2) Based on the communication equipment in (1), where

[0212] The controller receives GPIO configuration information from the master device, which includes sampling period, timestamp, and sampling mode information to specify the first mode or the second mode.

[0213] In the first mode, the wrapper generates a first GPIO packet comprising all sampled data items obtained by sampling the first GPIO signal of the receiving autonomous device according to the sampling period starting from the starting point; and

[0214] In the second mode, when the value of the sampled data item obtained by the first sampling timing is not equal to the value of the sampled data item obtained by the second sampling timing, which is later than the first sampling timing, the wrapper generates a first GPIO packet that includes the sampled data item obtained by the second sampling timing and a first time information indicating the second sampling timing.

[0215] (3) The communication equipment according to (2) also includes:

[0216] A second GPIO signal is generated and sent to the host device's decapsulator, whereby...

[0217] The PHY receives transmission signals that follow a predetermined communication protocol from the corresponding communication device;

[0218] LINK separates the second GPIO packet from the transmitted signal; and

[0219] The decapsulator reconstructs the second GPIO signal based on mode information, start point, sampling period, and second GPIO group.

[0220] (4) Based on the communication equipment in (3), where

[0221] In the first mode, one or more sampled data items are included in a second GPIO group. The decapsulator reproduces the second GPIO signal by assigning the sampled data items included in the second GPIO group to the corresponding sampled data items sampled each time a sampling period elapses from the start point; and

[0222] In the second mode, one or more sampled data items are included in a second GPIO group in association with second time information indicating the corresponding sampling timing. The decapsulator reproduces the second GPIO signal by repeating the following process: allocating sampled data items corresponding to the second time information at the sampling timing indicated by the second time information, and then allocating the same sampled data items during the sampling period until the next sampling timing indicated by the second time information included in the second GPIO group.

[0223] (5) The communication equipment according to (3) or (4) includes:

[0224] A second timer that outputs time information synchronized with a first timer included in the master device, wherein

[0225] The decapsulator includes a memory that stores the second GPIO signal;

[0226] The second GPIO packet includes timestamp information regarding the timing of the second GPIO signal output; and

[0227] When the timestamp information is set to the first value, the decapsulator sends the second GPIO signal to the master device without storing the second GPIO signal in the memory. When the timestamp information is set to the second value, the decapsulator stores the second GPIO signal in the memory. When the second timer time information matches the time information inserted after the timestamp information in the second GPIO group, the decapsulator reads the second GPIO signal from the memory and sends the second GPIO channel to the master device.

[0228] (6) A communication device based on any one of (2) to (5), wherein

[0229] Before GPIO communication with the master device begins, the controller control wrapper generates packets based on GPIO configuration information sent from the master device using a different communication method than GPIO communication.

[0230] (7) Based on the communication equipment in (6), where

[0231] GPIO configuration information includes at least one of the following: information about the sampling frequency of the GPIO signal, GPIO pin configuration information, GPIO configuration information, or information about the data length of the sampled data item.

[0232] (8) Based on the communication equipment in (6), where

[0233] The wrapper generates a first GPIO packet including header information, which includes at least one of the following: sampling mode information, sampling frequency information, GPIO pin setting information, GPIO configuration information, or data length information.

[0234] (9) According to the communication equipment in (8), where

[0235] GPIO configuration information includes the number of pins for implementing GPIO communication, GPIO pin settings, and time slots for storing GPIO communication information.

[0236] (10) The communication equipment according to (8) or (9), wherein

[0237] Before a packet containing the sampled data items is sent to the corresponding communication device, the wrapper generates a first GPIO packet that does not include the sampled data items but includes header information.

[0238] (11) The communication equipment according to (8) or (9), wherein

[0239] The wrapper generates at least one of the following: a first GPIO packet that does not include the sampled data items but includes header information, a first GPIO packet that includes both header information and the sampled data items, or a first GPIO packet that does not include header information but includes the sampled data items.

[0240] (12) According to the communication equipment in (11), where

[0241] The wrapper adds at least one of the timestamp information or error detection information to the first GPIO group.

[0242] (13) A communication device according to any one of (1) to (12), wherein

[0243] The communication protocol includes the communication protocol for the TDD (Time Division Duplex) communication method; and

[0244] The unit period is equal to one frame period of the TDD communication method.

[0245] (14) A communication device, comprising:

[0246] PHY (Physical Layer) receives transmission signals from the corresponding communication device that follow a predetermined communication protocol;

[0247] LINK (link layer) separates the first GPIO packet, including timing control commands, from the transmitted signal;

[0248] The controller determines the starting point based on time control commands; and

[0249] The decapsulator determines whether the sampling mode information in the header information included in the first GPIO packet is set to a first mode or a second mode, converts the first GPIO packet into a first GPIO signal, and sends the first GPIO signal to the slave device. The first mode indicates that it includes all sampled data items obtained by sampling the GPIO (General Purpose Input / Output) signal of the transmitting autonomous device at a fixed sampling period. The second mode indicates that it includes sampled data items obtained by sampling the GPIO signal at a sampling interval corresponding to the frequency of the logical change of the GPIO signal and information about the sampling position.

[0250] (15) According to the communication equipment in (14), where

[0251] In the first mode, one or more sampled data items are included in a first GPIO group. The decapsulator reproduces the first GPIO signal by assigning the sampled data items included in the first GPIO group to the corresponding sampled data items sampled each time a sampling period elapses from the start point; and

[0252] In the second mode, one or more sampled data items are included in a first GPIO group in association with first time information indicating the corresponding sampling timing. The decapsulator reproduces the first GPIO signal by repeating the following process: allocating sampled data items corresponding to the first time information at the sampling timing indicated by the first time information, and then allocating the same sampled data items during the sampling period until the next sampling timing indicated by the first time information included in the first GPIO group.

[0253] (16) The communication equipment according to (14) or (15) includes:

[0254] A second timer that outputs time information synchronized with a first timer included in the master device, wherein

[0255] The decapsulator includes a memory that stores the first GPIO signal;

[0256] The first GPIO packet includes timestamp information regarding the timing of the output of the first GPIO signal; and

[0257] When the timestamp information is set to a first value, the decapsulator sends the first GPIO signal to the slave device without storing the first GPIO signal in memory. When the timestamp information is set to a second value, the decapsulator stores the first GPIO signal in memory. When the second timer time information matches the time information inserted after the timestamp information in the first GPIO packet, the decapsulator reads the first GPIO signal from memory and sends the first GPIO channel to the slave device.

[0258] (17) A communication device according to any one of (14) to (16), comprising:

[0259] An encapsulator for generating a second GPIO group, the second GPIO group including sampled data items and information about the sampling position obtained by sampling a second GPIO signal provided from the device at a sampling interval corresponding to a fixed sampling period or a sampling interval corresponding to the frequency of a logical change in the GPIO signal, starting from the starting point.

[0260] (18) According to the communication equipment in (17), where

[0261] In the first mode, the wrapper generates a second GPIO packet comprising all sampled data items obtained by sampling the second GPIO signal received from the device according to the sampling period, starting from the starting point; and

[0262] In the second mode, when the value of the sampled data item obtained by the first sampling timing is not equal to the value of the sampled data item obtained by the second sampling timing, which is later than the first sampling timing, the wrapper generates a second GPIO packet that includes the sampled data item obtained by the second sampling timing and time information indicating the second sampling timing.

[0263] (19) A communication device according to any one of (14) to (18), wherein

[0264] Before communication with the slave device begins, the controller controls the input / output of the GPIO pins based on the GPIO pin configuration information sent from the master device via the corresponding communication device.

[0265] (20) A communication device according to any one of (14) to (19), wherein

[0266] The header information includes at least one of the following: sampling frequency information, GPIO pin setting information, GPIO configuration information, or information about the data length of the sampled data item.

[0267] (21) A communication device according to any one of (14) to (20), wherein

[0268] The communication protocol includes the communication protocol of the TDD (Time Division Duplex) communication method.

[0269] (22) A communication system, comprising:

[0270] The master SerDes and the slave SerDes communicate serially between them via a predetermined communication protocol.

[0271] The leading SerDes include:

[0272] The first controller determines the timestamp that will be used as the starting point and the unit period of that timestamp starting from that starting point;

[0273] The first wrapper generates a first GPIO (General Purpose Input / Output) packet, which includes all sampled data items obtained by sampling the GPIO signal of the autonomous device from the starting point in sync with the timestamp at a fixed sampling period, or by sampling at a sampling interval corresponding to the frequency of a logical change in the GPIO signal and information about the sampling position.

[0274] The first LINK (link layer) generates an uplink packet including the first GPIO packet; and

[0275] The first PHY (physical layer) sends transmission signals, including uplink packets and following a predetermined communication protocol, to the corresponding communication device.

[0276] Subordinate SerDes include:

[0277] The second PHY (physical layer) receives transmission signals that follow a predetermined communication protocol from the corresponding communication device;

[0278] The second LINK (link layer) separates the second GPIO packet, which includes timing control commands, from the transmitted signal;

[0279] The second controller determines the starting point based on time control commands; and

[0280] The first decapsulator determines whether the sampling mode information in the header information included in the second GPIO packet is set to a first mode or a second mode, converts the second GPIO packet into a second GPIO signal, and sends the second GPIO signal to the slave device. The first mode indicates that it includes all sampled data items obtained by sampling the second GPIO signal of the sending slave device according to a fixed sampling period. The second mode indicates that it includes sampled data items obtained by sampling the second GPIO signal at a sampling interval corresponding to the frequency of the logical change of the GPIO signal and information about the sampling position.

[0281] (23) A communication method for implementing serial communication between a master SerDes and a subordinate SerDes via a predetermined communication protocol, wherein

[0282] Dominant SerDes:

[0283] Determine the timestamp that will be used as the starting point and the unit period of that timestamp starting from that starting point;

[0284] Generate a first GPIO packet, which includes all sampled data items obtained by sampling the GPIO signal of the autonomous device from the starting point at a fixed sampling period synchronized with the timestamp, or by sampling at a sampling interval corresponding to the frequency of logical change of the GPIO signal and information about the sampling position;

[0285] Generate an uplink packet including the first GPIO packet; and

[0286] The transmission signal, including uplink packets and following a predetermined communication protocol, is sent to the subordinate SerDes; and

[0287] Subordinate to SerDes:

[0288] Receive transmission signals that follow a predetermined communication protocol from the corresponding communication device;

[0289] Separate the second GPIO packet containing the timing control command from the transmitted signal;

[0290] The second controller determines the starting point based on time control commands; and

[0291] Determine whether the sampling mode information in the header information included in the second GPIO packet is set to a first mode or a second mode, convert the second GPIO packet into a second GPIO signal, and send the second GPIO signal to the slave device. The first mode indicates that it includes all sampled data items obtained by sampling the second GPIO signal provided by the autonomous device at a fixed sampling period. The second mode indicates that it includes sampled data items obtained by sampling the second GPIO signal at a sampling interval corresponding to the frequency of the logical change of the GPIO signal and information about the sampling position.

[0292] This disclosure is not limited to the embodiments described above, and includes many modifications that can be conceived by those skilled in the art. The effects of this disclosure are also not limited to the foregoing description. That is, many additions, changes, and partial deletions can be made within the conceptual ideas and purposes of this disclosure derived from the content set forth in the claims and their equivalents.

[0293] List of reference numerals

[0294] 1: Communication System

[0295] 6: Transmission Path

[0296] 10: Main equipment

[0297] 11: Controller

[0298] 12: Timer

[0299] 13: Input / Output Buffer

[0300] 21: Controller

[0301] 22: Timer

[0302] 23: Input / Output Buffer

[0303] 51: Enc Core

[0304] 52: Encoder

[0305] 53: Sampler

[0306] 61: DeEnc Core

[0307] 62: Decoder

[0308] 63: Memory

[0309] 64: Selector

[0310] 100: M_SerDes

[0311] 101: Controller

[0312] 102: Timer

[0313] 103: Input / Output Buffer

[0314] 110: PHY

[0315] 120: LINK

[0316] 150: Packager

[0317] 160: Decapsulator

[0318] 160: Decapsulator

[0319] 200: S_SerDes

[0320] 201: Controller

[0321] 202: Timer

[0322] 203: Input / Output Buffer

[0323] 204: Input / Output Buffer

[0324] 210: PHY

[0325] 220: LINK

[0326] 250: Packager

[0327] 260: Decapsulator

[0328] 270: I2C controller

[0329] 400: M_SerDes

[0330] 401: Controller

[0331] 402: Timer

[0332] 450: Packager

[0333] 500: S_SerDes

[0334] 501: Controller

[0335] 502: Timer

Claims

1. A communication device, comprising: The controller determines the timestamp that will be used as the starting point and the unit period of that timestamp starting from that starting point; The wrapper generates a first GPIO (General Purpose Input / Output) packet, which includes all sampled data items obtained by sampling the GPIO signals of the autonomous device from the starting point at a fixed sampling period in sync with the timestamp, or information about the sampling position; LINK generates an uplink packet including the first GPIO packet; and The PHY transmits signals, including uplink packets and following a predetermined communication protocol, to the corresponding communication device. The controller receives GPIO configuration information from the master device. This GPIO configuration information includes the sampling period, timestamp, and sampling mode information to specify the first or second mode. In the first mode, the wrapper generates a first GPIO packet comprising all sampled data items obtained by sampling the first GPIO signal of the receiving autonomous device according to the sampling period starting from the starting point, and In the second mode, when the value of the sampled data item obtained by the first sampling timing is not equal to the value of the sampled data item obtained by the second sampling timing, which is later than the first sampling timing, the wrapper generates a first GPIO packet including first time information indicating the second sampling timing.

2. The communication device according to claim 1, further comprising: The second GPIO signal is reproduced and sent to the master device's decapsulator, whereby... The PHY receives transmission signals that follow a predetermined communication protocol from the corresponding communication device; LINK separates the second GPIO packet from the transmitted signal; The decapsulator reconstructs the second GPIO signal based on the sampling mode information, the starting point, the sampling period, and the second GPIO group. In the first mode, one or more sampled data items are included in a second GPIO group. The decapsulator reproduces the second GPIO signal by assigning the sampled data items included in the second GPIO group to the corresponding sampled data items sampled each time a sampling period elapses from the start point; and In the second mode, one or more sampled data items are included in a second GPIO group in association with second time information indicating the corresponding sampling timing. The decapsulator reproduces the second GPIO signal by repeating the following process: allocating sampled data items corresponding to the second time information at the sampling timing indicated by the second time information, and then allocating the same sampled data items during the sampling period until the next sampling timing indicated by the second time information included in the second GPIO group.

3. The communication device according to claim 2, comprising: A second timer that outputs time information synchronized with a first timer included in the master device, wherein The decapsulator includes a memory that stores the second GPIO signal; The second GPIO packet includes timestamp information regarding the timing of the second GPIO signal output; and When the timestamp information is set to the first value, the decapsulator sends the second GPIO signal to the master device without storing the second GPIO signal in the memory. When the timestamp information is set to the second value, the decapsulator stores the second GPIO signal in the memory. When the second timer time information matches the time information inserted after the timestamp information in the second GPIO packet, the second GPIO signal is read from the memory and the second GPIO channel is sent to the master device.

4. The communication device according to claim 1, wherein Before GPIO communication with the master device begins, the controller control wrapper generates packets based on GPIO configuration information sent from the master device using a different communication method than GPIO communication.

5. The communication device according to claim 4, wherein GPIO configuration information includes at least one of the following: information about the sampling frequency of the GPIO signal, GPIO pin configuration information, GPIO configuration information, or information about the data length of the sampled data item.

6. The communication device according to claim 5, wherein The wrapper generates a first GPIO packet including header information, which includes at least one of the following: sampling mode information, sampling frequency information, GPIO pin setting information, GPIO configuration information, or data length information.

7. The communication device according to claim 6, wherein GPIO configuration information includes the number of pins for implementing GPIO communication, GPIO pin settings, and time slots for storing GPIO communication information.

8. The communication device according to claim 6, wherein Before a packet containing the sampled data items is sent to the corresponding communication device, the wrapper generates a first GPIO packet that does not include the sampled data items but includes header information.

9. The communication device according to claim 6, wherein The wrapper generates at least one of the following: a first GPIO packet that does not include the sampled data items but includes header information, a first GPIO packet that includes both header information and the sampled data items, or a first GPIO packet that does not include header information but includes the sampled data items.

10. The communication device according to claim 9, wherein The wrapper adds at least one of the timestamp information or error detection information to the first GPIO group.

11. The communication device according to claim 1, wherein The communication protocol includes the communication protocol for the TDD (Time Division Duplex) communication method; and The unit period is equal to one frame period of the TDD communication method.

12. A communication device, comprising: PHY receives transmission signals from the corresponding communication device that follow a predetermined communication protocol; LINK separates the first GPIO packet, which includes timing control commands, from the transmitted signal; The controller determines the starting point based on time control commands; as well as The decapsulator determines whether the sampling mode information in the header information included in the first GPIO packet is set to a first mode or a second mode, converts the first GPIO packet into a first GPIO signal, and sends the first GPIO signal to the slave device. The first mode indicates that it includes all sampled data items obtained by sampling the GPIO (General Purpose Input / Output) signals of the transmitting autonomous device at a fixed sampling period, and the second mode indicates information about the sampling position. In the first mode, the wrapper generates a second GPIO packet comprising all sampled data items obtained by sampling the second GPIO signal received from the device according to the sampling period, starting from the starting point; and In the second mode, when the value of the sampled data item obtained by the first sampling timing is not equal to the value of the sampled data item obtained by the second sampling timing, which is later than the first sampling timing, the wrapper generates a second GPIO packet that includes timing information indicating the second sampling timing.

13. The communication device according to claim 12, wherein In the first mode, one or more sampled data items are included in a first GPIO group. The decapsulator reproduces the first GPIO signal by assigning the sampled data items included in the first GPIO group to the corresponding sampled data items sampled each time a sampling period elapses from the start point; and In the second mode, one or more sampled data items are included in a first GPIO group in association with first time information indicating the corresponding sampling timing, and the decapsulator reproduces the first GPIO signal by repeating the following process: allocating sampled data items corresponding to the first time information at the sampling timing indicated by the first time information, and then allocating the same sampled data items during the sampling period until the next sampling timing indicated by the first time information included in the first GPIO group.

14. The communication device according to claim 12, comprising: A second timer that outputs time information synchronized with a first timer included in the master device, wherein The decapsulator includes a memory that stores the first GPIO signal; The first GPIO packet includes timestamp information regarding the timing of the output of the first GPIO signal; and When the timestamp information is set to a first value, the decapsulator sends the first GPIO signal to the slave device without storing the first GPIO signal in memory. When the timestamp information is set to a second value, the decapsulator stores the first GPIO signal in memory. When the second timer time information matches the time information inserted after the timestamp information in the first GPIO packet, the first GPIO signal is read from memory and the first GPIO channel is sent to the slave device.

15. The communication device according to claim 12, comprising: An encapsulator for generating a second GPIO group, the second GPIO group including sampled data items and information about the sampling position obtained by sampling a second GPIO signal provided from the device at a sampling interval corresponding to a fixed sampling period or a sampling interval corresponding to the frequency of a logical change in the GPIO signal, starting from the starting point.

16. The communication device according to claim 12, wherein Before communication with the slave device begins, the controller controls the input / output of the GPIO pins based on the GPIO pin configuration information sent from the master device via the corresponding communication device.

17. The communication device according to any one of claims 12 to 16, wherein The header information includes at least one of the following: sampling frequency information, GPIO pin setting information, GPIO configuration information, or information about the data length of the sampled data item.

18. The communication device according to claim 12, wherein The communication protocol includes the communication protocol of the TDD (Time Division Duplex) communication method.

19. A communication system, comprising: The dominant SerDes and subordinate SerDes communicate serially between them via a predetermined communication protocol. The leading SerDes include: The first controller determines the timestamp that will be used as the starting point and the unit period of that timestamp starting from that starting point; The first wrapper generates a first GPIO (General Purpose Input / Output) packet, which includes all sampled data items obtained by sampling the GPIO signals of the autonomous device from the starting point at a fixed sampling period in sync with the timestamp, or information about the sampling position; The first LINK generates an uplink packet including the first GPIO packet; and The first PHY sends transmission signals, including uplink packets and following a predetermined communication protocol, to the corresponding communication device. The first controller receives GPIO configuration information from the master device. This GPIO configuration information includes the sampling period, timestamp, and sampling mode information to specify the first or second mode. In the first mode, the first wrapper generates a first GPIO packet comprising all sampled data items obtained by sampling the first GPIO signal of the receiving autonomous device according to the sampling period starting from the starting point, and In the second mode, when the value of the sampled data item obtained by the first sampling timing is not equal to the value of the sampled data item obtained by the second sampling timing, which is a sampling period later than the first sampling timing, the first wrapper generates a first GPIO packet including first time information indicating the second sampling timing. Subordinate SerDes include: The second PHY receives transmission signals that follow a predetermined communication protocol from the corresponding communication device; The second LINK separates the second GPIO packet, which includes timing control commands, from the transmitted signal; The second controller determines the starting point based on time control commands; and The first decapsulator determines whether the sampling mode information in the header information included in the second GPIO packet is set to a first mode or a second mode, converts the second GPIO packet into a second GPIO signal, and sends the second GPIO signal to the slave device. The first mode indicates that it includes all sampled data items obtained by sampling the second GPIO signal of the sending slave device according to a fixed sampling period. The second mode indicates that it includes sampled data items obtained by sampling the second GPIO signal at a sampling interval corresponding to the frequency of the logical change of the GPIO signal and information about the sampling position.

20. A communication method for implementing serial communication between a master SerDes and a slave SerDes via a predetermined communication protocol, wherein... Dominant SerDes: Determine the timestamp that will be used as the starting point and the unit period of that timestamp starting from that starting point; Generate a first GPIO packet, which includes all sampled data items obtained by sampling the GPIO signals of the autonomous device from the starting point at a fixed sampling period in sync with the timestamp, or information about the sampling position. Generate an uplink packet that includes the first GPIO packet; The transmission signal, which includes uplink packets and follows a predetermined communication protocol, is sent to the slave SerDes; Receive GPIO configuration information from the master device. This GPIO configuration information includes the sampling period, timestamp, and sampling mode information to specify the first or second mode. In the first mode, a first GPIO packet is generated, comprising all sampled data items obtained by sampling the first GPIO signal of the receiving autonomous device according to the sampling period starting from the starting point, and In the second mode, when the value of a sampled data item obtained at the first sampling timing is not equal to the value of a sampled data item obtained at the second sampling timing, which is a sampling period later than the first sampling timing, a first GPIO packet including first time information indicating the second sampling timing is generated; and Subordinate to SerDes: Receive transmission signals that follow a predetermined communication protocol from the corresponding communication device; Separate the second GPIO packet containing the timing control command from the transmitted signal; The starting point is determined based on time control commands; as well as Determine whether the sampling mode information in the header information included in the second GPIO packet is set to a first mode or a second mode, convert the second GPIO packet into a second GPIO signal, and send the second GPIO signal to the slave device. The first mode indicates that it includes all sampled data items obtained by sampling the second GPIO signal provided by the autonomous device at a fixed sampling period. The second mode indicates that it includes sampled data items obtained by sampling the second GPIO signal at a sampling interval corresponding to the frequency of the logical change of the GPIO signal and information about the sampling position.

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