A circuit for reducing static power consumption of an LDO

Abstract

The application discloses a circuit for reducing LDO static power consumption, which comprises a first amplifier for generating a first control signal according to a first reference signal and a first sampling signal; a first comparator for generating a second control signal according to a second sampling signal and a second reference signal; a second amplifier for generating a third control signal according to the first control signal; a power tube M3 for setting an output voltage of a circuit output end according to the third control signal; and an output sampling module for generating a first sampling signal and a second sampling signal related to the output voltage according to the voltage of the circuit output end; when the LDO input voltage is lower than the sum of the output voltage and a minimum voltage difference, the output voltage will decrease with the decrease of the input voltage; wherein when the output voltage is lower than an output voltage threshold value, the second control signal is a logic high level, and the MOS tube M2 is closed, so as to reduce the static current of the second amplifier to zero, thereby avoiding the problem of the increase of the static current when the input voltage is lower than the sum of the output voltage and the minimum voltage difference.

Description

Technical Field

[0001] This invention belongs to the field of low-power power management chip technology, and relates to a circuit for reducing the static power consumption of a low-dropout regulator (LDO). Background Technology

[0002] Power management integrated circuits are responsible for the conversion, distribution, detection, and other power management of electrical energy in electronic equipment systems. Their main responsibility is to convert source voltage and current into power that can be used by loads such as microprocessors and sensors. As a major component of power management integrated circuits, the low-dropout linear regulator can have an input voltage that is slightly higher than the output VOUT by a certain range. In other words, the output VOUT of a low-dropout linear regulator can be stabilized at a fixed value.

[0003] Please see Figure 1 , Figure 1 The diagram shows a typical low static power LDO circuit. Figure 1 As shown, the circuit may include a circuit input terminal, a circuit output terminal, a ground terminal, a first amplifier, a second amplifier, a power transistor M3, and an output sampling module for outputting a sampling signal.

[0004] In this configuration, one input terminal of the first amplifier is connected to a reference signal, and the other input terminal is connected to the output terminal of the output sampling module. The output terminal of the first amplifier is connected to the input terminal of the second amplifier, and is used to generate a first control signal based on the sampled signal and the reference signal. The other input terminal of the second amplifier is connected to the output terminal of the first amplifier, and the output terminal is connected to the gate of the power transistor M3, and is used to generate a second control signal based on the first control signal. The source of the power transistor M3 is connected to the input terminal, the drain is connected to the output terminal, and the gate is connected to the output terminal of the second amplifier, and is used to set the output voltage of the circuit output terminal based on the second control signal. The output sampling module is connected between the output terminal and the ground terminal, and the output terminal is connected to one input terminal of the first amplifier, and is used to generate a sampling signal related to the output voltage of the circuit output terminal based on the output voltage.

[0005] Furthermore, the second amplifier may include a MOS transistor M1 and a current sampling unit. The gate of the MOS transistor M1 is connected to the input terminal of the second amplifier, the source is grounded, and the drain is connected to the output terminal of the second amplifier. The current sampling unit is connected to the input terminal and the output terminal of the second amplifier and is used to generate a mirror current based on the current of the power transistor M3.

[0006] Please refer to Figure 2 , Figure 2 As shown Figure 1 A graph showing the relationship between quiescent current and input voltage in existing technologies. (Example:) Figure 2 As shown, when the input voltage is higher than the sum of the output voltage and the minimum voltage difference of the LDO, the static power consumption is very small; when the input voltage is lower than the sum of the output voltage and the minimum voltage difference of the LDO, the static current first increases to a peak value as the input voltage decreases and then decreases as the input voltage decreases.

[0007] Those skilled in the art will understand that static power consumption is the product of static current and input voltage. The reason why the static power consumption of the prior art increases sharply when the input voltage is lower than the preset output voltage is that when the input voltage is lower than the preset output voltage, the power transistor M3 is in the linear region and the current sampling unit is in the saturation region, which will lead to image mismatch of the current sampling unit.

[0008] Therefore, when the input voltage is lower than the preset voltage, if the static current becomes tens or even hundreds of times greater than the preset value when the input voltage is higher, this will result in very high static power consumption. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention proposes a circuit for reducing the static power consumption of an LDO, thus solving the problem of increased static power consumption in existing technologies when the input voltage is less than the sum of the output voltage and the minimum voltage difference of the LDO.

[0010] To achieve the above objectives, the technical solution of the present invention is as follows:

[0011] A circuit for reducing the static power consumption of an LDO includes a circuit input terminal, a circuit output terminal, and a ground terminal; characterized in that it further includes a first amplifier, a first comparator, a MOSFET M2, a second amplifier, a power transistor M3, and an output sampling module; wherein,

[0012] One input terminal of the first amplifier receives a first reference signal, and the other input terminal is connected to the first sampled signal output terminal of the output sampling module. The output terminal is connected to one input terminal of the second amplifier. The amplifier is used to generate a first control signal based on the first reference signal and the first sampled signal. When the first sampled signal is lower than the first reference signal, the first control signal increases. When the first sampled signal is higher than the first reference signal, the first control signal decreases.

[0013] One input terminal of the first comparator is connected to the second reference signal, the other input terminal is connected to the second sampling signal output terminal of the output sampling circuit, and the output terminal is connected to the gate of the MOS transistor M2, which is used to generate a second control signal based on the second sampling signal and the second reference signal;

[0014] The source of the MOS transistor M2 is connected to the circuit input terminal, the drain is connected to the other input terminal of the second amplifier, and the gate is connected to the output terminal of the first comparator.

[0015] The second amplifier, whose output terminal is connected to the gate of the power transistor M3, is used to generate a third control signal according to the first control signal; when the first control signal increases, the third control signal decreases; when the first control signal decreases, the third control signal increases.

[0016] The source of the power transistor M3 is connected to the input terminal of the circuit, the drain is connected to the output terminal of the circuit, and the gate is connected to the output terminal of the second amplifier; it is used to set the output voltage of the circuit output terminal according to the third control signal; when the third control signal increases, the output voltage of the circuit output terminal decreases; when the third control signal decreases, the output voltage of the circuit output terminal increases.

[0017] The output sampling module is connected between the circuit output terminal and the ground terminal. One output terminal is connected to one input terminal of the first amplifier, and the other output terminal is connected to one input terminal of the first comparator. It is used to generate a first sampling signal and a second sampling signal related to the output voltage based on the voltage of the circuit output terminal.

[0018] When the input voltage is lower than the sum of the output voltage and the minimum voltage difference of the LDO, the output voltage will decrease as the input voltage decreases.

[0019] When the output voltage is higher than the output voltage threshold, the second control signal is at a logic low level, the MOSFET M2 is turned on, and the second-stage amplifier operates normally; when the output voltage is lower than the output voltage threshold, the second control signal is at a logic high level, the MOSFET M2 is turned off, and the quiescent current of the second amplifier is reduced to zero.

[0020] Furthermore, the second amplifier includes a MOS transistor M1 and a current sampling unit. The gate of the MOS transistor M1 is connected to the output terminal of the first amplifier, the source is connected to the ground terminal, and the drain is connected to the gate of the power transistor M3. The current sampling circuit is connected between the drain of the MOS transistor M2 and the gate of the power transistor M3 to generate a mirror current based on the current of the power transistor M3.

[0021] Furthermore, the first sampling signal is output voltage / A, where A is a number not less than 1; the second sampling signal is output voltage / B, where B is another number not less than 1;

[0022] By adjusting the output sampling circuit, the first amplifier, the second amplifier, and the power transistor M3, the output voltage is generated as: (first reference signal + VOS1) * A

[0023] Wherein, VOS1 is the offset voltage of the first amplifier;

[0024] An output voltage threshold is set using the first comparator as follows:

[0025] (Second reference signal + VOS2)*B;

[0026] Wherein, VOS2 is the offset voltage of the first comparator;

[0027] Furthermore, the circuit for reducing the static power consumption of the LDO also includes a resistor R2, one end of which is connected to the input terminal and the other end is connected to the drain of the MOS transistor M2, for controlling the static current of the second amplifier.

[0028] As can be seen from the above technical solution, although the charging cutoff is not determined by detecting the current, the present invention reduces the static power consumption when the input voltage is less than the sum of the output voltage and the minimum voltage difference of the LDO to be comparable to the static power consumption when the input voltage is greater than the preset output voltage. Attached Figure Description

[0029] Figure 1 The diagram shown is a schematic of a traditional low static power LDO circuit.

[0030] Figure 2 As shown Figure 1 Relationship between static current and input voltage in existing technologies

[0031] Figure 3 The diagram shown is a circuit schematic for reducing the static power consumption of an LDO in an embodiment of the present invention.

[0032] Figure 4 As shown Figure 3 The schematic diagram shown in the embodiment illustrates the relationship between quiescent current and input voltage.

[0033] Figure 5 The diagram shown is a schematic diagram of another preferred embodiment of the circuit for reducing the static power consumption of an LDO according to the present invention. Detailed Implementation

[0034] The following is in conjunction with the appendix Figure 3-5 The specific embodiments of the present invention will be described in further detail below.

[0035] Example 1

[0036] Please see Figure 3 , Figure 3 The diagram shown is a schematic of a circuit for reducing the static power consumption of an LDO in an embodiment of the present invention. Figure 3 As shown, it includes a circuit input terminal, a circuit output terminal, and a ground terminal; its characteristic is that it also includes a first amplifier, a first comparator, a MOS transistor M2, a second amplifier, a power transistor M3, and an output sampling module.

[0037] Wherein, one input terminal of the first amplifier receives a first reference signal, the other input terminal is connected to the first sampling signal output terminal of the output sampling module, and the output terminal is connected to one input terminal of the second amplifier, for generating a first control signal based on the first reference signal and the first sampling signal; when the first sampling signal is lower than the first reference signal, the first control signal increases; when the first sampling signal is higher than the first reference signal, the first control signal decreases.

[0038] One input terminal of the first comparator is connected to a second reference signal, and the other input terminal is connected to the second sampling signal output terminal of the output sampling circuit. The output terminal is connected to the gate of the MOS transistor M2, and is used to generate a second control signal based on the second sampling signal and the second reference signal. The source of the MOS transistor M2 is connected to the circuit input terminal, the drain is connected to another input terminal of the second amplifier, and the gate is connected to the output terminal of the first comparator. The output terminal of the second amplifier is connected to the gate of the power transistor M3, and is used to generate a third control signal based on the first control signal. When the first control signal increases, the third control signal decreases; when the first control signal decreases, the third control signal increases.

[0039] The source of the power transistor M3 is connected to the input terminal of the circuit, the drain is connected to the output terminal of the circuit, and the gate is connected to the output terminal of the second amplifier; it is used to set the output voltage of the circuit output terminal according to the third control signal; when the third control signal increases, the output voltage of the circuit output terminal decreases; when the third control signal decreases, the output voltage of the circuit output terminal increases.

[0040] The output sampling module is connected between the output terminal and the ground terminal of the circuit. One output terminal is connected to an input terminal of the first amplifier, and the other output terminal is connected to an input terminal of the first comparator. It is used to generate a first sampling signal and a second sampling signal related to the output voltage based on the voltage of the output terminal of the circuit.

[0041] It should be noted that, preferably, the first sampling signal is the circuit's output voltage / A, where A can be a number greater than or equal to 1; the second sampling signal is the circuit's output voltage / B, where B can be a number greater than or equal to 1, and A can be equal to B or not equal to B.

[0042] By adjusting the output sampling circuit, the first amplifier, the second amplifier, and the power transistor M3, the output voltage is generated as: (first reference signal + VOS1) * A

[0043] Wherein, VOS1 is the offset voltage of the first amplifier;

[0044] The output voltage threshold of a circuit is set by the first comparator as follows:

[0045] (Second reference signal + VOS2)*B;

[0046] Wherein, VOS2 is the offset voltage of the first comparator;

[0047] In other words, when the input voltage at the circuit input terminal is lower than the set output voltage, the second control signal turns off the second-stage amplifier and adjusts the conduction capability of the MOS transistor M2 to reduce the quiescent current of the second amplifier; at the same time, the gate of the power transistor M3 is pulled low to ensure that the output voltage can follow the change of the input voltage.

[0048] In an embodiment of the present invention, the second amplifier includes a MOS transistor M1 and a current sampling unit. The gate of the MOS transistor M1 is connected to the output terminal of the first amplifier, the source is connected to the ground terminal, and the drain is connected to the gate of the power transistor M3. The current sampling circuit is connected between the drain of the MOS transistor M2 and the gate of the power transistor M3, and is used to generate a mirror current based on the current of the power transistor M3.

[0049] Please see Figure 4 , Figure 4 As shown Figure 3 The diagram illustrates the relationship between quiescent current and input voltage in the illustrated embodiment. Figure 4 As shown in the diagram, the relationship between the static current and the input voltage of the present invention is such that when the input voltage of the circuit is higher than the preset output voltage of the circuit, the static power consumption is very small. When the input voltage of the circuit is lower than the preset output voltage of the circuit, the static current does not increase sharply as the input voltage decreases, but decreases as the input voltage of the circuit decreases.

[0050] In other words, in the embodiments of the present invention, when the input voltage of the circuit is lower than the output voltage of the preset circuit, the second-stage amplifier is turned off or the current of the second-stage amplifier is limited to avoid the increase of static current caused by the mirror mismatch of the current sampling circuit when the input voltage of the circuit is lower than the output voltage of the preset circuit, thereby achieving the effect of reducing static current. At the same time, the gate of the power transistor M3 is pulled low to ensure that the output voltage of the circuit can follow the changes of the input voltage of the circuit.

[0051] Example 2

[0052] Please see Figure 5 , Figure 5The diagram shown is a preferred embodiment of the solar cell charging circuit of the present invention. In this embodiment, the circuit for reducing the static power consumption of the LDO may include a circuit input terminal, a circuit output terminal and a ground terminal, a first amplifier, a first comparator, a MOS transistor M2, a second amplifier, a power transistor M3 and an output sampling module, and may also include a resistor R2. One end of the resistor R2 is connected to the input terminal and the other end is connected to the drain of the MOS transistor M2, for controlling the static current of the second amplifier.

[0053] Wherein, one input terminal of the first amplifier receives a first reference signal, the other input terminal is connected to the first sampling signal output terminal of the output sampling module, and the output terminal is connected to one input terminal of the second amplifier, for generating a first control signal based on the first reference signal and the first sampling signal; when the first sampling signal is lower than the first reference signal, the first control signal increases; when the first sampling signal is higher than the first reference signal, the first control signal decreases.

[0054] One input terminal of the first comparator is connected to a second reference signal, and the other input terminal is connected to the second sampling signal output terminal of the output sampling circuit. The output terminal is connected to the gate of the MOS transistor M2, and is used to generate a second control signal based on the second sampling signal and the second reference signal. The source of the MOS transistor M2 is connected to the circuit input terminal, the drain is connected to another input terminal of the second amplifier, and the gate is connected to the output terminal of the first comparator. The output terminal of the second amplifier is connected to the gate of the power transistor M3, and is used to generate a third control signal based on the first control signal. When the first control signal increases, the third control signal decreases; when the first control signal decreases, the third control signal increases.

[0055] The source of the power transistor M3 is connected to the input terminal of the circuit, the drain is connected to the output terminal of the circuit, and the gate is connected to the output terminal of the second amplifier; it is used to set the output voltage of the circuit output terminal according to the third control signal; when the third control signal increases, the output voltage of the circuit output terminal decreases; when the third control signal decreases, the output voltage of the circuit output terminal increases.

[0056] The output sampling module is connected between the output terminal and the ground terminal of the circuit. One output terminal is connected to an input terminal of the first amplifier, and the other output terminal is connected to an input terminal of the first comparator. It is used to generate a first sampling signal and a second sampling signal related to the output voltage based on the voltage of the output terminal of the circuit.

[0057] It should be noted that, preferably, the first sampling signal is the circuit's output voltage / A, where A can be a number greater than or equal to 1; the second sampling signal is the circuit's output voltage / B, where B can be a number greater than or equal to 1, and A can be equal to B or not equal to B.

[0058] By adjusting the output sampling circuit, the first amplifier, the second amplifier, and the power transistor M3, the output voltage is generated as: (first reference signal + VOS1) * A

[0059] Wherein, VOS1 is the offset voltage of the first amplifier;

[0060] The output voltage threshold of a circuit is set by the first comparator as follows:

[0061] (Second reference signal + VOS2)*B;

[0062] Wherein, VOS2 is the offset voltage of the first comparator;

[0063] In other words, in the embodiments of the present invention, when the input voltage of the second control signal at the circuit input terminal is lower than the set output voltage, the resistor R2 is used to further control the quiescent current of the second amplifier. That is, when the MOS transistor M2 is turned off, the current from the circuit input terminal flows into the second amplifier through the resistor R2, limiting the current of the second-stage amplifier and adjusting the conduction capability of the MOS transistor M2 to reduce the quiescent current of the second amplifier; at the same time, the gate of the power transistor M3 is pulled low to ensure that the output voltage can follow the change of the input voltage.

[0064] In an embodiment of the present invention, the second amplifier includes a MOS transistor M1 and a current sampling unit. The gate of the MOS transistor M1 is connected to the output terminal of the first amplifier, the source is connected to the ground terminal, and the drain is connected to the gate of the power transistor M3. The current sampling circuit is connected between the drain of the MOS transistor M2 and the gate of the power transistor M3, and is used to generate a mirror current based on the current of the power transistor M3.

[0065] The above description is merely a preferred embodiment of the present invention. The embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made based on the description and drawings of the present invention should also be included within the scope of protection of the present invention.

Claims

1. A circuit for reducing the static power consumption of an LDO, comprising a circuit input terminal, a circuit output terminal, and a ground terminal; characterized in that, It also includes a first amplifier, a first comparator, a MOSFET M2, a second amplifier, a power transistor M3, and an output sampling module; among which, One input terminal of the first amplifier receives a first reference signal, and the other input terminal is connected to the first sampled signal output terminal of the output sampling module. The output terminal is connected to one input terminal of the second amplifier. The amplifier is used to generate a first control signal based on the first reference signal and the first sampled signal. When the first sampled signal is lower than the first reference signal, the first control signal increases; when the first sampled signal is higher than the first reference signal, the first control signal decreases. One input terminal of the first comparator is connected to the second reference signal, the other input terminal is connected to the second sampling signal output terminal of the output sampling circuit, and the output terminal is connected to the gate of the MOS transistor M2, which is used to generate a second control signal based on the second sampling signal and the second reference signal; The source of the MOS transistor M2 is connected to the circuit input terminal, the drain is connected to the other input terminal of the second amplifier, and the gate is connected to the output terminal of the first comparator. The second amplifier, whose output terminal is connected to the gate of the power transistor M3, is used to generate a third control signal according to the first control signal; when the first control signal increases, the third control signal decreases; when the first control signal decreases, the third control signal increases. The source of the power transistor M3 is connected to the input terminal of the circuit, the drain is connected to the output terminal of the circuit, and the gate is connected to the output terminal of the second amplifier; it is used to set the output voltage of the circuit output terminal according to the third control signal; when the third control signal increases, the output voltage of the circuit output terminal decreases; when the third control signal decreases, the output voltage of the circuit output terminal increases. The output sampling module is connected between the circuit output terminal and the ground terminal. One output terminal is connected to one input terminal of the first amplifier, and the other output terminal is connected to one input terminal of the first comparator. It is used to generate a first sampling signal and a second sampling signal related to the output voltage based on the voltage of the circuit output terminal. When the input voltage of the circuit is lower than the sum of the output voltage of the circuit and the minimum voltage difference of the LDO, the output voltage of the circuit will decrease as the input voltage of the circuit decreases. Specifically, when the output voltage of the circuit is higher than the output voltage threshold of the circuit, the second control signal is at a logic low level, the MOS transistor M2 is turned on, and the second-stage amplifier works normally; when the output voltage of the circuit is lower than the output voltage threshold of the circuit, the second control signal is at a logic high level, the MOS transistor M2 is turned off, and the quiescent current of the second amplifier is reduced to zero.

2. The circuit for reducing LDO static power consumption according to claim 1; characterized in that, The second amplifier includes a MOS transistor M1 and a current sampling unit. The gate of the MOS transistor M1 is connected to the output terminal of the first amplifier, the source is connected to the ground terminal, and the drain is connected to the gate of the power transistor M3. The current sampling unit is connected between the drain of the MOS transistor M2 and the gate of the power transistor M3, and is used to generate a mirror current based on the current of the power transistor M3.

3. The circuit for reducing LDO static power consumption according to claim 1 or 2, characterized in that, The first sampling signal is the output voltage / A at the circuit output terminal, where A is a number not less than 1; the second sampling signal is the output voltage / B, where B is another number not less than 1. By adjusting the output sampling circuit, the first amplifier, the second amplifier, and the power transistor M3, the output voltage at the output terminal of the generating circuit is: (first reference signal + VOS1) * A Wherein, VOS1 is the offset voltage of the first amplifier; An output voltage threshold is set using the first comparator as follows: (Second reference signal + VOS2)*B; Wherein, VOS2 is the offset voltage of the first comparator.

4. The circuit for reducing LDO static power consumption according to claim 3, characterized in that, It also includes a resistor R2, one end of which is connected to the circuit input terminal and the other end is connected to the drain of the MOS transistor M2, which is used to control the quiescent current of the second amplifier.

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