An anti-interference circuit and method for capacitance detection

Abstract

The present invention relates to an anti-interference circuit for capacitance detection, comprising a capacitance to be measured, a clock switch, a quantization unit, an integrator, and a counting unit, wherein the first end of the clock switch is connected to a reference voltage Vref or a common mode voltage Vcm, the second end of the clock switch is connected to the first end of the capacitance to be measured, and the second end of the capacitance to be measured is connected to a ground potential; the first input end of the integrator is connected to the quantization unit; and the counting unit is connected to the output end of the integrator. The present invention offsets low-frequency interference signals through an anti-interference mode, and offsets high-frequency interference signals through a combination of an anti-interference mode and a frequency hopping mode, effectively suppressing external interference signals, and preventing false triggering and non-triggering in capacitive touch applications due to the influence of interference signals.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitance detection, and in particular to an anti-interference circuit and method for capacitance detection. Background Art

[0002] Capacitive touch detection is widely used and its application environment is relatively complex. When detecting capacitance, it is necessary to suppress interference signals in multiple frequency bands. It is difficult to filter them all out by relying solely on digital filters. Especially when the interference signal is large, it will directly affect the performance of the quantization system, which is not handled by the digital filter. Therefore, the circuit needs to have a certain anti-interference mode and frequency hopping mode to avoid the influence of interference signals at specific frequencies, provide more options for digital processing, and ensure the accuracy of capacitive touch detection. Summary of the invention

[0003] The purpose of the present invention is to suppress interference signals of a circuit and to provide an anti-interference circuit and method for capacitance detection.

[0004] In order to achieve the above-mentioned object of the invention, the embodiment of the present invention provides the following technical solutions:

[0005] An anti-interference circuit for capacitance detection includes a capacitance to be measured, a clock switch, a quantization unit, an integrator, and a counting unit, wherein:

[0006] The first end of the clock switch is connected to the reference voltage Vref or the common mode voltage Vcm, the second end of the clock switch is connected to the first end of the capacitor to be measured, and the second end of the capacitor to be measured is connected to the ground potential;

[0007] The first input terminal of the integrator is connected to the quantization unit;

[0008] The counting unit is connected to the output end of the integrator.

[0009] Furthermore, the quantization unit includes a first quantization device and a second quantization device, and the first quantization device and the second quantization device are respectively connected to the first input terminal of the integrator.

[0010] Furthermore, the first quantization device includes a first switch CK_S1 and a first current detector; the first end of the first switch CK_S1 is connected to the first input end of the integrator, the second end of the first switch CK_S1 is connected to the first end of the first current detector, and the second end of the first current detector is connected to the ground.

[0011] Furthermore, the second quantization device includes a second switch CK_S2 and a second current detector; a first end of the second current detector is connected to the power supply AVDD, a second end of the second current detector is connected to the first end of the second switch CK_S2, and a second end of the second switch CK_S2 is connected to the first input end of the integrator.

[0012] Furthermore, the integrator further comprises an integrating capacitor Cint, a first end of the integrating capacitor Cint is connected to the first input end of the integrator, and a second end of the integrating capacitor Cint is connected to the output end of the integrator.

[0013] Furthermore, it also includes a comparator, wherein a first input terminal of the comparator is connected to an output terminal of the integrator, and an output terminal of the comparator is connected to an input terminal of the counting unit.

[0014] An anti-interference method for capacitance detection, applied to any of the above circuits, comprises the following steps:

[0015] Step 1, charging the capacitor to be measured by a reference voltage Vref, and transferring the charge in the capacitor to be measured to an integrating capacitor of an integrator for quantization, thereby obtaining a first quantization number N1;

[0016] Step 2, charging the capacitor to be measured through the common mode voltage Vcm, and transferring the charge in the capacitor to be measured to the integrating capacitor of the integrator for quantization, thereby obtaining a second quantization number N2;

[0017] Step 3, using the first quantization number N1 minus the second quantization number N2 to offset the low-frequency interference signal, or offset the low-frequency interference signal generated by the aliasing of the high-frequency interference signal and the sampling signal;

[0018] Step 4, control the sampling period of the clock switch to adjust the sampling frequency so that the high-frequency interference signal that is not offset in step 3 jumps to the low-frequency interference signal, and then repeat steps 1 to 3, and average the number of quantizations obtained after multiple repetitions to flatten or offset the interference signal amplitude at each frequency.

[0019] Furthermore, the step of obtaining the first quantization number N1 in step 1 includes:

[0020] Control the first quantization device to quantize the charge Qn in the integration capacitor Cint until the charge in the integration capacitor Cint is negative, stop the quantization of the first quantization device, and record the count value of the counting unit as the quantization number n1;

[0021] The process of the first quantization device quantizing the charge Qn on the integration capacitor Cint includes: repeatedly closing the first switch CK_S1 for a period of ∆t and then opening it until the charge on the integration capacitor Cint is negative, and recording the count value of the counting unit as the quantization number n1;

[0022] Control the second quantization device to continue quantizing the charge in the integration capacitor Cint until the charge in the integration capacitor Cint is positive, stop the quantization of the second quantization device, and record the count value of the counting unit as the quantization number n2;

[0023] The process of the second quantization device quantizing the charge on the integration capacitor Cint includes: repeatedly closing the second switch CK_S2 for a period of ∆t and then opening it until the charge on the integration capacitor Cint is positive, and recording the count value of the counting unit as the quantization number n2;

[0024] The quantization order n1 and the quantization order n2 are added to obtain the first quantization order N1.

[0025] Furthermore, before the step of transferring the charge amount in the capacitor to be measured to the integrating capacitor of the integrator for quantization in step 1, the step further includes:

[0026] After the capacitor Cs to be measured is charged by the power supply Vref, the charge amount in the capacitor Cs to be measured is Q, and the capacitor Cs to be measured is compensated. After the compensation, the capacitor Cs to be measured transfers the remaining charge amount Qn to the integration capacitor Cint.

[0027] Furthermore, the step of obtaining the second quantization number N2 in step 2 includes:

[0028] After the capacitor Cs to be measured is charged by the common mode voltage Vcm, the charge amount in the capacitor Cs to be measured is Qf, and the charge amount Qf in the capacitor Cs to be measured is transferred to the integration capacitor Cint for quantization;

[0029] Control the first quantization device to quantize the charge Qf in the integration capacitor Cint until the charge in the integration capacitor Cint is negative, stop the quantization of the first quantization device, and record the count value of the counting unit as the quantization number n3;

[0030] The process of quantizing the charge Qf on the integration capacitor Cint by the first quantization device includes: repeatedly closing the first switch CK_S1 for a time period of ∆t and then opening it until the charge on the integration capacitor Cint is negative, and recording the count value of the counting unit as the quantization number n3;

[0031] Control the second quantization device to continue quantizing the charge in the integration capacitor Cint until the charge in the integration capacitor Cint is positive, stop the quantization of the second quantization device, and record the count value of the counting unit as the quantization number n4;

[0032] The process of the second quantization device quantizing the charge on the integration capacitor Cint includes: repeatedly closing the second switch CK_S2 for a period of ∆t and then opening it until the charge on the integration capacitor Cint is positive, and recording the count value of the counting unit as the quantization number n4;

[0033] The quantization order n3 and the quantization order n4 are added to obtain the second quantization order N2.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] The present invention cancels low-frequency interference signals through an anti-interference mode, and cancels high-frequency interference signals through a combination of an anti-interference mode and a frequency hopping mode, thereby effectively suppressing external interference signals and preventing false triggering and non-triggering in capacitive touch applications due to the influence of interference signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a basic circuit schematic diagram of an embodiment of the present invention;

[0038] Figure 2 A circuit schematic diagram of an embodiment of the present invention with a comparator added;

[0039] Figure 3 A circuit schematic diagram of an embodiment of the present invention in which a capacitance compensation circuit is added;

[0040] Figure 4 A schematic diagram of a circuit for controlling a charging mode of a capacitor to be measured according to an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of a circuit for compensating a capacitance to be measured by a capacitance compensation circuit according to an embodiment of the present invention;

[0042] Figure 6 Schematic diagram of controlling the sampling period of the clock switch CK_CG according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0044] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance, or implying any such actual relationship or order between these entities or operations. In addition, the terms "connected", "connected", etc. can be directly connected between elements, or indirectly connected via other elements. Example

[0045] The present invention is achieved through the following technical solutions: Figure 1 As shown, an anti-interference circuit for capacitance detection includes a capacitance to be measured Cs, a clock switch CK_CG, a quantization unit, an integrator (an amplifier is used in some embodiments), and a counting unit, wherein:

[0046] The first end of the clock switch CK_CG is connected to the reference voltage Vref or the common mode voltage Vcm, the second end of the clock switch is connected to the first end of the capacitor to be measured Cs, and the second end of the capacitor to be measured Cs is connected to the ground potential.

[0047] As an implementable approach, see Figure 4 The capacitor Cs to be measured can be connected to the reference voltage Vref or the common-mode voltage Vcm through the single-pole double-throw switch. When the single-pole double-throw switch is closed at point K3 and the clock switch CK_CG is closed, the reference voltage Vref charges the capacitor Cs to be measured; when the single-pole double-throw switch is closed at point K4 and the clock switch CK_CG is closed, the common-mode voltage Vcm charges the capacitor Cs to be measured.

[0048] As another practicable manner, the voltage output to the capacitor to be measured Cs may be controlled by an external controller to be a reference voltage Vref or a common mode voltage Vcm.

[0049] The quantization unit includes a first quantization device and a second quantization device, and the first quantization device and the second quantization device are respectively connected to the first input terminal of the integrator. The first quantization device includes a first switch CK_S1 and a first current detector; the first end of the first switch CK_S1 is connected to the first input terminal of the integrator, the second end of the first switch CK_S1 is connected to the first end of the first current detector, and the second end of the first current detector is connected to the ground. The second quantization device includes a second switch CK_S2 and a second current detector; the first end of the second current detector is connected to the power supply AVDD, the second end of the second current detector is connected to the first end of the second switch CK_S2, and the second end of the second switch CK_S2 is connected to the first input terminal of the integrator.

[0050] The access potential of the second input terminal of the integrator is Vcm. The integrator further includes an integrating capacitor Cint, a first terminal of the integrating capacitor Cint is connected to the first input terminal of the integrator, and a second terminal of the integrating capacitor Cint is connected to the output terminal of the integrator.

[0051] The input end of the integrator is connected to a switch K5, and the integrating capacitor Cint is connected in parallel to a switch K6. When the reference voltage Vref or the common mode voltage Vcm charges the capacitor Cs to be measured, the switch K5 is disconnected. When the switch K6 is closed, the integrator and the integrating capacitor Cint are in a reset state; when the switch K6 is disconnected and K5 is closed, the integrator is connected to the circuit.

[0052] The counting unit is connected to the output end of the integrator.

[0053] In one embodiment, see Figure 2 A comparator is connected between the integrator and the counting unit, and the comparator is used to determine whether the charge amount in the integral capacitor Cint is positive or negative. When the charge amount on the integral capacitor Cint is positive, the comparator outputs a high level; when the charge amount on the integral capacitor Cint is negative, the comparator outputs a low level. Of course, other methods can also be used to determine whether the charge amount in the integral capacitor Cint is positive or negative.

[0054] As an implementable approach, see Figure 3, and also includes a capacitance compensation unit, which is used to compensate the capacitance Cs to be measured after the reference voltage Vref completes charging the capacitance Cs to be measured, and then the remaining charge after the capacitance Cs to be measured is compensated is transferred to the integration capacitor Cint. In one embodiment, the capacitance compensation unit includes a switch CK_COMP_N, a switch CK_COMP_P, and a compensation capacitor Cd; the first end of the switch CK_COMP_N is connected to the first end of the capacitance to be measured, the second end of the switch CK_COMP_N is connected to the first end of the switch CK_COMP_P and the first end of the compensation capacitor Cd, respectively, and the second end of the switch CK_COMP_P and the second end of the compensation capacitor Cd are both connected to the ground.

[0055] Before compensating the capacitance Cs to be measured, it is necessary to determine the number of compensation times N. The circuit further includes an initial capacitance C, a first end of which is connected to the first end of the capacitance Cs to be measured, and a second end of which is connected to the ground. The initial capacitance C is connected in parallel with the capacitance Cs to be measured, and is used to assist in determining the number of compensation times N of the capacitance compensation unit for the capacitance Cs to be measured. Of course, the capacitance Cs to be measured can also be compensated by other compensation methods.

[0056] As another practicable manner, after the reference voltage Vref has completed charging the capacitor Cs to be measured, there is no need to compensate the capacitor Cs to be measured, and the charge in the capacitor Cs to be measured is directly transferred to the integration capacitor Cint.

[0057] Based on the above circuit, this scheme also proposes an anti-interference method for capacitance detection, which applies the anti-interference mode and the frequency hopping mode. For low-frequency interference signals, such as external low-frequency interference signals, DC interference signals, etc., the low-frequency interference signals can be offset by the anti-interference model. As for high-frequency interference signals, they will be aliased with the sampling frequency inside the circuit to the frequency point position of the sampling frequency. Because according to the Nyquist sampling theorem, it can be known that a high-frequency signal (or high-frequency interference signal) greater than half of the sampling frequency will be aliased with the sampling frequency to the position of the low-frequency signal. For example, after the input of an 800kHz high-frequency interference signal is sampled by a 1MHz clock, a 200kHz sine wave will be aliased. Therefore, interference signals of different frequencies may be equivalent to low-frequency signals with similar frequency and amplitude to the capacitive touch signal after passing through a system with a fixed sampling frequency, thereby causing false triggering of the system. Therefore, this scheme offsets the high-frequency interference signal by combining the anti-interference mode and the frequency hopping mode.

[0058] The method comprises the following steps:

[0059] Step 1: The capacitor to be measured is charged by a reference voltage Vref, and the charge in the capacitor to be measured is transferred to the integrating capacitor of the integrator for quantization to obtain a first quantization number N1.

[0060] As an implementation option, see Figure 3 Before testing, the capacitor Cs to be measured needs to be compensated, and the remaining charge after compensation is transferred to the integrating capacitor. After determining the compensation times N for the capacitor Cs to be measured, the capacitor Cs to be measured can be compensated N times before testing the capacitors Cs to be measured in the same batch, without determining the compensation times N again.

[0061] An applicable compensation method can be selected. In one embodiment, the compensation method is: closing switch K2 to connect the initial capacitor C to the circuit, and opening switch K1 to disconnect the capacitor Cs to be measured from the circuit, closing switch CK_CG to charge the initial capacitor C with the reference voltage Vref, and after charging, the charge stored on the initial capacitor C is Q, and the charge Q on the initial capacitor C is quantized by the first quantization device, at which time switch K5 is closed and switch K6 is closed until the voltage on the initial capacitor C is the common mode voltage Vcm, and the common mode voltage Vcm is the access potential of the second input terminal of the comparator.

[0062] The current of the first current detector in the first quantization device is I. Each time the first switch CK_S1 is closed, the first quantization device quantizes the charge ∆Q on the initial capacitor C, and ∆Q=I·∆t, where ∆t is the duration of the switch CK_S1 being closed. The process of the first quantization device quantizing the charge Q on the initial capacitor C includes: repeatedly closing the first switch CK_S1 for a duration of ∆t and then disconnecting it until the voltage on the initial capacitor C is the common mode voltage Vcm, and recording the count value of the counting unit as the initial number of times m1, which is the number of times the first switch CK_S1 is closed.

[0063] The switch K1 is closed to connect the capacitor Cs to be measured to the circuit, and the switch K2 is opened to disconnect the initial capacitor C from the circuit. The switch CK_CG is closed to charge the capacitor Cs to be measured with the reference voltage Vref. After the charging is completed, the charge stored on the capacitor Cs to be measured is Q0. The capacitor compensation circuit compensates the capacitor Cs to be measured. The principle of the capacitor compensation circuit is as follows: Figure 5 As shown, there are:

[0064]

[0065] The capacitance compensation circuit compensates the capacitance Cs to be measured:

[0066]

[0067]

[0068]

[0069] Wherein, Cd is the compensation capacitor; V1 is the voltage at the intersection of the capacitor Cs to be measured and the compensation capacitor Cd after the capacitor Cs to be measured is compensated once; Q1 is the remaining charge on the capacitor Cs to be measured after the capacitor Cs to be measured is compensated once;

[0070] After the capacitance compensation circuit compensates the capacitance Cs to be measured N times:

[0071]

[0072] Among them, V N Q is the voltage at the intersection of the measured capacitance Cs and the compensation capacitance Cd after the measured capacitance Cs is compensated N times; n It is the remaining charge on the capacitor Cs to be measured after the capacitor to be measured is compensated N times.

[0073] The remaining charge Q on the capacitor Cs to be measured after the first quantization device performs N compensations n Quantization is performed until the voltage on the capacitor Cs to be measured reaches the common mode voltage Vcm.

[0074] The remaining charge Q on the capacitor Cs to be measured after the first quantization device performs N compensations n The quantization process includes: repeatedly closing the first switch CK_S1 for a time period of ∆t and then opening it until the voltage on the capacitor Cs to be measured reaches the common mode voltage Vcm, and recording the count value of the counting unit as the quantization number m2.

[0075] If m2 is greater than m1, the compensation times N are readjusted so that the remaining charge Q after the capacitor Cs to be measured is compensated N times n After the quantization unit completes the quantization, the obtained quantization number m2 is less than the initial number m1; at the same time, the compensation number N for the capacitance Cs to be measured is obtained when the quantization number m2 is less than the initial number m1.

[0076] After completing N compensations for the capacitor Cs to be measured, the remaining charge on the capacitor Cs to be measured is Qn, and the remaining charge Qn is transferred to the integrating capacitor Cint for quantization. The first quantization device is controlled to quantize the charge Qn in the integrating capacitor Cint until the charge in the integrating capacitor Cint is negative, then the quantization of the first quantization device is stopped, and the count value of the counting unit is recorded as the quantization number n1.

[0077] The process of quantizing the charge Qn on the integration capacitor Cint by the first quantization device includes: repeatedly closing the first switch CK_S1 for a period of ∆t and then opening it until the charge on the integration capacitor Cint is negative, and recording the count value of the counting unit as the quantization number n1.

[0078] The second quantization device is controlled to continue quantizing the charge in the integration capacitor Cint until the charge in the integration capacitor Cint is positive, then the quantization of the second quantization device is stopped, and the count value of the counting unit is recorded as the quantization number n2.

[0079] The process of quantizing the charge on the integration capacitor Cint by the second quantization device includes: repeatedly closing the second switch CK_S2 for a period of ∆t and then opening it until the charge on the integration capacitor Cint is positive, and recording the count value of the counting unit as the quantization number n2.

[0080] The quantization order n1 and the quantization order n2 are added to obtain the first quantization order N1.

[0081] As another possible implementation, after the reference voltage Vref completes charging the capacitor Cs to be measured, the capacitor Cs to be measured is not compensated, and the charge Q0 in the capacitor Cs to be measured is directly transferred to the integrating capacitor Cint for quantization, and at this time Q0=Qn.

[0082] Step 2, the capacitor to be measured is charged by the common mode voltage Vcm, and the charge in the capacitor to be measured is transferred to the integrating capacitor of the integrator for quantization to obtain a second quantization order N2.

[0083] After the capacitor Cs to be measured is charged by the common mode voltage Vcm, the charge amount in the capacitor Cs to be measured is Qf. At this time, there is no need to compensate the capacitor Cs to be measured, and the charge amount Qf in the capacitor Cs to be measured is directly transferred to the integrating capacitor Cint for quantization.

[0084] The first quantization device is controlled to quantize the charge Qf in the integration capacitor Cint until the charge in the integration capacitor Cint is negative, then the quantization of the first quantization device is stopped, and the count value of the counting unit is recorded as the quantization number n3.

[0085] The process of quantizing the charge Qf on the integration capacitor Cint by the first quantization device includes: repeatedly closing the first switch CK_S1 for a period of ∆t and then opening it until the charge on the integration capacitor Cint is negative, and recording the count value of the counting unit as the quantization number n3.

[0086] The second quantization device is controlled to continue quantizing the charge in the integration capacitor Cint until the charge in the integration capacitor Cint is positive, then the quantization of the second quantization device is stopped, and the count value of the counting unit is recorded as the quantization number n4.

[0087] The process of quantizing the charge on the integration capacitor Cint by the second quantization device includes: repeatedly closing the second switch CK_S2 for a period of ∆t and then opening it until the charge on the integration capacitor Cint is positive, and recording the count value of the counting unit as the quantization number n4.

[0088] The quantization order n3 and the quantization order n4 are added to obtain the second quantization order N2.

[0089] Step 3: Use the first quantization number N1 to subtract the second quantization number N2 to offset the low-frequency interference signal, or offset the low-frequency interference signal generated by the aliasing of the high-frequency interference signal and the sampling signal.

[0090] In this scheme, a low-frequency signal (or a low-frequency interference signal) is defined as a frequency less than 1 / 10T, where T is the sum of the time it takes for the system to obtain the first quantization number N1 and the second quantization number N2; a high-frequency signal (or a high-frequency interference signal) is defined as a frequency greater than 1 / 10T.

[0091] If the input interference signal is a low-frequency interference signal, the first quantization number N1 obtained includes the normal detection signal and the low-frequency interference signal, and the second quantization number N2 obtained only includes the low-frequency interference signal. Therefore, by subtracting the second quantization number N2 from the first quantization number N1, the low-frequency interference signal can be offset.

[0092] If the input interference signal is a high-frequency interference signal, the signal will fall at a low-frequency position after aliasing (related to the sampling frequency) through the sampling system, that is, the aliased low-frequency interference signal. At this time, this step can also offset the aliased low-frequency interference signal.

[0093] Step 4, control the sampling period of the clock switch to adjust the sampling frequency so that the high-frequency interference signal that is not offset in step 3 jumps to the low-frequency interference signal, and then repeat steps 1 to 3, and average the number of quantizations obtained after multiple repetitions to flatten or offset the interference signal amplitude at each frequency.

[0094] However, even after the high-frequency interference signal is aliased to the low-frequency signal, there is still a part of the interference signal that is not in the area of ​​the low-frequency signal. In this case, it is necessary to combine the frequency hopping mode to remove this part of the interference signal. The frequency hopping mode is achieved by controlling the sampling period of the clock switch CK_CG. For example, Figure 6 As shown in the figure, the original sampling period of the clock switch CK_CG is ∆T, where a high level indicates that the clock switch CK_CG is closed, and a low level indicates that the clock switch CK_CG is open. The waiting time is set to change the sampling period ∆T of the clock switch CK_CG to ∆T`, thereby adjusting the sampling frequency fs, for example, reducing the sampling frequency fs.

[0095] Then the high-frequency interference signal is aliased to the frequency point of the adjusted sampling frequency, so that part or all of the high-frequency interference signal belongs to the low-frequency signal, and it can be offset by steps 1 to 3. Repeat steps 1 to 3, and average the quantization times obtained after multiple repetitions to flatten or offset the interference signal amplitude at each frequency, thereby completing the suppression of the interference signal.

[0096] If there is a particularly high-frequency interference signal, the RC characteristics of the circuit itself can be used to filter out the ultra-high frequency interference signal first.

[0097] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An anti-interference circuit for capacitance detection, comprising a capacitance to be measured, characterized in that: It also includes a clock switch, a quantization unit, an integrator, and a counting unit, wherein: The first end of the clock switch is connected to the reference voltage Vref or the common mode voltage Vcm, the second end of the clock switch is connected to the first end of the capacitor to be measured, and the second end of the capacitor to be measured is connected to the ground potential; The first input terminal of the integrator is connected to the quantization unit; The counting unit is connected to the output end of the integrator; The quantization unit comprises a first quantization device and a second quantization device, wherein the first quantization device and the second quantization device are respectively connected to a first input terminal of the integrator; The integrator further comprises an integrating capacitor Cint, a first end of the integrating capacitor Cint is connected to a first input end of the integrator, and a second end of the integrating capacitor Cint is connected to an output end of the integrator; The first quantization device is used to quantize the amount of charge in the integrating capacitor Cint until the amount of charge in the integrating capacitor Cint is negative, and the counting unit outputs the quantization times of the first quantization device; the second quantization device is used to quantize the amount of charge in the integrating capacitor Cint until the amount of charge in the integrating capacitor Cint is positive, and the counting unit outputs the quantization times of the second quantization device.

2. The anti-interference circuit for capacitance detection according to claim 1, characterized in that: The first quantization device includes a first switch CK_S1 and a first current detector; a first end of the first switch CK_S1 is connected to a first input end of the integrator, a second end of the first switch CK_S1 is connected to a first end of the first current detector, and a second end of the first current detector is connected to ground.

3. The anti-interference circuit for capacitance detection according to claim 1, characterized in that: The second quantization device includes a second switch CK_S2 and a second current detector; a first end of the second current detector is connected to the power supply AVDD, a second end of the second current detector is connected to the first end of the second switch CK_S2, and a second end of the second switch CK_S2 is connected to the first input end of the integrator.

4. The anti-interference circuit for capacitance detection according to claim 1, characterized in that: A comparator is also included, wherein a first input terminal of the comparator is connected to the output terminal of the integrator, and an output terminal of the comparator is connected to the input terminal of the counting unit.

5. An anti-interference method for capacitance detection, applied to the circuit of any one of claims 1 to 4, characterized in that: The following steps are involved: Step 1, charging the capacitor to be measured by a reference voltage Vref, and transferring the charge in the capacitor to be measured to an integrating capacitor of an integrator for quantization, thereby obtaining a first quantization number N1; Step 2, charging the capacitor to be measured through the common mode voltage Vcm, and transferring the charge in the capacitor to be measured to the integrating capacitor of the integrator for quantization, thereby obtaining a second quantization number N2; Step 3, using the first quantization number N1 minus the second quantization number N2 to offset the low-frequency interference signal, or offset the low-frequency interference signal generated by the aliasing of the high-frequency interference signal and the sampling signal; Step 4, control the sampling period of the clock switch to adjust the sampling frequency so that the high-frequency interference signal that is not offset in step 3 jumps to the low-frequency interference signal, and then repeat steps 1 to 3, and average the number of quantizations obtained after multiple repetitions to flatten or offset the interference signal amplitude at each frequency.

6. The anti-interference method for capacitance detection according to claim 5, characterized in that: The step of obtaining the first quantization number N1 in step 1 includes: Control the first quantization device to quantize the charge Qn in the integration capacitor Cint until the charge in the integration capacitor Cint is negative, stop the quantization of the first quantization device, and record the count value of the counting unit as the quantization number n1; The process of the first quantization device quantizing the charge Qn on the integration capacitor Cint includes: repeatedly closing the first switch CK_S1 for a period of ∆t and then opening it until the charge on the integration capacitor Cint is negative, and recording the count value of the counting unit as the quantization number n1; Control the second quantization device to continue quantizing the charge in the integration capacitor Cint until the charge in the integration capacitor Cint is positive, stop the quantization of the second quantization device, and record the count value of the counting unit as the quantization number n2; The process of the second quantization device quantizing the charge on the integration capacitor Cint includes: repeatedly closing the second switch CK_S2 for a period of ∆t and then opening it until the charge on the integration capacitor Cint is positive, and recording the count value of the counting unit as the quantization number n2; The quantization order n1 and the quantization order n2 are added to obtain the first quantization order N1.

7. The anti-interference method for capacitance detection according to claim 6, characterized in that: Before the step of transferring the charge in the capacitor to be measured to the integrating capacitor of the integrator for quantization in step 1, the method further includes the following steps: After the capacitor Cs to be measured is charged by the power supply Vref, the charge amount in the capacitor Cs to be measured is Q, and the capacitor Cs to be measured is compensated. After the compensation, the capacitor Cs to be measured transfers the remaining charge amount Qn to the integration capacitor Cint.

8. The anti-interference method for capacitance detection according to claim 5, characterized in that: The step of obtaining the second quantization number N2 in step 2 includes: After the capacitor Cs to be measured is charged by the common mode voltage Vcm, the charge amount in the capacitor Cs to be measured is Qf, and the charge amount Qf in the capacitor Cs to be measured is transferred to the integration capacitor Cint for quantization; Control the first quantization device to quantize the charge Qf in the integration capacitor Cint until the charge in the integration capacitor Cint is negative, stop the quantization of the first quantization device, and record the count value of the counting unit as the quantization number n3; The process of quantizing the charge Qf on the integration capacitor Cint by the first quantization device includes: repeatedly closing the first switch CK_S1 for a time period of ∆t and then opening it until the charge on the integration capacitor Cint is negative, and recording the count value of the counting unit as the quantization number n3; Control the second quantization device to continue quantizing the charge in the integration capacitor Cint until the charge in the integration capacitor Cint is positive, stop the quantization of the second quantization device, and record the count value of the counting unit as the quantization number n4; The process of the second quantization device quantizing the charge on the integration capacitor Cint includes: repeatedly closing the second switch CK_S2 for a period of ∆t and then opening it until the charge on the integration capacitor Cint is positive, and recording the count value of the counting unit as the quantization number n4; The quantization order n3 and the quantization order n4 are added to obtain the second quantization order N2.

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