A space parallel hybrid multiplier based on probability calculation and a working method thereof

Abstract

This invention provides a spatially parallel hybrid multiplier based on probabilistic computation and its operating method. The spatially parallel hybrid multiplier based on probabilistic computation includes a traditional multiplier and two high-precision probabilistic multipliers. Each high-precision probabilistic multiplier includes a random sequence generator, a random computation circuit, a probability estimator, and a two's complement conversion circuit connected in sequence. The spatially parallel hybrid multiplier based on probabilistic computation provided by this invention successfully utilizes the characteristics of probabilistic computation, implementing multiplication operations using only a few wires, logic gates, and single-bit addition, thus reducing computational complexity and resource overhead. Simultaneously, the spatially parallel hybrid multiplier based on probabilistic computation provided by this invention strikes a good balance between computational accuracy and hardware resources, ensuring computational accuracy while significantly reducing hardware resources. This saves area and reduces power consumption.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence neural network technology, and more specifically, to a spatial parallel hybrid multiplier based on probability calculation and its working method. Background Technology

[0002] In recent years, with the rapid development of artificial intelligence in emerging fields such as 5G, pattern recognition, natural language processing, and the Internet of Things, deep learning, as an important branch and major development direction of machine learning in artificial intelligence, plays an extremely important role. The improvement in the performance of neural networks in deep learning is accompanied by an explosive growth in the scale of neural networks and computational demands, with billions of operations and tens to hundreds of megabytes of parameters in a single inference process. Simultaneously, with the advent of the post-Moore's Law era, chip computing and storage have reached their limits. Therefore, simpler hardware designs and faster, lower-power hardware processing have become key drivers for the further development of deep learning.

[0003] A recent paper by Z.Xia, J.Chen, Q.Huang, J.Luo and J.Hu, "Neural Synaptic Plasticity-Inspired Computing: A High Computing Efficient Deep Convolutional Neural Network Accelerator," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol.68, no.2, pp.728-740, Feb.2021, proposes a neural network utilizing axonal plasticity spatially encoded probabilistic multipliers. This achieves an ultra-low-complexity hardware implementation that mimics biological principles; however, many similar issues regarding flexibility and accuracy remain unresolved. Summary of the Invention

[0004] The present invention aims to provide a spatial parallel hybrid multiplier based on probability calculation and its working method, so as to solve the problems of high-precision multiplication being difficult and low computational accuracy in the prior art.

[0005] The present invention provides a spatially parallel hybrid multiplier based on probability calculation, comprising a conventional multiplier and two high-precision probability multipliers; each of the high-precision probability multipliers comprises a random sequence generator, a random calculation circuit, a probability estimator and a two's complement conversion circuit connected in sequence.

[0006] Furthermore, the random sequence generator includes a uniform sequence generator and a thermometer sequence generator.

[0007] Furthermore, the operating method of the spatially parallel hybrid multiplier based on probability computation includes:

[0008] The two 2n-bit multipliers are split and recombined into four new multipliers, including one high-bit multiplier, two high-low-bit multipliers, and one low-bit multiplier. The low-bit multiplier is omitted from calculation. The high-bit multiplier is input into a traditional multiplier to obtain an integer multiplication result. The two high-low-bit multipliers are input into two high-precision probability multipliers to obtain two high-precision probability multiplication results. The integer multiplication result and the two high-precision probability multiplication results are superimposed to obtain the multiplication result output by the spatial parallel hybrid multiplier. The calculation process of each high-precision probability multiplier includes:

[0009] The random sequence generator uses different encoding methods to produce two different random bit sequences depending on the multiplier;

[0010] The probability calculation circuit performs a bitwise AND operation on the two random bit sequences to synthesize a new random sequence;

[0011] The probability estimator uses an addition tree as a reverse transformation to accumulate each bit of the random sequence to obtain a probability multiplication absolute value result;

[0012] When the absolute value of the probability multiplication is negative, the two's complement conversion circuit performs a two's complement conversion on the absolute value of the probability multiplication to obtain a spatially parallel high-precision probability multiplication result.

[0013] Furthermore, the expression for splitting and recombining two 2n-bit multipliers into four new multipliers is as follows:

[0014] Y = AC + AD + BC + BD

[0015] Where Y represents the result of multiplying a 2n-bit integer multiplier a and a 2n-bit probability multiplier b. The 2n-bit integer multiplier a is split into n high-order bits A and n low-order bits B, and the 2n-bit probability multiplier b is split into n high-order bits C and n low-order bits D. AC represents the high-order multiplier formed by combining n high-order bits A and n high-order bits C; AD represents the high-low order multiplier formed by combining n high-order bits A and n low-order bits D; BC represents the high-low order multiplier formed by combining n low-order bits B and n high-order bits C; and CD represents the low-order multiplier formed by combining n low-order bits C and n low-order bits D. The high-order multiplier AD is calculated using a traditional multiplier, while the high-low order multipliers AD and BC are calculated using a high-precision probability multiplier. The low-order multiplier CD is omitted from calculation.

[0016] Furthermore, both the n-bit high-order bits A and C include 1 sign bit and n-1 data bits; the n-bit low-order bits B and D are both unsigned bits, i.e., n data bits; thus, the high-low multipliers AD and BC are both an n-bit signed number multiplied by an n-bit unsigned number.

[0017] Furthermore, in the random sequence generator, the n high-order bits A and n low-order bits B, derived from the integer multiplier a, are represented in binary and used to generate a uniform random bit sequence through a uniform sequence generator; the n high-order bits C and n low-order bits D, derived from the probability multiplier b, are represented in binary and used to generate a sequential random bit sequence through a thermometer sequence generator; that is, the n high-order bits A and n low-order bits B, as well as the n high-order bits C and n low-order bits D, are all converted into 2^n random bits within one clock cycle. n -1 bit random bit sequence; thus, the high and low bit multipliers AD are converted into a uniform random bit sequence by a uniform sequence generator, and the high and low bit multipliers BC are converted into a sequential random bit sequence by a thermometer sequence generator.

[0018] Furthermore, in the probability calculation circuit, the adjacent two bits of the uniform random bit sequence are XORed to obtain a new random sequence 1, the length of which is 2. n -1, a single bit is added after the new random sequence 1, and the odd number of bits of the sequential random bit sequence are taken to obtain the new random sequence 2. The random sequence 1 and random sequence 2 are bitwise ANDed to obtain the new random sequence 3.

[0019] Furthermore, in the two's complement conversion circuit, the absolute value result of the probability multiplication is bitwise XORed with the sign bit extension of the same bit width to obtain a new result, and then a sign bit is added to obtain a high-precision probability multiplication result.

[0020] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0021] 1. The spatial parallel hybrid multiplier based on probabilistic computation provided by this invention successfully utilizes the characteristics of probabilistic computation, and implements multiplication operations using only some wires, logic gates and single-bit addition, thereby reducing computational complexity and resource overhead.

[0022] 2. The spatially parallel hybrid multiplier based on probabilistic computation provided in this invention strikes a good balance between computational accuracy and hardware resources, ensuring computational accuracy while significantly reducing hardware resource consumption. This saves area and reduces power consumption.

[0023] 3. The spatial parallel hybrid multiplier based on probability calculation provided by this invention completes the calculation within one clock cycle, reducing the calculation latency.

[0024] 4. The spatial parallel hybrid multiplier based on probabilistic computation provided by this invention has equal weight for each bit in a probabilistic random sequence. The error caused by a single bit error is very small, which improves the fault tolerance of the computation.

[0025] Therefore, previous research on low-overhead, low-power neural network accelerators has largely focused on neural network compression and neuron sparsity, with insufficient research on optimizing basic computing units. While some innovative algorithms theoretically reduce computational complexity, their actual computational efficiency and performance remain significantly lower. This invention, starting with the basic computing units of CNN neural networks, proposes a low-complexity, low-area, low-overhead, and low-power spatial parallel high-precision multiplier based on probabilistic computation. It strikes a good balance between computational accuracy and hardware resources, ensuring accuracy while significantly reducing hardware requirements. Based on this spatial parallel high-precision probabilistic multiplier, a multi-segment decomposition-based spatial parallel high-precision probabilistic multiplier conforming to neural network characteristics was derived and applied to CNN networks. The success of this computing unit was verified using LeNet-5 and VGG13 networks. The spatial parallel hybrid multiplier based on probabilistic computation proposed in this invention can solve a series of AI chip design problems in power / area and energy / resource-constrained intelligent edge devices, and has a good application environment. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a block diagram of the high-precision multiplier system structure in the spatial parallel hybrid multiplier based on probability calculation, according to an embodiment of the present invention.

[0028] Figure 2a This is a circuit diagram of a uniform sequence generator in a spatially parallel hybrid multiplier based on probability calculation, according to an embodiment of the present invention.

[0029] Figure 2b This is a circuit diagram of a thermometer sequence generator in a spatially parallel hybrid multiplier based on probability calculation, according to an embodiment of the present invention.

[0030] Figure 3 This is a circuit diagram of an unsigned number spatial parallel high-precision probabilistic multiplication in a spatial parallel hybrid multiplier based on probability calculation, according to an embodiment of the present invention.

[0031] Figure 4This is a circuit diagram of a signed number spatially parallel high-precision probabilistic absolute multiplication circuit in a spatially parallel hybrid multiplier based on probability calculation, according to an embodiment of the present invention.

[0032] Figure 5 This is a circuit diagram of the two's complement conversion in a spatially parallel hybrid multiplier based on probability calculation, according to an embodiment of the present invention.

[0033] Figure 6 This is a schematic diagram of an example of a spatially parallel hybrid multiplier based on probability computation, according to an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0036] Example

[0037] This embodiment proposes a spatially parallel hybrid multiplier based on probabilistic computation, comprising a traditional multiplier and two high-precision probabilistic multipliers; such as Figure 1 As shown, each of the high-precision probability multipliers includes a random sequence generator, a random computation circuit, a probability estimator, and a two's complement conversion circuit connected in sequence. For both integer multipliers and probability multipliers, the random sequence generator in this embodiment includes a uniform sequence generator and a thermometer sequence generator.

[0038] Therefore, the working method of a spatially parallel hybrid multiplier based on probabilistic computation includes:

[0039] The two 2n-bit multipliers are split and reassembled into four new multipliers, including one high-order multiplier, two high-low-order multipliers, and one low-order multiplier. The low-order multiplier is omitted from calculation. The high-order multiplier is input into a traditional multiplier to obtain an integer multiplication result. The two high- and low-order multipliers are input into two high-precision probability multipliers to obtain two high-precision probability multiplication results. The integer multiplication result and the two high-precision probability multiplication results are superimposed to obtain the multiplication result output by the spatially parallel hybrid multiplier. In this embodiment, the expression for splitting and reassembling the two 2n-bit multipliers into four new multipliers is:

[0040] Y = a × b = AC + AD + BC + BD

[0041] Where Y represents the result of multiplying a 2n-bit integer multiplier a and a 2n-bit probability multiplier b. The 2n-bit integer multiplier a is split into n high-order A bits and n low-order B bits, and the 2n-bit probability multiplier b is split into n high-order C bits and n low-order D bits. AC represents the high-order multiplier formed by combining n high-order A bits and n high-order C bits; AD represents the high-low order multiplier formed by combining n high-order A bits and n low-order D bits; BC represents the high-low order multiplier formed by combining n low-order B bits and n high-order C bits; and CD represents the low-order multiplier formed by combining n low-order C bits and n low-order D bits. The high-order multiplier AD has a large weight in the result and is calculated using a traditional multiplier; the high-low order multipliers AD and BC are calculated using a high-precision probability multiplier; and the low-order multiplier CD has a very small weight in the result and can be directly omitted from calculation, i.e., it does not occupy any computational overhead. Furthermore, both the n-bit high-order bits A and C include 1 sign bit and n-1 data bits; the n-bit low-order bits B and D are both unsigned bits, i.e., n data bits; thus, the high-low multipliers AD and BC are both an n-bit signed number multiplied by an n-bit unsigned number.

[0042] The calculation process for each high-precision probability multiplier includes:

[0043] (1) The random sequence generator uses different encoding methods to generate two different random bit sequences based on different multipliers; in the random sequence generator:

[0044] For the integer multiplier 'a' split into n high-order bits A and n low-order bits B, their binary representation is used to generate a uniform random bit sequence through a uniform sequence generator; such as... Figure 2a As shown, the n-bit high-order A and n-bit low-order B are converted to 2 in one clock cycle. n A random bit sequence of -1 bits, where the i-th bit of an n-bit integer multiplier a is extended to 2. i The bit index of i ∈ [0, n-1]. The i-th bit A i Arranged in either high-to-low or low-to-high order. For any input with a given bit width, the wiring pattern is determined, where the probability of the integer multiplier sequence "1" is (a×2). n ) / (2 n -1);

[0045] The probability multiplier b is split into n high-order bits C and n low-order bits D. The probability multiplier and fixed-point number are essentially decimals, which can also be represented as binary numbers in hardware circuits. This binary representation is used to generate a sequential random bit sequence through a thermometer sequence generator; for example... Figure 2b As shown, the n-bit probability multiplier b is converted to 2 in one clock cycle. n-1 random sequence value. The i-th bit of the n-bit fixed-point probability multiplier b is extended to 2. i The bit index of i ∈ [0, n-1]. The i-th bit B i The first location it appears in is 2. n-i-1 Then every 2 n-i The bit appears. For any input with a given bit width, the wiring pattern is also determined, where the probability of the probability multiplier sequence "1" is (b×2). n ) / (2 n -1).

[0046] Through the above process, the n-bit high-order A and n-bit low-order B, as well as the n-bit high-order C and n-bit low-order D, are all converted to 2 bits within one clock cycle. n -1 bit random bit sequence; thus, the high and low bit multipliers AD are converted into a uniform random bit sequence by a uniform sequence generator, and the high and low bit multipliers BC are converted into a sequential random bit sequence by a thermometer sequence generator.

[0047] (2) The probability calculation circuit performs a bitwise AND operation on the two random bit sequences to synthesize a new random sequence;

[0048] (3) The probability estimator uses an addition tree as a reverse transformation to accumulate each bit of the random sequence to obtain a probability multiplication absolute value result;

[0049] like Figure 3 As shown, this is an example of a high-precision probabilistic multiplier using unsigned multiplication. A uniformly random bit sequence and a sequentially random bit sequence are fed into the probability calculation circuit and its probability estimation are completed within the same clock cycle. The binary representation of the integer multiplier 3 is (011). b Its weight is expressed as 0×2 2 +1×2 1 +1×2 0 Following the rules of a uniform sequence generator, a 7-bit uniform random bit sequence (0101010) is generated. b A binary clock pointer (100) with a probability multiplier of 0.5. b Its weight is expressed as 1×2-1+0×2-2+0×2-3, and according to the rules of the thermometer sequence generator, a 7-bit sequential random bit sequence (1111000) is generated. b A new random sequence (0101000) is generated by using seven AND gates to perform probability calculations. b The new random sequence is processed by an addition tree as a reverse transformation, which accumulates each bit of the sequence to obtain an unsigned probability multiplication result. The actual result 1.5 is rounded to 2, and the probability multiplier result of 2 is achieved simply by using some wires, AND gates, and single-bit adders.

[0050] like Figure 4 As shown, this is an example of a high-precision probabilistic multiplier with signed multiplication. Uniform random bit sequences and sequential random bit sequences are fed into the probability calculation circuit and its probability estimation is completed within the same clock cycle. The binary representation of the integer multiplier -2 is shown in (110). b Its weight is expressed as -1×2 2 +1×2 1 +0×2 0 Following the rules of a uniform sequence generator, a 7-bit uniform random bit sequence (1110111) is generated. b Binary representation of probability multiplier 0.5 (100) b Its weight is expressed as 1×2-1+0×2-2+0×2-3, and according to the rules of the thermometer sequence generator, a 7-bit sequential random bit sequence (1111000) is generated. b The XOR operation of two adjacent bits in a uniform random bit sequence yields a new random sequence (010). b The length of the random sequence is 2. n -1, the single bit is added to the new random order to get (0101). b Take the odd number of bits from the sequential random bit sequence to obtain a new random sequence (1100). b The bitwise AND operation of two new random sequences yields a new random sequence (0100). b That is, the new random sequence (0100) b By using an addition tree as a reverse transformation, each bit of the sequence is accumulated to obtain a signed multiplication result of -1 with an absolute probability of 1.

[0051] (4) When the absolute value of the probability multiplication is negative, the two's complement conversion circuit performs a two's complement conversion on the absolute value of the probability multiplication to obtain the output spatially parallel high-precision probability multiplication result. For example... Figure 5 As shown, the result of the absolute value of the probability multiplication is (0001). b Extending the sign bit to the same width, we get (1111). b The bitwise XOR operation yields a new result (1110). b Adding a sign bit "1" gives the high-precision probabilistic multiplication two's complement result (1111). b and -1.

[0052] Furthermore, based on the expression Y = a × b = AC + AD + BC + BD, we begin with a mathematical algorithm to understand the spatially parallel hybrid multiplier based on multi-segment decomposition.

[0053] Define a 2n-bit signed integer multiplier a:

[0054]

[0055] Define a 2n-bit signed probability multiplier b:

[0056]

[0057] According to mathematical decomposition, we can let:

[0058] A=(A 2n-1 A 2n-2 …A n ) signed

[0059] B = (A n-1 …A1A0) unsigned

[0060] C = (B 2n-1 B 2n-2 …B n ) signed

[0061] D = (B n-1 …B1B0) unsigned

[0062] The weighted calculation formula is further obtained as follows:

[0063] Y = a × b = 2·AC + 2 1-n ·D+2 1-n ·C+2 1-2n ·D

[0064] To analyze the impact of multiplication on the result between different types of combinations, we can segment the multiplier. The coefficient before AC is 2, which has the largest weight in the result, so we directly use the traditional signed multiplier. The coefficient before BD is 2. 1-2n The result with the smallest weight has a weight of ≤2. 1-2n ·2 n ·2 n =2, which can be ignored, thus saving hardware overhead. The above-mentioned spatially parallel hybrid multiplier based on probability computation is used to apply high-precision probability multipliers to both AD and BC. However, one multiplier in the high-precision probability multiplier is an integer, and the other is a probability multiplier. Observing BC and AD, B and D can be converted to unsigned fixed-point numbers to obtain:

[0065] B = 2 n ·(0.A n-1 …A1A0) unsigned

[0066] D = 2 n ·(0.B n-1 …B1B0) unsigned

[0067] Return to the calculation formula: Y=a×b≈2·C+2·D+2·C.

[0068] Furthermore, based on the algorithm, a circuit diagram of a spatially parallel hybrid multiplier based on probability computation is obtained, such as... Figure 6 As shown, the three multipliers of this invention (one conventional multiplier and two high-precision probabilistic multipliers) perform partial parallel computation, and the entire design produces a probabilistic multiplication result within one clock cycle. In an exemplary embodiment, the integer multiplier a is -31, whose binary representation is (100001). b The two segments A decomposed are (100). b B is (001) b The probability multiplier b is 0.4625, and its binary representation is (001110). b The two segments C decomposed are (001). b D is (110) b The signed bits A and C are processed by a uniform sequence generator to output sequences 1 and 3, while the unsigned bits B and D are processed by a thermometer sequence generator to output sequences 2 and 4. Next, the high-weighted A and B are processed by a traditional signed number multiplier to obtain the first part of the multiplication result -4. Then, sequences 1 and 4, and sequences 2 and 3 are processed by a high-precision probability multiplier to obtain two parts of the multiplication result -3 and 0. According to the calculation formula Y = a × b ≈ 2·AC + 2·AD + 2·BC of the spatial parallel hybrid multiplier based on probability calculation, each part has a weight coefficient of 2. The specific operation of the circuit multiplying by 2 is achieved by left shifting by one bit. Furthermore, during the probability calculation circuit calculation, sequence 2... n -1 is a single bit. In the example, the compensation for both high-precision probability multiplications is 0. This bit needs to be added to achieve error compensation, and then a two's complement conversion is performed to obtain Y = -14.3375 ≈ 2·(-4) + 2·(-3) + 2·0 ≈ -14. Therefore, this embodiment decomposes the multiplier into multiple segments, which solves the problem that the higher the number of bits in the input multiplier, the longer the resulting random bit sequence becomes, leading to greater precision loss when directly using a high-precision probability multiplier, thus ensuring high precision with low overhead.

[0069] The above demonstrates the design of the spatially parallel hybrid multiplier based on probabilistic computation, as described in this invention.

[0070] Example 2

[0071] In this embodiment, taking the other three cases as examples, the input is into the spatial parallel hybrid multiplier based on probability calculation of the present invention, such as... Figure 6 As shown.

[0072] The first method: With both multipliers being positive, a = 17, b = 0.362, the corresponding binary representations are (010001). band (001011) b Then, by decomposition, A, B, C, and D are (0, 1, 0) respectively. b (001) b (001) b (011) b Secondly, the result of traditional multiplication AB is 2, while the results of high-precision probability multiplication AD and BC are 1 and 0 respectively; the last two compensations are 0, so Y = 6.154 ≈ 2·2 + 2·1 + 2·0 ≈ 6.

[0073] The second method: with positive integer multipliers and negative probability multipliers, and a = 19, b = -0.6891, the corresponding binary representations are (010011). b and (101011) b Then, by decomposition, A, B, C, and D are (0, 1, 0) respectively. b (011) b (101) b (011) b Secondly, the result of traditional multiplication AB is -6, while the result of high-precision probability multiplication AD and BC are both 1; the last two compensations are 0 and 1, so Y = -13.0929 ≈ 2·(-6) + [2·1+0] + [-(2·1+1)] ≈ -13.

[0074] The third method: with both multipliers being negative, and a = -32, b = -0.5352, the corresponding binary representations are (100000). b and (101111) b Then, by decomposition, A, B, C, and D are obtained as (100) respectively. b (000) b (101) b (111) b Secondly, the result of traditional multiplication AB is 12, while the results of high-precision probability multiplication AD and BC are 3 and 0 respectively; the last two compensations are 1 and 0, so Y = 17.1264 ≈ 2·12 + [-(2·3+1)] + [(2·0+0)] ≈ 17.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A working method for a spatially parallel hybrid multiplier based on probabilistic computation, characterized in that, include: Two 2s n The bit multiplier is split and reassembled into four new multipliers, including one high-bit multiplier, two high-low-bit multipliers, and one low-bit multiplier. The low-bit multiplier is omitted from calculation. The high-bit multiplier is input into a traditional multiplier to obtain an integer multiplication result. The two high- and low-bit multipliers are input into two high-precision probability multipliers to obtain two high-precision probability multiplication results. The integer multiplication result and the two high-precision probability multiplication results are superimposed to form the multiplication result output by the spatially parallel hybrid multiplier. The calculation process of each high-precision probability multiplier includes: The random sequence generator uses different encoding methods to produce two different random bit sequences depending on the multiplier; The probability calculation circuit performs a bitwise AND operation on the two random bit sequences to synthesize a new random sequence; The probability estimator uses an addition tree as a reverse transformation to accumulate each bit of the random sequence to obtain a probability multiplication absolute value result; When the absolute value of the probability multiplication is negative, the two's complement conversion circuit performs a two's complement conversion on the absolute value of the probability multiplication to obtain a spatially parallel high-precision probability multiplication result. The two 2 n The expression for splitting and recombining a digit multiplier into 4 new multipliers is: Where Y represents 2 n The integer multiplier a and 2 n The result of multiplication by the probability multiplier b, 2 n A 2-bit integer multiplier 'a' is split into n high-order bits 'A' and n low-order bits 'B'. n The probability multiplier b is split into n high-order C and n low-order D; AC represents the high-order multiplier formed by combining n high-order A and n high-order C; AD represents the high-low multiplier formed by combining n high-order A and n low-order D; BC represents the high-low multiplier formed by combining n low-order B and n high-order C; CD represents the low-order multiplier formed by combining n low-order C and n low-order D; the high-order multiplier AD is calculated using a traditional multiplier, the high-low multiplier AD and BC are calculated using a high-precision probability multiplier, and the low-order multiplier CD is omitted and not calculated. In the random sequence generator, the n high-order bits A and n low-order bits B, derived from the integer multiplier a, are represented in binary and used to generate a uniform random bit sequence through a uniform sequence generator; the n high-order bits C and n low-order bits D, derived from the probability multiplier b, are represented in binary and used to generate a sequential random bit sequence through a thermometer sequence generator; that is, the n high-order bits A and n low-order bits B, as well as the n high-order bits C and n low-order bits D, are all converted into 2^n random bits within one clock cycle. n -1 bit random bit sequence; thus, the high and low bit multipliers AD are converted into a uniform random bit sequence by a uniform sequence generator, and the high and low bit multipliers BC are converted into a sequential random bit sequence by a thermometer sequence generator. In the probability calculation circuit, XORing adjacent two bits of a uniform random bit sequence yields a new random sequence 1, with a length of 2. n -1, a single bit is added after the new random sequence 1, and the odd number of bits of the sequential random bit sequence are taken to obtain the new random sequence 2. The random sequence 1 and random sequence 2 are bitwise ANDed to obtain the new random sequence 3.

2. The working method of the spatial parallel hybrid multiplier based on probability calculation according to claim 1, characterized in that, Both the n-bit high-order bits A and C include 1 sign bit and n-1 data bits; the n-bit low-order bits B and D are both unsigned bits, i.e., n data bits; therefore, the high-low multipliers AD and BC are both an n-bit signed number multiplied by an n-bit unsigned number.

3. The working method of the spatially parallel hybrid multiplier based on probability calculation according to claim 1, characterized in that, In the two's complement conversion circuit, the absolute value result of the probability multiplication is XORed with the sign bit extension of the same bit width to obtain a new result, and then a sign bit is added to obtain a high-precision probability multiplication result.

4. A spatially parallel hybrid multiplier based on probabilistic computation, used to perform the working method as described in any one of claims 1-3, characterized in that, It includes a conventional multiplier and two high-precision probabilistic multipliers; each of the high-precision probabilistic multipliers includes a random sequence generator, a random computation circuit, a probability estimator, and a two's complement conversion circuit connected in sequence.

5. The spatially parallel hybrid multiplier based on probabilistic computation according to claim 4, characterized in that, The random sequence generator includes a uniform sequence generator and a thermometer sequence generator.

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