Gate driving circuit and display device including the same

Abstract

The present disclosure relates to a gate driving circuit and a display apparatus including the same. A gate driving circuit is disclosed, the gate driving circuit including: a plurality of stage circuits connected in dependence on each other and configured to output “j” output signals, where “j” is an integer of 2 or more, wherein each of the plurality of stage circuits includes a logic controller for controlling a voltage of each of a first node and a second node, and an output circuit unit responsive to the voltage of the first node to output each of “j” clock signals as the “j” output signals, wherein the output circuit unit includes “j” output buffers responsive to the voltage of the first node to output each of the “j” clock signals through an output node as the “j” output signals, and a capacitor prepared between the first node and output nodes of some of the “j” output buffers.

Description

Technical Field

[0001] This disclosure relates to a gating drive circuit and a display device including the same. Background Technology

[0002] With the development of information technology, the market for display devices that serve as a medium for communication between users and information is increasing. In addition to text messaging between users, various forms of communication are active. As the types of information change, the performance of display devices also evolves. Therefore, the use of various types of display devices, such as OLEDs, LCDs, microLEDs, and quantum dot displays (QDs), is expected to increase.

[0003] The display device includes: a display panel having a plurality of pixels having thin-film transistors connected to a plurality of gating lines and a plurality of data lines; a data driving circuit for supplying data voltage to the data lines; and a gating driving circuit including a shift register having a plurality of stages for supplying gating signals to the gating lines.

[0004] The gating drive circuit can be simultaneously formed on the non-display area of ​​the display panel during the manufacturing process of the data lines, gating lines, and thin-film transistors of each pixel. That is, it applies the in-panel gating (GIP) method, which directly integrates the gating drive circuit into the display panel. Summary of the Invention

[0005] To achieve a narrow bezel, the inventors conducted various experiments on a gating drive circuit with a novel structure that utilizes a single stage to drive multiple gating lines to reduce the bezel width, and on a display device including the same. According to the various experiments, when a stage sequentially outputs multiple scan signals, output deviations occur between the individual scan signals. Therefore, based on the results of these experiments, this disclosure relates to a gating drive circuit with a novel structure capable of reducing output deviations between multiple scan signals output from a single stage, and on a display device including the same.

[0006] This disclosure was made in view of the above problems. The technical advantage of this disclosure is to provide a gating drive circuit capable of reducing the output deviation of multiple scan signals output from a stage and reducing their size, as well as a display device including the same.

[0007] According to one aspect of this disclosure, the above and other technical benefits can be achieved by providing a gating drive circuit comprising multiple stages of circuitry connected interdependently and configured to output "j" output signals ("j" being an integer greater than or equal to 2), wherein each of the multiple stages of circuitry includes a logic controller for controlling a first voltage of a first node and a second voltage of a second node, and an output circuitry that outputs each of the "j" clock signals as "j" output signals in response to the voltage of the first node, wherein the output circuitry includes "j" output buffers that output each of the "j" clock signals as a corresponding output signal of the "j" output signals through an output node in response to the first voltage of the first node, and multiple capacitors connected between the first node and some of the output nodes of the "j" output buffers.

[0008] According to another aspect of this disclosure, a display device is provided, comprising: a display panel including a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, and a plurality of sub-pixels connected to adjacent pairs of data lines and gate lines; a gate driving circuit including a plurality of stage circuits for outputting scan signals as a group of "j" gate lines among the plurality of gate lines based on a predetermined or selected order; a data driving circuit connected to each of the plurality of data lines; and a timing controller for controlling the driving timing of each of the gate driving circuit and the data driving circuit, wherein the gate driving circuit includes a gate driver, and the gate driver includes components that are dependently connected to each other. Multiple stages of circuitry configured to output "j" output signals ("j" being an integer of 2 or greater), wherein each of the multiple stages of circuitry includes a logic controller for controlling the voltage of each of a first node and a second node, and an output circuitry that outputs each of "j" clock signals as "j" output signals in response to the voltage of the first node, wherein the output circuitry includes "j" output buffers that output each of the "j" clock signals as a corresponding output signal through a corresponding output node in response to the voltage of the first node, and capacitors connected between the first node and some of the output nodes of the "j" output buffers. Attached Figure Description

[0009] The above and other technical benefits, features and other advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram of a display device according to various embodiments of the present disclosure;

[0011] Figure 2 The stage circuits constituting the gating drive circuit according to various embodiments of the present disclosure are schematically shown.

[0012] Figure 3 The gating drive circuits according to various embodiments of the present disclosure are shown;

[0013] Figure 4 The stage circuit of the gating drive circuit according to various embodiments of the present disclosure is shown;

[0014] Figure 5 This is a circuit diagram of an output circuit unit according to one embodiment of the present disclosure;

[0015] Figure 6 It shows that it is applied to Figure 5 The waveform diagrams show the scan clock signal of the output circuit unit, the scan signal output from the output circuit unit, and the voltage waveform of the first node.

[0016] Figure 7 This is a circuit diagram of the output circuit unit according to the first embodiment of the present disclosure;

[0017] Figure 8 It shows that it is applied to Figure 7 The scan clock signal of the output circuit unit shown, from Figure 7 The output circuit unit shown in the figure outputs a scanning signal and a waveform diagram of the first node;

[0018] Figure 9 This is a circuit diagram of the output circuit unit according to the second embodiment of the present disclosure;

[0019] Figure 10 It shows that it is applied to Figure 9 The scan clock signal of the output circuit unit shown, from Figure 9 The output circuit unit shown in the figure outputs a scanning signal and a waveform diagram of the first node;

[0020] Figure 11 This is a circuit diagram of the output circuit unit according to the third embodiment of this disclosure;

[0021] Figure 12 It shows that it is applied to Figure 11 The scan clock signal of the output circuit unit shown, from Figure 11 The output circuit unit shown in the figure outputs a scanning signal and a waveform diagram of the first node;

[0022] Figure 13 This is a circuit diagram of the output circuit unit according to the fourth embodiment of this disclosure;

[0023] Figure 14 It shows that it is applied to Figure 13 The scan clock signal of the output circuit unit shown, from Figure 13 The output circuit unit shown in the figure outputs a scanning signal and a waveform diagram of the first node;

[0024] Figure 15 This is a circuit diagram of the output circuit unit according to the fifth embodiment of this disclosure;

[0025] Figure 16 It shows that it is applied to Figure 15 The scan clock signal of the output circuit unit shown, from Figure 15 The output circuit unit shown displays the scan signal and waveform of the first node; and

[0026] Figure 17 and Figure 18 This is a diagram illustrating the scan signal and the output waveform of the first node according to an example and a first embodiment of this disclosure. Detailed Implementation

[0027] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0028] The shapes, dimensions, ratios, angles, and quantities disclosed in the drawings for the purpose of describing embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, similar reference numerals denote similar elements. In the following description, detailed descriptions of related known functions or configurations will be omitted where it is determined that such descriptions would unnecessarily obscure the focus of this disclosure.

[0029] When using the terms “comprising,” “having,” and “including” as described in this specification, an additional part may be added unless “only” is used. Unless otherwise indicated, singular terms may include plural forms.

[0030] When interpreting components, even if not explicitly described, the components are interpreted as including a range of error.

[0031] When describing positional relationships, for example, when the positional relationship is described as "on," "above," "below," and "next to," one or more parts may be arranged between two other parts unless "exactly" or "directly" is used.

[0032] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “just” or “directly” is used.

[0033] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0034] The terms “first horizontal axis direction”, “second horizontal axis direction” and “vertical axis direction” should not be interpreted solely based on the geometric relationship that the directions are perpendicular to each other, but can be used to refer to directions with a wider directionality within the scope of the functionality of the components disclosed herein.

[0035] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third items" means all combinations of items proposed from two or more of the first, second, and third items, as well as the first, second, or third item.

[0036] Features of the various embodiments of this disclosure may be partially or wholly linked or combined with each other, and may interoperate differently with each other and be driven in a manner that will be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other, or may be implemented together in an interdependent relationship.

[0037] In this disclosure, the pixel circuits and gating drive circuits formed on the substrate of the display panel can be implemented using N-type or P-type transistors. For example, the transistor can be implemented as a thin-film transistor having an N-type or P-type metal-oxide-semiconductor field-effect transistor (MOSFET) structure. A thin-film transistor is a three-electrode device including a gate, a source, and a drain. In a thin-film transistor, charge carriers can flow from the source to the drain. In the case of an N-type thin-film transistor, since the charge carriers are electrons, the source voltage is relatively lower than the drain voltage, allowing electrons to flow from the source to the drain. In an N-type thin-film transistor, electrons flow from the source to the drain, thus the current direction is from the drain to the source. In the case of a P-type thin-film transistor, since the charge carriers are holes, the source voltage is relatively higher than the drain voltage, allowing holes to flow from the source to the drain. In a P-type thin-film transistor, holes flow from the source to the drain, thus the current direction is from the source to the drain. In a thin-film transistor with a MOSFET structure, the source and drain are not fixed but change according to the applied voltage. Therefore, in the description of this disclosure, either the source or the drain will be described as a first source / drain electrode, and the remaining one will be described as a second source / drain electrode.

[0038] Hereinafter, preferred embodiments of the gating drive circuit and the display device including the present disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts. Since the scales of the various elements shown in the drawings differ from the actual scales for ease of description, the present disclosure is not limited to the scales shown.

[0039] Figure 1 This is a block diagram of a display device according to various embodiments of the present disclosure.

[0040] Reference Figure 1 The display device 100 according to various embodiments of the present disclosure may include: a display panel 110 having a plurality of data lines DL and a plurality of gating lines GL and a plurality of pixels PX connected to the plurality of data lines DL and the plurality of gating lines GL; and a driving circuit for providing driving signals to the display panel 110.

[0041] In the accompanying drawings, multiple pixels PX are arranged in a matrix and configured to form a pixel array. However, this is not the only arrangement. Multiple pixels PX can be arranged in various ways, not limited to this.

[0042] The driving circuit may include: a data driving circuit 120 for providing data signals to multiple data lines DL; a gating driving circuit GD for providing gating signals to multiple gating lines GL; and a timing controller 130 for controlling the data driving circuit 120 and the gating driving circuit GD.

[0043] The display panel 110 may include a display area DA for displaying images and a non-display area NDA disposed around the periphery of the display area DA. Within the display area DA, there are multiple pixels PX, a data line DL for providing data signals to the multiple pixels PX, and a gating line GL for providing gating signals to the multiple pixels PX.

[0044] Multiple gate lines GL, located in the display area DA, can extend to the non-display area NDA and be electrically connected to the gate drive circuit GD. The gate lines GL electrically connect multiple pixels PX, located in a first direction (or horizontal direction), to the gate drive circuit GD. Additionally, in the non-display area, wiring related to gate driving can be provided to drive the multiple pixels PX or generate various gate signals for the gate drive circuit GD. For example, the wiring related to gate driving may include one or more high-level gate voltage lines for supplying a high-level gate voltage to the gate drive circuit GD, one or more low-level gate voltage lines for supplying a low-level gate voltage to the gate drive circuit GD, multiple clock lines for supplying multiple clock signals to the gate drive circuit GD, and one or more start lines for supplying one or more start signals to the gate drive circuit GD.

[0045] Multiple data lines DL disposed in the display area DA can extend to the non-display area NDA and can be electrically connected to the data driving circuit 120. The data lines DL electrically connect multiple pixels PX disposed in a second direction (or perpendicular direction) intersecting the first direction to the data driving circuit 120, or can be implemented as a single lead, or can be implemented by connecting multiple leads through contact holes using link wires.

[0046] In the display panel 110, multiple data lines DL and multiple gating lines GL are arranged together with the pixel array. As described above, the multiple data lines DL and multiple gating lines GL can be arranged horizontally or vertically. For ease of explanation, it is assumed that the multiple data lines DL are arranged vertically and the multiple gating lines GL are arranged horizontally, but this structure is not limited to.

[0047] The timing controller 130 starts scanning the data signal according to the timing implemented in each frame, converts the input image data from the outside according to the data signal format used in the data driving circuit 120, outputs the converted image data, and controls the data driving circuit 120 at the appropriate time according to the scanning.

[0048] The timing controller 130 receives timing signals from an external source, including a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a clock signal, along with the input image data. Upon receiving the timing signals, the timing controller 130 generates and outputs control signals for controlling the data drive circuit 120 and the gating drive circuit GD.

[0049] For example, the timing controller 130 outputs various data control signals, including a source start pulse, a source sampling clock, and a source output enable signal, to control the data drive circuit 120. The source start pulse controls the data sampling start timing of one or more data signal generation circuits constituting the data drive circuit 120. The source sampling clock is a clock signal used to control the sampling timing of data in each data signal generation circuit. The source output enable signal controls the output timing of the data drive circuit 120.

[0050] Additionally, the timing controller 130 outputs gating control signals, including a gating start pulse, a gating shift clock, and a gating output enable signal, to control the gating drive circuit GD. The gating start pulse controls the start timing of the operation of one or more gating signal generation circuits constituting the gating drive circuit GD. The gating shift clock is a clock signal that is commonly input to one or more gating signal generation circuits and controls the shift timing of the scan signal. The gating output enable signal specifies the timing information for one or more gating signal generation circuits.

[0051] The timing controller 130 can be a timing controller used in conventional display devices or a control device capable of performing other control functions (including the timing controller).

[0052] The timing controller 130 can be implemented as a component separate from the data drive circuit 120, or it can be integrated with the data drive circuit 120 to be implemented as an integrated circuit.

[0053] The data driving circuit 120 may include one or more data signal generation circuits. These data signal generation circuits may include shift registers, latch circuits, digital-to-analog converters, output buffers, etc. They may also include analog-to-digital converters.

[0054] The data signal generation circuit can be connected to the bonding pads of the display panel 110 via the tape-on-board (TAB) method, chip-on-glass (COG) method, or chip-on-panel (COP) method. It can be directly mounted on the display panel 110 or integrated into it. Alternatively, multiple data signal generation circuits can be implemented using the chip-on-film (COF) method, which mounts the data on the source circuit film connected to the display panel 110.

[0055] The gating drive circuit GD sequentially supplies gating signals to multiple gating lines GL, thereby driving multiple pixels PX connected to the multiple gating lines GL. The gating drive circuit GD may include shift registers, level shifters, etc.

[0056] The gating drive circuit GD can be connected to the bonding pads of the display panel 110 via the tape auto-bonding (TAB) method, the chip-on-glass (COG) method, or the chip-on-panel (COP) method, or it can be implemented according to the in-panel gating (GIP) method and directly disposed on the display panel 110. Additionally, multiple gating signal generation circuits can be mounted on the gate circuit film connected to the display panel 110 and can be implemented according to the chip-on-film (COF) method. The gating drive circuit GD includes multiple gating signal generation circuits, and these multiple gating signal generation circuits can be implemented according to the GIP type and disposed in the non-display area NDA of the display panel 110.

[0057] The gating drive circuit GD, under the control of the timing controller 130, sequentially supplies either a gating signal with a high gating voltage VGH (a first voltage level that turns the transistor on or off) or a gating signal with a low gating voltage VGL (a second voltage level that turns the transistor on or off). When the gating drive circuit GD supplies a signal to a specific gating line, the data drive circuit 120 converts the image data received from the timing controller 130 into an analog data signal and supplies the analog data signal to multiple data lines DL.

[0058] The data driving circuit 120 can be disposed on one side of the display panel 110. For example, the gating driving circuit GD can be disposed on the upper, lower, left, or right side of the display panel 110. Alternatively, the data driving circuit 120 can be disposed on both sides of the display panel 110 depending on the driving method, panel design method, etc. For example, the data driving circuit 120 can be disposed on the upper and lower sides, or the left and right sides of the display panel 110.

[0059] The gating drive circuit GD can be disposed on one side of the display panel 110. For example, the gating drive circuit GD can be disposed on the upper, lower, left, or right side of the display panel 110. Alternatively, the gating drive circuit GD can be disposed on both sides of the display panel 110 depending on the driving method, panel design method, etc. For example, the gating drive circuit GD can be disposed on the upper and lower sides or the left and right sides of the display panel 110. The gating drive circuit GD can be formed in the left and / or right non-display area NDA of the substrate along with the process of manufacturing the thin-film transistors of the pixel PX, and can operate according to a single-feed method to supply a gating signal to each of the multiple gating lines GL. Alternatively, the gating drive circuit GD can be formed on the left and right non-display areas NDA of the substrate, and can operate according to a dual-feed method to supply a gating signal to each of the multiple gating lines GL. Alternatively, the gating drive circuit GD can be formed in the left and right non-display areas NDA of the substrate, and can operate according to the interleaving method of the dual-feed method to supply gating signals to each of the multiple gating lines GL.

[0060] The gating drive circuit GD may include multiple stages of circuitry, which are connected interdependently to sequentially supply gating signals to each of the multiple gating lines GL.

[0061] Figure 2 The stage circuit of the gating drive circuit according to various embodiments of the present disclosure is schematically shown.

[0062] Reference Figure 2 The gating drive circuit GD may include multiple stages of circuit ST to drive multiple gating lines GL.

[0063] Each of the multiple stage circuits ST may include at least one logic controller 200 and at least one output circuit unit 300. The output circuit unit 300 may be an output circuit 300 and may be referred to as an output circuit 300.

[0064] Each output circuit unit 300 may include a pull-up transistor Tu and a pull-down transistor Td that alternately operate. The pull-up transistor Tu and the pull-down transistor Td may be represented as output buffers for output signals.

[0065] The clock signal CLK is applied to the drain node (or source node) of the pull-up transistor Tu. The source node (or drain node) of the pull-up transistor Tu is electrically connected to the output node Nout. The gate node of the pull-up transistor Tu can be the first node Q controlled by the logic controller 200.

[0066] A low-level voltage VSS (e.g., low-level voltage, low-level voltage, etc.) is applied to the drain node (or source node) of the pull-down transistor Td, the source node (or drain node) of the pull-down transistor Td is electrically connected to the output node Nout, and the gate node of the pull-down transistor Td can be a second node QB controlled by the logic controller 200.

[0067] The first node Q and the second node QB can have opposite voltage states. For example, if the first node Q is at a high voltage level, then the second node QB can be at a low voltage level. Conversely, if the first node Q is at a low voltage level, then the second node QB can be at a high voltage level.

[0068] When the pull-up transistor Tu is turned on according to the high voltage level (or low voltage level) of the first node Q, the pull-down transistor Td is turned off according to the low voltage level (or high voltage level) of the second node QB. When the pull-up transistor Tu is turned off according to the low voltage level (or high voltage level) of the first node Q, the pull-down transistor Td is turned on according to the high voltage level (or low voltage level) of the second node QB.

[0069] The output node Nout can be electrically connected to one of the scan control line, sense control line, and transmit control line among multiple gating lines GL.

[0070] When the pull-up transistor Tu is turned on, the clock signal CLK applied to the pull-up transistor Tu is output as an output signal through the output node Nout. The output signal output to the output node Nout can be one of a scan signal with a turn-on voltage level (or a first voltage level), a sensing signal, and a transmit signal EM.

[0071] When the pull-down transistor Td is in the ON state, the gating low potential voltage VSS (e.g., low potential voltage, gating low voltage, etc.) applied to the pull-down transistor Td is output as an output signal through the output node Nout. The output signal output to the output node Nout can be one of a scan signal, a sensing signal, and a transmit signal EM with a cutoff voltage level (or a second voltage level).

[0072] Logic controller 200 is a circuit for controlling the voltage of each of the first node Q and the second node QB, and may include two or more transistors (switching elements). Logic controller 200 can receive a set signal VST and set the operation of the corresponding stage circuit ST, and can receive a reset signal VRST and reset the operation of the corresponding stage circuit ST. Logic controller 200 can receive individual voltages to control the voltage of each of the first node Q and the second node QB.

[0073] However, if each stage circuit ST is connected one-to-one to one of the scan control line, sense control line, and transmit control line among the multiple gating lines GL, it is difficult to meet the requirements of new designs that require high resolution and narrow bezels.

[0074] The inventors of this disclosure propose a gating drive circuit capable of outputting "j" ("j" is an integer of 2 or greater) output signals, and a display device including the same.

[0075] Figure 3 The following diagram illustrates gating drive circuits according to various embodiments of the present disclosure. Figure 4 The stage circuit of the gating drive circuit according to various embodiments of the present disclosure is shown.

[0076] Reference Figure 3 The gating drive circuit GD according to various embodiments of this disclosure may include multiple stage circuits ST1, ST2, ST3, and ST4 that are interdependently connected. The gating drive circuit GD may also include a dummy stage circuit DST disposed at the front end of the first stage circuit ST1. Furthermore, the dummy stage circuit DST may be disposed at the end of the multiple stage circuits ST1, ST2, ST3, and ST4. It should be understood that "interdependently connected" circuits imply that the operation of some or all circuits depends on one or more outputs from another circuit. For example, multiple stage circuits ST1, ST2, ST3, and ST4 may be daisy-chained electrically connected to each other, wherein the operation of stage circuit ST4 is triggered by the output of stage circuit ST3, the operation of stage circuit ST3 is triggered by the output of stage circuit ST2, and the operation of stage circuit ST2 is triggered by the output of stage circuit ST1.

[0077] Multiple clock signals CRCLKs and SCCLKs, a gating high voltage VGH (or a gating high potential voltage, high potential voltage, etc.), multiple gating low voltages VGLs (or a gating low potential voltage, low potential voltage, etc.) and a gating start signal VST (or a setting signal) can be applied from the timing controller 130 to the gating drive circuit GD.

[0078] Multiple clock signals CRCLKs and SCCLKs may include scan clock signal SCCLKs and carry clock signal CRCLKs.

[0079] Each of the multiple stage circuits ST1, ST2, ST3, and ST4 can output "j" (where "j" is an integer of 2 or greater) output signals. Each of the stage circuits ST1, ST2, ST3, and ST4 can be connected to "j" gating lines GL, and can sequentially output "j" output signals to each of the "j" gating lines GL according to the clock signals CRCLKs and SCCLKs applied from the timing controller 130. For example, multiple scan clock signals SCCLKs can be sequentially applied to each of the stage circuits ST1, ST2, ST3, and ST4, and each of the stage circuits ST1, ST2, ST3, and ST4 can sequentially output each of the multiple scan clock signals SCCLKs as "j" scan signals SC. In addition, each stage circuit ST1, ST2, ST3, and ST4 can receive a carry clock signal CRCLK and output the carry clock signal CRCLK as a carry signal CR. The system provides "j" scan signals SC from the outputs of each of the slave circuits ST1, ST2, ST3, and ST4 to sequentially drive the corresponding gating lines GL. The carry signal CR from the outputs of each of the slave circuits ST1, ST2, ST3, and ST4 can be supplied as the previous carry signal (or gating start signal, setting signal) to any of the next stage circuits, or as the next carry signal (or reset signal) to any of the previous stage circuits.

[0080] The strobe drive circuit GD can receive a strobe start signal VST supplied from the timing controller 130. For example, the strobe start signal VST can be applied to the dummy stage circuit DST.

[0081] The strobe start signal (VST) is used to control the start time point of each of the image display segment and the black display segment in each frame, and can be generated immediately before the start time point of each of the image display segment and the black display segment. For example, the strobe start signal (VST) can be generated twice per frame.

[0082] The gating drive circuit GD can receive multiple clock signals CRCLKs and SCCLKs supplied from the timing controller 130. The multiple clock signals CRCLKs and SCCLKs may include scan clock signals SCCLKs and carry clock signals CRCLKs. For example, the carry clock signals CRCLKs may be a 3-phase clock signal shifted for a predetermined or selected time period, and the scan clock signals SCCLKs may be a 12-phase clock signal shifted for a predetermined or selected time period, but are not limited thereto.

[0083] The gating drive circuit GD can receive gating drive voltages VGH and VGLs with different voltage levels from a power supply (not shown). The gating drive voltages VGH and VGLs may include a gating high voltage VGH (or a gating high potential voltage, high potential voltage, etc.) and multiple gating low voltages VGLs (or gating low potential voltage, low potential voltage, etc.).

[0084] The dummy stage circuit DST can be located at the front end of the first stage circuit ST1. The dummy stage circuit DST can generate a dummy carry signal CR[d] in response to a strobe start signal VST supplied from the timing controller 130, and can supply the dummy carry signal CR[d] as either the previous carry signal or the strobe start signal to any one of the stage circuits ST1, ST2, ST3, and ST4. Alternatively, the dummy stage circuit DST can be located at the end of the stage circuits ST1, ST2, ST3, and ST4. The dummy stage circuit DST can generate the dummy carry signal CR[d] and can supply the dummy carry signal CR[d] as the next carry signal (or reset signal) to any one of the stage circuits ST1, ST2, ST3, and ST4.

[0085] Multiple stage circuits ST1, ST2, ST3, and ST4 can be connected interdependently. Each of the multiple stage circuits ST1, ST2, ST3, and ST4 can sequentially generate "j" ("j" is an integer of 2 or greater) scan signals SC[1]~SC[j], SC[j+1]~SC[2j], SC[2j+1]~SC[3j], and SC[3j+1]~SC[4j], and can supply the scan signals to the corresponding gating lines GL provided on the display panel 110. In addition, each of the multiple stage circuits ST1, ST2, ST3, and ST4 can generate carry signals CR[1], CR[2], CR[3], and CR[4], and can supply the generated carry signals as the previous carry signal (or gating start signal, setting signal) to any of the next stage circuits, or can supply the generated carry signals as the next carry signal (or reset signal) to any of the previous stage circuits.

[0086] Reference Figure 4 The stage circuit ST[1] may include a logic controller 200 and an output circuit unit 300.

[0087] The logic controller 200 is a circuit for controlling the voltage in each of the first node Q and the second node QB, and may include two or more transistors (switching elements). The logic controller 200 receives a set signal VST and sets the operation of the corresponding stage circuit ST[1], and receives a reset signal VRST and resets the operation of the corresponding stage circuit ST[1]. The set signal VST may be the previous carry signal output from the previous stage circuit, and the reset signal VRST may be the next carry signal output from the next stage circuit.

[0088] The output circuit unit 300 can output an output signal according to the voltage of the first node Q or the second node QB controlled by the logic controller 200. The output circuit unit 300 can receive "j" scan clock signals SCCLKs from a plurality of scan clock signals SCCLKs and one carry clock signal CRCLK from a plurality of carry clock signals CRCLKs, and can output "j" scan signals SC[1] to SC[j] and a carry signal CR[1] according to the voltage of the first node Q or the second node QB controlled by the logic controller 200.

[0089] Figure 5 This is a circuit diagram of an output circuit unit according to one embodiment of the present disclosure. Figure 6 It shows that it is applied to Figure 5 The diagram shows the waveforms of the scan clock signal of the output circuit unit, the scan signal output from the output circuit unit, and the voltage waveform of the first node.

[0090] Reference Figure 5 According to one embodiment of the present disclosure, the output circuit unit 300 may include a scan output circuit unit 310 and a carry output circuit unit 320. The scan output circuit unit 310 and the carry output circuit unit 320 may be respectively the scan output circuit 310 and the carry output circuit 320, and may be referred to as the scan output circuit 310 and the carry output circuit 320.

[0091] The carry output circuit unit 320 can output a carry clock signal CRCLK[n] as a carry signal CR[n] based on the voltage level of the first node Q or the second node QB. The carry output circuit unit 320 may include a carry signal output buffer, which includes a carry pull-up transistor Tuc and a carry pull-down transistor Tdc. The carry output circuit unit 320 can be a single carry signal output buffer used to output one of multiple carry clock signals CRCLKs, CRCLK[n], as the carry signal CR[n].

[0092] The carry pull-up transistor Tuc and the carry pull-down transistor Tdc can be connected in series between the terminal where the carry clock signal CRCLK[n] is applied and the terminal where the first gating low voltage VGL1 is applied, and the carry pull-up transistor Tuc can output the carry signal CR[n] through the carry output node connected between the carry pull-up transistor Tuc and the carry pull-down transistor Tdc.

[0093] The carry pull-up transistor Tuc can output a carry signal CR[n] with a first voltage level corresponding to the carry clock signal CRCLK[n] in response to the voltage of the first node Q. The carry signal CR[n] can be supplied to any of the next stage circuits as the previous carry signal (or strobe start signal, set signal, etc.). For example, the carry pull-up transistor Tuc may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the carry output node, and a second source / drain electrode connected to the terminal where the carry clock signal CRCLK[n] is applied.

[0094] The carry pull-down transistor Tdc can output a carry signal CR[n] with a second voltage level corresponding to the first gating low voltage VGL1 (or gating low potential voltage, low potential voltage, etc.) based on the voltage of the second node QB. The carry signal CR[n] can be supplied to any of the next stage circuits as the next carry signal (or reset signal). For example, the carry pull-down transistor Tdc may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the carry output node, and a second source / drain electrode connected to the terminal where the first gating low voltage VGL1 is applied.

[0095] The scan output circuit unit 310 can output "j" scan signals SC[n] to SC[n+3] in a predetermined order according to the voltage level of the first node Q or the second node QB.

[0096] like Figure 5 As shown, when "j" is 4, the scan output circuit unit 310 may include a first scan signal output buffer 311, a second scan signal output buffer 312, a third scan signal output buffer 313 and a fourth scan signal output buffer 314, which are respectively used to output the four scan clock signals of the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] among the multiple scan clock signals SCCLKs as the (n)th scan signal SC[n] to the (n+3)th scan signal SC[n+3].

[0097] The first scan signal output buffer 311 may include a first scan pull-up transistor Tu1, a first scan pull-down transistor Td1, and a first capacitor C1. The second scan signal output buffer 312 may include a second scan pull-up transistor Tu2, a second scan pull-down transistor Td2, and a second capacitor C2. The third scan signal output buffer 313 may include a third scan pull-up transistor Tu3, a third scan pull-down transistor Td3, and a third capacitor C3. The fourth scan signal output buffer 314 may include a fourth scan pull-up transistor Tu4, a fourth scan pull-down transistor Td4, and a fourth capacitor C4.

[0098] Each of the first to fourth scan pull-up transistors Tu1, Tu2, Tu3, and Tu4, and each of the first to fourth scan pull-down transistors Td1, Td2, Td3, and Td4, may be connected in series between the terminal where the respective scan clock signals SCCLK[n] to SCCLK[N+3] are applied and the terminal where the second gate low voltage VGL2 is applied. Each of the first to fourth capacitors C1, C2, C3, and C4 may be connected between the gate electrode of the respective first to fourth scan pull-up transistors Tu1, Tu2, Tu3, and Tu4 and the respective scan output node between the respective first to fourth scan pull-up transistors Tu1, Tu2, Tu3, and Tu4 and the respective first to fourth scan pull-down transistors Td1, Td2, Td3, and Td4. The first to fourth capacitors C1, C2, C3, and C4 may be capacitors with the same capacitance. For example, the first to fourth capacitors C1, C2, C3, and C4 may all have a capacitance of 2.5 picofarads (pF).

[0099] Reference Figure 6According to one embodiment of this disclosure, each of the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] applied to the scan output circuit unit 310 can oscillate between a first voltage level (or a gated high voltage) and a second voltage level (or a gated low voltage), and may include a pulse period that maintains the first voltage level for a predetermined or selected level period. For example, the pulse period of each of the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] can be maintained for two level periods 2H, and the rise time and fall time of each pulse period may be different from each other. Each of the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] can be sequentially shifted for a predetermined or selected period and may have a first voltage level within two level periods 2H, and adjacent scan clock signals may overlap with each other within a period shorter than two level periods 2H. For example, adjacent scan clock signals may overlap with each other within one level period 1H. It should be understood that a "sequentially shifted" signal implies that the pulse period of an earlier signal in the sequence begins before the pulse period of a later signal in the sequence, such that the later signal in a neighboring pair rises after the earlier signal in the neighboring pair. For example, as... Figure 6 As shown, the rising edge of the pulse period of the (n)th scan clock signal SCCLK[n] occurs before the rising edge of the pulse period of the (n+1)th scan clock signal SCCLK[n+1], the rising edge of the pulse period of the (n+1)th scan clock signal SCCLK[n+1] occurs before the rising edge of the pulse period of the (n+2)th scan clock signal SCCLK[n+2], and so on. Although Figure 6 The pulse durations shown are the same (i.e., 2H), but "sequential shifting" does not require the pulse durations to be the same.

[0100] Reference Figure 5 and Figure 6 In the scan output circuit unit 310, the first scan pull-up transistor Tu1 can output the (n)th scan clock signal SCCLK[n] as the (n)th scan signal SC[n] through the scan output node in response to the voltage of the first node Q. At this time, the voltage of the first node Q is bootstrapping through the first capacitor C1 formed between the gate electrode of the first scan pull-up transistor Tu1 and the scan output node.

[0101] The second scan pull-up transistor Tu2 can respond to the voltage of the first node Q boosted by the first capacitor C1 by outputting the (n+1)th scan clock signal SCCLK[n+1] as the (n+1)th scan signal SC[n+1] through the scan output node. At this time, the boosted voltage of the first node Q is again bootstrapped by the second capacitor C2 formed between the gate electrode of the second scan pull-up transistor Tu2 and the scan output node.

[0102] Subsequently, the third scan pull-up transistor Tu3, in response to the voltage of the first node Q being boosted again through the second capacitor C2, outputs the (n+2)th scan clock signal SCCLK[n+2] as the (n+2)th scan signal SC[n+2] through the scan output node. At this time, the rising time of the (n+2)th scan clock signal SCCLK[n+2] coincides with the falling time of the (n)th scan clock signal SCCLK[n], and the third capacitor C3 formed between the gate electrode of the third scan pull-up transistor Tu3 and the scan output node is offset relative to the first capacitor C1, so that the voltage of the first node Q is not increased again through the third capacitor C3 and the boosted voltage is maintained through the second capacitor C2.

[0103] The fourth scan pull-up transistor Tu4 can output the (n+3)th scan clock signal SCCLK[n+3] as the (n+3)th scan signal SC[n+3] through the scan output node in response to the voltage of the first node Q maintained by the third capacitor C3. At this time, the rising time of the (n+3)th scan clock signal SCCLK[n+3] coincides with the falling time of the (n+1)th scan clock signal SCCLK[n+1], and the fourth capacitor C4 and the second capacitor C2 formed between the gate electrode of the fourth scan pull-up transistor Tu4 and the scan output node are offset relative to each other, so that the voltage of the first node Q is not increased by the fourth capacitor C4, and the boost voltage is maintained by the third capacitor C3 and the voltage of the first node Q is continuously reduced by the falling of the (n+2)th scan clock signal SCCLK[n+2] and the falling of the (n+3)th scan clock signal SCCLK[n+3].

[0104] like Figure 5 and Figure 6 As shown, in a scan output circuit unit 310 according to one embodiment of the present disclosure, a method is proposed to arrange capacitors C1, C2, C3 and C4 with the same capacitance for each of the first to fourth scan signal output buffers 311, 312, 313 and 314.

[0105] Therefore, since the first scan signal output buffer 311 has a small impact on the first node Q, and the first capacitor C1 of the first scan signal output buffer 311 and the second capacitor C2 of the second scan signal output buffer 312 act as holding capacitors, a deviation Δq occurs in the boost level of the first node Q. Consequently, a deviation ΔV occurs between the (n)th scan signal SC[n] output from the first scan signal output buffer 311 and the (n+1)th scan signal SC[n+1] output from the second scan signal output buffer 312, thereby generating a periodic brightness deviation in the image displayed on the display panel 110. Furthermore, the rise time of the (n)th scan signal SC[n] output from the first scan signal output buffer 311 can be delayed.

[0106] Therefore, in order to achieve a narrow bezel, the inventors of this disclosure propose a gating drive circuit with a novel structure and a display device including the same, which is capable of outputting "j" (j is an integer of 2 or greater) output signals and reducing the output deviation of each scan signal when multiple scan signals are output sequentially from a stage circuit.

[0107] First Implementation Method

[0108] Figure 7 This is a circuit diagram of the output circuit unit according to the first embodiment of the present disclosure. Figure 8 It shows that it is applied to Figure 7 The scan clock signal of the output circuit unit shown, from Figure 7 The output circuit unit shown in the diagram displays the scan signal output by the first node and the waveform of the first node.

[0109] Reference Figure 7 The output circuit unit 300 according to the first embodiment of this disclosure may include a scan output circuit unit 310 and a carry output circuit unit 320. The output circuit unit 300 according to the first embodiment of this disclosure implements the scan output circuit unit 310 to output four scan signals. For example, when a pixel PX of the display panel 110 has four sub-pixels, the output circuit unit 300 according to the first embodiment of this disclosure can drive each sub-pixel by sequentially supplying the four scan signals to the corresponding gating lines GL. Alternatively, the output circuit unit 300 according to the first embodiment of this disclosure can drive the pixel PX corresponding to the four horizontal lines by sequentially supplying the four scan signals to the gating lines GL corresponding to the four horizontal lines in the display panel 110. However, the output circuit unit 300 of this disclosure is not limited to outputting only scan signals; it may be implemented to provide a sensing signal SENSE or a transmission signal EM.

[0110] The carry output circuit unit 320 can output a carry clock signal CRCLK[n] as a carry signal CR[n] based on the voltage level of the first node Q or the second node QB. The carry output circuit unit 320 may include a carry signal output buffer, which includes a carry pull-up transistor Tuc and a carry pull-down transistor Tdc. The carry output circuit unit 320 may be a single carry signal output buffer for outputting one of multiple carry clock signals CRCLKs, CRCLK[n], as the carry signal CR[n].

[0111] The carry pull-up transistor Tuc and the carry pull-down transistor Tdc can be connected in series between the terminal where the carry clock signal CRCLK[n] is applied and the terminal where the first gating low voltage VGL1 is applied, and the carry signal CR[n] can be output through the carry output node connected between the carry pull-up transistor Tuc and the carry pull-down transistor Tdc.

[0112] The carry pull-up transistor Tuc can output a carry signal CR[n] with a first voltage level corresponding to the carry clock signal CRCLK[n] in response to the voltage of the first node Q. The carry signal CR[n] can be supplied to any of the next stage circuits as the previous carry signal (or strobe start signal, set signal, etc.). For example, the carry pull-up transistor Tuc may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the carry output node, and a second source / drain electrode connected to the terminal where the carry clock signal CRCLK[n] is applied.

[0113] The carry pull-down transistor Tdc can output a carry signal CR[n] with a second voltage level corresponding to the first gating low voltage VGL1 (or gating low potential voltage, low potential voltage, etc.) based on the voltage of the second node QB. The carry signal CR[n] can be supplied to any of the next stage circuits as the next carry signal (or reset signal). For example, the carry pull-down transistor Tdc may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the carry output node, and a second source / drain electrode connected to the terminal where the first gating low voltage VGL1 is applied.

[0114] According to the first embodiment of the present disclosure, the scan output circuit unit 310 may include first to fourth scan signal output buffers 311, 312, 313 and 314 to output the four scan clock signals SCCLK[n] to SCCLK[n+3] of the plurality of scan clock signals SCCLKs as the (n) scan signal SC[n] to the (n+3) scan signal SC[n+3].

[0115] The first scan signal output buffer 311 may include a first scan pull-up transistor Tu1, a first scan pull-down transistor Td1, and a first boost capacitor Cb1. The second scan signal output buffer 312 may include a second scan pull-up transistor Tu2 and a second scan pull-down transistor Td2. The third scan signal output buffer 313 may include a third scan pull-up transistor Tu3, a third scan pull-down transistor Td3, and a second boost capacitor Cb2. The fourth scan signal output buffer 314 may include a fourth scan pull-up transistor Tu4 and a fourth scan pull-down transistor Td4.

[0116] Each of the first to fourth scan pull-up transistors Tu1, Tu2, Tu3, and Tu4, and each of the first to fourth scan pull-down transistors Td1, Td2, Td3, and Td4, can be connected in series between the terminal where the respective scan clock signals SCCLK[n] to SCCLK[n+3] are applied and the terminal where the second gate low voltage VGL2 is applied. A first boost capacitor Cb1 can be connected between the gate electrode of the first scan pull-up transistor Tu1 and the output node between the first scan pull-up transistor Tu1 and the first scan pull-down transistor Td1, and a second boost capacitor Cb2 can be connected between the gate electrode of the third scan pull-up transistor Tu3 and the output node between the third scan pull-up transistor Tu3 and the third scan pull-down transistor Td3. The first boost capacitor Cb1 and the second boost capacitor Cb2 can have different capacitances. For example, the first boost capacitor Cb1 can have a larger capacitance than the second boost capacitor Cb2. For example, the first boost capacitor Cb1 may have a capacitance greater than that of the second boost capacitor Cb2, and may have a capacitance equal to or less than twice the capacitance of the second boost capacitor Cb2. For example, the first boost capacitor Cb1 may be set to 5pF, and the second boost capacitor Cb2 may be set to 2.5pF.

[0117] Reference Figure 8According to the first embodiment of this disclosure, each of the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] applied to the scan output circuit unit 310 can swing between a first voltage level (or a gated high voltage) and a second voltage level (or a gated low voltage), and may include a pulse period for maintaining the first voltage level for a predetermined or selected level period. For example, the pulse period of each of the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] can be maintained for two level periods 2H, and the rise time and fall time of each pulse period may be different from each other. Each of the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] can be sequentially shifted for a predetermined or selected period and may have a first voltage level within two level periods 2H, and adjacent scan clock signals may overlap with each other within a period shorter than two level periods 2H. For example, adjacent scan clock signals may overlap with each other within one level period 1H. Furthermore, the rising time of any one of the scan clock signals SCCLK[n] to SCCLK[n+3] can coincide with the falling time of another scan clock signal. For example, the falling time of the (n)th scan clock signal SCCLK[n] can coincide with the rising time of the (n+2)th scan clock signal SCCLK[n+2], and the falling time of the (n+1)th scan clock signal SCCLK[n+1] can coincide with the rising time of the (n+3)th scan clock signal SCCLK[n+3].

[0118] Reference Figure 7 and Figure 8 In the scan output circuit unit 310 according to the first embodiment of the present disclosure, the first scan signal output buffer 311 can output the first scan clock signal SCCLK[n] among the (n)th scan clock signals SCCLK[n] to (n+3)th scan clock signals SCCLK[n+3] as the (n)th scan signal SC[n]. In the case of the first scan signal output buffer 311, the first boost capacitor Cb1 can be disposed between the gate electrode of the first scan pull-up transistor Tu1 and the scan output node. The first scan signal output buffer 311 can be represented as a boost scan signal output buffer for boosting the voltage of the first node Q through the first boost capacitor Cb1.

[0119] The first scan pull-up transistor Tu1 of the first scan signal output buffer 311 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal of the first applied (n) scan clock signal SCCLK[n]. The first scan pull-up transistor Tu1 may be represented as a boost scan pull-up transistor that switches according to the voltage of the first node Q to output the (n) scan clock signal SCCLK[n] through the scan output node as the (n) scan signal SC[n] with a first voltage level.

[0120] The first scan pull-down transistor Td1 of the first scan signal output buffer 311 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The first scan pull-down transistor Td1 may be represented by a boost scan pull-down transistor, which switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n)th scan signal SC[n] having a second voltage level.

[0121] The first boost capacitor Cb1 of the first scan signal output buffer 311 can be implemented between the first node Q and the scan output node. The first boost capacitor Cb1 can generate bootstrapping in the first node Q according to the phase transition (or the rise of the pulse period) of the first applied (n) scan clock signal SCCLK[n]. Since the first boost capacitor Cb1 is not affected by the carry clock signal CRCLK[n], the boost voltage of the first node Q can be increased. The first boost capacitor Cb1 can be set to have sufficient capacitance to increase the bootstrapping time of the first node Q in order to improve the rise time of the (n) scan signal SC[n] first output from the scan output circuit unit 310.

[0122] The second scan signal output buffer 312 can output the (n+1)th scan clock signal SCCLK[n+1] as the (n+1)th scan signal SC[n+1] through the scan output node. The second scan signal output buffer 312 can be represented as a normal scan signal output buffer without a capacitor.

[0123] The second scan pull-up transistor Tu2 of the second scan signal output buffer 312 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+1)th scan clock signal SCCLK[n+1]. The second scan pull-up transistor Tu2 may be represented as a normal scan pull-up transistor, which switches according to the voltage of the first node Q boosted by the first boost capacitor Cb1 to output the (n+1)th scan clock signal SCCLK[n+1] through the scan output node as the (n+1)th scan signal SC[n+1] with a first voltage level. At this time, since the (n+1)th scan clock signal SCCLK[n+1] overlaps with the (n)th scan clock signal SCCLK[n] corresponding to the previous signal in a horizontal time period 1H, the rise time of the pulse period does not coincide with the fall time of the other scan clock signal. Therefore, the second scan signal output buffer 312 is not affected by the (n)th scan clock signal SCCLK[n], that is, it does not generate enhancement or offset, thereby maintaining the boost voltage through the first boost capacitor Cb1.

[0124] The second scan pull-down transistor Td2 of the second scan signal output buffer 312 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The second scan pull-down transistor Td2 may be represented as a normal scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+1)th scan signal SC[n+1] with a second voltage level.

[0125] The third scan signal output buffer 313 can output the (n+2)th scan clock signal SCCLK[n+2] as the (n+2)th scan signal SC[n+2] through the scan output node. At this time, the (n+2)th scan clock signal SCCLK[n+2] can rise to coincide with the falling time of the (n)th scan clock signal SCCLK[n] corresponding to the previous signal. In the case of the third scan signal output buffer 313, the second boost capacitor Cb2 can be disposed between the gate electrode of the third scan pull-up transistor Tu3 and the scan output node. The third scan signal output buffer 313 can be represented as a boost scan signal output buffer for boosting the voltage of the first node Q through the second boost capacitor Cb2.

[0126] The third scan pull-up transistor Tu3 of the third scan signal output buffer 313 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+2)th scan clock signal SCCLK[n+2]. The third scan pull-up transistor Tu3 may be represented as a boost scan pull-up transistor, which switches according to the voltage of the first node Q to output the (n+2)th scan clock signal SCCLK[n+2] through the scan output node as the (n+2)th scan signal SC[n+2] with a first voltage level.

[0127] The third scan pull-down transistor Td3 of the third scan signal output buffer 313 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The third scan pull-down transistor Td3 may be represented as a boost scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+2)th scan signal SC[n+2] with a second voltage level.

[0128] The second boost capacitor Cb2 of the third scan signal output buffer 313 can be implemented between the first node Q and the scan output node. The second boost capacitor Cb2 can generate a bootstrap in the first node Q according to the phase transition (or the rise of the pulse period) of the (n+2)th scan clock signal SCCLK[n+2]. According to the (n+2)th scan clock signal SCCLK[n+2], it can rise to coincide with the fall time of the (n)th scan clock signal SCCLK[n] corresponding to the previous signal, and can be affected to offset it. The second boost capacitor Cb2 can boost the voltage of the first node Q to prevent the output deviation of the (n+2)th scan signal SC[n+2]. If the second boost capacitor Cb2 can only generate a bootstrap level sufficient to maintain the boost voltage of the first node Q, the capacitance of the second boost capacitor Cb2 can be set to be smaller than the capacitance of the first boost capacitor Cb1.

[0129] The fourth scan signal output buffer 314 can output the (n+3)th scan clock signal SCCLK[n+3] as the (n+3)th scan signal SC[n+3] through the scan output node. The fourth scan signal output buffer 314 can be represented as a normal scan signal output buffer without a capacitor.

[0130] The fourth scan pull-up transistor Tu4 of the fourth scan signal output buffer 314 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+3)th scan clock signal SCCLK[n+3]. The fourth scan pull-up transistor Tu4 can be represented as a normal scan pull-up transistor, which switches according to the voltage of the first node Q boosted by the second boost capacitor Cb2 to output the (n+3)th scan clock signal SCCLK[n+3] through the scan output node as the (n+3)th scan signal SC[n+3] with a first voltage level. At this time, since the (n+3)th scan clock signal SCCLK[n+3] can rise to coincide with the falling time of the (n)th scan clock signal SCCLK[n] corresponding to the previous signal. However, since no capacitor is provided in the second scan signal output buffer 312, no boost or offset is generated without any effect, thereby maintaining the boost voltage through the second boost capacitor Cb2.

[0131] The fourth scan pull-down transistor Td4 of the fourth scan signal output buffer 314 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The fourth scan pull-down transistor Td4 may be represented as a normal scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+3)th scan signal SC[n+3] with a second voltage level.

[0132] like Figure 7 and Figure 8 As shown, in the scan output circuit unit 310 according to the first embodiment of the present disclosure, boost capacitors Cb1 and Cb2 are only provided in the first scan signal output buffer 311 for first outputting the (n)th scan signal SC[n] and the third scan signal output buffer 313 affected by the (n)th scan clock signal SCCLK[n] applied to the first scan signal output buffer 311.

[0133] Therefore, the voltage of the first node Q is sufficiently bootstrapping during the timing of the first output of the (n)th scan signal SC[n] by the scan output circuit unit 310. This improves the rise time of the (n)th scan signal SC[n] and reduces the output deviation between the (n)th scan signal SC[n] and the subsequent (n+1)th to (n+3)th scan signals SC[n+3]. Furthermore, the boost capacitors Cb1 and Cb2 can be arranged only in some of the scan signal output buffers 311 and 313 of the scan output circuit unit 310, thereby reducing the size of the gating drive circuit GD and easily achieving a narrow bezel.

[0134] Second Implementation Method

[0135] Figure 9 This is a circuit diagram of the output circuit unit according to the second embodiment of the present disclosure. Figure 10 It shows that it is applied to Figure 9 The scan clock signal of the output circuit unit shown, from Figure 9 The diagram shows the scan signal output by the output circuit unit and the waveform of the first node. In the description of the second embodiment, descriptions of configurations identical to those in the first embodiment will be omitted.

[0136] Reference Figure 9 and Figure 10 According to the second embodiment of this disclosure, the output circuit unit 300 implements the scan output circuit unit 310 to output two scan signals. For example, when a pixel PX of the display panel 110 has four sub-pixels, the output circuit unit 300 according to the second embodiment of this disclosure can drive each sub-pixel by sequentially supplying two scan signals to the gating lines GL corresponding to two of the four sub-pixels. Alternatively, the output circuit unit 300 according to the second embodiment of this disclosure can drive the pixel PX corresponding to the two horizontal lines by sequentially supplying two scan signals to the gating lines GL corresponding to the two horizontal lines of the display panel 110. However, the output circuit unit 300 according to this disclosure is not limited to outputting only scan signals, and can be implemented to provide a sensing signal SENSE or a transmission signal EM.

[0137] According to the second embodiment of the present disclosure, the scan output circuit unit 310 may include a first scan signal output buffer 311 and a second scan signal output buffer 312 for outputting the (n)th scan clock signal SCCLK[n] and the (n+1)th scan clock signal SCCLK[n+1] of a plurality of scan clock signals SCCLKs as the (n)th scan signal SC[n] and the (n+1)th scan signal SC[n+1].

[0138] The first scan signal output buffer 311 may include a first scan pull-up transistor Tu1, a first scan pull-down transistor Td1, and a first boost capacitor Cb1. The second scan signal output buffer 312 may include a second scan pull-up transistor Tu2 and a second scan pull-down transistor Td2.

[0139] The first scan pull-up transistor Tu1 and the second scan pull-up transistor Tu2, as well as the first scan pull-down transistor Td1 and the second scan pull-down transistor Td2, can be connected in series between the terminals where the scan clock signals SCCLK[n] and SCCLK[n+1] are applied and the terminal where the second gate low voltage VGL2 is applied. The first boost capacitor Cb1 can be connected between the gate electrode of the first scan pull-up transistor Tu1 and the output node between the first scan pull-up transistor Tu1 and the first scan pull-down transistor Td1.

[0140] Reference Figure 10 According to the second embodiment of this disclosure, the (n)th scan clock signal SCCLK[n] and the (n+1)th scan clock signal SCCLK[n+1] applied to the scan output circuit unit 310 may include pulse periods that oscillate between a first voltage level (or a gated high voltage) and a second voltage level (or a gated low voltage) and remain at the first voltage level within a predetermined or selected horizontal period. For example, the pulse periods of the (n)th scan clock signal SCCLK[n] and the (n+1)th scan clock signal SCCLK[n+1] may be maintained for two horizontal periods 2H, and the rise and fall times of each pulse period may be different from each other. The (n)th scan clock signal SCCLK[n] and the (n+1)th scan clock signal SCCLK[n+1] are sequentially shifted by a predetermined or selected period and have the first voltage level within the two horizontal periods, and adjacent scan clock signals may overlap with each other within a period shorter than the two horizontal periods 2H. For example, adjacent scan clock signals may overlap with each other during a horizontal period 1H. In addition, the rise time and fall time of each of the (n)th scan clock signal SCCLK[n] and the (n+1)th scan clock signal SCCLK[n+1] may not coincide with each other.

[0141] Reference Figure 9 and Figure 10 In the scan output circuit unit 310 according to the second embodiment of the present disclosure, the first scan signal output buffer 311 can output the first applied (n) scan clock signal SCCLK[n] as the (n) scan signal SC[n] through the scan output node. In the first scan signal output buffer 311, the first boost capacitor Cb1 can be disposed between the gate electrode of the first scan pull-up transistor Tu1 and the scan output node. The first scan signal output buffer 311 can be represented as a boost scan signal output buffer for boosting the voltage of the first node Q through the first boost capacitor Cb1.

[0142] The first scan pull-up transistor Tu1 of the first scan signal output buffer 311 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal of the first applied (n) scan clock signal SCCLK[n]. The first scan pull-up transistor Tu1 may be represented as a boost scan pull-up transistor that switches according to the voltage of the first node Q to output the (n) scan clock signal SCCLK[n] through the scan output node as the (n) scan signal SC[n] with a first voltage level.

[0143] The first scan pull-down transistor Td1 of the first scan signal output buffer 311 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The first scan pull-down transistor Td1 may be represented by a boost scan pull-down transistor, which switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n)th scan signal SC[n] having a second voltage level.

[0144] The first boost capacitor Cb1 of the first scan signal output buffer 311 can be implemented between the first node Q and the scan output node. The first boost capacitor Cb1 can generate bootstrapping in the first node Q according to the phase transition (or the rise of the pulse period) of the first applied (n) scan clock signal SCCLK[n]. Since the first boost capacitor Cb1 is not affected by the carry clock signal CRCLK[n], the boost voltage of the first node Q can be increased. The first boost capacitor Cb1 can be set to have sufficient capacitance to increase the bootstrapping time of the first node Q in order to improve the rise time of the (n) scan signal SC[n] first output from the scan output circuit unit 310.

[0145] The second scan signal output buffer 312 can output the (n+1)th scan clock signal SCCLK[n+1] as the (n+1)th scan signal SC[n+1] through the scan output node. The second scan signal output buffer 312 can be represented as a normal scan signal output buffer without a capacitor.

[0146] The second scan pull-up transistor Tu2 of the second scan signal output buffer 312 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+1)th scan clock signal SCCLK[n+1]. The second scan pull-up transistor Tu2 may be represented as a normal scan pull-up transistor, which switches according to the voltage of the first node Q boosted by the first boost capacitor Cb1 to output the (n+1)th scan clock signal SCCLK[n+1] through the scan output node as the (n+1)th scan signal SC[n+1] with a first voltage level. At this time, since the (n+1)th scan clock signal SCCLK[n+1] overlaps with the (n)th scan clock signal SCCLK[n] corresponding to the previous signal in a horizontal time period 1H, the rise time of the pulse period does not coincide with the fall time of the other scan clock signal. Therefore, the second scan signal output buffer 312 is not affected by the (n)th scan clock signal SCCLK[n], that is, it does not generate enhancement or offset, thereby maintaining the boost voltage through the first boost capacitor Cb1.

[0147] The second scan pull-down transistor Td2 of the second scan signal output buffer 312 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The second scan pull-down transistor Td2 may be represented as a normal scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+1)th scan signal SC[n+1] with a second voltage level.

[0148] Third Implementation Method

[0149] Figure 11 This is a circuit diagram of the output circuit unit according to the third embodiment of this disclosure. Figure 12 It shows that it is applied to Figure 11 The scan clock signal of the output circuit unit shown, from Figure 11 The diagram shows the scan signal output by the output circuit unit and the waveform of the first node. In the description of the third embodiment, descriptions of configurations identical to those in the first and second embodiments will be omitted.

[0150] Reference Figure 11 and Figure 12According to the third embodiment of this disclosure, the output circuit unit 300 implements the scan output circuit unit 310 to output three scan signals. For example, when a pixel PX of the display panel 110 has three sub-pixels, the output circuit unit 300 according to the third embodiment of this disclosure can drive each sub-pixel by sequentially supplying three scan signals to the gating lines GL corresponding to the three sub-pixels. Alternatively, the output circuit unit 300 according to the third embodiment of this disclosure can drive the pixel PX corresponding to the three horizontal lines by sequentially supplying three scan signals to the gating lines GL corresponding to the three horizontal lines of the display panel 110. However, the output circuit unit 300 according to this disclosure is not limited to outputting only scan signals, and can be implemented to provide a sensing signal SENSE or a transmission signal EM.

[0151] According to the third embodiment of the present disclosure, the scan output circuit unit 310 may include first to third scan signal output buffers 311, 312 and 313 to output the (n)th scan clock signal SCCLK[n] to the (n+2)th scan clock signal SCCLK[n+2] of the plurality of scan clock signals SCCLKs as the (n)th scan signal SC[n] to the (n+2)th scan signal SC[n+2].

[0152] The first scan signal output buffer 311 may include a first scan pull-up transistor Tu1, a first scan pull-down transistor Td1, and a first boost capacitor Cb1. The second scan signal output buffer 312 may include a second scan pull-up transistor Tu2 and a second scan pull-down transistor Td2. The third scan signal output buffer 313 may include a third scan pull-up transistor Tu3, a third scan pull-down transistor Td3, and a second boost capacitor Cb2.

[0153] The first to third scan pull-up transistors Tu1, Tu2, and Tu3 and the first to third scan pull-down transistors Td1, Td2, and Td3 can be connected in series between the terminals to which scan clock signals SCCLK[n] to SCCLK[N+2] are applied and the terminals to which the second gate low voltage VGL2 is applied. A first boost capacitor Cb1 can be connected between the gate electrode of the first scan pull-up transistor Tu1 and the output node between the first scan pull-up transistor Tu1 and the first scan pull-down transistor Td1, and a second boost capacitor Cb2 can be connected between the gate electrode of the third scan pull-up transistor Tu3 and the output node between the third scan pull-up transistor Tu3 and the third scan pull-down transistor Td3. The first boost capacitor Cb1 and the second boost capacitor Cb2 can have different capacitances. For example, the first boost capacitor Cb1 can have a larger capacitance than the second boost capacitor Cb2. For example, the first boost capacitor Cb1 can have a larger capacitance than the second boost capacitor Cb2, and can have a capacitance equal to or less than twice the capacitance of the second boost capacitor Cb2.

[0154] Reference Figure 11 According to the third embodiment of this disclosure, each of the (n)th scan clock signal SCCLK[n] to the (n+2)th scan clock signal SCCLK[n+2] applied to the scan output circuit unit 310 may include a pulse period that oscillates between a first voltage level (or a gated high voltage) and a second voltage level (or a gated low voltage), and maintains the first voltage level within a predetermined or selected horizontal period. For example, the pulse period of each of the (n)th scan clock signal SCCLK[n] to the (n+2)th scan clock signal SCCLK[n+2] may be maintained for two horizontal periods 2H, and the rise and fall times of each pulse period may be different from each other. Each of the (n)th scan clock signal SCCLK[n] to the (n+2)th scan clock signal SCCLK[n+2] may be sequentially shifted by a predetermined or selected period and may have the first voltage level within two horizontal periods 2H, and adjacent scan clock signals may overlap with each other within a period shorter than two horizontal periods 2H. For example, adjacent scan clock signals may overlap with each other during a horizontal period 1H. Furthermore, the rise time of any one of the scan clock signals SCCLK[n] to SCCLK[n+2] can coincide with the fall time of the other scan clock signal. For example, the fall time of the (n)th scan clock signal SCCLK[n] can coincide with the rise time of the (n+2)th scan clock signal SCCLK[n+2].

[0155] Reference Figure 11 and Figure 12In the scan output circuit unit 310 according to the third embodiment of this disclosure, the first scan signal output buffer 311 can output the first scan clock signal SCCLK[n] from the (n)th scan clock signal SCCLK[n] to the (n+2)th scan clock signal SCCLK[n+2] as the (n)th scan signal SC[n]. In the first scan signal output buffer 311, the first boost capacitor Cb1 can be disposed between the gate electrode of the first scan pull-up transistor Tu1 and the scan output node. The first scan signal output buffer 311 can be represented as a boost scan signal output buffer for boosting the voltage of the first node Q through the first boost capacitor Cb1.

[0156] The first scan pull-up transistor Tu1 of the first scan signal output buffer 311 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the first applied (n) scan clock signal SCCLK[n]. The first scan pull-up transistor Tu1 may be represented as a boost scan pull-up transistor that switches according to the voltage of the first node Q to output the (n) scan clock signal SCCLK[n] through the scan output node as the (n) scan signal SC[n] with a first voltage level.

[0157] The first scan pull-down transistor Td1 of the first scan signal output buffer 311 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The first scan pull-down transistor Td1 may be represented by a boost scan pull-down transistor, which switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n)th scan signal SC[n] having a second voltage level.

[0158] The first boost capacitor Cb1 of the first scan signal output buffer 311 can be implemented between the first node Q and the scan output node. The first boost capacitor Cb1 can generate bootstrapping in the first node Q according to the phase transition (or the rise of the pulse period) of the first applied (n) scan clock signal SCCLK[n]. Since the first boost capacitor Cb1 is not affected by the carry clock signal CRCLK[n], the boost voltage of the first node Q can be increased. The first boost capacitor Cb1 can be set to have sufficient capacitance to increase the bootstrapping time of the first node Q in order to improve the rise time of the (n) scan signal SC[n] first output from the scan output circuit unit 310.

[0159] The second scan signal output buffer 312 can output the (n+1)th scan clock signal SCCLK[n+1] as the (n+1)th scan signal SC[n+1] through the scan output node. The second scan signal output buffer 312 can be represented as a normal scan signal output buffer without a capacitor.

[0160] The second scan pull-up transistor Tu2 of the second scan signal output buffer 312 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+1)th scan clock signal SCCLK[n+1]. The second scan pull-up transistor Tu2 may be represented as a normal scan pull-up transistor, which switches according to the voltage of the first node Q boosted by the first boost capacitor Cb1 to output the (n+1)th scan clock signal SCCLK[n+1] through the scan output node as the (n+1)th scan signal SC[n+1] with a first voltage level. At this time, since the (n+1)th scan clock signal SCCLK[n+1] overlaps with the (n)th scan clock signal SCCLK[n] corresponding to the previous signal in a horizontal time period 1H, the rise time of the pulse period does not coincide with the fall time of the other scan clock signal. Therefore, the second scan signal output buffer 312 is not affected by the (n)th scan clock signal SCCLK[n], that is, it does not generate enhancement or offset, thereby maintaining the boost voltage through the first boost capacitor Cb1.

[0161] The second scan pull-down transistor Td2 of the second scan signal output buffer 312 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The second scan pull-down transistor Td2 may be represented as a normal scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+1)th scan signal SC[n+1] with a second voltage level.

[0162] The third scan signal output buffer 313 can output the (n+2)th scan clock signal SCCLK[n+2] as the (n+2)th scan signal SC[n+2] through the scan output node. At this time, the (n+2)th scan clock signal SCCLK[n+2] can rise to coincide with the falling time of the (n)th scan clock signal SCCLK[n] corresponding to the previous signal. In the case of the third scan signal output buffer 313, the second boost capacitor Cb2 can be disposed between the gate electrode of the third scan pull-up transistor Tu3 and the scan output node. The third scan signal output buffer 313 can be represented as a boost scan signal output buffer for boosting the voltage of the first node Q through the second boost capacitor Cb2.

[0163] The third scan pull-up transistor Tu3 of the third scan signal output buffer 313 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+2)th scan clock signal SCCLK[n+2]. The third scan pull-up transistor Tu3 may be represented as a boost scan pull-up transistor, which switches according to the voltage of the first node Q and outputs the (n+2)th scan clock signal SCCLK[n+2] through the scan output node as the (n+2)th scan signal SC[n+2] with a first voltage level.

[0164] The third scan pull-down transistor Td3 of the third scan signal output buffer 313 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The third scan pull-down transistor Td3 may be represented as a boost scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+2)th scan signal SC[n+2] with a second voltage level.

[0165] The second boost capacitor Cb2 of the third scan signal output buffer 313 can be implemented between the first node Q and the scan output node. The second boost capacitor Cb2 can generate a bootstrap in the first node Q according to the phase transition (or the rise of the pulse period) of the (n+2)th scan clock signal SCCLK[n+2]. According to the (n+2)th scan clock signal SCCLK[n+2], it can rise to coincide with the fall time of the (n)th scan clock signal SCCLK[n] corresponding to the previous signal and can be affected to offset it. The second boost capacitor Cb2 can boost the voltage of the first node Q to prevent the output deviation of the (n+2)th scan signal SC[n+2]. If the second boost capacitor Cb2 can generate only a bootstrap level sufficient to maintain the boost voltage of the first node Q, the second boost capacitor Cb2 can be set to have a capacitance smaller than that of the first boost capacitor Cb1.

[0166] Fourth Implementation Method

[0167] Figure 13 This is a circuit diagram of the output circuit unit according to the fourth embodiment of this disclosure. Figure 14 It shows that it is applied to Figure 13 The scan clock signal of the output circuit unit shown, from Figure 13 The diagram shows the scan signal output by the output circuit unit and the waveform of the first node. In the description of the third embodiment, descriptions of configurations identical to those in the first to third embodiments will be omitted.

[0168] Reference Figure 13 and Figure 14 According to the fourth embodiment of this disclosure, the output circuit unit 300 implements the scan output circuit unit 310 to output five scan signals. For example, when a pixel PX of the display panel 110 has three or four sub-pixels, the output circuit unit 300 according to the fourth embodiment of this disclosure can drive each sub-pixel by sequentially supplying five scan signals to the gate lines GL corresponding to the five sub-pixels. Alternatively, the output circuit unit 300 according to the fourth embodiment of this disclosure can drive the pixel PX corresponding to the five horizontal lines by sequentially supplying five scan signals to the gate lines GL corresponding to the five horizontal lines of the display panel 110. However, the output circuit unit 300 according to this disclosure is not limited to outputting only scan signals, and can be implemented to provide a sensing signal SENSE or a transmission signal EM.

[0169] According to the fourth embodiment of the present disclosure, the scan output circuit unit 310 may include first to fifth scan signal output buffers 311, 312, 313, 314 and 315 to output the (n)th scan clock signal SCCLK[n] to the (n+4)th scan clock signal SCCLK[n+4] of the plurality of scan clock signals SCCLKs as the (n)th scan signal SC[n] to the (n+4)th scan signal SC[n+4].

[0170] The first scan signal output buffer 311 may include a first scan pull-up transistor Tu1, a first scan pull-down transistor Td1, and a first boost capacitor Cb1. The second scan signal output buffer 312 may include a second scan pull-up transistor Tu2 and a second scan pull-down transistor Td2. The third scan signal output buffer 313 may include a third scan pull-up transistor Tu3, a third scan pull-down transistor Td3, and a second boost capacitor Cb2. The fourth scan signal output buffer 314 may include a fourth scan pull-up transistor Tu4 and a fourth scan pull-down transistor Td4. The fifth scan signal output buffer 315 may include a fifth scan pull-up transistor Tu5, a fifth scan pull-down transistor Td5, and a third boost capacitor Cb3.

[0171] The first to fifth scan pull-up transistors Tu1, Tu2, Tu3, Tu4, and Tu5, and the first to fifth scan pull-down transistors Td1, Td2, Td3, Td4, and Td5 can be connected in series between the terminal where the scan clock signals SCCLK[n] to SCCLK[n+4] are applied and the terminal where the second gate low voltage VGL2 is applied. A first boost capacitor Cb1 can be connected between the gate electrode of the first scan pull-up transistor Tu1 and the output node between the first scan pull-up transistor Tu1 and the first scan pull-down transistor Td1. A second boost capacitor Cb2 can be connected between the gate electrode of the third scan pull-up transistor Tu3 and the output node between the third scan pull-up transistor Tu3 and the third scan pull-down transistor Td3. A third boost capacitor Cb3 can be connected between the gate electrode of the fifth scan pull-up transistor Tu5 and the output node between the fifth scan pull-up transistor Tu5 and the fifth scan pull-down transistor Td5. The capacitance of the first boost capacitor Cb1 can be greater than the capacitance of each of the second boost capacitor Cb2 and the third boost capacitor Cb3. Furthermore, the second boost capacitor Cb2 and the third boost capacitor Cb3 may have the same capacitance or different capacitances. Additionally, the capacitance of the first boost capacitor Cb1 may be equal to or less than the total capacitance of the second boost capacitor Cb2 and the third boost capacitor Cb3. For example, the first boost capacitor Cb1 may have a larger capacitance than each of the second boost capacitor Cb2 and the third boost capacitor Cb3. Furthermore, the first boost capacitor Cb1 may have a capacitance greater than that of the second boost capacitor Cb2, and may have a capacitance equal to or less than twice the capacitance of the second boost capacitor Cb2. Furthermore, the first boost capacitor Cb1 may have a capacitance greater than that of the third boost capacitor Cb3, and may have a capacitance equal to or less than twice the capacitance of the third boost capacitor Cb3. Additionally, twice the capacitance of the first boost capacitor Cb1 may have a capacitance equal to or less than twice the sum of the capacitances of the second boost capacitor Cb2 and the third boost capacitor Cb3.

[0172] Reference Figure 14According to the fourth embodiment of this disclosure, the (n)th scan clock signal SCCLK[n] to the (n+4)th scan clock signal SCCLK[n+4] applied to the scan output circuit unit 310 may include a pulse period that oscillates between a first voltage level (or a gated high voltage) and a second voltage level (or a gated low voltage), and is maintained at the first voltage level within a predetermined or selected horizontal period. For example, the pulse period of each of the (n)th scan clock signal SCCLK[n] to the (n+4)th scan clock signal SCCLK[n+4] may be maintained for two horizontal periods 2H, and the rise time and fall time of each pulse period may be different from each other. Each of the (n)th scan clock signal SCCLK[n] to the (n+4)th scan clock signal SCCLK[n+4] may be sequentially shifted by a predetermined or selected period and have the first voltage level within two horizontal periods 2H, and adjacent scan clock signals may overlap with each other within a period shorter than two horizontal periods 2H. For example, adjacent scan clock signals may overlap with each other during a horizontal period 1H. Furthermore, the rise time of any one of the scan clock signals SCCLK[n] to SCCLK[n+4] can coincide with the fall time of another scan clock signal. For example, the fall time of the (n)th scan clock signal SCCLK[n] can coincide with the rise time of the (n+2)th scan clock signal SCCLK[n+2], the fall time of the (n+1)th scan clock signal SCCLK[n+1] can coincide with the rise time of the (n+3)th scan clock signal SCCLK[n+3], and the fall time of the (n+2)th scan clock signal SCCLK[n+2] can coincide with the rise time of the (n+4)th scan clock signal SCCLK[n+4].

[0173] Reference Figure 13 and Figure 14 In the scan output circuit unit 310 according to the fourth embodiment of this disclosure, the first scan signal output buffer 311 can output the first scan clock signal SCCLK[n] among the (n)th scan clock signals SCCLK[n] to (n+4)th scan clock signals SCCLK[n+4] as the (n)th scan signal SC[n]. In the first scan signal output buffer 311, the first boost capacitor Cb1 can be disposed between the gate electrode of the first scan pull-up transistor Tu1 and the scan output node. The first scan signal output buffer 311 can be represented as a boost scan signal output buffer for boosting the voltage of the first node Q through the first boost capacitor Cb1.

[0174] The first scan pull-up transistor Tu1 of the first scan signal output buffer 311 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the first applied (n) scan clock signal SCCLK[n]. The first scan pull-up transistor Tu1 may be represented as a boost scan pull-up transistor that switches according to the voltage of the first node Q to output the (n) scan clock signal SCCLK[n] through the scan output node as the (n) scan signal SC[n] with a first voltage level.

[0175] The first scan pull-down transistor Td1 of the first scan signal output buffer 311 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The first scan pull-down transistor Td1 may be represented by a boost scan pull-down transistor, which switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n)th scan signal SC[n] having a second voltage level.

[0176] The first boost capacitor Cb1 of the first scan signal output buffer 311 can be implemented between the first node Q and the scan output node. The first boost capacitor Cb1 can generate bootstrapping in the first node Q according to the phase transition (or the rise of the pulse period) of the first applied (n) scan clock signal SCCLK[n]. Since the first boost capacitor Cb1 is not affected by the carry clock signal CRCLK[n], the boost voltage of the first node Q can be increased. The first boost capacitor Cb1 can be set to have sufficient capacitance to increase the bootstrapping time of the first node Q in order to improve the rise time of the (n) scan signal SC[n] first output from the scan output circuit unit 310.

[0177] The second scan signal output buffer 312 can output the (n+1)th scan clock signal SCCLK[n+1] as the (n+1)th scan signal SC[n+1] through the scan output node. The second scan signal output buffer 312 can be represented as a normal scan signal output buffer without a capacitor.

[0178] The second scan pull-up transistor Tu2 of the second scan signal output buffer 312 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+1)th scan clock signal SCCLK[n+1]. The second scan pull-up transistor Tu2 may be represented as a normal scan pull-up transistor, which switches according to the voltage of the first node Q boosted by the first boost capacitor Cb1 to output the (n+1)th scan clock signal SCCLK[n+1] through the scan output node as the (n+1)th scan signal SC[n+1] with a first voltage level. At this time, since the (n+1)th scan clock signal SCCLK[n+1] overlaps with the (n)th scan clock signal SCCLK[n] corresponding to the previous signal in a horizontal time period 1H, the rise time of the pulse period does not coincide with the fall time of the other scan clock signal. Therefore, the second scan signal output buffer 312 is not affected by the (n)th scan clock signal SCCLK[n], that is, it does not generate enhancement or offset, thereby maintaining the boost voltage through the first boost capacitor Cb1.

[0179] The second scan pull-down transistor Td2 of the second scan signal output buffer 312 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The second scan pull-down transistor Td2 may be represented as a normal scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+1)th scan signal SC[n+1] with a second voltage level.

[0180] The third scan signal output buffer 313 can output the (n+2)th scan clock signal SCCLK[n+2] as the (n+2)th scan signal SC[n+2] through the scan output node. At this time, the (n+2)th scan clock signal SCCLK[n+2] can rise to coincide with the falling time of the (n)th scan clock signal SCCLK[n] corresponding to the previous signal. In the case of the third scan signal output buffer 313, the second boost capacitor Cb2 can be disposed between the gate electrode of the third scan pull-up transistor Tu3 and the scan output node. The third scan signal output buffer 313 can be represented as a boost scan signal output buffer for boosting the voltage of the first node Q through the second boost capacitor Cb2.

[0181] The third scan pull-up transistor Tu3 of the third scan signal output buffer 313 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+2)th scan clock signal SCCLK[n+2]. The third scan pull-up transistor Tu3 may be represented as a boost scan pull-up transistor, which switches according to the voltage of the first node Q to output the (n+2)th scan clock signal SCCLK[n+2] through the scan output node as the (n+2)th scan signal SC[n+2] with a first voltage level.

[0182] The third scan pull-down transistor Td3 of the third scan signal output buffer 313 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The third scan pull-down transistor Td3 may be represented as a boost scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+2)th scan signal SC[n+2] with a second voltage level.

[0183] The second boost capacitor Cb2 of the third scan signal output buffer 313 can be implemented between the first node Q and the scan output node. The second boost capacitor Cb2 can generate a bootstrap in the first node Q according to the phase transition (or the rise of the pulse period) of the (n+2)th scan clock signal SCCLK[n+2]. According to the (n+2)th scan clock signal SCCLK[n+2], it can rise to coincide with the fall time of the (n)th scan clock signal SCCLK[n] corresponding to the previous signal, and can be affected to offset it. The second boost capacitor Cb2 can boost the voltage of the first node Q to prevent the output deviation of the (n+2)th scan signal SC[n+2]. If the second boost capacitor Cb2 can generate only a bootstrap level sufficient to maintain the boost voltage of the first node Q, the second boost capacitor Cb2 can be set to have a capacitance smaller than that of the first boost capacitor Cb1.

[0184] The fourth scan signal output buffer 343 can output the (n+3)th scan clock signal SCCLK[n+3] as the (n+3)th scan signal SC[n+3] through the scan output node. The fourth scan signal output buffer 314 can be represented as a normal scan signal output buffer without a capacitor.

[0185] The fourth scan pull-up transistor Tu4 of the fourth scan signal output buffer 314 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+3)th scan clock signal SCCLK[n+3]. The fourth scan pull-up transistor Tu4 can be represented as a normal scan pull-up transistor, which switches according to the voltage of the first node Q boosted by the second boost capacitor Cb2 and outputs the (n+3)th scan clock signal SCCLK[n+3] as the (n+3)th scan signal SC[n+3] with a first voltage level through the scan output node. At this time, the (n+3)th scan clock signal SCCLK[n+3] may rise to coincide with the falling time of the (n+1)th scan clock signal SCCLK[n+1] corresponding to the previous signal. However, since no capacitor is provided in the second scan signal output buffer 312, no boost or offset occurs, thereby maintaining the boost voltage through the second boost capacitor Cb2.

[0186] The fourth scan pull-down transistor Td4 of the fourth scan signal output buffer 312 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The fourth scan pull-down transistor Td4 may be represented as a normal scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+3)th scan signal SC[n+3] with a second voltage level.

[0187] The fifth scan signal output buffer 315 can output the (n+4)th scan clock signal SCCLK[n+4] as the (n+4)th scan signal SC[n+4] through the scan output node. At this time, the (n+4)th scan clock signal SCCLK[n+4] can rise to coincide with the falling time of the (n+2)th scan clock signal SCCLK[n+2] corresponding to the previous signal. In the case of the fifth scan signal output buffer 315, the third boost capacitor Cb3 can be disposed between the gate electrode of the fifth scan pull-up transistor Tu5 and the scan output node. The fifth scan signal output buffer 315 can be represented as a boost scan signal output buffer for boosting the voltage of the first node Q through the third boost capacitor Cb3.

[0188] The fifth scan pull-up transistor Tu5 of the fifth scan signal output buffer 315 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+4)th scan clock signal SCCLK[n+4]. The fifth scan pull-up transistor Tu5 may be represented as a boost scan pull-up transistor, which switches according to the voltage of the first node Q to output the (n+4)th scan clock signal SCCLK[n+4] through the scan output node as the (n+4)th scan signal SC[n+4] with a first voltage level.

[0189] The fifth scan pull-down transistor Td5 of the fifth scan signal output buffer 315 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The fifth scan pull-down transistor Td5 may be represented as a boost scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+4)th scan signal SC[n+4] with a second voltage level.

[0190] The third boost capacitor Cb3 of the fifth scan signal output buffer 315 can be implemented between the first node Q and the scan output node. The third boost capacitor Cb3 can generate a bootstrap in the first node Q according to the phase transition (or the rise of the pulse period) of the (n+4)th scan clock signal SCCLK[n+4]. Since the (n+4)th scan clock signal SCCLK[n+4] can rise to coincide with and be affected by the fall time of the (n+2)th scan clock signal SCCLK[n+2] corresponding to the previous signal, the third boost capacitor Cb3 can boost the voltage of the first node Q to prevent output deviation of the (n+4)th scan signal SC[n+4]. If the third boost capacitor Cb3 can only generate a bootstrap level sufficient to maintain the boost voltage of the first node Q, then the third boost capacitor Cb3 can be set to have a capacitance smaller than that of the first boost capacitor Cb1. Furthermore, the second boost capacitor Cb2 and the third boost capacitor Cb3 can have the same capacitance or different capacitances. Furthermore, the capacitance of the first boost capacitor Cb can be equal to or less than the total capacitance corresponding to the sum of the capacitances of the second boost capacitor Cb2 and the third boost capacitor Cb3. For example, the first boost capacitor Cb1 can have a capacitance greater than that of each of the second boost capacitor Cb2 and the third boost capacitor Cb3. Additionally, the first boost capacitor Cb1 can have a capacitance greater than that of the second boost capacitor Cb2 and can have a capacitance equal to or less than twice the capacitance of the second boost capacitor Cb2. Furthermore, the first boost capacitor Cb1 can have a capacitance greater than that of the third boost capacitor Cb3 and can have a capacitance equal to or less than twice the capacitance of the third boost capacitor Cb3. Additionally, twice the capacitance of the first boost capacitor Cb1 can have a capacitance equal to or less than twice the sum of the capacitances of the second boost capacitor Cb2 and the third boost capacitor Cb3.

[0191] Fifth Implementation Method

[0192] Figure 15 This is a circuit diagram of the output circuit unit according to the fifth embodiment of this disclosure. Figure 16 It shows that it is applied to Figure 15 The scan clock signal of the output circuit unit shown, from Figure 15 The diagram shows the scan signal output by the output circuit unit and the waveform of the first node. In the description of the third embodiment, descriptions of configurations identical to those in the first and second embodiments will be omitted.

[0193] Reference Figure 15 and Figure 16According to the fifth embodiment of this disclosure, the output circuit unit 300 implements the scan output circuit unit 310 to output four scan signals. Furthermore, the pulse duration of each scan clock signal can be maintained for three horizontal time periods 3H. For example, when a pixel PX of the display panel 110 has four sub-pixels, the output circuit unit 300 according to the fifth embodiment of this disclosure can drive each sub-pixel by sequentially supplying four scan signals to the corresponding gating line GL from each sub-pixel. Alternatively, the output circuit unit 300 according to the fifth embodiment of this disclosure can drive the pixel PX corresponding to the four horizontal lines by sequentially supplying four scan signals to the gating lines GL corresponding to the four horizontal lines of the display panel 110. However, the output circuit unit 300 according to this disclosure is not limited to outputting only scan signals; it can be implemented to provide a sensing signal SENSE or a transmission signal EM.

[0194] According to the fifth embodiment of the present disclosure, the scan output circuit unit 310 may include first to fourth scan signal output buffers 311, 312, 313 and 314 to output the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] of the plurality of scan clock signals SCCLKs as the (n)th scan signal SC[n] to the (n+3)th scan signal SC[n+3].

[0195] The first scan signal output buffer 311 may include a first scan pull-up transistor Tu1, a first scan pull-down transistor Td1, and a first boost capacitor Cb1; the second scan signal output buffer 312 may include a second scan pull-up transistor Tu2 and a second scan pull-down transistor Td2; the third scan signal output buffer 313 may include a third scan pull-up transistor Tu3 and a third scan pull-down transistor Td3; and the fourth scan signal output buffer 314 may include a fourth scan pull-up transistor Tu4, a fourth scan pull-down transistor Td4, and a second boost capacitor Cb2.

[0196] The first to fourth scan pull-up transistors Tu1, Tu2, Tu3, and Tu4, and the first to fourth scan pull-down transistors Td1, Td2, Td3, and Td4 can be connected in series between the terminals to which scan clock signals SCCLK[n] to SCCLK[n+3] are applied and the terminals to which the second gate low voltage VGL2 is applied. A first boost capacitor Cb1 can be connected between the gate electrode of the first scan pull-up transistor Tu1 and the output node between the first scan pull-up transistor Tu1 and the first scan pull-down transistor Td1. A second boost capacitor Cb2 can be connected between the gate electrode of the fourth scan pull-up transistor Tu4 and the output node between the fourth scan pull-up transistor Tu4 and the fourth scan pull-down transistor Td4. The first boost capacitor Cb1 can have a capacitance greater than that of the second boost capacitor Cb2.

[0197] Reference Figure 16 According to the fifth embodiment of this disclosure, the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] applied to the scan output circuit unit 310 may include a pulse period that oscillates between a first voltage level (or a gated high voltage) and a second voltage level (or a gated low voltage), and is maintained at the first voltage level within a predetermined or selected horizontal period. For example, the pulse period of each of the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] may be maintained for three horizontal periods 3H, and the rise time and fall time of each pulse period may be different from each other. Each of the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] may be sequentially shifted by a predetermined or selected period and have the first voltage level within the three horizontal periods 3H, and adjacent scan clock signals may overlap with each other within a period shorter than the three horizontal periods 3H. For example, adjacent scan clock signals may overlap with each other during two horizontal periods 2H. Furthermore, the rise time of any one of the scan clock signals SCCLK[n] to SCCLK[n+3] can coincide with the fall time of the other scan clock signal. For example, the fall time of the (n)th scan clock signal SCCLK[n] can coincide with the rise time of the (n+3)th scan clock signal SCCLK[n+3].

[0198] Reference Figure 15 and Figure 16 In the scan output circuit unit 310 according to the fifth embodiment of this disclosure, the first scan signal output buffer 311 can output the first scan clock signal SCCLK[n] from the (n)th scan clock signal SCCLK[n] to the (n+3)th scan clock signal SCCLK[n+3] as the (n)th scan signal SC[n]. In the first scan signal output buffer 311, the first boost capacitor Cb1 can be disposed between the gate electrode of the first scan pull-up transistor Tu1 and the scan output node. The first scan signal output buffer 311 can be represented as a boost scan signal output buffer for boosting the voltage of the first node Q through the first boost capacitor Cb1.

[0199] The first scan pull-up transistor Tu1 of the first scan signal output buffer 311 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal of the first applied (n) scan clock signal SCCLK[n]. The first scan pull-up transistor Tu1 may be represented as a boost scan pull-up transistor that switches according to the voltage of the first node Q to output the (n) scan clock signal SCCLK[n] through the scan output node as the (n) scan signal SC[n] with a first voltage level.

[0200] The first scan pull-down transistor Td1 of the first scan signal output buffer 311 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The first scan pull-down transistor Td1 may be represented by a boost scan pull-down transistor, which switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n)th scan signal SC[n] having a second voltage level.

[0201] The first boost capacitor Cb1 of the first scan signal output buffer 311 can be implemented between the first node Q and the scan output node. The first boost capacitor Cb1 can generate bootstrapping in the first node Q according to the phase transition (or the rise of the pulse period) of the first applied (n) scan clock signal SCCLK[n]. Since the first boost capacitor Cb1 is not affected by the carry clock signal CRCLK[n], the boost voltage of the first node Q can be increased. The first boost capacitor Cb1 can be set to have sufficient capacitance to increase the bootstrapping time of the first node Q in order to improve the rise time of the (n) scan signal SC[n] first output from the scan output circuit unit 310.

[0202] The second scan signal output buffer 312 can output the (n+1)th scan clock signal SCCLK[n+1] as the (n+1)th scan signal SC[n+1] through the scan output node. The second scan signal output buffer 312 can be represented as a normal scan signal output buffer without a capacitor.

[0203] The second scan pull-up transistor Tu2 of the second scan signal output buffer 312 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+1)th scan clock signal SCCLK[n+1]. The second scan pull-up transistor Tu2 may be represented as a normal scan pull-up transistor, which switches according to the voltage of the first node Q boosted by the first boost capacitor Cb1 to output the (n+1)th scan clock signal SCCLK[n+1] through the scan output node as the (n+1)th scan signal SC[n+1] with a first voltage level. At this time, since the (n+1)th scan clock signal SCCLK[n+1] overlaps with the (n)th scan clock signal SCCLK[n] corresponding to the previous signal in a horizontal time period 1H, the rise time of the pulse period does not coincide with the fall time of the other scan clock signal. Therefore, the second scan signal output buffer 312 is not affected by the (n)th scan clock signal SCCLK[n], that is, it does not generate enhancement or offset, thereby maintaining the boost voltage through the first boost capacitor Cb1.

[0204] The second scan pull-down transistor Td2 of the second scan signal output buffer 312 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The second scan pull-down transistor Td2 may be represented as a normal scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+1)th scan signal SC[n+1] with a second voltage level.

[0205] The third scan signal output buffer 313 can output the (n+2)th scan clock signal SCCLK[n+2] as the (n+2)th scan signal SC[n+2] through the scan output node. The third scan signal output buffer 313 can be represented as a normal scan signal output buffer without a capacitor.

[0206] The third scan pull-up transistor Tu3 of the third scan signal output buffer 313 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+2)th scan clock signal SCCLK[n+2]. The third scan pull-up transistor Tu3 may be represented as a normal scan pull-up transistor, which switches according to the voltage of the first node Q boosted by the first boost capacitor Cb1 to output the (n+2)th scan clock signal SCCLK[n+2] through the scan output node as the (n+2)th scan signal SC[n+2] with a first voltage level. At this time, since the (n+2)th scan clock signal SCCLK[n+2] overlaps with the (n)th scan clock signal SCCLK[n] corresponding to the previous signal in one horizontal time period 1H, and overlaps with the (n+1)th scan clock signal SCCLK[n+1] in two horizontal time periods 2H, the rise time of the pulse period does not coincide with the fall time of the other scan clock signal. Therefore, the third scan signal output buffer 313 is not affected by the (n)th scan clock signal SCCLK[n] and the (n+1)th scan clock signal SCCLK[n+1], that is, it does not generate enhancement or offset, thereby maintaining the boost voltage through the first boost capacitor Cb1.

[0207] The third scan pull-down transistor Td3 of the third scan signal output buffer 313 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The third scan pull-down transistor Td3 may be represented as a normal scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+2)th scan signal SC[n+2] with a second voltage level.

[0208] The fourth scan signal output buffer 314 can output the (n+3)th scan clock signal SCCLK[n+3] as the (n+3)th scan signal SC[n+3] through the scan output node. At this time, the (n+3)th scan clock signal SCCLK[n+3] can rise to coincide with the falling time of the (n)th scan clock signal SCCLK[n] corresponding to the previous signal. In the case of the fourth scan signal output buffer 314, the second boost capacitor Cb2 can be disposed between the gate electrode of the fourth scan pull-up transistor Tu4 and the scan output node. The fourth scan signal output buffer 314 can be represented as a boost scan signal output buffer for boosting the voltage of the first node Q through the second boost capacitor Cb2.

[0209] The fourth scan pull-up transistor Tu4 of the fourth scan signal output buffer 314 may include a gate electrode connected to the first node Q, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to the terminal of the (n+3)th scan clock signal SCCLK[n+3]. The fourth scan pull-up transistor Tu4 may be represented as a boost scan pull-up transistor, which switches according to the voltage of the first node Q to output the (n+3)th scan clock signal SCCLK[n+3] through the scan output node as the (n+3)th scan signal SC[n+3] with a first voltage level.

[0210] The fourth scan signal output buffer 314 may include a gate electrode connected to the second node QB, a first source / drain electrode connected to the scan output node, and a second source / drain electrode connected to a terminal to which a second gating low voltage VGL2 is applied. The fourth scan pull-down transistor Td4 may be represented as a boost scan pull-down transistor that switches according to the voltage of the second node QB and outputs the second gating low voltage VGL2 through the scan output node as the (n+3)th scan signal SC[n+3] with a second voltage level.

[0211] The second boost capacitor Cb2 of the fourth scan signal output buffer 314 can be implemented between the first node Q and the scan output node. The second boost capacitor Cb2 can generate a bootstrap in the first node Q according to the phase transition (or the rise of the pulse period) of the (n+3)th scan clock signal SCCLK[n+3]. According to the (n+3)th scan clock signal SCCLK[n+3], it can rise to coincide with the fall time of the (n)th scan clock signal SCCLK[n] corresponding to the previous signal and can be affected to offset it. The second boost capacitor Cb2 can boost the voltage of the first node Q to prevent the output deviation of the (n+3)th scan signal SC[n+3]. If the second boost capacitor Cb2 can generate only a bootstrap level sufficient to maintain the boost voltage of the first node Q, the second boost capacitor Cb2 can be set to have a capacitance smaller than that of the first boost capacitor Cb1.

[0212] Figure 17 and Figure 18 This is a diagram illustrating the scan signal and the output waveform of the first node according to an example and first embodiment of the present disclosure.

[0213] Reference Figure 17One example of this disclosure uses a method of arranging capacitors with the same capacitance for each scan signal output buffer of the scan output circuit unit 310. Therefore, in one example, it can be confirmed that the voltage of the first node Q is lower at the timing of the first output scan signal (n) SC[n]. Specifically, due to the low voltage of the first node Q in one example, it can be confirmed that the first output scan signal (n) SC[n] has an output deviation from the (n+1) scan signals SC[n+1] to (n+2) scan signals SC[n+2] output after the output of the (n) scan signal SC[n]. Furthermore, due to the output deviation of the (n) scan signal SC[n], the rise time of the (n) scan signal SC[n] is 3.09 μs, which is relatively longer than the rise time of the other scan signal.

[0214] Reference Figure 18 In the scan output circuit unit 310 according to the first embodiment of this disclosure, boost capacitors Cb1 and Cb2 are respectively provided only in the first scan signal output buffer 311 for first outputting the (n)th scan signal SC[n] and the third scan signal output buffer 313 affected by the (n)th scan clock signal SCCLK[n] applied to the first scan signal output buffer 311. The voltage of the first node Q is sufficiently boosted during the timing of the first output of the (n)th scan signal SC[n] by the scan output circuit unit 310, preventing output deviation between the (n)th scan signal SC[n] and the (n+1)th to (n+2)th scan signals SC[n+2]. Furthermore, it can be seen that the rise time of the (n)th scan signal SC[n] is 1.57 μs, which is significantly faster.

[0215] Therefore, according to the first embodiment of this disclosure, when multiple scan signals are output sequentially from a single stage circuit, output deviation between the multiple scan signals can be prevented.

[0216] The gating drive circuit and the display device including the gating drive circuit according to embodiments of the present disclosure can be described as follows.

[0217] The gating drive circuit according to embodiments of the present disclosure may include multiple stages of circuitry connected interdependently and configured to output "j" output signals ("j" being an integer of 2 or greater), wherein each of the multiple stages of circuitry includes a logic controller for controlling the voltage of each of the first node and the second node, and an output circuit unit that outputs each of the "j" clock signals as "j" output signals in response to the voltage of the first node, wherein the output circuit unit includes: "j" output buffers for outputting each of the "j" clock signals as "j" output signals through the output node in response to the voltage of the first node; and a capacitor disposed between the first node and some of the output nodes of the "j" output buffers.

[0218] In the gating drive circuit according to an embodiment of the present disclosure, a capacitor may be placed in the first output buffer, which is the first to output the output signal among "j" output buffers.

[0219] In the gating drive circuit according to an embodiment of the present disclosure, each of the "j" output buffers can be applied using any one of the "j" clock signals, and each of the "j" clock signals can include a pulse period that swings between a first voltage level and a second voltage level different from the first voltage level, and is maintained at the first voltage level for a predetermined or selected level period.

[0220] In the gating drive circuit according to an embodiment of the present disclosure, the rise time and fall time of each pulse period in the "j" clock signals may be different.

[0221] In the gating drive circuit according to an embodiment of the present disclosure, the rising time of any one of the "j" clock signals may coincide with the falling time of another scan clock signal.

[0222] In a gating drive circuit according to an embodiment of the present disclosure, the capacitor may include: a first capacitor disposed in a first output buffer that first outputs an output signal among "j" output buffers; and a second capacitor disposed in the (g) output buffer to which a (g) clock signal ("g" is an integer from 2 to "j") is applied, the (g) clock signal rising to coincide with the falling time of the clock signal applied to the first output buffer in the "j" output buffer.

[0223] In the gating drive circuit according to an embodiment of the present disclosure, the first capacitor may have a capacitance greater than that of the second capacitor.

[0224] In a gating drive circuit according to an embodiment of the present disclosure, the capacitor may include a third capacitor disposed in the (h)th output buffer to which a (h)th clock signal ("h" is an integer from "g+1" to "j") is applied, the (h)th clock signal rising to coincide with the falling time of the clock signal applied to the (g)th output buffer in the "j"th output buffer.

[0225] In the gating drive circuit according to an embodiment of the present disclosure, the second capacitor and the third capacitor may have the same capacitance or different capacitances from each other.

[0226] In the gating drive circuit according to an embodiment of the present disclosure, the first capacitor may have a capacitance equal to or less than the sum of the capacitances of the second and third capacitors.

[0227] In the gating drive circuit according to an embodiment of the present disclosure, the "j" clock signals may include first to (j) scan clock signals, each of the first to (j) scan clock signals being shifted sequentially, each scan clock signal having a first voltage level in a first time period, and adjacent scan clock signals overlapping each other in a second time period shorter than the first time period, and the output circuit unit may include first to (j) scan signal output buffers to which the first to (j) scan clock signals are respectively applied.

[0228] In the gating drive circuit according to an embodiment of the present disclosure, the first scan signal output buffer in the first to (j) scan signal output buffers can output the first scan clock signal among the "j" scan clock signals as the first scan signal, and the first capacitor is disposed between the first node and the output node of the first scan signal.

[0229] In the gating drive circuit according to an embodiment of the present disclosure, the falling time of the first scan clock signal may coincide with the rising time of any one of the "j" scan clock signals.

[0230] In the gating drive circuit according to an embodiment of the present disclosure, a second capacitor with a capacitance smaller than that of the first capacitor may be disposed in a first scan signal output buffer to which a first scan clock signal is applied, the first scan clock signal rising to coincide with the falling time of the first scan clock signal.

[0231] In the gating drive circuit according to an embodiment of the present disclosure, a third capacitor with a capacitance smaller than that of the first capacitor and which is the same as or different from that of the second capacitor may be disposed in the output buffer of the (h) scan signal to which the (h) scan clock signal is applied, the (h) scan clock signal rising to coincide with the falling time of the (g) scan clock signal.

[0232] In the gating drive circuit according to an embodiment of the present disclosure, the boost scan signal output buffer including a capacitor among the first to (j) scan signal output buffers may include: a boost scan pull-up transistor, which is applied with any one of the first scan clock signal, the (g) scan clock signal, and the (h) scan clock signal among the "j" scan clock signals and is switched by the voltage of the first node, and outputs the applied scan clock signal as a scan signal through the scan output node; a boost scan pull-down transistor, which is switched by the voltage of the second node and outputs a gating low potential voltage through the scan output node; and a capacitor between the scan output node and the first node.

[0233] In the gating drive circuit according to an embodiment of the present disclosure, the normal scan signal output buffer, excluding capacitors, among the first to (j) scan signal output buffers may include: a normal scan pull-up transistor, which is applied with another scan clock signal among the "j" scan clock signals, in addition to the first scan clock signal, the (g) scan clock signal, and the (h) scan clock signal, and is switched by the voltage of the first node, and outputs the applied scan clock signal through the scan output node; and a normal scan pull-down transistor, which is switched by the voltage of the second node, and outputs a gating low potential voltage through the scan output node.

[0234] In the gating drive circuit according to an embodiment of the present disclosure, the output circuit unit may further include a carry signal output buffer, which is applied with at least one carry clock signal, and outputs the at least one carry clock signal as a carry signal through the carry output node in response to the voltage of the first node.

[0235] In the gating drive circuit according to an embodiment of the present disclosure, the carry signal output buffer may include: a carry pull-up transistor that is switched by the voltage of a first node and outputs a carry clock signal as a carry signal through a carry output node; and a carry pull-down transistor that is switched by the voltage of a second node and outputs a gating low potential voltage through a carry output node.

[0236] A display device according to embodiments of the present disclosure may include: a display panel including a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, and a plurality of sub-pixels connected to adjacent data lines and gate lines; a gate driving circuit unit including a plurality of stage circuits for outputting a scan signal corresponding to a predetermined or selected order in units of each "j" gate line among the plurality of gate lines; a data driving circuit unit connected to each of the plurality of data lines; and a timing control unit for controlling the driving timing of each of the gate driving circuit unit and the data driving circuit unit, wherein the gate driving circuit unit includes a gate driving circuit.

[0237] The gating drive circuit and display device including the present disclosure can reduce the output deviation of multiple scan signals output from a single stage, and can reduce the size of the device, thereby achieving a narrow bezel and overcoming brightness deviation.

[0238] It will be apparent to those skilled in the art that this disclosure is not limited to the above embodiments and drawings, and various substitutions, modifications, and variations can be made in this disclosure without departing from the spirit or scope of this disclosure. Therefore, all changes or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this disclosure.

Claims

1. A gating drive circuit, the gating drive circuit comprising: Multiple circuit stages are connected interdependently, and each of the multiple circuit stages is configured to output j output signals, where j is an integer greater than or equal to 2. Each of the plurality of stage circuits includes: A logic controller for controlling a first voltage at a first node and a second voltage at a second node; and An output circuit is configured to output each of j clock signals as a corresponding output signal in response to the first voltage of the first node. The output circuit includes: j output buffers, each of the j output buffers being configured to output a corresponding clock signal from the j clock signals as one of the j output signals in response to the first voltage of the first node; and Multiple capacitors are connected between the first node and the corresponding output nodes of some of the j output buffers. The j clock signals include the first scan clock signal to the j-th scan clock signal. The first scan clock signal to the j-th scan clock signal are shifted sequentially. Each scan clock signal from the first scan clock signal to the j-th scan clock signal has a first voltage level during a first time period, and adjacent scan clock signals from the first scan clock signal to the j-th scan clock signal overlap each other during a second time period shorter than the first time period. The j output buffers include a first scan signal output buffer to a jth scan signal output buffer, which are respectively applied with the first scan clock signal to the jth scan clock signal.

2. The gating drive circuit according to claim 1, wherein, The first capacitor of the plurality of capacitors is disposed in the first output buffer of the j output buffers that first outputs the output signal of the j output signals.

3. The gating drive circuit according to claim 1, in, Each of the j output buffers is applied with one of the j clock signals, and Each of the j clock signals includes a pulse period that swings between a first clock voltage level and a second clock voltage level different from the first clock voltage level, and remains at the first clock voltage level within a selected horizontal period.

4. The gating drive circuit according to claim 3, wherein, In each of the j clock signals, the rise time and fall time of the pulse period are different.

5. The gating drive circuit according to claim 4, wherein, The rise time of at least one of the j clock signals coincides with the fall time of another of the j clock signals.

6. The gating drive circuit according to claim 5, in, The plurality of capacitors includes: A first capacitor is disposed in the first output buffer that first outputs one of the j output signals; and A second capacitor is disposed in the g-th output buffer among the j output buffers. The g-th output buffer is supplied with the g-th clock signal among the j clock signals. The g-th clock signal rises at the same time as the falling point of the first clock signal among the j clock signals. The first clock signal is supplied to the first output buffer among the j output buffers. Here, g is an integer greater than or equal to 2 and less than or equal to j.

7. The gating drive circuit according to claim 6, wherein, The capacitance of the first capacitor is greater than the capacitance of the second capacitor.

8. The gating drive circuit according to claim 6, in, The plurality of capacitors includes a third capacitor disposed in the h-th output buffer among the j output buffers, the h-th output buffer being applied with the h-th clock signal among the j clock signals, the h-th clock signal rising concurrently with the falling time point of the g-th clock signal applied to the g-th output buffer among the j output buffers, wherein h is an integer greater than or equal to g+1 and less than or equal to j.

9. The gating drive circuit according to claim 8, wherein, The second capacitor and the third capacitor have the same capacitance or different capacitances from each other.

10. The gating drive circuit according to claim 9, wherein, The capacitance of the first capacitor is equal to or less than the sum of the capacitances of the second capacitor and the third capacitor.

11. The gating drive circuit according to claim 1, wherein, The first scan signal output buffer outputs the first scan clock signal from the first scan signal output buffer to the j-th scan clock signal as the first scan signal, and the first capacitor is connected between the first node and the first output node of the first scan signal output buffer.

12. The gating drive circuit according to claim 11, wherein, The falling time point of the first scan clock signal coincides with the rising time point of any one of the j clock signals.

13. The gating drive circuit according to claim 12, wherein, A second capacitor with a capacitance smaller than that of the first capacitor is placed in the output buffer of the g-th scan signal to which the g-th scan clock signal is applied, the g-th scan clock signal rising at the same falling time point as the first scan clock signal.

14. The gating drive circuit according to claim 13, wherein, A third capacitor, with a capacitance smaller than that of the first capacitor and the same as or different from that of the second capacitor, is disposed in the h-th scan signal output buffer to which the h-th scan clock signal is applied, the h-th scan clock signal rising at the same time as the falling point of the g-th scan clock signal.

15. The gating drive circuit according to claim 14, in, The boost scan signal output buffer, which includes one of the plurality of capacitors, from the first scan signal output buffer to the j-th scan signal output buffer, comprises: A boost scan pull-up transistor is applied with any one of the first scan clock signal, the g-th scan clock signal, and the h-th scan clock signal among the j clock signals. The boost scan pull-up transistor is switched on and off by the first voltage of the first node, and outputs any one of the applied scan clock signals as scan signals through the scan output node. A boost-scanning pull-down transistor, which is switched by the second voltage at the second node and outputs a low-level gate voltage through the scan output node; and One of the plurality of capacitors is the capacitor connected between the scan output node and the first node.

16. The gating drive circuit according to claim 15, in, The normal scan signal output buffers, excluding any one of the plurality of capacitors, among the first scan signal output buffers to the j-th scan signal output buffers include: A normal scan pull-up transistor is applied with the first scan clock signal to another scan clock signal in the j-th scan clock signal, excluding the first scan clock signal, the g-th scan clock signal, and the h-th scan clock signal. This normal scan pull-up transistor is switched on and off by the first voltage at the first node, and outputs the other scan clock signal through the second scan output node; and A normal scan pull-down transistor is switched by the second voltage of the second node and outputs a low-potential voltage through the second scan output node.

17. The gating drive circuit according to claim 1, wherein, The output circuit further includes a carry signal output buffer, which is applied with at least one carry clock signal and outputs the at least one carry clock signal as a carry signal through the carry output node in response to the first voltage of the first node.

18. The gating drive circuit according to claim 17, in, The carry signal output buffer includes: A carry pull-up transistor, which is switched on and off by the first voltage of the first node, and outputs the carry clock signal as the carry signal through the carry output node; and A carry-down transistor is switched by the second voltage of the second node and outputs a low-potential voltage through the carry-out output node.

19. A display device comprising: The display panel includes multiple data lines, multiple gate lines intersecting the multiple data lines, and multiple sub-pixels, each of the multiple sub-pixels being connected to a corresponding adjacent pair of data lines and gate lines in the multiple data lines and the multiple gate lines; Selection drive circuit; A data driving circuit, which is connected to each of the plurality of data lines; as well as A timing controller is provided to control the driving timing of each of the gating drive circuit and the data drive circuit. The gating drive circuit is the gating drive circuit according to any one of claims 1 to 18.

20. A display device comprising: The display panel includes multiple sub-pixels; A data driver electrically connected to the plurality of sub-pixels; as well as A gating driver, electrically connected to the plurality of sub-pixels, the gating driver comprising: This stage circuit outputs multiple scan signals during operation. The stage circuit includes: A first output buffer, which is connected to a first node and a first output node, receives a first clock signal having a first pulse period during operation; A second output buffer, connected to the first node and the second output node, receives a second clock signal having a second pulse period during operation, the second pulse period lagging behind and overlapping with the first pulse period; and A third output buffer, connected to the first node and the third output node, receives a third clock signal with a third pulse period during operation. This third pulse period lags behind and overlaps with the second pulse period. Wherein, the first capacitance between the first node and the first output node is greater than the third capacitance between the first node and the third output node, and the second capacitance between the first node and the second output node is less than the third capacitance.

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