Active matrix substrate and display panel

Abstract

An object of the present invention is to more reliably suppress display defects while reducing the number of source wirings. The active matrix substrate includes a plurality of gate wirings, a plurality of source wirings, a plurality of column wirings, a plurality of switching elements, a plurality of pixel electrodes, and a plurality of connection electrodes that cross one column wiring of the plurality of column wirings via an insulating layer. The first pixel electrode and the third pixel electrode are disposed on one side of one column wiring, the second pixel electrode and the fourth pixel electrode are disposed on the other side of one column wiring, the third switching element is disposed on one side of one column wiring, the fourth switching element is disposed on the other side of one column wiring, the first pixel electrode is connected to the first switching element via the first connection electrode, the second pixel electrode is connected to the second switching element via the second connection electrode, the third pixel electrode is connected to the third switching element, and the fourth pixel electrode is connected to the fourth switching element.

Description

Technical Field

[0001] The present technology relates to an active matrix substrate and a display panel. Background Art

[0002] Conventionally, a liquid crystal panel has a plurality of pixels arranged in a matrix, and each pixel has a pixel electrode. The voltage applied to the pixel electrode is supplied through a switching element (specifically, a TFT), a source wiring (data wiring) in the column direction connected to the switching element, and a gate wiring in the row direction. In recent years, a technique has been proposed in which by providing two source wirings for every three pixel columns and three gate wirings for every two pixel rows, the number of source wirings can be reduced. An example thereof is disclosed in Patent Document 1. According to the technique described in Patent Document 1, the flexibility of the circuit design of the liquid crystal panel can be improved and the manufacturing cost can be reduced.

[0003] In addition, an improved example of the technique described in Patent Document 1 is disclosed in Patent Document 2. According to the technique described in Patent Document 2, it is possible to suppress flicker (so-called blinking) of the screen that occurs when the voltage polarity applied to the source wiring is inverted for each display frame. In Patent Document 2, pixels of the same color (for example, red pixels) are arranged in the column direction, and pixels of different colors (red pixels, green pixels, blue pixels) are sequentially repeated in the row direction. In addition, in a pixel column of the same color (for example, a pixel column of red pixels), one pixel column to which a positive voltage is applied to the pixel electrode and other pixel columns to which a negative voltage is applied are mixed alternately in the row direction. As a result, the voltage polarity of pixels of the same color (for example, red pixels) is less likely to be biased toward one polarity, and flicker can be suppressed.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2007-188089

[0007] Patent Document 2: International Publication No. 2018 / 221477 Summary of the Invention

[0008] Technical Problem to be Solved by the Present Invention

[0009] However, in reality, even when the improved technique described in Patent Document 2 is applied, it is difficult to suppress flicker in cases other than monochromatic display. In addition, in the case of intermediate gray display where the voltage applied to the pixel electrode is an intermediate value, vertical stripe display defects are likely to occur.

[0010] The present technology has been completed based on the above actual situation, and its purpose is to more reliably suppress display defects while reducing the number of source wirings arranged.

[0011] Solution for solving problems

[0012] (1) The active matrix substrate involved in the present technology includes: a plurality of gate wirings extending in a first direction; a plurality of source wirings extending in a second direction intersecting with the first direction; a plurality of column wirings extending in the second direction; a plurality of switching elements respectively connected to any one of the plurality of gate wirings and any one of the plurality of source wirings; a plurality of pixel electrodes arranged in a matrix in the first direction and the second direction and respectively connected to the plurality of switching elements; and a plurality of connection electrodes intersecting with one column wiring of the plurality of column wirings via an insulating layer. The plurality of gate wirings include a first gate wiring, a second gate wiring, and a third gate wiring. The plurality of source wirings include a first source wiring and a second source wiring. The plurality of pixel electrodes include a first pixel electrode and a second pixel electrode arranged in a first row parallel to the first direction, and a third pixel electrode and a fourth pixel electrode arranged in a second row adjacent to the first row. The plurality of switching elements include a first switching element, a second switching element, a third switching element, and a fourth switching element. The plurality of connection electrodes include a first connection electrode and a second connection electrode. The first pixel electrode and the third pixel electrode are arranged on one side of the one column wiring, the second pixel electrode and the fourth pixel electrode are arranged on the other side of the one column wiring. The third switching element is arranged on the one side of the one column wiring, the fourth switching element is arranged on the other side of the one column wiring. The first pixel electrode is connected to the first switching element via the first connection electrode, the second pixel electrode is connected to the second switching element via the second connection electrode, the third pixel electrode is connected to the third switching element, and the fourth pixel electrode is connected to the fourth switching element.

[0013] (2) Additionally, based on the above (1), the active matrix substrate may also be such that the first switching element and the second switching element are respectively connected to different gate wirings included in the plurality of gate wirings and different source wirings included in the plurality of source wirings, and the third switching element and the fourth switching element are respectively connected to different source wirings included in the plurality of source wirings.

[0014] (3) Additionally, based on the above (1) or (2), in the above active matrix substrate, the first switching element is connected to the first gate wiring and the second source wiring, the second switching element is connected to the second gate wiring and the first source wiring, the third switching element is connected to any one of a plurality of gate wirings other than the second gate wiring and the first source wiring, and the fourth switching element is connected to the third gate wiring and the second source wiring.

[0015] (4) Additionally, based on the above (1) or (2), in the above active matrix substrate, the first switching element is connected to the second gate wiring and the second source wiring, the second switching element is connected to the first gate wiring and the first source wiring, the third switching element is connected to any one of a plurality of gate wirings other than the first gate wiring and the first source wiring, and the fourth switching element is connected to the third gate wiring and the second source wiring.

[0016] (5) Additionally, based on any one of the above (1) to (4), in the above active matrix substrate, the third switching element is connected to the third gate wiring.

[0017] (6) Additionally, based on any one of the above (1) to (5), in the above active matrix substrate, when a first data voltage is applied to the first source wiring and a second data voltage having a polarity opposite to that of the first data voltage is applied to the second source wiring, the voltage polarities of the pixel electrodes are different from those of each adjacent pixel electrode in the first direction and the second direction, respectively.

[0018] (7) Additionally, based on any one of the above (1) to (6), in the above active matrix substrate, one column wiring overlaps at least one of the third pixel electrode and the fourth pixel electrode while crossing the first connection electrode and the second connection electrode.

[0019] (8) Additionally, based on the above (7), in the above active matrix substrate, the column wiring protrudes toward at least one of the third pixel electrode and the fourth pixel electrode, and overlaps at least one of the third pixel electrode and the fourth pixel electrode at the protruding portion.

[0020] (9) Additionally, based on any one of the above (1) to (8), in the above active matrix substrate, the first connection electrode and the second connection electrode are connection electrodes integrally provided with the first pixel electrode and the second pixel electrode, respectively.

[0021] (10) Additionally, the above-mentioned active matrix substrate may also be based on any one of the above (1) to (8), and the connection electrodes are connection electrodes separately provided from the first pixel electrode and the second pixel electrode.

[0022] (11) Additionally, the above-mentioned active matrix substrate may also be based on any one of the above (1) to (10), and includes at least one common electrode for supplying a specified reference potential, and the one column wiring is a common electrode wiring connected to the common electrode.

[0023] (12) Additionally, the above-mentioned active matrix substrate may also be based on the above (11), and at least a part of the connection electrode and the common electrode are arranged on the same layer.

[0024] (13) Additionally, the above-mentioned active matrix substrate may also be based on the above (11) or (12), and the common electrode has a plurality of first openings respectively overlapping with the plurality of source wirings and a second opening overlapping with the common electrode wiring.

[0025] (14) Additionally, the above-mentioned active matrix substrate may also be based on any one of the above (1) to (13), and the common electrode includes a connection part connected to the common electrode wiring, and the connection part overlaps with the region between two adjacent gate wirings among the plurality of gate wirings. In the region between the two adjacent gate wirings, none of the plurality of pixel electrodes is arranged.

[0026] (15) Additionally, the above-mentioned active matrix substrate may also be based on any one of the above (1) to (10), and includes at least one common electrode for supplying a specified reference potential. The common electrode also serves as a plurality of sensor electrodes that are divided into a matrix shape by slits and can detect the touched position, and the one column wiring also serves as a sensor electrode wiring connected to any one of the plurality of sensor electrodes.

[0027] (16) Additionally, the above-mentioned active matrix substrate may also be based on the above (15), and the plurality of column wirings include short-circuit wirings that connect multiple parts within the same sensor electrode and have a length shorter than twice the length of the sensor electrode in the second direction.

[0028] (17) Additionally, the above-mentioned active matrix substrate may also be based on the above (15) or (16), and the common electrode includes a connection part connected to the sensor electrode wiring. A part of the slit overlaps with the region between two adjacent gate wirings among the plurality of gate wirings. In the region between the two adjacent gate wirings, none of the plurality of pixel electrodes is arranged, and the slit does not overlap with the connection part.

[0029] (18) Further, on the basis of any one of the above (1) to (17), the active matrix substrate may also include at least one common electrode for supplying a specified reference potential. The one column wiring is a common electrode wiring connected to the common electrode. The active matrix substrate further includes: a source driver for supplying data voltages to the plurality of source wirings, a first lead wiring connecting the first source wiring and the source driver, a second lead wiring connecting the second source wiring and the source driver, and a third lead wiring connecting the common electrode wiring and the source driver. At least a part of the first lead wiring and the third lead wiring is formed of a first metal film, and the second lead wiring is formed of a second metal film disposed on a layer different from the first metal film.

[0030] (19) Further, on the basis of the above (18), the third lead wiring of the active matrix substrate may be multi-layered into the first metal film and the second metal film.

[0031] (20) The display panel according to the present technology may also include: an active matrix substrate according to any one of the above (1) to (19); and a color filter having a plurality of colored portions opposed to the plurality of pixel electrodes. The colored portions are composed of a first colored portion, a second colored portion, and a third colored portion having different colors. For the colored portions, the first colored portion, the second colored portion, and the third colored portion are repeatedly arranged in sequence along the first direction, and the same color is arranged along the second direction.

[0032] (21) Further, on the basis of the above (20), the display panel may be a liquid crystal display panel having a liquid crystal layer, and the liquid crystal layer contains liquid crystal molecules whose alignment state changes according to the voltage applied to the pixel electrodes.

[0033] Advantages of the Invention

[0034] According to the technology described in the specification of the present application, it is possible to more reliably suppress display defects while reducing the number of source wirings. Brief Description of the Drawings

[0035] Figure 1 is a top view of a liquid crystal panel according to an embodiment.

[0036] Figure 2 is a cross-sectional view of the liquid crystal panel.

[0037] Figure 3 is a top view schematically showing the configuration in the display area of the active matrix substrate.

[0038] Figure 4 is Figure 3 a partial enlarged view of

[0039] Figure 5 It is a top view showing the voltage polarity of the pixel electrode.

[0040] Figure 6 It is a top view showing Figure 4 the wiring layout pattern of

[0041] Figure 7 It is a top view showing the wiring layout pattern of the common electrode.

[0042] Figure 8 It is a top view showing the overlap of Figure 6 and Figure 7

[0043] Figure 9 It is a cross-sectional view of the liquid crystal panel cut along the I-I line position of Figure 6 and Figure 8

[0044] Figure 10 It is a cross-sectional view of the liquid crystal panel cut along the II-II line position of Figure 6 and Figure 8

[0045] Figure 11 It is a cross-sectional view of the liquid crystal panel cut along the III-III line position of Figure 6 and Figure 8

[0046] Figure 12 It is Figure 1 the cross-sectional view of the lead-out wiring of

[0047] Figure 13 It is a top view showing the voltage polarity of the pixel electrode in the active matrix substrate related to Comparative Example 1.

[0048] Figure 14 It is a top view schematically showing the constitution in the display area of the liquid crystal panel related to other embodiments.

[0049] Figure 15 It is a top view of the liquid crystal panel related to other embodiments.

[0050] Figure 16 It is a top view showing the slit for dividing the sensor electrode.

[0051] Figure 17 It is a top view of the wiring layout pattern of the liquid crystal panel related to other embodiments.

[0052] Figure 18 It is related to other embodiments in Figure 6 and Figure 8Cross-sectional view of a liquid crystal panel cut along the I-I line position.

[0053] Figure 19 It is for other embodiments and is Figure 6 and Figure 8 Cross-sectional view of a liquid crystal panel cut along the II-II line position.

[0054] Figure 20 It is for other embodiments and is Figure 6 and Figure 8 Cross-sectional view of a liquid crystal panel cut along the III-III line position.

[0055] Figure 21 Top view of the wiring layout pattern of the liquid crystal panel for other embodiments.

[0056] Figure 22 It is for other embodiments and is Figure 6 and Figure 8 Cross-sectional view of a liquid crystal panel cut along the I-I line position.

[0057] Figure 23 It is for other embodiments and is Figure 6 and Figure 8 Cross-sectional view of a liquid crystal panel cut along the II-II line position.

[0058] Figure 24 It is for other embodiments and is Figure 6 and Figure 8 Cross-sectional view of a liquid crystal panel cut along the III-III line position.

[0059] Figure 25 It is for other embodiments and is Figure 6 and Figure 8 Cross-sectional view of a liquid crystal panel cut along the I-I line position.

[0060] Figure 26 It is for other embodiments and is Figure 6 and Figure 8 Cross-sectional view of a liquid crystal panel cut along the I-I line position.

[0061] Figure 27 Cross-sectional view of the lead-out wiring for other embodiments. Specific Embodiments

[0062] <Embodiment 1>

[0063] Refer to Figures 1 to 12Describe Embodiment 1 of the present technology. In this embodiment, a liquid crystal display device 100 (an example of a display device) including a liquid crystal panel 10 (an example of a display panel) is illustrated. In addition, the X-axis, Y-axis, and Z-axis are shown in a part of each drawing, and the axial directions are depicted in a common direction in each drawing. Further, in each sectional view, the upper side of the drawing is set as the front side (display surface side) of the liquid crystal panel 10, and the lower side is set as the back side (rear surface side).

[0064] The liquid crystal display device 100 generally includes a liquid crystal panel 10 and a known backlight device (lighting device) that irradiates light onto the liquid crystal panel 10. As Figure 1 shown, the in-plane of the liquid crystal panel 10 is divided into a display area (active area) AA and a non-display area (non-active area) NAA. The display area AA is the area on the central side in the plane and displays an image. The non-display area NAA is a frame-shaped (border-shaped) area that surrounds the display area AA and does not display an image. In Figure 1 it, the single-dot chain line indicates the outer shape of the display area AA, and the area outside this single-dot chain line is the non-display area NAA. The shape of the liquid crystal panel 10 is Figure 1 a vertically long rectangle in the plan view, but it may be other shapes.

[0065] In the non-display area NAA, in order to drive the liquid crystal panel 10, a source driver 12 and two GDM circuit (Gate Driver Monolithic circuit) units 14 are provided. The source driver 12 is an LSI incorporating a source drive circuit. The GDM circuit unit 14 is a gate drive circuit monolithically formed on the substrate 30. The source driver 12 and the GDM circuit unit 14 are connected to a flexible substrate 13 whose one end is mounted in the non-display area NAA. The other end of the flexible substrate 13 is connected to an external control substrate that is a supply source of various signals.

[0066] As Figure 2As shown in the cross-sectional view, the liquid crystal panel 10 includes two substrates 20, 30, a liquid crystal layer 15, a sealing portion 16, and two polarizing plates 17, 18. The liquid crystal layer 15 is a medium layer containing liquid crystal molecules and is sandwiched between the substrates 20, 30. The sealing portion 16 adheres to the outer peripheral portions of the substrates 20, 30 and seals the liquid crystal layer 15. The polarizing plates 17, 18 are respectively pasted on the outer surface sides of the adhered substrates 20, 30. The front-side substrate among the substrates 20, 30 is a CF substrate (color filter substrate, counter substrate) 20, and the back-side substrate is an active matrix substrate (array substrate, TFT substrate) 30. Various thin films 20A, 30A patterned on the inner surface side of the glass substrate GS are respectively laminated on the CF substrate 20 and the active matrix substrate 30. After the various thin films 20A, 30A are laminated on the glass substrate GS by a known photolithography method, an alignment film for aligning the liquid crystal molecules contained in the liquid crystal layer 15 is coated and formed. The alignment film is made of an insulating material such as polyimide resin.

[0067] As Figure 3 shown in the plan view, in the display area AA of the active matrix substrate 30, a plurality of source wirings (data lines, signal lines) 41, a plurality of gate wirings (scan lines) 42, a plurality of common electrode wirings 43 (an example of column wirings), a plurality of TFTs (Thin Film Transistors) 46 (an example of switching elements), a plurality of pixel electrodes 47, a common electrode 48, and a plurality of connection electrodes 45 are formed. The gate wiring 42 extends along the X-axis direction (an example of the row direction (first direction)). As Figure 1 shown, the left and right end portions of the gate wiring 42 extend into the non-display area NAA and are connected to at least one of the two GDM circuit portions 14. A gate voltage (scan signal) is supplied from the GDM circuit portion 14 to the gate wiring 42.

[0068] As Figure 3 shown, the source wiring 41 extends along the Y-axis direction (an example of the column direction (second direction)) intersecting the gate wiring 42. As Figure 1As shown, the source wiring 41 is connected to the source driver 12 via the first lead wiring 61 or the second lead wiring 62 in the non-display area NAA. A data voltage (image signal) is supplied from the source driver 12 to the source wiring 41. The data voltage is supplied in a frame inversion driving method in which the polarity of each source wiring 41 is inverted every one display frame. Thereby, it is possible to suppress so-called sintering in which the direction of the liquid crystal molecules in the liquid crystal layer 15 becomes a state facing a specific direction. In addition, in each display frame, the data voltage is supplied such that the voltage polarities of two adjacent source wirings 41 are opposite polarities. Approximately half of the source wirings 41 are connected to the first lead wiring 61, and a data voltage of one polarity (for example, positive polarity +) is supplied via the first lead wiring 61. In addition, the remaining approximately half of the source wirings 41 are connected to the second lead wiring 62, and a data voltage of the other polarity (for example, negative polarity -) is supplied via the second lead wiring 62.

[0069] The common electrode wiring 43 extends in the Y-axis direction and is connected to the source driver 12 via the third lead wiring 64 in the non-display area NAA. A prescribed reference potential is supplied from the source driver 12 to the common electrode wiring 43. The common electrode wiring 43 is not connected to the TFT 46. Here, "not connected to the TFT 46" means that none of the drain electrode 46R, the source electrode 46S, and the gate electrode 46G of the TFT 46 are directly electrically connected.

[0070] The pixel electrode 47 has a substantially rectangular shape that is longitudinally long and is arranged in a matrix. The TFT 46 is connected to each pixel electrode 47 one by one. The drain electrode 46R, the source electrode 46S, and the gate electrode 46G of the TFT 46 are connected to the pixel electrode 47, the source wiring 41, and the gate wiring 42, respectively.

[0071] Although the common electrode 48 is omitted in Figure 3 and Figure 4 (partial enlarged view), it is formed over substantially the entire display area AA. The common electrode 48 is connected to the common electrode wiring 43, and a prescribed reference potential is supplied through the common electrode wiring 43.

[0072] When a gate voltage is applied to the TFT 46 through the gate wiring 42 and a data voltage is applied through the source wiring 41, the potential difference between the pixel electrode 47 and the common electrode 48 changes. By this potential difference, the electric field applied to the liquid crystal layer 15 is controlled, and the alignment state of the liquid crystal molecules is appropriately switched to drive the liquid crystal panel 10. A third opening 52 described later is provided in the common electrode 48, whereby a so-called fringe electric field (oblique electric field) is generated between the common electrode 48 and the pixel electrode 47. Therefore, the liquid crystal panel 10 operates in a so-called FFS (Fringe Field Switching) mode. In addition, an opening for generating a fringe electric field may also be formed in the pixel electrode 47. Further, the operation mode of the liquid crystal panel 10 may also be other than FFS (for example, an IPS (In-Plane-Switching) mode or the like).

[0073] In the display area AA of the CF substrate 20, as Figures 9 to 11 shown in the cross-sectional view, a color filter 22, a light-shielding portion (black matrix) 23, and an overcoat film 24 are formed. The color filter 22 is composed of coloring portions 22R, 22G, and 22B of three colors, red, green, and blue (R, G, B). The coloring portions 22R, 22G, and 22B transmit light in the wavelength ranges corresponding to the respective colors. The coloring portions 22R, 22G, and 22B are arranged in a matrix at positions opposed to the pixel electrodes 47 of the active matrix substrate 30. The coloring portions 22R, 22G, and 22B are repeatedly arranged in sequence along the row direction, and the same color is arranged along the column direction. The black matrix 23 is provided in a lattice pattern so as to overlap with the gate wiring 42, the source wiring 41, the common electrode wiring 43, and the TFT 46 of the active matrix substrate 30. Further, on the outer surface side of the CF substrate 20, a conductive layer 26 for preventing electrification is provided in a substantially entire area in a planar shape. Further, in Figure 2 the conductive layer 26 is omitted.

[0074] A unit composed of a coloring portion of one color and one pixel electrode 47 opposed thereto is one pixel PIX (picture element, sub-pixel). Figures 3 to 6 In the top view of the pixel electrode 47 shown in Figure 4 each of the characters R, G, and B indicates which of an R pixel, a G pixel, or a B pixel the pixel including the pixel electrode 47 is. The pixels PIX are arranged in a matrix. The liquid crystal panel 10 uses three pixels, an R pixel, a G pixel, and a B pixel, as one display unit, and performs color display in a prescribed color tone for each display unit. In the present embodiment,

[0075] As Figures 3 to 4As shown, three gate wirings 42 are provided for every two adjacent pixel rows. The gate wirings 42 include a first gate wiring 42A, a second gate wiring 42B, and a third gate wiring 42C. The first gate wiring 42A and the second gate wiring 42B are adjacent to each other with a pixel electrode 47 therebetween, and the second gate wiring 42B and the third gate wiring 42C are adjacent to each other with a pixel electrode 47 therebetween.

[0076] As Figures 3 to 4 shown, two source wirings 41 are provided for every three adjacent pixel columns. The source wirings 41 include a first source wiring 41A and a second source wiring 41B. The first source wiring 41A is disposed on one side of the common electrode wiring 43, and the second source wiring 41B is disposed on the other side of the common electrode wiring 43.

[0077] As Figure 4 shown, the TFT 46 includes a first TFT 46A, a second TFT 46B, a third TFT 46C, and a fourth TFT 46D. The first TFT 46A and the fourth TFT 46D are connected to the second source wiring 41B, and the second TFT 46B and the third TFT 46C are connected to the first source wiring 41A. In addition, the first TFT 46A is connected to the first gate wiring 42A, the second TFT 46B is connected to the second gate wiring 42B, and the fourth TFT 46D is connected to the third gate wiring 42C. The third TFT 46C may be connected to any one of the gate wirings 42 other than the second gate wiring 42B, and is connected to the third gate wiring 42C in the present embodiment.

[0078] As Figure 3 and Figure 4 shown, one common electrode wiring 43 is provided for every three adjacent pixel columns. By providing a plurality of common electrode wirings 43 disposed between the first source wiring 41A and the second source wiring 41B, the common electrode wiring 43 can reduce the resistance distribution in the common electrode 48 and stably maintain the reference potential. In addition, as described in Embodiment 2 to be described later, the common electrode wiring 43 can also be used as a sensor electrode wiring 143A for realizing a touch panel function.

[0079] As Figures 3 to 4 shown, the connection electrode 45 intersects the common electrode wiring 43 and connects the pixel electrode 47 and the TFT 46. The connection electrode 45 includes a first connection electrode 45A and a second connection electrode 45B.

[0080] As Figure 3As shown, the source wiring 41 to which the pixel electrode 47 is connected via the TFT 46 varies according to the position in the column direction. The pixel electrode 47 includes a first pixel electrode 47A and a second pixel electrode 47B arranged in the first row, and a third pixel electrode 47C and a fourth pixel electrode 47D arranged in the second row adjacent to the first row. The first pixel electrode 47A and the third pixel electrode 47C are arranged on one side of the common electrode wiring 43 in the row direction ( Figure 3 on the left side in [[]]), and the second pixel electrode 47B and the fourth pixel electrode 47D are arranged on the other side of the common electrode wiring 43 in the row direction ( Figure 3 on the right side in [[]]). The first pixel electrode 47A is connected to the first TFT 46A via the first connection electrode 45A, and the second pixel electrode 47B is connected to the second TFT 46B via the second connection electrode 45B. The third pixel electrode 47C is connected to the third TFT 46C, and the fourth pixel electrode 47D is connected to the fourth TFT 46D.

[0081] According to the above wiring structure, as shown in the plan view of Figure 5 , when data voltages of opposite polarities are applied to adjacent source wirings 41, the voltage polarities of the pixel electrodes 47 are alternately different in the column direction and the row direction, respectively. For example, if a negative data voltage is applied to the first source wiring 41A and a positive data voltage is applied to the second source wiring 41B, the voltage polarity of the first pixel electrode 47A connected to the second source wiring 41B via the first TFT 46A becomes positive ( Figure 5 shown by vertical stripes in [[]]), and the voltage polarity of the fourth pixel electrode 47D connected to the second source wiring 41B via the fourth TFT 46D becomes positive. In addition, the voltage polarity of the second pixel electrode 47B connected to the first source wiring 41A via the second TFT 46B becomes negative ( Figure 5 shown by horizontal stripes in [[]]), and the voltage polarity of the third pixel electrode 47C connected to the first source wiring 41A via the third TFT 46C becomes negative.

[0082] Therefore, the liquid crystal panel 10 is configured such that when data voltages of opposite polarities are applied to adjacent source wirings 41, so-called dot inversion driving can be performed in which the voltage polarity of the pixel electrode 47 is inverted (reversed) for each pixel (dot). According to the dot inversion driving, it is difficult for the voltage polarity of the pixel electrode 47 to be biased toward one polarity with respect to either the column direction or the row direction, and display defects such as flicker or stripes can be suppressed. In addition, when performing dot inversion driving, power consumption can be reduced by inverting the polarity of each source wiring 41 for each display frame.

[0083] Next, the planar layout pattern of the above wiring structure will be described. As shown in the plan view of Figure 6 and Figure 9As shown in the cross-sectional view, the second pixel electrode 47B is connected to the drain electrode 46R of the second TFT 46B via the second connection electrode 45B. The second connection electrode 45B crosses the common electrode wiring 43 via the first interlayer insulating film 54 (an example of an insulating layer). The second connection electrode 45B is connected to a part of the second pixel electrode 47B, crosses the common electrode wiring 43 from the second pixel electrode 47B, and protrudes to a position overlapping the drain electrode 46R of the second TFT 46B. The second connection electrode 45B is integrally formed with the second pixel electrode 47B on the same layer (the first transparent electrode film described later) as the second pixel electrode 47B. The second connection electrode 45B overlaps with the black matrix 23 described later in the same layer (the first transparent electrode film) as the second pixel electrode 47B and extends to a part of a pixel different from the pixel including the second pixel electrode 47B. The second connection electrode 45B is interlayer-connected to the drain electrode 46R through a contact hole. By providing the second connection electrode 45B, the second pixel electrode 47B and the drain electrode 46R can be connected across the common electrode wiring 43. Since the first interlayer insulating film 54 is interposed between the second connection electrode 45B and the common electrode wiring 43, no leakage current is generated between the two. A parasitic capacitance (auxiliary capacitance) C45 is generated between the second connection electrode 45B and the common electrode wiring 43. The structure of the first connection electrode 45A is the same as that of the second connection electrode 45B described above, so repeated description is omitted.

[0084] As Figures 7 to 8 shown in the plan view, a plurality of first openings 50, a plurality of second openings 51, and a plurality of third openings 52 are formed in the common electrode 48. The first openings 50 overlap with the source electrode wiring 41. The parasitic capacitance generated between the common electrode 48 and the source electrode wiring 41 is reduced through the first openings 50. The second openings 51 overlap with the common electrode wiring 43. The parasitic capacitance generated between the common electrode 48 and the common electrode wiring 43 is reduced through the second openings 51. The third openings 52 overlap with the pixel electrode 47, and three third openings 52 are formed for each pixel electrode 47. The width (length in the row direction) of each third opening 52 is about several μm.

[0085] The common electrode 48 includes a connection portion 49 (interlayer connection portion) connected to the common electrode wiring 43. As Figure 8 shown in the plan view and Figure 11As shown in the cross-sectional view, the connection portion 49 overlaps with the region between the two gate wirings 42 where the pixel electrode 47 is not disposed. The region between the two gate wirings 42 overlaps with the black matrix 23 described later, which is not helpful for display. In addition, the region between the two gate wirings 42 is located at a position separated from the pixel electrode 47 to a certain extent. Moreover, from the viewpoint of yield, the two gate wirings 42 are arranged at a prescribed interval, so the region between the two gate wirings 42 has a space where the connection portion 49 can be formed. Therefore, by providing the connection portion 49 in the region between the two gate wirings 42, the aperture ratio is not reduced and the alignment disorder of the liquid crystal layer 15 is not generated, and the space can be effectively utilized.

[0086] Next, refer to Figures 9 to 11 the cross-sectional view to describe the layer structure of the active matrix substrate 30. The gate electrode 46G and the gate wiring 42 of the TFT 46 are formed of a gate metal film (an example of the first metal film) laminated on the glass substrate GS. The source electrode 46S, the drain electrode 46R, the source wiring 41, and the common electrode wiring 43 of the TFT 46 are formed of a source metal film (an example of the second metal film). The source metal layer is laminated on the upper side of the gate metal film with the gate insulating film 56 interposed therebetween. The TFT 46 is a bottom-gate type TFT, and in their formation region, a semiconductor film 57 that becomes the channel region of the TFT 46 is laminated between the gate insulating film 56 and the source metal film. A first interlayer insulating film (passivation film) 54 is laminated on the source metal film. The pixel electrode 47 is formed of a first transparent electrode film laminated on the first interlayer insulating film 54. The common electrode 48 is formed of a second transparent electrode film laminated on the upper side of the first transparent electrode film with a second interlayer insulating film (passivation film) 58 interposed therebetween. In addition, the alignment film is omitted in these cross-sectional views.

[0087] In addition, as Figure 12 shown in the cross-sectional view, the first lead wiring 61 and the third lead wiring 64 in the non-display region NAA are formed of a gate metal film. The second lead wiring 62 is formed of a source metal film. The first lead wiring 61 and the second lead wiring 62 are layered at positions where they do not overlap with the third lead wiring 64. Thereby, narrow bezelization can be achieved, and the load on the third lead wiring 64 connected to the common electrode wiring 43 can be reduced. In particular, as described in the second embodiment, when the common electrode wiring 43 is also used as the sensor electrode wiring 143A, it is easy to suppress signal sluggishness of the common electrode wiring 43 (sensor electrode wiring 143A) and the third lead wiring 64. As a result, the display quality and the detection accuracy can be improved.

[0088] The gate metal film and the source metal film include a single layer film of a metal such as copper (Cu), an alloy, or a stacked film thereof. The materials of the gate metal film and the source metal film may be the same or different. The gate insulating film 56, the interlayer insulating films 54 and 58 are composed of a single layer of transparent inorganic insulating materials such as silicon oxide (SiOx), silicon oxynitride (SiON), silicon nitride (SiNx), or a stacked layer thereof. The semiconductor film 57 is composed of an oxide semiconductor, amorphous silicon, or the like. The first and second transparent electrode films are composed of transparent electrode materials such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0089] Next, the functions and effects of the active matrix substrate 30 described above will be described. The active matrix substrate 30 includes a first source wiring 41A, a second source wiring 41B, a first gate wiring 42A, a second gate wiring 42B, and a third gate wiring 42C for three adjacent pixel columns. In this way, compared with a more general structure in which each of three pixel columns has three source wirings 41 and gate wirings 42, the number of source wirings 41 can be reduced. By reducing the number of source wirings 41, the source driver 12 can be replaced with a low-cost product, or the number of source drivers 12 can be not increased. In addition, narrow bezelization can be achieved. Furthermore, by providing a common electrode wiring 43 in the space of the reduced source wiring 41, compared with the case where one common electrode wiring 43 is provided between each of the three source wirings 41, the space for providing the common electrode wiring 43 is reduced, and accordingly, the aperture ratio is increased. Furthermore, as described in Embodiment 3, by providing a sensor electrode wiring 143A in the space of the reduced source wiring 41, the touch panel function can be realized with space saving.

[0090] On the other hand, if the number of source wirings 41 is reduced, display defects such as flicker and streaks are likely to occur in the wiring design. For example, in the case of the active matrix substrate 930 according to Comparative Example 1 shown in the top view of Figure 13 , the source wirings 41 to which the pixel electrodes 947 of the R pixel column and the B pixel column are connected via the TFTs 46 are not different according to the column direction positions, but are connected to the same source wiring 41. For example, the pixel electrode 947 of the B pixel column is connected to the first source wiring 41A via the TFT 46, but is not connected to the second source wiring 41B. The pixel electrode 947 is different from the pixel electrode 47 of the present embodiment and is not connected to the TFT 46 connected to the second source wiring 41B via the connection electrode 45. Therefore, the voltage polarity of the pixel electrode 947 of the B pixel column is likely to be biased to one side, and display defects such as flicker and streaks are likely to occur. Suppose, even in Figure 13When the polarities of the data voltages applied to the first source wiring 41A and the second source wiring 41B are set to the same polarity, the pixel electrodes 947 of the R pixel columns and the B pixel columns are also connected to the same source wiring 41. Therefore, they will be biased to one side, and display defects such as flicker and streaks are likely to occur.

[0091] In contrast, in the active matrix substrate 30 according to the present embodiment, by adopting the above-described configuration, the voltage polarity of the pixel electrode 47 does not bias to one side along the column direction for any of the R pixel columns, G pixel columns, and B pixel columns. As a result, dot inversion driving can be achieved, and the voltage polarity of the pixel electrode 47 can be prevented from biasing to one polarity with respect to either the column direction or the row direction. Therefore, display defects such as flicker and streaks can be more reliably suppressed.

[0092] <Embodiment 2>

[0093] Refer to Figure 14 the top view of to describe the wiring configuration according to Embodiment 2. The configuration of the TFT 146 in the present embodiment is different from that in Embodiment 1. In Embodiment 2, repeated descriptions of the same structures, operations, and effects as in Embodiment 1 are omitted.

[0094] In the present embodiment, the first TFT 146A is connected to the second gate wiring 42B, the second TFT 146B is connected to the first gate wiring 42A, and the fourth TFT 146D is connected to the third gate wiring 42C. The third TFT 146C may be connected to any one of the gate wirings 42 other than the first gate wiring 42A, and is connected to the third gate wiring 42C in the present embodiment.

[0095] <Embodiment 3>

[0096] Refer to Figures 15 to 17 the top view of to describe the liquid crystal panel according to Embodiment 3. The liquid crystal panel 110 is different from that in Embodiment 1 in that it has a touch panel function for detecting the position of a user input. In Embodiment 3, repeated descriptions of the same structures, operations, and effects as in Embodiment 1 are omitted.

[0097] As Figure 15As shown, the active matrix substrate 130 includes a plurality of sensor electrodes 148, a plurality of sensor electrode wirings 143A (an example of column wirings), and a plurality of short-circuit wirings 143B (an example of column wirings). The sensor electrode 148 is an electrode for detecting an input position and is arranged in a matrix in the display area AA. When a user brings a finger (a position input body as a conductor) close to the surface (display surface) of the liquid crystal panel 110, a static capacitance is formed between the finger and the sensor electrode 148. Thus, the static capacitance detected by the sensor electrode 148 located near the finger changes, which is different from the sensor electrode 148 far from the finger. Therefore, based on this, the input position is detected. The liquid crystal panel 110 uses the self-capacitance method as the detection method in this way, but it can also be the mutual-capacitance method.

[0098] The sensor electrode 148 divides the common electrode 48 related to Embodiment 1 into a rectangular shape through the slit 55. The sensor electrode 148 also has the function of the common electrode 48. The slit 55 is arranged in a grid pattern such that the planar size of the sensor electrode 148 is much larger than that of the pixel electrode 47 (for example, from 2 mm square to 5 mm square). As Figures 16 to 17 shown, at least a part of the slit 55 along the row direction overlaps with the area between two gate wirings 42 that are adjacent without sandwiching the pixel electrode 47. In addition, the slit 55 along the column direction overlaps with at least one of the source wiring 41, the sensor electrode wiring 143A, and the short-circuit wiring 143B. Since these areas overlap with the black matrix 23, the slit 55 can be provided without reducing the aperture ratio. However, depending on whether there is an overlap with the slit 55, there are differences in the capacitance generated in the wiring, which may affect the display quality. Therefore, the slit 55 along the column direction is preferably provided at a position where the overlap with the wiring has the least possible impact on the display quality. For example, in the case of providing dummy wirings described in the following other embodiment (1), it is preferably provided at a position where it overlaps with the dummy wirings.

[0099] As Figure 15 shown, the sensor electrode wiring 143A extends in the column direction and is connected to the sensor electrode 148. The sensor electrode wiring 143A also has the function of the common electrode wiring 43. The sensor electrode wiring 143A is connected to at least one of each sensor electrode 148. The connection portion 149 between the sensor electrode 148 and the sensor electrode wiring 143A is formed in the area between two gate wirings 42 where the pixel electrode 47 is not arranged and where the slit 55 is not formed. In other words, the connection portion 149 does not overlap with the slit 55.

[0100] The sensor electrode wirings 143A are each provided for every three adjacent pixel columns, similarly to the common electrode wiring 43 in Embodiment 1. The sensor electrode wirings 143A extend in the column direction from the third lead wiring 164 to the sensor electrodes 148. The sensor electrode wirings 143A are connected to the position detection circuit in the source driver 112 via the third lead wiring 164. The sensor electrode wirings 143A supply a reference potential signal related to the display function and a position detection signal related to the touch panel function to the sensor electrodes 148 at different timings. The reference potential signal is transmitted to all the sensor electrode wirings 143A at the same timing, so that all the sensor electrodes 148 become the reference potential and function as the common electrode 48.

[0101] As Figure 15 shown, the short - circuit wiring 143B extends in the column direction and is provided on the extension line of the sensor electrode wiring 143A. The short - circuit wiring 143B connects (shorts) multiple parts within the same sensor electrode 148. The length of the short - circuit wiring 143B in the column direction is shorter than twice the length of one side of the sensor electrode 148. More specifically, it is substantially the same as the length of one side of the sensor electrode 148 or shorter than the length of one side of the sensor electrode 148. Signals from the source driver 12 are not input to the short - circuit wiring 143B. Due to the short - circuit wiring 143B, it is easy to instantaneously equalize the potential within the same sensor electrode 148, and the detection accuracy can be improved.

[0102] According to the present embodiment, by providing the sensor electrode wiring 143A and the short - circuit wiring 143B in the space of the reduced source wiring 41, it is possible to save space and achieve the touch panel function with high precision.

[0103] <Embodiment 4>

[0104] Refer to Figures 18 to 20 the cross - sectional view to describe the liquid crystal panel 210 according to Embodiment 4. The layer structure of the active matrix substrate 230 of the liquid crystal panel 210 and the structure of the connection electrode 145 are different from those in Embodiment 1. In Embodiment 4, repeated descriptions of the same structures, operations, and effects as in Embodiments 1 to 3 are omitted.

[0105] In the active matrix substrate 230, as Figure 18 shown, the pixel electrode 247 formed of the first transparent electrode film is laminated on the same layer as the source electrode 46S, drain electrode 46R, source wiring 41, and common electrode wiring 43 formed of the source metal film. The first transparent electrode film is formed on the gate insulating film 56. In addition, a first interlayer insulating film 54 is formed on the first transparent electrode film and the source metal film. The common electrode 248 is formed of the first transparent electrode film laminated on the first interlayer insulating film 54.

[0106] The connection electrode 145 is different from that in Embodiment 1 and is formed separately from the pixel electrode 247. The connection electrode 145 is composed of the same second transparent electrode film as the common electrode 248 and is disposed on the same layer as the common electrode 248. One end of the connection electrode 145 is connected between layers with the pixel electrode 247, and the other end is connected between layers with the drain electrode 46R. The connection electrode 145 connects the two across the common electrode wiring 43 and intersects the common electrode wiring 43 via the first interlayer insulating film 54. In addition, since the connection electrode 145 is formed by patterning the second transparent electrode film forming the common electrode 248, the common electrode 248 has an opening for not being electrically connected to the connection electrode 145.

[0107] According to this embodiment, different from Embodiment 1, there is no need to provide a second interlayer insulating film, so the number of manufacturing processes can be reduced. In addition, it is easy to increase the intensity of the lateral component (the component along the in-plane direction) of the edge electric field. Moreover, since the connection electrode 145 is formed separately from the pixel electrode 247 using the second transparent electrode film, it is easy to make the pattern shape of the portion of the first transparent electrode film including the pixel electrode 247 common.

[0108] <Embodiment 5>

[0109] Refer to Figure 21 The top view of shows the wiring layout pattern of the active matrix substrate 330 according to Embodiment 5. The active matrix substrate 330 is different from Embodiment 1 in that an overlapping portion 59 is provided on the common electrode wiring 243. In Embodiment 5, repeated descriptions of the same structures, functions, and effects as those in Embodiments 1 to 4 are omitted.

[0110] Between the connection electrode 45 and the common electrode wiring 243, an auxiliary capacitor C45 is generated as described in Embodiment 1. Therefore, in the pixel PIX including the first pixel electrode 47A or the second pixel electrode 47B connected to the connection electrode 45 and the pixel PIX including the third pixel electrode 47C or the fourth pixel electrode 47D not connected to the connection electrode 45, the capacitance generated on the pixel electrode 47 is only different from the auxiliary capacitor C45, and display defects such as flicker and burning may occur.

[0111] Therefore, the active matrix substrate 330 according to this embodiment includes a structure for capacitively matching by superimposing a capacitance of a magnitude equivalent to the auxiliary capacitor C45 on the third pixel electrode 47C and the fourth pixel electrode 47D. Specifically, as Figure 21As shown, an overlapping portion 59 with the third pixel electrode 47C and the fourth pixel electrode 47D is provided on a part of the common electrode wiring 243 that intersects with the connection electrode 45. The overlapping portion 59 is a part of the common electrode wiring 243 that protrudes left and right to a position overlapping with the third pixel electrode 47C and the fourth pixel electrode 47D. The overlapping portion 59 overlaps with the third pixel electrode 47C and the fourth pixel electrode 47D, but no interlayer connection is made. Thereby, the capacitance generated in the pixel electrode 47 can be made uniform between pixels PIX, and display defects such as flicker and sintering can be suppressed.

[0112] The shape and size of the overlapping portion 59 are adjusted so that the capacitance generated by the pixel electrode 47 is made uniform. Alternatively, the shape and size of the connection electrode 45 can also be adjusted.

[0113] If a capacitance of the same size as the auxiliary capacitance C45 can be generated, the overlapping portion 59 can also be provided Figure 21 at a position other than the position shown (the diagonal position of the third TFT 46C and the fourth TFT 46D). Within the region overlapping with the black matrix 23, any position where a space for providing the overlapping portion 59 can be ensured is acceptable. For example, it can also be provided at a position adjacent to the interlayer connection portion 60 of the third pixel electrode 47C, the fourth pixel electrode 47D, and the drain electrode 46R connected to them.

[0114] In addition, the overlapping portion 59 does not need to overlap both the third pixel electrode 47C and the fourth pixel electrode 47D, and it is sufficient if it overlaps at least one of them. Moreover, the overlapping portion 59 can also be provided outside the common electrode wiring 243. For example, an overlapping portion with the common electrode wiring 243 can also be formed on the third pixel electrode 47C and the fourth pixel electrode 47D. Additionally, for example, in the case of forming the layer structure of Embodiment 4, the overlapping portion can also be formed using a second transparent electrode film of the same layer as the connection electrode 45.

[0115] <Other Embodiments>

[0116] The present technology is not limited to the embodiments described above and illustrated in the accompanying drawings. For example, the following embodiments are also included in the technical scope of the present invention.

[0117] (1) The column wirings that cross the connection electrodes 45 and 145 are not limited to the common electrode wirings 43, 243, the sensor electrode wiring 143A, and the short - circuit wiring 143B. For example, it may also be a wiring that is not connected to the common electrodes 48, 248, and the sensor electrode 148 but is applied with a signal similar to the reference potential signal and the position detection signal. Additionally, it may also be a dummy wiring that is in an electrically floating state without inputting a signal. Further, in the case of a dummy wiring, since the auxiliary capacitance C45 is not generated, the structure for capacitance adjustment (specifically, the overlapping portion 59) described in Embodiment 5 is not required.

[0118] (2) The structure of the display area of the active - matrix substrates 30, 130, 230, 330 is not limited to Figure 3 , Figure 14 the exemplified cases.

[0119] (3) The layer structure in the active - matrix substrates 30, 130, 230, 330 can also be other structures. For example, as shown in the cross - sectional view of Figures 22 to 24 , it may also be a structure in which the pixel electrode 47 and the connection electrode 45 are formed in a pattern by laminating a first transparent electrode film on a glass substrate GS, and a gate electrode 46G made of a gate metal film and a gate insulating film (an example of an insulating layer) are sequentially laminated on the first transparent electrode film. In this way, since there is no need to provide a second interlayer insulating film, the number of manufacturing processes can be reduced.

[0120] (4) Additionally, for example, as shown in the cross - sectional view of Figure 25 , it may also be a structure in which an interlayer connection portion 60 between the pixel electrode 47 and the drain electrode 46R is formed by a second transparent electrode film of the same layer as the common electrode 48. An opening portion for not conducting with this interlayer connection portion 60 is formed on the common electrode 48. In this way, since the process of forming a contact hole on the first interlayer insulating film 54 and the process of forming a contact hole on the second interlayer insulating film can be combined, the number of photomasks used can be reduced, and the number of manufacturing processes can be reduced.

[0121] (5) Additionally, for example, by combining the above - mentioned Figure 22 and Figure 25 shown layer structures, a layer structure shown in the cross - sectional view of Figure 26 can be formed.

[0122] (6) Additionally, for example, as shown in the cross - sectional view of Figure 27 , the third lead - out wirings 64, 164 in the non - display area NAA can also be multi - layerized into two layers of a gate metal film and a source metal film. By multi - layerization, the third lead - out wirings 64, 164 are made to have a lower resistance, and signal passivation is more easily suppressed. As a result, the display quality and detection accuracy can be further improved.

[0123] Explanation of Reference Numerals

[0124] 10, 110, 210, 310... liquid crystal panel (display panel), 15... liquid crystal layer, 22... color filter, 22R, 22G, 22B... colored portions, 30, 130, 230... active matrix substrate, 41... source wiring, 41A... first source wiring, 41B... second source wiring, 42... gate wiring, 42A... first gate wiring, 42B... second gate wiring, 42C... third gate wiring, 43, 243... common electrode wiring (column wiring), 45, 145... connection electrode, 45A... first connection electrode, 45B... second connection electrode, 46, 146... TFT (switching element), 46A, 146A... first TFT (switching element), 46B, 146B... second TFT (switching element), 46C, 146C... third TFT (switching element), 46D, 146D... fourth TFT (switching element), 47, 247... pixel electrode, 47A... first pixel electrode, 47B... second pixel electrode, 47C... third pixel electrode, 47D... fourth pixel electrode, 48, 248... common electrode, 49, 149... connection portion, 50... first opening, 51... second opening, 54... first interlayer insulating film (insulating layer), 55... slit, 56... gate insulating film (insulating layer), 61... first lead wiring, 62... second lead wiring, 64, 164... third lead wiring, 143A... sensor electrode wiring (column wiring), 143B... short-circuit wiring (column wiring), 148... sensor electrode.

Claims

1. An active matrix substrate, characterized in that, Comprising: A plurality of gate wirings extending in a first direction; A plurality of source wirings extending in a second direction intersecting the first direction; A plurality of column wirings extending in the second direction; A plurality of switching elements respectively connected to any one of the plurality of gate wirings and any one of the plurality of source wirings; A plurality of pixel electrodes arranged in a matrix in the first direction and the second direction and respectively connected to the plurality of switching elements; And A plurality of connection electrodes intersecting one column wiring of the plurality of column wirings via an insulating layer, The plurality of gate wirings include a first gate wiring, a second gate wiring, and a third gate wiring, The plurality of source wirings include a first source wiring and a second source wiring, The plurality of pixel electrodes include a first pixel electrode and a second pixel electrode arranged in a first row parallel to the first direction, and a third pixel electrode and a fourth pixel electrode arranged in a second row adjacent to the first row, The plurality of switching elements include a first switching element, a second switching element, a third switching element, and a fourth switching element, The plurality of connection electrodes include a first connection electrode and a second connection electrode, The first pixel electrode and the third pixel electrode are arranged on one side of the one column wiring, The second pixel electrode and the fourth pixel electrode are arranged on the other side of the one column wiring, The third switching element is arranged on the one side of the one column wiring, The fourth switching element is arranged on the other side of the one column wiring, The first pixel electrode is connected to the first switching element via the first connection electrode, The second pixel electrode is connected to the second switching element via the second connection electrode, The third pixel electrode is connected to the third switching element, The fourth pixel electrode is connected to the fourth switching element, The one column wiring intersects the first connection electrode and intersects the second connection electrode, The one column wiring has an overlapping portion overlapping at least one of the third pixel electrode and the fourth pixel electrode, The overlapping portion protrudes from the one column wiring toward at least one of the third pixel electrode and the fourth pixel electrode and overlaps at least one of the third pixel electrode and the fourth pixel electrode.

2. The active matrix substrate according to claim 1, wherein The first switching element and the second switching element are respectively connected to different gate wirings included in the plurality of gate wirings and different source wirings included in the plurality of source wirings, The third switching element and the fourth switching element are respectively connected to different source wirings included in the plurality of source wirings.

3. The active matrix substrate according to claim 1 or 2, wherein The first switching element is connected to the first gate wiring and the second source wiring, The second switching element is connected to the second gate wiring and the first source wiring, The third switching element is connected to any one of the plurality of gate wirings other than the second gate wiring and the first source wiring, The fourth switching element is connected to the third gate wiring and the second source wiring.

4. The active matrix substrate according to claim 1 or 2, wherein the first switching element is connected to the second gate wiring and the second source wiring, the second switching element is connected to the first gate wiring and the first source wiring, the third switching element is connected to any one of a plurality of gate wirings other than the first gate wiring and the first source wiring, the fourth switching element is connected to the third gate wiring and the second source wiring.

5. The active matrix substrate according to claim 1 or 2, wherein the third switching element is connected to the third gate wiring.

6. The active matrix substrate according to claim 1 or 2, wherein when a first data voltage is applied to the first source wiring and a second data voltage having a polarity opposite to that of the first data voltage is applied to the second source wiring, the voltage polarities of the pixel electrodes are different from each adjacent pixel electrode in the first direction and the second direction, respectively.

7. The active matrix substrate according to claim 1 or 2, wherein the first connection electrode and the second connection electrode are connection electrodes integrally provided with the first pixel electrode and the second pixel electrode, respectively.

8. The active matrix substrate according to claim 1 or 2, wherein the connection electrodes are connection electrodes separately provided from the first pixel electrode and the second pixel electrode, respectively.

9. The active matrix substrate according to claim 1 or 2, wherein at least one common electrode for supplying a predetermined reference potential is included, the one column wiring is a common electrode wiring connected to the common electrode.

10. The active matrix substrate according to claim 9, wherein at least a part of the connection electrode is arranged in the same layer as the common electrode.

11. The active matrix substrate according to claim 9, wherein the common electrode has a plurality of first openings overlapping the plurality of source wirings and a second opening overlapping the common electrode wiring.

12. The active matrix substrate according to claim 9, wherein the common electrode includes a connection portion connected to the common electrode wiring, the connection portion overlaps a region between two adjacent gate wirings among the plurality of gate wirings, and none of the plurality of pixel electrodes is arranged in the region between the two adjacent gate wirings.

13. The active matrix substrate according to claim 1 or 2, wherein at least one common electrode for supplying a predetermined reference potential is included, the common electrode also serves as a plurality of sensor electrodes that are divided into a matrix shape by slits and can detect a touched position, the one column wiring also serves as a sensor electrode wiring connected to any one of the plurality of sensor electrodes.

14. The active matrix substrate according to claim 13, wherein The plurality of column wirings include short-circuit wirings that connect a plurality of portions within the same sensor electrode and have a length shorter than twice the length of the sensor electrode in the second direction.

15. The active matrix substrate according to claim 13, wherein the common electrode includes a connection portion connected to the sensor electrode wiring, a part of the slit overlaps with an area between two adjacent gate wirings among the plurality of gate wirings, in the area between the two adjacent gate wirings, none of the plurality of pixel electrodes is arranged, the slit does not overlap with the connection portion.

16. The active matrix substrate according to claim 1 or 2, wherein it includes at least one common electrode that supplies a predetermined reference potential, one of the column wirings is a common electrode wiring connected to the common electrode, the active matrix substrate further includes: a source driver that supplies data voltages to the plurality of source wirings, a first lead wiring that connects the first source wiring and the source driver, a second lead wiring that connects the second source wiring and the source driver, and a third lead wiring that connects the common electrode wiring and the source driver, at least a part of the first lead wiring and the third lead wiring is formed of a first metal film, the second lead wiring is formed of a second metal film arranged on a layer different from the first metal film.

17. The active matrix substrate according to claim 16, wherein the third lead wiring is multilayered into the first metal film and the second metal film.

18. A display panel, characterized in that, It includes: the active matrix substrate according to any one of claims 1 to 17; and a color filter having a plurality of colored portions opposed to the plurality of pixel electrodes, the colored portions are composed of a first colored portion, a second colored portion, and a third colored portion having different colors, for the colored portions, the first colored portion, the second colored portion, and the third colored portion are sequentially and repeatedly arranged along the first direction, and the same color is arranged along the second direction.

19. The display panel according to claim 18, wherein it includes a liquid crystal layer that contains liquid crystal molecules whose alignment state changes according to a voltage applied to the pixel electrode.

Images