Metal interconnect structure parallel test structure and method of forming the same

Abstract

The application provides a metal interconnection structure parallel test structure and a forming method thereof. The test structure comprises a semiconductor substrate, a first dielectric layer on the surface of the semiconductor substrate, a first metal layer and a barrier layer on the sidewall and bottom of the first metal layer, the barrier layer on the bottom of the first metal layer being alloyed with a part of the semiconductor substrate, a second dielectric layer on the surface of the first dielectric layer, and a metal connecting structure in the second dielectric layer, wherein the metal connecting structure penetrates through the second dielectric layer and is electrically connected with the first metal layer. The first metal layer and the metal connecting structure are completely the same as the first metal layer and the metal connecting structure in the main body area of the semiconductor substrate. The application provides a metal interconnection structure parallel test structure and a forming method thereof, which can realize good electrical connection between the metal layer and the semiconductor substrate, thereby improving the accuracy of test results.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a metal interconnection structure parallel test structure and a forming method thereof. BACKGROUND

[0002] In a back end of line (BEOL) process of a semiconductor device, a metal interconnection structure forming process is usually needed. The metal interconnection structure forming process is usually performed on a semiconductor substrate, which usually has an active region on which semiconductor devices such as transistors and capacitors are formed.

[0003] In the metal interconnection structure, there are usually multiple metal connection structures and metal layers. When the metal connection structures and the metal layers are made, an interlayer dielectric layer is usually formed on the semiconductor substrate, and then a via and a trench are formed in the interlayer dielectric layer, and then a metal layer is formed in the trench and a metal connection structure is formed in the via.

[0004] In the metal interconnection structure, whether the metal connection structures and the metal layers can be well electrically connected is very important. Therefore, it is necessary to test the connection of the metal connection structures and the metal layers. However, some test structures currently still have problems, and it is necessary to provide a more effective and reliable technical solution. SUMMARY

[0005] The present application provides a metal interconnection structure parallel test structure and a forming method thereof, which can improve the accuracy of test results.

[0006] One aspect of the present application provides a forming method of a metal interconnection structure parallel test structure, comprising: providing a semiconductor substrate; forming a first dielectric layer on the surface of the semiconductor substrate; forming a first opening exposing the surface of the semiconductor substrate in the first dielectric layer; forming a barrier layer on the sidewall and the bottom of the first opening; alloying a part of the barrier layer and the semiconductor substrate which are in direct contact; filling the first opening with a first metal layer; forming a second dielectric layer on the surface of the first dielectric layer and a metal connection structure penetrating through the second dielectric layer and electrically connected to the first metal layer, wherein the first metal layer and the metal connection structure are formed synchronously with the first metal layer and the metal connection structure in a main body region of the semiconductor substrate.

[0007] In some embodiments of the present application, the method of alloying a part of the barrier layer and the semiconductor substrate which are in direct contact comprises an annealing process.

[0008] In some embodiments of the present application, the process parameters of the annealing process include: an annealing temperature of 600-1500K and an annealing time of 5-170 seconds.

[0009] In some embodiments of the present application, the method for forming a second dielectric layer on the surface of the first dielectric layer and a metal connection structure penetrating through the second dielectric layer and electrically connecting the first metal layer comprises: forming a second dielectric layer on the surface of the first dielectric layer; forming a second opening in the second dielectric layer to expose the surface of the first metal layer; and forming the metal connection structure in the second opening.

[0010] In some embodiments of the present application, the material of the barrier layer comprises any one of TiN, Ti, TaN, and Ta.

[0011] In some embodiments of the present application, the method for forming the test structure further comprises: forming a third dielectric layer on the surface of the second dielectric layer and a second metal layer penetrating through the third dielectric layer and electrically connecting the metal connection structure.

[0012] In some embodiments of the present application, the method for forming a third dielectric layer on the surface of the second dielectric layer and a second metal layer penetrating through the third dielectric layer and electrically connecting the metal connection structure comprises: forming a third dielectric layer on the surface of the second dielectric layer; forming a third opening in the third dielectric layer to expose the surface of the metal connection structure; and forming the second metal layer in the third opening.

[0013] Another aspect of the present application further provides a metal interconnection structure parallel test structure, comprising: a semiconductor substrate; a first dielectric layer on the surface of the semiconductor substrate; a first metal layer and a barrier layer on the sidewall and bottom of the first metal layer, the barrier layer on the bottom of the first metal layer being alloyed with a part of the semiconductor substrate; a second dielectric layer on the surface of the first dielectric layer, the second dielectric layer being provided with a metal connection structure penetrating through the second dielectric layer and electrically connecting the first metal layer, wherein the first metal layer and the metal connection structure are completely identical to the first metal layer and the metal connection structure in a main body region of the semiconductor substrate.

[0014] In some embodiments of the present application, the material of the barrier layer comprises any one of TiN, Ti, TaN, and Ta.

[0015] In some embodiments of the present application, the test structure further comprises: a third dielectric layer on the surface of the second dielectric layer, the third dielectric layer being provided with a second metal layer penetrating through the third dielectric layer and electrically connecting the metal connection structure.

[0016] The present application provides a metal interconnection structure parallel test structure and a forming method thereof, which can achieve good electrical connection between the metal layer and the semiconductor substrate, thereby improving the accuracy of test results. BRIEF DESCRIPTION OF DRAWINGS

[0017] The following drawings set forth particular applications of the present application. Identical reference numerals in the drawings represent similar structures throughout the several views. Those skilled in the art will appreciate that the embodiments described herein are non-limiting, exemplary embodiments, and the drawings are for purposes of illustration and description only and are not intended as a definition of the scope of the application. Other embodiments can be readily devised in light of the instant disclosure without departing from the spirit and scope of the application. It is to be understood that the drawings are not to scale.

[0018] wherein:

[0019] Figure 1 A schematic diagram of a parallel test structure for a metal interconnect structure;

[0020] Figures 2 to 13 A schematic diagram of a structure in each step of a method for forming a parallel test structure for a metal interconnect structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following description provides specific details for the purpose of providing a thorough understanding of the application. Those skilled in the art will recognize that the application can be practiced without one or more of the specific details set forth herein. Various modifications can be made to the embodiments described herein, and other embodiments can be obtained from this disclosure, without departing from the spirit and scope of the application. Therefore, the present application should not be construed as being limited to the embodiments set forth herein but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0022] The technical solutions of the present application will be described in detail below in conjunction with the embodiments and drawings.

[0023] Currently, e-beam is widely used to detect via open in full loop wafers. However, in the current development process, full loop BEOL wafers are not common. In addition, all the materials and waiting time related to the FEOL process are a huge waste. According to the principle, under e-beam inspection, the electrical ground via can extract enough VC electrons, and if the via is open, it will cause the VC to be dark. Therefore, another process (short loop wafer) is proposed and verified online to manufacture a ground BEOL structure to detect via open defects, which skips most of the FEOL process steps to reduce cycle time and save materials.

[0024] The use of short loop wafers to study and verify BEOL process integration is a trend in advanced technology development and a new type of outlet (New Type Out, NTO) to reduce material costs and cycle time.

[0025] Figure 1A schematic view of a metal interconnection structure parallel test structure. Figure 1 The metal interconnection structure parallel test structure shown is a short-circuit wafer structure, i.e. a structure that skips all FEOL and MEOL process steps and only retains BEOL process steps.

[0026] Reference is made to Figure 1 As shown, the metal interconnection structure parallel test structure includes a semiconductor substrate 100. Since it is a short-circuit wafer structure, it skips all FEOL and MEOL process steps, and therefore the semiconductor substrate 100 does not have active devices such as transistors, but is grounded.

[0027] Reference is made to Figure 1 As shown, the semiconductor substrate 100 is formed with a first dielectric layer 110, which for example includes a pad oxide layer and a hard mask oxide layer.

[0028] The first dielectric layer 110 is formed with a second dielectric layer 120, which is formed with a metal layer 140 and a barrier layer 130 on both sides and the bottom of the metal layer 140.

[0029] The second dielectric layer 120 is formed with a third dielectric layer 150, which is formed with a metal connection structure 160 that electrically connects the metal layer 140.

[0030] The metal interconnection structure parallel test structure is a parallel test structure for testing whether the metal connection structure and the metal layer in actual process on line can be electrically connected well. Therefore, the manufacturing process of the metal layer 140 and the metal connection structure 160 in the parallel test structure is completely the same as that of the metal connection structure and the metal layer in actual process on line.

[0031] However, in Figure 1 In the test structure shown, since the metal layer 140 and the semiconductor substrate 100 are insulated and isolated by the first dielectric layer 110, it causes the entire circuit to be disconnected (because the metal layer 140 is floating due to insulation of the first dielectric layer 110) regardless of whether the metal connection structure 160 and the metal layer 140 are electrically connected well, so that the function of testing whether the metal connection structure 160 and the metal layer 140 are electrically connected well is lost.

[0032] To solve the above problems, the present application provides a metal interconnection structure parallel test structure and a forming method thereof, which can make the metal layer and the semiconductor substrate be electrically connected well, thereby improving the accuracy of test results.

[0033] Figure 1A structure diagram of each step in a forming method of a parallel test structure of a metal interconnection structure.

[0034] Reference Figures 2 to 13 As shown in FIG. 1, a semiconductor substrate 200 is provided. Since the present application relates to a short-circuit wafer structure, all FEOL and MEOL process steps are skipped, and thus there are no active devices such as transistors on the semiconductor substrate 200, but the semiconductor substrate 200 is grounded.

[0035] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, etc.; or (iv) a combination thereof. In addition, the semiconductor substrate 200 can be doped (for example, a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 can be doped with a P-type dopant (for example, boron, indium, aluminum, or gallium) or an N-type dopant (for example, phosphorus or arsenic).

[0036] Reference Figure 2 As shown in FIG. 2, a first dielectric layer 210 is formed on the surface of the semiconductor substrate 200. The material of the first dielectric layer 210 includes silicon oxide or silicon nitride, etc. The method of forming the first dielectric layer 210 includes a chemical vapor deposition process or a physical vapor deposition process, etc. The first dielectric layer 210 is used to form a metal layer and a barrier layer.

[0037] In the technical solution of the present application, the structure of the pad oxide layer and the hard mask oxide layer, etc. which isolates the metal layer and the semiconductor substrate is no longer formed. Instead, the metal layer and the barrier layer are directly made on the surface of the semiconductor substrate, avoiding the problem that the semiconductor substrate and the metal layer cannot be electrically connected, which leads to inaccurate test results.

[0038] Reference Figure 3 As shown in FIG. 3, a first opening 211 exposing the surface of the semiconductor substrate 200 is formed in the first dielectric layer 210.

[0039] In some embodiments of the present application, the method of forming the first opening 211 exposing the surface of the semiconductor substrate 200 in the first dielectric layer 210 includes: forming a patterned first photoresist layer on the surface of the first dielectric layer 210, the patterned first photoresist layer defining the position of the first opening 211; etching the first dielectric layer 210 to expose the semiconductor substrate 200 to form the first opening 211 with the patterned first photoresist layer as a mask; and removing the patterned first photoresist layer.

[0040] Reference Figure 4A barrier layer 220 is formed on the sidewall and bottom of the first opening 211. The barrier layer 220 is used to prevent the metal particles in the metal layer from diffusing into the first dielectric layer 210.

[0041] In some embodiments of the present application, the method of forming the barrier layer 220 on the sidewall and bottom of the first opening 211 includes: depositing a barrier layer material on the sidewall and bottom of the first opening 211 and the surface of the first dielectric layer 220; removing the barrier layer material on the surface of the first dielectric layer 220 to leave the barrier layer material on the sidewall and bottom of the first opening 211 to form the barrier layer 220.

[0042] In some embodiments of the present application, the material of the barrier layer 220 includes any one of TiN, Ti, TaN, and Ta.

[0043] Referring to Figure 5 The barrier layer 220 and a portion of the semiconductor substrate 200 that are in direct contact are allowed to alloy to form an alloy layer 221.

[0044] Although the metal layer can be connected to the semiconductor substrate through the barrier layer after the pad oxide layer and the hard mask oxide layer are removed, in order to further improve the electrical connection between the metal layer and the semiconductor substrate, a portion of the barrier layer 220 and a portion of the semiconductor substrate 200 are directly alloyed to form the alloy layer 221.

[0045] The alloy layer 221 is the alloy product of the barrier layer 220 and the semiconductor substrate 200. For example, the semiconductor substrate 200 is silicon, and the barrier layer 220 is TiN or Ti, and the alloy layer 221 is then TiSi. The alloy layer 221 can reduce the joint resistance between the semiconductor substrate 200 and the barrier layer 220, thereby improving the electrical connection performance.

[0046] In some embodiments of the present application, the method of allowing the barrier layer 220 and a portion of the semiconductor substrate 200 that are in direct contact to alloy includes an annealing process. The annealing process is, for example, a rapid annealing process such as DSA.

[0047] In some embodiments of the present application, the process parameters of the annealing process include: an annealing temperature of 600-1500K, and an annealing time of 5-170 seconds.

[0048] The annealing process is performed before the subsequent formation of the first metal layer, which can avoid affecting the first metal layer.

[0049] Referring to Figure 6The first metal layer 230 is filled in the first opening 211. The material of the first metal layer 230 is tungsten or copper, etc.

[0050] In some embodiments of the present application, the method of filling the first metal layer 230 in the first opening 211 includes: forming the first metal layer 230 in the first opening 211 and on the surface of the first dielectric layer 210 by using a chemical vapor deposition process; and then removing the part of the first metal layer 230 above the surface of the first dielectric layer 210.

[0051] In the technical solution of the present application, the first metal layer 230 can be well electrically connected with the semiconductor substrate 200 through the barrier layer 220 and the alloy layer 221, thereby improving the accuracy of the test result.

[0052] Reference Figure 7 The second dielectric layer 240 is formed on the surface of the first dielectric layer 210, and the metal connection structure 250 is formed through the second dielectric layer 240 and electrically connected with the first metal layer 230. The first metal layer 230 and the metal connection structure 250 are formed synchronously with the first metal layer and the metal connection structure in the main area of the semiconductor substrate.

[0053] The technical solution of the present application relates to a parallel test structure for testing whether the metal connection structure and the metal layer in the actual process on line can be well electrically connected. Therefore, the manufacturing process of the metal layer 230 and the metal connection structure 250 in the parallel test structure is completely the same as that of the metal connection structure and the metal layer in the actual process on line. In this way, the test result can be ensured not to be affected by irrelevant variables. Specifically, the first metal layer 230 and the metal connection structure 250 can be formed synchronously with the first metal layer and the metal connection structure in the main area of the semiconductor substrate. The main area of the semiconductor substrate is used for forming the actual semiconductor device on line, and the test structure described in the present application is manufactured in the test area of the semiconductor substrate. The test area is used for forming the test structure described in the present application. That is, the semiconductor substrate is divided into the main area and the test area. The main area is used for forming the actual semiconductor device on line, and the test area is used for forming the test structure described in the present application. In this way, the accuracy of the tested part (i.e. the first metal layer 230 and the metal connection structure 250) can be ensured.

[0054] Reference Figures 8 to 10 The second dielectric layer 240 is formed on the surface of the first dielectric layer 210. The material of the second dielectric layer 240 includes silicon oxide or silicon nitride, etc. The method of forming the second dielectric layer 240 includes a chemical vapor deposition process or a physical vapor deposition process, etc. The second dielectric layer 240 is used for forming the metal connection structure.

[0055] Referring to Figure 8 A second opening 241 exposing a surface of the first metal layer 230 is formed in the second dielectric layer 240.

[0056] In some embodiments of the present application, the method of forming the second opening 241 exposing the surface of the first metal layer 230 in the second dielectric layer 240 includes: forming a patterned second photoresist layer on a surface of the second dielectric layer 240, the patterned second photoresist layer defining a position of the second opening 241; etching the second dielectric layer 240 to expose the first metal layer 230 to form the second opening 241 using the patterned second photoresist layer as a mask; and removing the patterned second photoresist layer.

[0057] Referring to Figure 9 The metal connection structure 250 is formed in the second opening 241. The material of the metal connection structure 250 is, for example, tungsten or copper, etc.

[0058] In some embodiments of the present application, the method of forming the metal connection structure 250 in the second opening 241 includes: forming a metal material layer in the second opening 241 and on a surface of the second dielectric layer 240 using a chemical vapor deposition process; and removing a portion of the metal material layer above the surface of the second dielectric layer 240 to form the metal connection structure.

[0059] Referring to Figure 10 In some embodiments of the present application, the method of forming the test structure further includes: forming a third dielectric layer 260 on a surface of the second dielectric layer 240 and a second metal layer 270 penetrating through the third dielectric layer 260 and electrically connected to the metal connection structure 250. The second metal layer 270 can be used as a metal pad for electrical connection by a probe when testing.

[0060] Referring to Figures 11 to 13 The third dielectric layer 260 is formed on a surface of the second dielectric layer 240. The material of the third dielectric layer 260 includes silicon oxide or silicon nitride, etc. The method of forming the third dielectric layer 260 includes a chemical vapor deposition process or a physical vapor deposition process, etc. The third dielectric layer 260 is used to form a second metal layer 270.

[0061] Referring to Figure 11 A third opening 261 exposing a surface of the metal connection structure 250 is formed in the third dielectric layer 260.

[0062] In some embodiments of the present application, the method for forming the third opening 261 in the third dielectric layer 260 to expose the surface of the metal connection structure 250 includes: forming a patterned third photoresist layer on the surface of the third dielectric layer 260, the patterned third photoresist layer defining the position of the third opening 261; etching the third dielectric layer 260 to expose the metal connection structure 250 to form the third opening 261 using the patterned third photoresist layer as a mask; and removing the patterned third photoresist layer.

[0063] Referring to Figure 12 As shown in the figure, the second metal layer 270 is formed in the third opening 261. The material of the second metal layer 270 is, for example, tungsten or copper, etc.

[0064] In some embodiments of the present application, the method for forming the second metal layer 270 in the third opening 261 includes: forming a second metal layer 270 in the third opening 261 and on the surface of the third dielectric layer 260 using a chemical vapor deposition process; and then removing the portion of the second metal layer 270 above the surface of the third dielectric layer 260.

[0065] The present application provides a method for forming a metal interconnection structure parallel test structure, which can make good electrical connection between the metal layer and the semiconductor substrate through the alloy layer, thereby improving the accuracy of test results.

[0066] Embodiments of the present application also provide a metal interconnection structure parallel test structure, referring to Figure 13 As shown in the figure, the metal interconnection structure parallel test structure includes: a semiconductor substrate 200; a first dielectric layer 210 on the surface of the semiconductor substrate 200; a first metal layer 230 and a barrier layer 220 on the sidewall and bottom of the first metal layer 230, the barrier layer 220 on the bottom of the first metal layer 230 being alloyed with a portion of the semiconductor substrate 200 (forming an alloy layer 221); a second dielectric layer 240 on the surface of the first dielectric layer 210, the second dielectric layer 240 being provided with a metal connection structure 250 penetrating the second dielectric layer 240 and electrically connecting the first metal layer 230, wherein the first metal layer 230 and the metal connection structure 250 are completely the same as the first metal layer and the metal connection structure in the main body region of the semiconductor substrate.

[0067] Referring to Figure 13 As shown in the figure, since the present application relates to a short-circuit wafer structure, which does not include the structure of FEOL and MEOL, there are no active devices such as transistors on the semiconductor substrate 200, but the semiconductor substrate 200 is grounded.

[0068] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or indium gallium phosphide, etc.; or (iv) a combination thereof. In addition, the semiconductor substrate 200 can be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 can be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0069] With continued reference to Figure 13 As shown, the semiconductor substrate 200 is provided with a first dielectric layer 210. The material of the first dielectric layer 210 includes silicon oxide or silicon nitride, etc.

[0070] In the technical solution of the present application, structures such as pad oxide layers and hard mask oxide layers, which isolate the metal layer and the semiconductor substrate, are not included. The semiconductor substrate and the barrier layer are directly connected, avoiding the problem that the semiconductor substrate and the metal layer cannot be electrically connected, which leads to inaccurate test results.

[0071] With continued reference to Figure 13 As shown, the first dielectric layer 210 is provided with a first metal layer 230 and a barrier layer 220 located on the sidewall and bottom of the first metal layer 230. The barrier layer 220 at the bottom of the first metal layer 230 is alloyed with a portion of the semiconductor substrate 200 (forming an alloy layer 221).

[0072] In some embodiments of the present application, the material of the first metal layer 230 is, for example, tungsten or copper, etc.

[0073] The barrier layer 220 is used to block the diffusion of metal particles in the metal layer into the first dielectric layer 210. In some embodiments of the present application, the material of the barrier layer 220 includes any one of TiN, Ti, TaN, and Ta.

[0074] Although the pad oxide layer and the hard mask oxide layer are removed, the metal layer can be connected to the semiconductor substrate through the barrier layer. However, in order to further improve the electrical connection between the metal layer and the semiconductor substrate, a portion of the barrier layer 220 and a portion of the semiconductor substrate 200 are directly alloyed into one body, forming an alloy layer 221.

[0075] The alloy layer 221 is an alloy product of the barrier layer 220 and the semiconductor substrate 200. For example, the semiconductor substrate 200 is silicon, the barrier layer 220 is TiN or Ti, and the alloy layer 221 is then TiSi. The alloy layer 221 can reduce the joint resistance of the semiconductor substrate 200 and the barrier layer 220, thereby improving the electrical connection performance.

[0076] In the technical solution of the present application, the first metal layer 230 can be well electrically connected to the semiconductor substrate 200 through the barrier layer 220 and the alloy layer 221, thereby improving the accuracy of the test results.

[0077] With reference to Figure 13 As shown, the first dielectric layer 210 is provided with a second dielectric layer 240 and a metal connection structure 250 penetrating the second dielectric layer 240 and electrically connected to the first metal layer 230, wherein the structure of the first metal layer 230 and the metal connection structure 250 is exactly the same as that of the metal connection structure on the line.

[0078] The technical solution of the present application relates to a parallel test structure for testing whether the metal connection structure and the metal layer on the line can be well electrically connected in the actual process. Therefore, the structure of the metal layer 230 and the metal connection structure 250 in the parallel test structure is exactly the same as that of the metal connection structure and the metal layer formed in the actual process on the line. In this way, the accuracy of the test results can be ensured to be not affected by irrelevant variables. Specifically, the semiconductor substrate can be divided into a main body area and a test area. The main body area is used to form the actual semiconductor device on the line, and the test area is used to form the test structure of the present application. The actual semiconductor device of the main body area is synchronously formed with the test part (i.e., the first metal layer 230 and the metal connection structure 250) of the test structure in the test area of the present application. In this way, the accuracy of the tested part can be ensured.

[0079] In some embodiments of the present application, the material of the second dielectric layer 240 includes silicon oxide or silicon nitride, etc.

[0080] In some embodiments of the present application, the material of the metal connection structure 250 is, for example, tungsten or copper, etc.

[0081] With reference to Figure 13 Figure 13 As shown, in some embodiments of the present application, the test structure further includes a third dielectric layer 260 located on the surface of the second dielectric layer 240, and a second metal layer 270 penetrating the third dielectric layer 260 and electrically connected to the metal connection structure 250 is arranged in the third dielectric layer 260. The second metal layer 270 can be used as a metal pad for the probe to be electrically connected when testing.

[0082] In some embodiments of the present application, the material of the third dielectric layer 260 includes silicon oxide or silicon nitride, etc.

[0083] In some embodiments of the present application, the material of the second metal layer 270 is tungsten or copper, etc.

[0084] The present application provides a metal interconnection structure parallel test structure and a forming method thereof, which can make a good electrical connection between the metal layer and the semiconductor substrate, thereby improving the accuracy of test results.

[0085] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing content of the application can be presented only in an exemplary manner and can not be limiting. Although not explicitly stated herein, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0086] It should be understood that the term "and / or" used in the present embodiments includes any or all combinations of one or more associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be an intermediate element.

[0087] Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediate element. In contrast, the term "directly" means that there is no intermediate element. It should also be understood that the terms "comprise", "comprising", "include", or "including", as used in the present document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0088] It should also be understood that although the terms first, second, third, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, the first element in some embodiments can be referred to as the second element in other embodiments without departing from the teachings of the present application. The same reference numbers or the same reference signs represent the same elements throughout the specification.

[0089] Furthermore, the description herein describes example embodiments by reference to idealized illustrative cross-sectional and / or plan and / or perspective views. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the example embodiments should not be construed as limited to the precise shapes illustrated herein but are to include deviations in shapes that result from such tollerances and / or manufacturing techniques. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the example embodiments.

Claims

1. A method for forming a parallel test structure for a metal interconnect structure, comprising: The method comprises: providing a semiconductor substrate; forming a first dielectric layer on the surface of the semiconductor substrate; forming a first opening in the first dielectric layer to expose the surface of the semiconductor substrate; forming a barrier layer on the sidewall and bottom of the first opening; alloying a portion of the semiconductor substrate directly contacting the barrier layer to form an alloy layer; filling the first opening with a first metal layer, the first metal layer being electrically connected to the semiconductor substrate through the barrier layer and the alloy layer; forming a second dielectric layer on the surface of the first dielectric layer and a metal connection structure penetrating the second dielectric layer and electrically connected to the first metal layer, wherein the first metal layer and the metal connection structure are formed synchronously with the first metal layer and the metal connection structure in the body region of the semiconductor substrate.

2. The method of claim 1, wherein the test structure is formed by: The method of alloying a portion of the semiconductor substrate directly contacting the barrier layer comprises an annealing process.

3. The method of claim 2, wherein the test structure is formed by: The process parameters of the annealing process include an annealing temperature of 600-1500K and an annealing time of 5-170 seconds.

4. The method of claim 1, wherein the test structure is formed by: The method of forming a second dielectric layer on the surface of the first dielectric layer and a metal connection structure penetrating the second dielectric layer and electrically connected to the first metal layer comprises: forming a second dielectric layer on the surface of the first dielectric layer; forming a second opening in the second dielectric layer to expose the surface of the first metal layer; forming the metal connection structure in the second opening.

5. The method of claim 1, wherein the test structure is formed by: The material of the barrier layer includes any one of TiN, Ti, TaN, and Ta.

6. The method of claim 1, wherein Further comprising: forming a third dielectric layer on the surface of the second dielectric layer and a second metal layer penetrating the third dielectric layer and electrically connected to the metal connection structure.

7. The method of claim 6, wherein the test structure is formed by: The method of forming a third dielectric layer on the surface of the second dielectric layer and a second metal layer penetrating the third dielectric layer and electrically connected to the metal connection structure comprises: forming a third dielectric layer on the surface of the second dielectric layer; forming a third opening in the third dielectric layer to expose the surface of the metal connection structure; forming the second metal layer in the third opening.

8. A metal interconnect structure parallel test structure, characterized by, The method comprises: a semiconductor substrate; a first dielectric layer on the surface of the semiconductor substrate; a first metal layer and a barrier layer on the sidewall and bottom of the first metal layer, the first metal layer being located in the first dielectric layer, the barrier layer on the bottom of the first metal layer being alloyed with a portion of the semiconductor substrate to form an alloy layer, the first metal layer being electrically connected to the semiconductor substrate through the barrier layer and the alloy layer; a second dielectric layer on the surface of the first dielectric layer, the second dielectric layer being provided with a metal connection structure penetrating the second dielectric layer and electrically connected to the first metal layer, wherein the first metal layer and the metal connection structure are completely identical to the first metal layer and the metal connection structure in the body region of the semiconductor substrate.

9. The test structure of claim 8, wherein, The material of the barrier layer includes any one of TiN, Ti, TaN, and Ta.

10. The test structure of claim 8, wherein, Further comprising: a third dielectric layer on the surface of the second dielectric layer, the third dielectric layer being provided with a second metal layer penetrating the third dielectric layer and electrically connected to the metal connection structure.

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