Display device and driving method thereof

Abstract

A display apparatus includes a display panel in which a plurality of pixels are disposed, a timing controller configured to output a sensing pulse and a video data signal, and a data driver configured to receive the sensing pulse and output a data voltage to the plurality of pixels according to the video data signal, wherein the data driver includes a plurality of source integrated circuits, each of the plurality of source integrated circuits receives a plurality of delay pulses, and the timing controller compares a timing of the plurality of delay pulses and compensates the video data signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0181701, filed on December 17, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device and a driving method thereof, and more specifically, to a display device and a driving method thereof configured to compensate for data. Background Technology

[0004] Organic light-emitting display devices (OLEDs), which are self-emissive devices, and liquid crystal display devices (LCDs), which require a separate light source, have been used in computer monitors, televisions, or mobile phones.

[0005] An organic light-emitting display device includes a display panel having multiple sub-pixels and a driver for driving the display panel. The driver includes a gate driver that provides gate signals to the display panel and a data driver that provides data voltages. When signals such as gate signals and data voltages are provided to the sub-pixels of the organic light-emitting display device, selected sub-pixels emit light to display an image.

[0006] In recent years, to improve image quality, threshold voltages of driving transistors located in sub-pixels have been sensed to compensate data based on these threshold voltages. However, during the processing or use of a display device, moisture infiltration can occur in the configuration of the threshold voltage sensing. In this case, the sensed value of the threshold voltage changes, causing errors in data compensation. Summary of the Invention

[0007] Therefore, this disclosure provides a display device that can perform compensation operations normally even if moisture penetration occurs.

[0008] This disclosure also provides a display device capable of converting the degree of moisture penetration into a numerical value to compensate for the data.

[0009] This disclosure is not limited to the above and other features, and those skilled in the art will clearly understand other features not mentioned above through the following description.

[0010] To achieve the above, according to one aspect of this disclosure, a display device includes: a display panel having a plurality of pixels disposed therein; a timing controller configured to output sensing pulses and video data signals; and a data driver configured to receive sensing pulses and output data voltages to the plurality of pixels according to the video data signals, wherein the data driver includes a plurality of source integrated circuits, each of the plurality of source integrated circuits receiving a plurality of delayed pulses obtained by delaying the sensing pulses, and the timing controller comparing the timing of the plurality of delayed pulses to compensate for the video data signals.

[0011] In another aspect of this disclosure, a method for driving a display device includes: a signal generation step for outputting sensing pulses; a delay detection step for analyzing a plurality of delay pulses to output delay information indicating a faulty source integrated circuit; and a data compensation step for compensating video data signals based on the delay information.

[0012] In another aspect of this disclosure, a display device includes: a display panel having a plurality of pixels disposed therein; a timing controller configured to output sensing pulses via a first sensing line to determine moisture penetration in the plurality of pixels; and a plurality of source integrated circuits configured to receive the sensing pulses and output a plurality of delayed pulses to the timing controller, wherein the timing controller is configured to compare the timing of the plurality of delayed pulses under normal and fault conditions, generate data reflecting moisture penetration, compensate a video data signal based on the generated data reflecting moisture penetration, output the compensated video signal to the first source integrated circuit via a first feedback line, and wherein the plurality of source integrated circuits are configured to output a data voltage to the plurality of pixels according to the compensated video data signal.

[0013] Further details of the exemplary aspects are included in the detailed description and accompanying drawings.

[0014] According to this disclosure, faults caused by moisture penetration in the source integrated circuit are identified, and video data signals are compensated to resolve the faults caused by moisture penetration.

[0015] According to this disclosure, only a sensing line is added to the source integrated circuit to detect faults in the source integrated circuit.

[0016] The effects of this disclosure are not limited to those illustrated above; this specification includes many more effects. Attached Figure Description

[0017] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1This is a schematic diagram of a display device according to an exemplary aspect of the present disclosure;

[0019] Figure 2 This is a circuit diagram of a sub-pixel of a display device according to an exemplary aspect of this disclosure;

[0020] Figure 3 This is a view used to explain the connection relationships of the data drivers of the display device according to exemplary aspects of this disclosure;

[0021] Figure 4 yes Figure 3 A magnified view of region A in the middle;

[0022] Figure 5 This is a circuit diagram illustrating the RC circuit of a data driver for a display device according to an exemplary aspect of this disclosure;

[0023] Figure 6 These are the waveforms of the sensing pulse and the delayed pulse of the display device under normal conditions, according to an exemplary aspect of this disclosure;

[0024] Figure 7 This is a block diagram for explaining the timing controller of a display device according to an exemplary aspect of this disclosure;

[0025] Figure 8 The waveforms of the sensing pulse and delayed pulse of the display device according to an exemplary aspect of this disclosure in a fault state; and

[0026] Figure 9 This is a flowchart for explaining a driving method of a display device according to an exemplary aspect of the present disclosure. Detailed Implementation

[0027] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from reference to the exemplary aspects described in detail below in conjunction with the accompanying drawings. However, this disclosure is not limited to the exemplary aspects disclosed herein, but will be implemented in various forms. These exemplary aspects are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0028] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings to describe exemplary aspects of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0029] Even if not explicitly stated, components are interpreted as including the normal error range.

[0030] When using terms such as “on top of,” “above,” “below,” and “after” to describe the positional relationship between two parts, one or more parts may be placed between the two parts, unless these terms are used with the terms “immediately following” or “directly.”

[0031] When one element or layer is disposed "on" another element or layer, the element or layer may be disposed directly on the other element or layer or other elements or layers may be inserted between them.

[0032] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from other components. Therefore, within the technical concept of this disclosure, the first component mentioned below can be a second component.

[0033] The same reference numerals generally denote the same elements throughout the application.

[0034] For ease of illustration, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, but this disclosure is not limited to the dimensions and thickness of the illustrated components.

[0035] Features of the various aspects of this disclosure may be combined or integrated with each other, either partially or in whole, and may be technically interlocked and operated in various ways. These aspects may be implemented independently of each other or in relation to each other.

[0036] The transistors used in the display device of this disclosure can be implemented using one or more of n-channel transistors (NMOS) and p-channel transistors (PMOS). The transistors can be implemented using oxide semiconductor transistors with oxide semiconductor as the active layer or LTPS transistors with low-temperature polycrystalline silicon (LTPS) as the active layer. The transistors can include at least a gate, a source, and a drain. The transistors can be implemented using thin-film transistors on a display panel. In the transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor (NMOS), since the charge carriers are electrons, the source voltage can be lower than the drain voltage to allow electrons to flow from the source to the drain. The current direction in an n-channel transistor (NMOS) is from the drain to the source, and the source can be used as an output terminal. In the case of a p-channel transistor (PMOS), since the charge carriers are holes, the source voltage is higher than the drain voltage to allow holes to flow from the source to the drain. In a p-channel transistor (PMOS), holes flow from the source to the drain, causing current to flow from the source to the drain, and the drain is used as an output terminal. Therefore, the source and drain can be switched according to the applied voltage; it should be noted that the source and drain of a transistor are not fixed. In this specification, it is assumed that the transistor is an n-channel transistor (NMOS), but it is not limited to this; a p-channel transistor can be used, which would change the circuit configuration.

[0037] The gate signal of a transistor used as a switching element oscillates between a turn-on voltage and a turn-off voltage. The turn-on voltage is set above the transistor's threshold voltage Vth, and the turn-off voltage is set below the transistor's threshold voltage Vth. The transistor turns on in response to the turn-on voltage and turns off in response to the turn-off voltage. In the case of NMOS, the turn-on voltage is high, and the turn-off voltage is low. In the case of PMOS, the turn-on voltage can be low, and the turn-off voltage can be high.

[0038] In the following, various exemplary aspects of this disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 This is a schematic diagram of a display device according to an exemplary aspect of the present disclosure.

[0040] refer to Figure 1 The display device 100 includes a display panel 110, a data driver 120, a gate driver 130, and a timing controller 140.

[0041] Display panel 110 is a panel for displaying images and may include various circuits, wiring, and light-emitting diodes disposed on a substrate. Multiple data lines DL and multiple gate lines GL intersect each other in display panel 110. The display panel also includes multiple pixels PX connected to the multiple data lines DL and the multiple gate lines GL. Display panel 110 has a display area defined by the multiple pixels PX and a non-display area in which various signal lines or pads are formed. Display panel 110 can be implemented using display panels 110 used in various display devices such as liquid crystal display devices, organic light-emitting display devices, or electrophoretic display devices. Hereinafter, display panel 110 will be described as a panel for use in OLED devices, but is not limited thereto.

[0042] The timing controller 140 receives timing signals such as vertical synchronization signals, horizontal synchronization signals, data enable signals, or point clocks via a receiver circuit connected to the host system, such as an LVDS (Low Voltage Differential Signaling) or TMDS (Transition Minimum Differential Signaling) interface. Based on the input timing signals, the timing controller 140 generates data control signals for controlling the data driver 120 and gate control signals for controlling the gate driver 130.

[0043] The timing controller 140 processes externally input image data RGB that is suitable for the size and resolution of the display panel 110, converts the image data RGB into a video data signal RGB, and then provides the video data signal RGB to the data driver 120.

[0044] The timing controller 140 provides a sensing pulse SP, used to determine the degree of moisture penetration, to the data driver 120. For example, the sensing pulse SP may be a square wave synchronized with the first rise time of the point clock to be output.

[0045] Data driver 120 provides data voltage DATA to multiple sub-pixels. Data driver 120 includes a source printed circuit board and multiple source integrated circuits. Each of the multiple source integrated circuits is supplied with video data RGB and data control signals from timing controller 140 via the source printed circuit board.

[0046] The data driver 120 converts the video data RGB into gamma voltage in response to the data control signal to generate the data voltage DATA, and provides the data voltage DATA through the data line DL of the display panel 110.

[0047] Multiple source integrated circuits can be connected to the data lines DL of the display panel 100 in the form of chip-on-film (COF). More specifically, each of the multiple source integrated circuits can be implemented as a chip disposed on a connecting film, and wiring connecting to the source integrated circuit formed as a chip can be formed on the connecting film. However, the arrangement of the multiple source driver integrated circuits is not limited to this, and they can also be connected to the data lines DL of the display panel 110 via chip-on-glass (COG) technology or tape-on-board (TAB) technology.

[0048] Gate driver 130 provides gate signals to multiple sub-pixels. Gate driver 130 may include a level shifter and a shift register. The level shifter shifts the level of a clock signal input from timing controller 140 at transistor-transistor-logic (TTL) levels, and then provides the clock signal to the shift register. The shift register may be formed in a non-display area of ​​display panel 110 using a GIP configuration, but is not limited thereto. The shift register is configured to shift the gate signal in response to clock and drive signals in multiple stages as outputs. The multiple stages included in the shift register sequentially output gate signals through multiple output terminals.

[0049] The display panel 110 may include multiple subpixels. These subpixels may be subpixels that emit different colors of light. For example, the multiple subpixels may be red subpixels, green subpixels, blue subpixels, and white subpixels, but are not limited to these. The multiple subpixels may constitute a pixel PX. That is, red subpixels, green subpixels, blue subpixels, and white subpixels constitute one pixel PX, and the display panel 110 may include multiple pixel PXs.

[0050] In the following text, reference will be made to Figure 2 and Figure 1 A more detailed description of the driving circuitry used to drive a pixel.

[0051] Figure 2 This is a circuit diagram of the pixels of a display device according to an exemplary aspect of this disclosure.

[0052] Figure 2 A circuit diagram of one pixel among a plurality of pixels in a display device 100 is shown.

[0053] refer to Figure 2 The pixel may include a switching transistor SWT, a sensing transistor SET, a driving transistor DT, a storage capacitor SC, and a light-emitting diode 150.

[0054] The light-emitting diode 150 may include an anode, an organic layer, and a cathode. The organic layer may include various organic layers, such as a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer. The anode of the light-emitting diode 150 may be connected to the output of the driving transistor DT, and a low-potential voltage VSS is applied to the cathode via a low-potential voltage line VSSL. Even when... Figure 2 The light-emitting diode 150 is described as an organic light-emitting diode 150, but this disclosure is not limited thereto; an inorganic light-emitting diode, i.e., an LED, may also be used as the light-emitting diode 150.

[0055] The aforementioned low-potential voltage line VSSL is a positive voltage line to which a low-potential voltage is applied as a positive voltage, and is indicated as the ground terminal.

[0056] refer to Figure 2 The switching transistor SWT is a transistor that transmits the data voltage DATA to a first node N1 connected to the gate of the driving transistor DT. The switching transistor SWT may include a drain connected to the data line DL, a gate connected to the gate line GL, and a source connected to the gate of the driving transistor DT. The switching transistor SWT is turned on by a scan signal SCAN applied from the gate line GL to transmit the data voltage DATA provided from the data line DL to the first node N1 connected to the gate of the driving transistor DT.

[0057] refer to Figure 2 The driving transistor DT is a transistor that provides driving current to the light-emitting diode 150 to drive the light-emitting diode 150. The driving transistor DT may include a gate connected to the first node N1, a source connected to the second node N2 as an output terminal, and a drain connected to the third node N3 as an input terminal. The gate of the driving transistor DT is connected to the switching transistor SWT, the drain is given a high-potential voltage VDD through the high-potential voltage line VDDL, and the source is connected to the anode of the light-emitting diode 150.

[0058] refer to Figure 2 The storage capacitor SC is a capacitor that maintains the voltage corresponding to the data voltage DATA for one frame. One electrode of the storage capacitor SC is connected to the first node N1, and the other electrode is connected to the second node N2.

[0059] Meanwhile, in the case of display device 100, as the driving time of each pixel increases, circuit elements such as the driving transistor DT may degrade. Therefore, the unique characteristic values ​​of circuit elements such as the driving transistor DT will change. Here, the unique characteristic values ​​of the circuit elements may include the threshold voltage Vth of the driving transistor DT or the mobility α of the driving transistor DT. Changes in the characteristic values ​​of the circuit elements will cause changes in the brightness of the corresponding pixels. Therefore, changes in the characteristic values ​​of the circuit elements can be used as the same concept as changes in the brightness of pixels.

[0060] Furthermore, the degree of variation in the eigenvalues ​​between the circuit elements of each pixel can vary depending on the degree of degradation of each circuit element. This difference in the degree of variation in the eigenvalues ​​between circuit elements can lead to brightness deviations between pixels. Therefore, the eigenvalue deviation between circuit elements can be used as the same concept as the brightness deviation between pixels. Variations in the eigenvalues ​​of circuit elements, i.e., pixel brightness variations, and eigenvalue deviations between circuit elements, i.e., brightness deviations between pixels, can lead to problems such as reduced brightness performance accuracy of pixels or screen anomalies.

[0061] Therefore, the display device 100 according to the exemplary aspect of this disclosure provides a sensing function for sensing the feature values ​​of the sensing pixels and a compensation function for compensating the feature values ​​of the pixels using the sensing results.

[0062] Therefore, as Figure 2 As shown, in addition to the switching transistor SWT, driving transistor DT, storage capacitor SC, and light-emitting diode 150, the pixel may also include a sensing transistor SET to effectively control the voltage state of the source of the driving transistor DT.

[0063] refer to Figure 2 The sensing transistor SET is connected between the source of the driving transistor DT and the reference voltage line RVL, which provides the reference voltage Vref, and its gate is connected to the gate line GL. Therefore, the sensing transistor SET is turned on by the sensing signal SENSE applied through the gate line GL to apply the reference voltage Vref provided through the reference voltage line RVL to the source of the driving transistor DT. Furthermore, the sensing transistor SET can be used as one of the voltage sensing paths for the source of the driving transistor DT.

[0064] refer to Figure 2In this pixel, the switching transistor SWT and the sensing transistor SET can share a single gate line GL. That is, the switching transistor SWT and the sensing transistor SET are connected to the same gate line GL to receive the same gate signal. However, for ease of explanation, the voltage applied to the gate of the switching transistor SWT is called the scan signal SCAN, and the voltage applied to the gate of the sensing transistor SET is called the sensing signal SENSE. However, the scan signal SCAN and the sensing signal SENSE applied to a pixel are the same signal transmitted from the same gate line GL.

[0065] However, this disclosure is not limited to this, and it is possible that only the switching transistor SWT is connected to the gate line GL, while the sensing transistor SET can be connected to a separate sensing line. Thus, the scan signal SCAN is applied to the switching transistor SWT through the gate line GL, while the sensing signal SENSE is applied to the sensing transistor SET through the sensing line.

[0066] Therefore, the reference voltage Vref is applied to the source of the driving transistor DT through the sensing transistor SET. Furthermore, the threshold voltage Vth or the mobility α of the driving transistor DT is detected via the reference voltage line RVL. Additionally, the data driver 120 can compensate for the data voltage DATA based on changes in the threshold voltage Vth or the mobility α of the driving transistor DT.

[0067] In the following text, reference will be made to Figure 3 and Figure 4 A detailed description of the data driver of a display device according to exemplary aspects of this disclosure.

[0068] Figure 3 This is a view used to explain the connection relationships of the data drivers of a display device according to exemplary aspects of this disclosure.

[0069] Figure 4 yes Figure 3 A magnified view of region A.

[0070] refer to Figure 3 The data driver 120 includes multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn and a source printed circuit board SPCB arranged in a chip-on-film (COF) configuration.

[0071] Specifically, the display panel 110 and the source printed circuit board SPCB are connected by multiple connecting films CF, and multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn can be disposed on the multiple connecting films CF. In other words, the display panel 110 and the source printed circuit board SPCB are attached to both sides of the multiple connecting films CF, and the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn can be disposed in the multiple connecting films CF.

[0072] Sensing lines and feedback lines can be set in the source printed circuit board (SPCB) and multiple source integrated circuits (SDIC1, SDIC2, SDIC3, ..., SDICn).

[0073] The feedback lines include the main feedback line MFL and multiple branch feedback lines BFL1, BFL2, BFL3, ..., BFLn that branch off from the main feedback line MFL.

[0074] refer to Figure 3 The main feedback line MFL extends from the timing controller 140 to be formed on the source printed circuit board SPCB. Multiple branch feedback lines BFL1, BFL2, BFL3, ..., BFLn extend from the source printed circuit board SPCB to connect to multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn.

[0075] For example, the first branch feedback line BFL1 extends from the main feedback line MFL to connect to the first source integrated circuit SDIC1. The second branch feedback line BFL2 extends from the main feedback line MFL to connect to the second source integrated circuit SDIC2. The third branch feedback line BFL3 extends from the main feedback line MFL to connect to the third source integrated circuit SDIC3. The nth branch feedback line BFLn extends from the main feedback line MFL to connect to the nth source integrated circuit SDICn.

[0076] Therefore, multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn are transmitted to the main feedback line MFL via multiple branch feedback lines BFL1, BFL2, BFL3, ..., BFLn, each reflecting the threshold voltage Vth or the mobility α of the driving transistor DT, along with a clock signal. The main feedback line MFL then transmits the voltage value reflecting the threshold voltage Vth or the mobility α of the driving transistor DT, along with a clock signal, to the timing controller 140.

[0077] Furthermore, the timing controller 140 outputs video data signal RGB through the main feedback line MFL. The video data signal RGB is transmitted to multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn through each of the multiple branch feedback lines BFL1, BFL2, BFL3, ..., BFLn.

[0078] refer to Figure 4 Each of the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn is connected to multiple data lines DL via multiple pads PD disposed on the display panel 110. Therefore, each of the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn outputs a data voltage to the data lines DL.

[0079] Meanwhile, the sensing lines include the main sensing line MSL and multiple branch sensing lines BSL1, BSL2, BSL3, ..., BSLn branching from the main sensing line MSL.

[0080] refer to Figure 3 The main sensing line MSL extends from the timing controller 140 to be formed on the source printed circuit board SPCB. Multiple branch sensing lines BSL1, BSL2, BSF3, ..., BSLn extend from the source printed circuit board SPCB to be connected to multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn, respectively.

[0081] For example, the first branch sensing line BSL1 extends from the main sensing line MSL to connect to the first source integrated circuit SDIC1. The second sensing feedback line BSL2 extends from the main sensing line MSL to connect to the second source integrated circuit SDIC2. The third sensing feedback line BSL3 extends from the main sensing line MSL to connect to the third source integrated circuit SDIC3. The nth sensing feedback line BSLn extends from the main sensing line MSL to connect to the nth source integrated circuit SDICn.

[0082] Therefore, the timing controller 140 outputs a sensing pulse SP to the main sensing line MSL, and the sensing pulse PS is transmitted to multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn through multiple branch sensing lines BSL1, BSL2, BSL3, ..., BSLn.

[0083] refer to Figure 3 Multiple resistors R1, R2, R3, ..., R n It can be set in the main sensing line MSL. Multiple resistors R1, R2, R3, ..., R nEach of the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn can be set between the timing controller 140 and any one of them, or can be set between the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn.

[0084] Specifically, a first resistor R1 is disposed between the timing controller 140 and the first branch sensing line BSL1 connected to the first source integrated circuit SDIC1. A second resistor R2 is disposed between the first branch sensing line BSL1 connected to the first source integrated circuit SDIC1 and the second branch sensing line BSL2 connected to the second source integrated circuit SDIC2. A third resistor R3 is disposed between the second branch sensing line BSL2 connected to the second source integrated circuit SDIC2 and the third branch sensing line BSL3 connected to the third source integrated circuit SDIC3. The nth resistor R... n It is positioned between the (n-1)th branch sensing line BSLn-1 connected to the (n-1)th source integrated circuit SDICn-1 and the nth branch sensing line BSLn connected to the nth source integrated circuit SDICn.

[0085] refer to Figure 4 Each of the multiple branch sensing lines BSLn passes through multiple source integrated circuits SDICn to extend to the pad PD formed on the display panel 110. Each of the multiple low-potential voltage lines VSSL passes through each of the multiple source integrated circuits SDICn to extend into the display panel 110 via the pad PD formed on the display panel 110. Multiple data lines DL can extend into the display panel 110 via the pad PD formed on the display panel 110. That is, unlike the data lines DL and low-potential lines VSSL, each of the multiple branch sensing lines BSLn does not extend into the display panel 110, but only extends to the pad PD located on the outside of the display panel 110.

[0086] A sealing region SA can be set to cover multiple pads PD and multiple source integrated circuits SDICn. Specifically, in the sealing region SA, the adhesive component not only covers multiple pads PD and multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn, but also covers the branch sensing line BSLn, the low-potential voltage line VSSL, and multiple data lines DL.

[0087] However, as described above, the multiple branch sensing lines BSL1, BSL2, BSL3, ..., BSLn do not extend into the display panel 110, but only extend to the pads PD located on the outside of the display panel, so that the multiple branch sensing lines BSL1, BSL2, BSL3, ..., BSLn are located in the sealing area SA. Conversely, the data line DL and the low-potential line VSSL can extend outside the sealing area SA to extend into the display panel 110.

[0088] Each of the multiple low-potential voltage lines VSSL can be set on one side of each of the multiple branch sensing lines BSL1, BSL2, BSL3, ... BSLn.

[0089] Therefore, the dielectric bonding member is disposed between each of the multiple sensing branch lines BSL1, BSL2, BSL3, ..., BSLn and each of the multiple low-potential voltage lines VSSL, so that a capacitor C can be formed in the sealed region SA. n .

[0090] In other words, the first capacitor C1 can be formed in the sealed region SA covering the first source integrated circuit SDIC1. The second capacitor C2 can be formed in the sealed region SA covering the second source integrated circuit SDIC2. The third capacitor C3 can be formed in the sealed region SA covering the third source integrated circuit SDIC3. The nth capacitor C... n It can be formed in the sealed region SA covering the nth source integrated circuit SDICn.

[0091] Figure 5 This is a circuit diagram for explaining the RC circuit of the data driver of a display device according to an exemplary aspect of this disclosure.

[0092] Figure 6 These are the waveforms of the sensing pulse and the delay pulse of the display device under normal conditions according to an exemplary aspect of this disclosure.

[0093] like Figure 5 As shown, according to the structure of the data driver 120, an RC circuit is formed between the timing controller 140 and multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn.

[0094] Specifically, the first capacitor C1 is disposed between the first source integrated circuit SDIC1 and the ground terminal, and the first resistor R1 is disposed between the first source integrated circuit SDIC1 and the timing controller 140. The second capacitor C2 is disposed between the second source integrated circuit SDIC2 and the ground terminal, and the first resistor R1 and the second resistor R2 are disposed between the second source integrated circuit SDIC2 and the timing controller 140. The third capacitor C3 is disposed between the third source integrated circuit SDIC3 and the ground terminal, and the first resistors R1 to the third resistor R3 are disposed between the third source integrated circuit SDIC3 and the timing controller 140. The nth capacitor C... n The resistors are positioned between the nth source integrated circuit SDICn and the ground terminal, and the first resistor R1 to the nth resistor R... n It is positioned between the nth source integrated circuit SDICn and the timing controller 140.

[0095] That is, the above RC circuit can be modeled as an Elmore delay circuit.

[0096] Therefore, the nth time constant τ of the nth delayed pulse DPn received by the nth source integrated circuit SDICn among multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn can be calculated using Formula 1. n .

[0097] [Formula 1]

[0098]

[0099] The aforementioned time constant is a parameter representing 63.2% of the time it takes for any pulse to reach the target level, and serves as a benchmark for indicating the degree of delay in a delayed pulse.

[0100] Where, τ n R is the time constant of the nth delayed pulse. i It is the resistance of any one of multiple resistors, C i It is the capacitance of any one of the multiple capacitors, and n is a natural number of 1 or greater.

[0101] In other words, the sensing pulse SP output from the timing controller 140 is delayed by a first time constant τ1, so as to be received by the first source integrated circuit SDIC1 as a first delayed pulse DP1. The first time constant τ1 can be calculated by R1×C1.

[0102] The sensing pulse SP output from the timing controller 140 is delayed by a second time constant τ2, so as a second delayed pulse DP2, which is received by the second source integrated circuit SDIC2. The second time constant τ2 can be calculated by (R1+R2)×(C1+C2).

[0103] The sensing pulse SP output from the timing controller 140 is delayed by a third time constant τ3, and is received by the third source integrated circuit SDIC3 as a third delayed pulse DP3. The third time constant τ3 can be calculated by (R1+R2+R3)×(C1+C2+C3).

[0104] The sensing pulse SP output from the timing controller 140 is delayed by the nth time constant τ. n The nth delayed pulse DPn is received by the nth source integrated circuit SDICn. The nth time constant τ n It can be calculated using Formula 1.

[0105] That is, the second time constant τ2 is greater than the first time constant τ1, the third time constant τ3 is greater than the second time constant τ2, and the nth time constant τ n Greater than the (n-1)th time constant τ (n-1) .

[0106] Therefore, the rise time of the first delayed pulse DP1 is later than the rise time of the second delayed pulse DP2, the rise time of the third delayed pulse DP3 is later than the rise time of the second delayed pulse DP2, and the rise time of the nth delayed pulse DPn is later than the rise time of the (n-1)th delayed pulse DP(n-1).

[0107] That is, multiple delayed pulses DP1, DP2, DP3, ..., DPn increase sequentially.

[0108] Figure 7 This is a block diagram for explaining the timing controller of a display device according to exemplary aspects of this disclosure.

[0109] Figure 8 These are the waveforms of the sensing pulse and the delayed pulse of the display device under a fault state, according to an exemplary aspect of this disclosure.

[0110] For reference, Figure 8 In the diagram, the delayed pulses DP1, DP2, DP3, ..., DPn under normal conditions are represented by solid lines, while the delayed pulses DP1, DP2, DP3, ..., DPn under fault conditions are represented by dashed lines.

[0111] refer to Figure 7 The timing controller 140 of the display device according to an exemplary aspect of this disclosure includes a signal generator 141, a delay detector 143, and a data compensator 145. The signal generator 141 generates a sensing pulse SP, the delay detector 143 outputs delay information DS, and the data compensator 145 compensates the video data signal RGB to output a compensated video data signal.

[0112] Signal generator 141 outputs a sensing pulse SP to the sensing line. The sensing pulse SP can be a square wave synchronized with the first rise time of the point clock to be output.

[0113] Delay detector 143 identifies the delay time of each of multiple delay pulses DP1, DP2, DP3, ..., DPn to generate delay information DS. That is, delay detector 143 compares the timing of each of the multiple delay pulses DP1, DP2, DP3, ..., DPn under normal conditions with the timing of each of the delay pulses DP1, DP2, DP3, ..., DPn under fault conditions to generate delay information DS. Delay information DS indicates information about the faulty source integrated circuit among the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn.

[0114] Specifically, moisture infiltration may occur in the sealing region SA between at least one of the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn and the display panel 110. That is, water having a dielectric constant higher than that of the adhesive members can penetrate the sealing region SA of a particular source integrated circuit. For example, the dielectric constant of the adhesive members disposed in the sealing region SA is 3 to 10, while the dielectric constant of water is 55 to 77. Therefore, in the source integrated circuit that has failed, the capacitance of the capacitor formed between the branch sensing lines BSL1, BSL2, BSL3, ..., BSLn and the low-potential voltage line VSSL increases.

[0115] For example, refer to Figures 3 to 5 When moisture penetrates into the sealed region SA of the second source integrated circuit SDIC2 among the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn, the capacitance of the second capacitor C2 will increase.

[0116] As described above, the nth time constant is calculated using Formula 1, which allows all time constants after the second time constant τ2 to be increased.

[0117] refer to Figure 8 The first time constant τ1 under fault conditions is equal to the first time constant τ1 under normal conditions, so the rise time of the first delayed pulse DP1 remains unchanged.

[0118] Conversely, under fault conditions, the second time constant τ2 increases, causing the rise time of the second delayed pulse DP2 under fault conditions to be delayed more than that under normal conditions.

[0119] Under fault conditions, the third time constant τ3 increases, causing the rise time of the third delayed pulse DP3 under fault conditions to be delayed more than that under normal conditions.

[0120] Under fault conditions, the nth time constant τ n The increase makes the rise time of the nth delayed pulse DPn in the fault state more delayed than the rise time of the nth delayed pulse DPn in the normal state.

[0121] Simultaneously, the data compensator 145 outputs a video data signal RGB compensated according to the delay information DS. Specifically, the data compensator 145 compensates for the video data signal RGB allocated to the faulty source integrated circuit according to the delay information DS. As a method for compensating the video data signal RGB, the average value of the video data signals RGB allocated to the adjacent, non-faulty source integrated circuits is used to compensate for the video data signal RGB. However, the method for compensating the video data signal RGB is not limited to this, and various compensation methods can be applied.

[0122] For example, such as Figure 8 As shown, when the second delay pulse DP2 to the nth delay pulse DPn are further delayed, thereby confirming the infiltration of water into the second source integrated circuit SDIC2 through the delay information DS, the video data signal RGB allocated to the second source integrated circuit SDIC2 can be the average of the video data signal RGB allocated to the first source integrated circuit SDIC1 and the video data signal RGB allocated to the third source integrated circuit SDIC3.

[0123] Therefore, the display device according to the exemplary aspects of this disclosure identifies a fault in the source integrated circuit caused by moisture penetration and compensates the video data signal to resolve the fault caused by moisture penetration.

[0124] In other words, the display device according to the exemplary aspects of this disclosure only requires additional sensing lines to be provided in the source integrated circuit to detect faults in the source integrated circuit.

[0125] Hereinafter, a driving method for a display device according to an exemplary aspect of this disclosure will be described. The driving method for the display device according to an exemplary aspect of this disclosure will be described based on the above-described configuration of the display device, and similar components will be labeled with similar reference numerals.

[0126] Figure 9 This is a flowchart for explaining a driving method of a display device according to an exemplary aspect of the present disclosure.

[0127] refer to Figure 9The driving method S100 of the display device according to an exemplary aspect of this disclosure includes a signal generation step S110, a delay detection step S120, and a data compensation step S130. In the signal generation step S110, a sensing pulse is output; in the delay detection step S120, delay information DS is output; and in the data compensation step S130, video data signal RGB is compensated for output.

[0128] In the signal sensing step S110, a sensing pulse SP is output to the sensing line. The sensing pulse SP can be a square wave synchronized with the first rise time of the point clock to be output.

[0129] In delay detection step S120, the delay time of each of the multiple delay pulses DP1, DP2, DP3, ..., DPn is identified to generate delay information DS. That is, in delay detection step S120, the timing of each of the multiple delay pulses DP1, DP2, DP3, ..., DPn under normal conditions is compared with the timing of each delay pulse DP1, DP2, DP3, ..., DPn under fault conditions to generate delay information DS. Delay information DS indicates information about the source integrated circuit that has failed among the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn.

[0130] Specifically, moisture infiltration may occur in the sealing region SA between at least one of the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn and the display panel 110. That is, water with a dielectric constant higher than that of the adhesive members can penetrate the sealing region SA of a particular source integrated circuit. For example, the dielectric constant of the adhesive members disposed in the sealing region SA is 3 to 10, while the dielectric constant of water is 55 to 77. Therefore, in the source integrated circuit that has failed, the capacitance of the capacitor formed between the branch sensing line and the low-potential voltage line increases.

[0131] For example, refer to Figures 3 to 5 When moisture penetrates into the sealed region SA of the second source integrated circuit SDIC2 among the multiple source integrated circuits SDIC1, SDIC2, SDIC3, ..., SDICn, the capacitance of the second capacitor C2 will increase.

[0132] As described above, the nth time constant is calculated using Formula 1, which allows all time constants after the second time constant τ2 to be increased.

[0133] refer to Figure 8 The first time constant τ1 under fault conditions is equal to the first time constant τ1 under normal conditions, so the rise time of the first delayed pulse DP1 remains unchanged.

[0134] Conversely, under fault conditions, the second time constant τ2 increases, causing the rise time of the second delayed pulse DP2 under fault conditions to be delayed more than the rise time of the second delayed pulse DP2.

[0135] Under fault conditions, the third time constant τ3 increases, causing the rise time of the third delayed pulse DP3 under fault conditions to be delayed more than that of the third delayed pulse DP3 under normal conditions.

[0136] Under fault conditions, the nth time constant τ n The increase causes the rise time of the nth delayed pulse DPn in the fault state to be delayed more than the rise time of the nth delayed pulse DPn in the normal state.

[0137] Simultaneously, in the data compensation step S130, a video data signal RGB compensated according to the delay information DS is output. Specifically, in the data compensation step S130, the video data signal RGB allocated to the faulty source integrated circuit is compensated according to the delay information DS. As a compensation method for the video data signal RGB, the average value of the video data signals RGB allocated to the adjacent, non-faulty source integrated circuits is used to compensate the video data signal RGB. However, the compensation method for the video data signal RGB is not limited to this, and various compensation methods can be applied.

[0138] For example, such as Figure 8 As shown, when the second delay pulse DP2 to the nth delay pulse DPn are further delayed, thereby confirming the infiltration of water into the second source integrated circuit SDIC2 through the delay information DS, the video data signal RGB allocated to the second source integrated circuit SDIC2 can be the average of the video data signal RGB allocated to the first source integrated circuit SDIC1 and the video data signal RGB allocated to the third source integrated circuit SDIC3.

[0139] Therefore, the driving method of the display device according to the exemplary aspect of this disclosure can identify faults in the source integrated circuit caused by moisture penetration and compensate the video data signal to resolve the faults caused by moisture penetration.

[0140] Exemplary aspects of this disclosure may also be described as follows:

[0141] According to one aspect of this disclosure, a display device includes: a display panel having a plurality of pixels disposed therein; a timing controller configured to output sensing pulses and video data signals; and a data driver configured to receive sensing pulses and output data voltages to the plurality of pixels according to the video data signals, wherein the data driver includes a plurality of source integrated circuits, each of the plurality of source integrated circuits receiving a plurality of delayed pulses obtained by delaying the sensing pulses, and the timing controller comparing the timing of the plurality of delayed pulses to compensate for the video data signals.

[0142] The data driver may also include a source printed circuit board connected to the plurality of source integrated circuits, in which sensing lines are formed to transmit sensing pulses.

[0143] The sensing lines may include: a main sensing line disposed on the source printed circuit board, and branch sensing lines branching from the main sensing line and connected to each of the plurality of source integrated circuits.

[0144] Each of the multiple branch sensing lines can extend only to the pads formed on the display panel.

[0145] At least one positive power line can be provided on one side of each of the multiple branch sensing lines.

[0146] Each and at least one of the multiple branch sensing lines can be covered by an adhesive component.

[0147] Each of the multiple branch sensing lines and at least one positive power supply line can form multiple capacitors.

[0148] Multiple resistors can be set in the sensing line, and each of the multiple resistors can be set between any source integrated circuit and the timing controller or between multiple source integrated circuits.

[0149] The time constant of the nth delayed pulse received by the nth source integrated circuit in a plurality of source integrated circuits is calculated using Formula 1:

[0150]

[0151] Here, τ n R is the time constant of the nth delayed pulse. i C is the resistance of any one of the multiple resistors. i Let n be the capacitance of any one of the multiple capacitors, where n is a natural number greater than or equal to 1.

[0152] The timing controller may include: a signal generator that generates sensing pulses; a delay detector that analyzes the plurality of delay pulses to output delay information indicating a faulty source integrated circuit; and a data compensator that compensates for the video data signal based on the delay information.

[0153] The delay detector compares the timing of each delay pulse under normal conditions with the timing of each delay pulse under fault conditions to generate delay information indicating the source integrated circuit that has failed.

[0154] The data compensator can compensate for the video data signal allocated to the faulty source integrated circuit by using the average value of the video data signal allocated to the source integrated circuit adjacent to the faulty source integrated circuit, based on the delay information.

[0155] According to another aspect of this disclosure, a driving method for a display device includes: a signal generation step for outputting sensing pulses; a delay detection step for analyzing a plurality of delay pulses to output delay information indicating a faulty source integrated circuit; and a data compensation step for compensating video data signals based on the delay information.

[0156] In the delay detection step, the timing of each delay pulse under normal conditions is compared with the timing of each delay pulse under fault conditions to generate delay information indicating that a fault has occurred in the source integrated circuit.

[0157] In the data compensation step, the average value of the video data signal allocated to the source integrated circuit adjacent to the source integrated circuit that has failed is used to compensate the video data signal allocated to the source integrated circuit that has failed.

[0158] Although exemplary aspects of this disclosure have been described in detail with reference to the accompanying drawings, this disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of this disclosure. Therefore, the exemplary aspects of this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of this disclosure. The scope of the technical concept of this disclosure is not limited thereto. Therefore, it should be understood that the foregoing exemplary aspects are exemplary in all respects and do not limit this disclosure. The scope of this disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be construed as falling within the scope of this disclosure.

Claims

1. A display device, comprising: A display panel having multiple pixels; The timing controller is configured to output sensing pulses and video data signals; and A data driver, configured to receive the sensing pulses and output data voltages to the plurality of pixels according to the video data signal, includes a plurality of source integrated circuits that receive a plurality of delayed pulses from the timing controller. The timing controller compares the timing of each of a plurality of delay pulses in a normal state with the timing of each of a plurality of delay pulses in a fault state to generate delay information indicating a faulty source integrated circuit, and compensates the video data signal based on the delay information.

2. The display device of claim 1, wherein the data driver further comprises a source printed circuit board connected to the plurality of source integrated circuits and sensing lines formed in the source printed circuit board and the plurality of source integrated circuits, and, The sensing pulse is transmitted through the sensing line.

3. The display device according to claim 2, wherein the sensing line comprises: The main sensing line is disposed on the source printed circuit board and the timing controller, and Branch sensing lines branch off from the main sensing line and connect to each of the plurality of source integrated circuits.

4. The display device according to claim 3, wherein each of the plurality of branch sensing lines extends to a pad disposed on the display panel.

5. The display device according to claim 3 further includes at least one positive power supply line disposed at each of the plurality of branch sensing lines.

6. The display device according to claim 5, further comprising an adhesive member covering each of the plurality of branch sensing lines and the at least one positive power line.

7. The display device according to claim 6, wherein each of the plurality of branch sensing lines and the at least one positive power supply line constitute a capacitor.

8. The display device according to claim 7, wherein a plurality of resistors are provided in the sensing line, each of the plurality of resistors being disposed between one of the plurality of source integrated circuits and the timing controller or between the plurality of source integrated circuits.

9. The display device according to claim 8, The time constant of the nth delay pulse of the nth source integrated circuit in the plurality of source integrated circuits is calculated by formula 1: (Official 1), Here, τ n R is the time constant of the nth delayed pulse. i C is the resistance of any one of the multiple resistors. i Let n be the capacitance of any one of the multiple capacitors, where n is a natural number.

10. The display device according to claim 1, wherein the timing controller comprises: A signal generator configured to generate the sensing pulses; A delay detector configured to analyze the plurality of delay pulses to output delay information indicating a faulty source integrated circuit; and A data compensator configured to compensate for video data signals based on the delay information.

11. The display device of claim 10, wherein the data compensator is configured to compensate the video data signal allocated to the faulty source integrated circuit based on delay information, using the average value of the video data signal allocated to the source integrated circuit adjacent to the faulty source integrated circuit.

12. A driving method for a display device, the display device comprising: A display panel having multiple pixels; Time series The controller is configured to output sensing pulses and video data signals; And a data driver, receiving multiple delayed pulses, the driving method includes: The signal generation step for output sensing pulses; A delay detection step that analyzes the multiple delay pulses to output delay information indicating a faulty source integrated circuit; and The data compensation step is to compensate for the video data signal based on the aforementioned delay information. In the delay detection step, the timing of each of the multiple delay pulses under normal conditions is compared with the timing of each of the multiple delay pulses under fault conditions, and delay information indicating that the source integrated circuit has a fault is generated.

13. The driving method of claim 12, wherein in the data compensation step, the video data signal allocated to the faulty source integrated circuit is compensated based on the delay information using the average value of the video data signal allocated to the source integrated circuit adjacent to the faulty source integrated circuit.

14. A display device, comprising: A display panel having multiple pixels; A timing controller is configured to output sensing pulses via a first sensing line to determine moisture penetration in multiple pixels; Multiple source integrated circuits are configured to receive the sensing pulses and output multiple delayed pulses to the timing controller. The timing controller is configured to compare the timing of the plurality of delayed pulses under normal and fault conditions, generate data reflecting moisture penetration, compensate the video data signal based on the generated data reflecting moisture penetration, and output the compensated video signal to the first source integrated circuit via a first feedback line. The plurality of source integrated circuits are configured to output data voltages to the plurality of pixels based on the compensated video data signal.

15. The display device according to claim 14, further comprising a plurality of interconnect films in which the plurality of source integrated circuits are disposed.

16. The display device of claim 15, further comprising a source printed circuit board in which a first sensing line and a first feedback line are disposed.

17. The display device of claim 16, wherein the source printed circuit board forms an RC circuit.

18. The display device of claim 15, wherein the plurality of connecting films connect the display panel and the plurality of source integrated circuits.

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