Semiconductor device and method of forming the same

Abstract

Embodiments in accordance with the present application provide a semiconductor device including a semiconductor device structure including a first dielectric layer. A first plurality of nanostructures is disposed on the first dielectric layer, the first plurality of nanostructures overlapping one another. A first source / drain region is disposed laterally adjacent to a first side of the first plurality of nanostructures. A second dielectric layer is on the first side of the first source / drain region. A front side source / drain contact is disposed on a second side of the first source / drain region opposite the first side, and a backside source / drain contact is disposed on the first side of the first source / drain region. The backside source / drain contact extends through the second dielectric layer. Methods of forming a semiconductor device are also provided in accordance with other embodiments of the present application.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] There is a continuous demand for increasing computing power in electronic devices, including smartphones, tablets, desktop computers, laptops, and many other types of electronic devices. Semiconductor devices provide this computing power. One way to increase computing power in semiconductor devices is to increase the number of transistors and the number of other semiconductor device components that can be included in a given area of ​​a semiconductor substrate.

[0003] Nanostructured transistors can help improve computing power because they can be very small and offer improved functionality compared to conventional transistors. A nanostructured transistor can comprise multiple semiconductor nanostructures (e.g., nanowires, nanosheets, etc.) that act as the channel region of the transistor. A gate electrode can be coupled to the nanostructure. Summary of the Invention

[0004] According to one embodiment of this application, a semiconductor device is provided, comprising: a first dielectric layer; a first plurality of nanostructures on the first dielectric layer, the first plurality of nanostructures overlapping each other; a first source / drain region disposed laterally adjacent to a first side of the first plurality of nanostructures; a second dielectric layer on the first side of the first source / drain region; a front source / drain contact on a second side of the first source / drain region opposite to the first side; and a back source / drain contact on the first side of the first source / drain region, the back source / drain contact extending through the second dielectric layer.

[0005] According to another embodiment of this application, a semiconductor device is provided, comprising: a channel region; a first source / drain region disposed laterally adjacent to a first side of the channel region; a second source / drain region disposed laterally adjacent to a second side of the channel region opposite to the first side; a gate electrode at least partially surrounding the channel region; a dielectric layer on the first side of the first source / drain region; a front source / drain contact on the second side of the first source / drain region opposite to the first side; and a back source / drain contact having a first portion on the first side of the first source / drain region and a second portion on the first portion, the second portion having a wider width than the first portion.

[0006] According to another embodiment of this application, a method for forming a semiconductor device is provided, comprising: forming a channel region of a transistor covering a first dielectric layer; forming a source / drain region laterally adjacent to a first side of the channel region; forming a second dielectric layer on the first side of the source / drain region; forming a front source / drain contact on a second side of the source / drain region opposite to the first side; and forming a back source / drain contact on the first side of the source / drain region, the back source / drain contact extending through the second dielectric layer.

[0007] Embodiments of this application relate to semiconductor devices having front and back source / drain contacts. Attached Figure Description

[0008] When with attachment Figure 1 When reading this document, the best understanding of all aspects of this disclosure can be obtained from the following detailed description. It is worth noting that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be increased or decreased arbitrarily.

[0009] Figure 1 This is a perspective view of a semiconductor device according to some embodiments.

[0010] Figures 2A-2P These are cross-sectional and perspective views of semiconductor devices at different processing stages according to some embodiments.

[0011] Figure 3A This is a cross-sectional view of a semiconductor device according to some embodiments.

[0012] Figure 3B This is an illustration based on some embodiments. Figure 3A A cross-sectional view of the magnified region of the semiconductor device shown, and Figure 3C This is an illustration based on some embodiments. Figure 3B A cross-sectional view of an additional component of the semiconductor device shown.

[0013] Figure 4 This is a perspective view of a semiconductor device according to some embodiments.

[0014] Figure 5 This is a cross-sectional view showing a portion of a semiconductor device according to some embodiments.

[0015] Figure 6 This is a cross-sectional view showing a portion of a semiconductor device according to some embodiments. Detailed Implementation

[0016] In the following description, numerous thicknesses and materials are described for various layers and structures within a semiconductor device die. Specific dimensions and materials are given by way of example for each embodiment. Those skilled in the art will recognize that other dimensions and materials may be used in many cases without departing from the scope of this disclosure.

[0017] The following disclosure provides numerous different embodiments or instances of various components for implementing the described subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0019] In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the present disclosure. However, those skilled in the art will understand that the present disclosure can be practiced without these specific details. In other instances, well-known structures related to electronic components and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the description of embodiments of the present disclosure.

[0020] Unless the context otherwise requires, the word “comprising” and its variations, such as “including” and “comprise”, in the following description and claims shall be interpreted in an open, inclusive sense, meaning “including, but not limited to”.

[0021] The use of ordinal numbers such as first, second, and third does not necessarily imply a sense of order, but may simply distinguish multiple instances of behavior or structure.

[0022] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular component, structure, or feature described in connection with that embodiment is included in at least some of the embodiments. Therefore, the phrases "in one embodiment," "in an embodiment," or "in some embodiments" appearing in various places throughout the specification do not necessarily refer to the same embodiment. Furthermore, particular components, structures, or features may be combined in any suitable manner in one or more embodiments.

[0023] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural indicators unless otherwise expressly provided. It should also be noted that, unless otherwise expressly provided, the term “or” is generally used to mean “and / or.”

[0024] Embodiments of this disclosure provide a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including a back-side self-aligned source / drain contact that completely falls on or contacts an epitaxial source / drain region. A sacrificial dielectric structure or layer is formed on the gate region or a metal gate electrode, and during the formation of the back-side source / drain contact, the sacrificial dielectric structure protects against or otherwise reduces or prevents damage to the gate region, for example, during an etching process that may be used to form the back-side source / drain contact. As part of the process for forming the back-side source / drain contact, including the sacrificial dielectric structure is advantageous for enlarging the patterned window or opening formed in a hard mask or other layer, because an etching process that selectively removes the underlying portion of the semiconductor region can be employed while retaining the sacrificial dielectric structure.

[0025] Figure 1 This is a schematic diagram illustrating a semiconductor device 100 according to some embodiments.

[0026] Semiconductor device 100 includes a plurality of transistors 104 which can be formed on various structures. As described in more detail below, semiconductor device 100 includes back-side self-aligned source / drain contacts that completely fall on or contact epitaxial source / drain regions. Device 100 includes a sacrificial dielectric structure or layer formed on the gate region or metal gate electrode, and during the formation of the back-side source / drain contacts, the sacrificial dielectric structure protects or otherwise reduces or prevents damage to the gate region, for example, during an etching process that may be used to form the back-side source / drain contacts. As part of the process for forming the back-side source / drain contacts, including the sacrificial dielectric structure is advantageous for enlarging the patterned window or opening formed in a hard mask or other layers, because an etching process that selectively removes the underlying portion of the semiconductor region while retaining the sacrificial dielectric structure can be employed.

[0027] By introducing a sacrificial dielectric structure on the back side of device 100 to facilitate an enlarged patterned window or opening, back-side source / drain contacts can be formed through the enlarged window or opening. This advantageously facilitates the formation of back-side source / drain contacts in a self-aligned manner, ensuring that the patterned window or opening fully falls on or contacts the epitaxial source / drain region even if it is offset relative to the desired position. For example, the patterned window or opening can be formed slightly offset relative to the desired position due to the overlay offset of the photolithography process or tooling used to form the back-side source / drain contacts; however, the enlarged patterned window or opening can have a sufficiently enlarged size to fully expose the upper surface of the semiconductor region covering the epitaxial source / drain region. Therefore, the semiconductor region can be removed through the enlarged patterned window or opening, and the back-side source / drain contacts can be formed to fully contact or fall on the epitaxial source / drain region. Thus, semiconductor device 100 can be formed with a larger overlay offset tolerance than devices without a sacrificial dielectric structure, because such devices could be damaged during the formation of back-side source / drain contacts without very precise photolithographic overlay control. More specifically, overlay offset during the formation of back source / drain contacts in devices that do not include sacrificial dielectric structures can damage underlying structures such as gate electrodes or gate spacers, as such underlying structures may be undesirably exposed and the back source / drain contacts are formed in contact with these structures due to the overlay offset.

[0028] Transistor 104 includes a gate electrode 216 which can be formed of any suitable conductive material. In some embodiments, the gate electrode 216 is formed of one or more of titanium (Ti), titanium nitride (TiN), or tungsten (W), and in some embodiments, the gate electrode 216 may include one or more dopant materials such as lanthanum (La), zirconium (Zr), or hafnium (Hf).

[0029] In some embodiments, a gate dielectric is disposed on the gate electrode 216 and may surround (e.g., surround at least four sides) portions of the gate electrode 216 disposed between the nanostructures 118 of each transistor. In various embodiments, the gate dielectric may be formed of a single layer or multiple dielectric layers.

[0030] In some embodiments, each of the plurality of transistors 104 is a nanostructure transistor. In such an embodiment, the channel region of each transistor 104 includes a plurality of semiconductor nanostructures 118 extending between the source / drain regions 194 of the transistor 104.

[0031] The semiconductor nanostructure 118 may include nanosheets, nanowires, or other types of nanostructures. The semiconductor nanostructure 118 forms the channel region of each transistor 104. Other types of transistors may be used without departing from the scope of this disclosure. The number of semiconductor nanostructures 118 included in the channel region of each transistor may vary in various embodiments. In some embodiments, the channel region of each transistor 104 may include one or more semiconductor nanostructures 118. In some embodiments, the channel region of each transistor 104 may include one to five or more semiconductor nanostructures 118. The channel regions of each transistor 104 may be stacked and arranged such that the nanostructures 118 are substantially vertically aligned and overlap each other.

[0032] In some embodiments, the semiconductor device 100 includes a dielectric layer 160, and a semiconductor nanostructure 118 may be formed on the dielectric layer 160. A pad layer 320 may be disposed over the stack of the semiconductor nanostructure 118, and a sacrificial dielectric layer 318 is disposed on the pad layer 320. A front source / drain contact 220 is formed on one side (e.g., the underside) of the source / drain region 194, and a back source / drain contact 340 is formed on the opposite side of the source / drain region 194. In some embodiments, the back source / drain contact 340 may extend through the sacrificial dielectric layer 318 and the pad layer 320.

[0033] As will be described in further detail herein, the sacrificial dielectric layer 318 can be retained during an etching process, for example, to form the back source / drain contacts 340 as part of the process of forming the back source / drain contacts, thereby enlarging the patterned window or opening in the hard mask or other layers, since an etching process can be employed that selectively removes the portion below the semiconductor region 308 while at least partially retaining the sacrificial dielectric layer 318.

[0034] Figures 2A-2P This is a cross-sectional view of a semiconductor device 100 at different processing stages according to some embodiments. Figures 2A-2P An exemplary process for producing semiconductor devices including nanostructured transistors is shown. Figures 2A-2P The principles of this disclosure illustrate how to fabricate these transistors using a simple and efficient process. Other process steps and combinations thereof may be used without departing from the scope of this disclosure. Nanostructured transistors may include all-ring gate transistors, multi-bridge transistors, nanosheet transistors, nanowire transistors, or other types of nanostructured transistors.

[0035] Nanostructured transistor structures can be patterned using any suitable method. For example, structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure structure.

[0036] like Figure 2A As shown, semiconductor device 100 includes semiconductor substrate 102. In some embodiments, substrate 102 includes a semiconductor material. The semiconductor material may include a single-crystal semiconductor layer at least on a surface portion. Substrate 102 may include single-crystal semiconductor materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In the exemplary process described herein, substrate 102 includes Si, but other semiconductor materials may be used without departing from the scope of this disclosure.

[0037] Substrate 102 may include one or more buffer layers (not shown) in its surface regions. The buffer layers can be used to gradually change the lattice constant from the substrate to the source / drain regions. The buffer layers may be formed from epitaxially grown single-crystal semiconductor materials, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. Substrate 102 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). Dopants may include, for example, boron (BF2) for n-type transistors and phosphorus for p-type transistors.

[0038] A plurality of semiconductor layers 118 are formed on substrate 102. Semiconductor layers 118 are layers of semiconductor material. Semiconductor layers 118 correspond to the channel regions of a full-ring gate transistor and will be produced by the processes described herein. Semiconductor layers 118 may be formed above substrate 102. In various embodiments, semiconductor layers 118 may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In some embodiments, semiconductor layers 118 are formed of the same semiconductor material as substrate 102. Other semiconductor materials may be used for semiconductor layers 118 without departing from the scope of this disclosure. In some embodiments, semiconductor layers 118 are silicon layers and substrate 102 is a silicon substrate.

[0039] Multiple sacrificial semiconductor layers 120 are formed between semiconductor layers 118. In some embodiments, the sacrificial semiconductor layers 120 comprise a semiconductor material different from that of semiconductor layers 118. In instances where semiconductor layers 118 comprise silicon, the sacrificial semiconductor layer 120 may comprise SiGe. In one instance, the silicon-germanium sacrificial semiconductor layer 120 may comprise between 5% and 10% germanium, and in some embodiments may comprise between 20% and 30% germanium, but other concentrations of germanium may be used without departing from the scope of this disclosure.

[0040] In some embodiments, semiconductor layer 118 and sacrificial semiconductor layer 120 are formed from semiconductor substrate 102 using alternating epitaxial growth processes. For example, a first epitaxial growth process may result in the formation of a lowest sacrificial semiconductor layer 120 on the top surface of substrate 102. A second epitaxial growth process may result in the formation of a lowest semiconductor layer 118 on the top surface of the lowest sacrificial semiconductor layer 120. A third epitaxial growth process may result in the formation of a second lowest sacrificial semiconductor layer 120 on top of the lowest semiconductor layer 118. Alternating epitaxial growth processes are performed until a selected number of semiconductor layers 118 and sacrificial semiconductor layers 120 have been formed.

[0041] In some embodiments, the vertical thickness of semiconductor layer 118 can be between 2 nm and 15 nm. Similarly, in some embodiments, the vertical thickness of sacrificial semiconductor layer 120 can be between 5 nm and 15 nm. Other thicknesses and materials may be used for semiconductor layer 118 and sacrificial semiconductor layer 120 without departing from the scope of this disclosure.

[0042] As will be explained in more detail below, the sacrificial semiconductor layer 120 will be patterned to form a semiconductor nanostructure for the all-around gate transistor. The semiconductor nanostructure will correspond to the channel region of the all-around gate transistor.

[0043] In one embodiment, the sacrificial semiconductor layer 120 corresponds to a first sacrificial epitaxial semiconductor region having a first semiconductor composition. In subsequent steps, the sacrificial semiconductor layer 120 is removed and replaced with other materials and structures. For this reason, the semiconductor layer 120 is described as sacrificial.

[0044] In some embodiments, the oxide layer 117 may be formed on the topmost layer of the semiconductor layer 118, for example, as shown in the figure. Figure 2A As shown. However, it should be noted that in some embodiments, oxide layer 117 is not formed, or may instead be another semiconductor layer 118 in a stack of semiconductor layers. According to various embodiments, any number of semiconductor layers 118 may be formed. In some embodiments, oxide layer 117 may be formed of any oxide material. In some embodiments, oxide layer 117 comprises silicon oxide. Oxide layer 117 may have any suitable thickness. In some embodiments, the thickness of oxide layer 117 is less than 50 nm. In some embodiments, the thickness of oxide layer 117 is less than 20 nm. In some embodiments, the thickness of oxide layer 117 is between 1 nm and 5 nm.

[0045] An upper semiconductor layer 119 is formed on an oxide layer 117. The upper semiconductor layer 119 can be formed of any suitable semiconductor material. In some embodiments, the upper semiconductor layer 119 is formed of the same material as the semiconductor layer 118 or the substrate 102. Other semiconductor materials can be used for the upper semiconductor layer 119 without departing from the scope of this disclosure. In some embodiments, the upper semiconductor layer 119, the semiconductor layer 118, and the substrate 102 are formed of silicon.

[0046] like Figure 2B As shown, the trench 121 is formed in Figure 2A In the illustrated structure, more specifically, trench 121 is formed to extend through the upper semiconductor layer 119, oxide layer 117, semiconductor layer 118, and sacrificial semiconductor layer 120, and at least partially into the substrate 102. Trench 121 can be formed by any suitable technique, including, for example, by patterning and etching trenches. In some embodiments, trench 121 can be formed by depositing a hard mask layer (not shown) on the upper semiconductor layer 121 and patterning and etching the hard mask using standard photolithography processes. The hard mask layer can include one or more of aluminum, Al2O3, SiN, or other suitable materials. In some embodiments, the hard mask layer can have a thickness between 5 nm and 50 nm. The hard mask layer can be deposited using PVD, ALD, CVD, or other suitable deposition processes. The hard mask layer can have other thicknesses, materials, and deposition processes without departing from the scope of this disclosure.

[0047] After the hard mask layer has been patterned and etched, the upper semiconductor layer 119, oxide layer 117, semiconductor layer 118, sacrificial semiconductor layer 120, and substrate 102 can be etched at locations not covered by the hard mask layer. The etching process results in the formation of trench 121. The etching process may include multiple etching steps. For example, a first etching step may be performed to etch the upper semiconductor layer 119. A second etching step may be performed to etch the oxide layer 117. A third etching step may be performed to etch the top semiconductor layer 118, and a fourth etching step may be performed to etch the top sacrificial semiconductor layer 120. The etching steps may be performed alternately until the upper semiconductor layer 119, oxide layer 117, semiconductor layer 118, sacrificial semiconductor layer 120, and substrate 102 are properly etched in the exposed areas. In other embodiments, trench 121 may be formed in a single etching process.

[0048] Trench 121 defines a plurality of fins 124, each fin 124 including a corresponding portion of an upper semiconductor layer 119, an oxide layer 117, a semiconductor layer 118, and a sacrificial semiconductor layer 120. Each fin 124 corresponds to an individual full-ring gate transistor, which will ultimately be generated by further processing steps described herein. In particular, the semiconductor layer 118 in each column or stack will correspond to the channel region of a particular full-ring gate nanosheet transistor.

[0049] although Figure 2B Three fins 124 are shown, but it will be readily understood that in various embodiments, fewer or more than three fins 124 may be formed in the semiconductor device 100.

[0050] like Figure 2B As shown, a shallow trench isolation structure 126 is formed in the trench 121. The shallow trench isolation structure 126 can be formed by any suitable technique. In some embodiments, the shallow trench isolation structure 126 can be formed by depositing a dielectric material in the trench 121 and by recessing the deposited dielectric material such that the top surface of the dielectric material is below the level of the lowest sacrificial semiconductor layer 120. For example, the hard mask can be removed after the shallow trench isolation structure 126 is formed.

[0051] The shallow trench isolation structure 126 can be used to isolate individual transistors or groups of transistors formed in conjunction with the semiconductor substrate 102. The dielectric material used for the shallow trench isolation structure 126 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material, formed by LPCVD (low-pressure chemical vapor deposition), plasma-enhanced CVD, or flowable CVD. Other materials and structures may be used for the shallow trench isolation structure 126 without departing from the scope of this disclosure.

[0052] like Figure 2CAs shown, a polysilicon layer 138 has been formed on the top surface of the upper semiconductor layer 119 and the shallow trench isolation structure 126. Furthermore, the polysilicon layer 138 may extend at least partially into the trench and contact the side surfaces of the upper semiconductor layer 119, oxide layer 117, semiconductor layer 118, and sacrificial semiconductor layer 120. In some embodiments, the polysilicon layer 138 may have a thickness between 20 nm and 100 nm. The polysilicon layer 138 may be formed by any suitable technique, including, for example, by deposition, epitaxial growth, CVD processes, physical vapor deposition (PVD) processes, or ALD processes. Other thicknesses and processes may be used to form the polysilicon layer 138 without departing from the scope of this disclosure.

[0053] A dielectric layer 140 is formed on a polysilicon layer 138, and a dielectric layer 142 is formed on the dielectric layer 140. In one example, the dielectric layer 142 comprises silicon nitride. In another example, the dielectric layer 140 comprises silicon oxide. In some embodiments, the dielectric layers 140 and 142 can be deposited by CVD. In some embodiments, the dielectric layer 140 may have a thickness between 5 nm and 15 nm. In some embodiments, the dielectric layer 142 may have a thickness between 15 nm and 50 nm. Other thicknesses, materials, and deposition processes may be used for the dielectric layers 140 and 142 without departing from the scope of this disclosure.

[0054] In some embodiments, dielectric layers 140 and 142 may be patterned and etched to form a hard mask for the polysilicon layer 138. Dielectric layers 140 and 142 may be patterned and etched, for example, using standard photolithography processes. After dielectric layers 140 and 142 have been patterned and etched to form a hard mask, the polysilicon layer 138 may be etched such that only the portion of the polysilicon layer 138 directly beneath dielectric layers 140 and 142 remains.

[0055] In some embodiments, a thin dielectric layer 143 may be formed, for example, by deposition or any other suitable technique prior to the formation of the polysilicon layer 138. In such embodiments, the thin dielectric layer 143 may be formed on the top surface of the upper semiconductor layer 119 and the shallow trench isolation structure 126, and the thin dielectric layer 143 may extend at least partially into the trench and contact the side surfaces of the upper semiconductor layer 119, the oxide layer 117, the semiconductor layer 118, and the sacrificial semiconductor layer 120. In some embodiments, the thin dielectric layer 143 may have a thickness between 1 nm and 5 nm. In some embodiments, the thin dielectric layer 143 may comprise or be formed of silicon oxide. Other materials, deposition processes, and thicknesses may be used for the thin dielectric layer 143 without departing from the scope of this disclosure.

[0056] like Figure 2D As shown, in relation to Figure 2CThe illustrated process produces a spacer 174 formed on the structure of a semiconductor device 100. The spacer 174 may comprise one or more layers, such as dielectric layers, and may be formed by any suitable technique, such as deposition. The spacer 174 may be formed on and in contact with the upper surface of dielectric layer 142, and may be formed on the side surfaces of each of dielectric layer 142, dielectric layer 140, polysilicon layer 138, and thin dielectric layer 143. Furthermore, the spacer 174 may extend on the upper surface of upper semiconductor layer 119 and on the side surfaces of upper semiconductor layer 119, oxide layer 117, semiconductor layer 118, and sacrificial semiconductor layer 118 in trench 124. In some embodiments, the spacer 174 contacts the upper surface of shallow trench isolation structure 126 in trench 124.

[0057] Spacer 174 can be formed of any suitable dielectric material. In some embodiments, spacer 174 is formed of a silicon-based low-k dielectric material. In some embodiments, spacer 174 comprises silicon (Si), oxygen (O), carbon (C), and nitrogen (N). In some embodiments, spacer 174 is a silicon carbonitride oxynitride (SiOCN) layer. In some embodiments, spacer 174 can be deposited by CVD, ALD, or other suitable processes. Other materials and processes can be used for spacer 174 without departing from the scope of this disclosure.

[0058] In some embodiments, spacer 174 may have a thickness of less than 50 nm. In some embodiments, spacer 174 has a thickness of less than 30 nm. In some embodiments, spacer 174 has a thickness of less than 10 nm. In some embodiments, spacer 174 has a thickness between 1 nm and 5 nm.

[0059] like Figure 2E As shown, a source / drain trench 302 is formed in the semiconductor device 100. The source / drain trench 302 can be formed by any suitable technique, and in some embodiments, it is formed by removing portions of one or more of the separator 174, semiconductor layer 118, semiconductor layer 119, sacrificial semiconductor layer 120, or substrate 102. For example, portions of these layers and structures can be removed by one or more etching processes or any suitable technique, including, for example, using dielectric layers 140 and 142 as hard masks for etching the respective layers.

[0060] In some embodiments, the shallow trench isolation structure 126 may include a protrusion 304, which may be formed by any suitable technique. In some embodiments, the protrusion 304 is a protruding portion of the shallow trench isolation structure 126, which may be caused by the formation of source / drain recesses 302, such as, for example, at or near the interface of spacer 174 with the interface of alternating stacks of semiconductor layers 118, semiconductor layers 119, and sacrificial semiconductor layers 120 at different etch rates or directions. In at least one embodiment, the protrusion 304 is present because the spacer 174 is located on top of the shallow trench isolation 126. The presence of the spacer 174 at the top of the shallow trench isolation 126 isolates a portion of the shallow trench isolation structure 126 such that, after strained source / drain and shallow trench isolation etching, the portion of the shallow trench isolation structure 126 below the spacer 174 is retained. In some embodiments, more than one processing step may be used to form the protrusion 304. In some embodiments, the protrusion 304 is not formed. For example, the shallow trench isolation structure 126 may have a smooth or substantially flat surface.

[0061] like Figure 2E As shown, in some embodiments, device 100 may include a buried semiconductor layer 306, which may be on or within substrate 102. For example, in some embodiments, substrate 102 may include the buried semiconductor layer 306 as a region extending between portions of substrate 102 (e.g., between upper and lower layers of substrate 102). In some embodiments, the buried semiconductor layer 306 is formed of a semiconductor material different from the semiconductor material of substrate 102. For example, in some embodiments, semiconductor substrate 102 may be a silicon substrate, and buried semiconductor layer 306 may be a SiGe layer disposed between upper and lower layers of silicon substrate 102.

[0062] like Figure 2F As shown, an internal spacer 192 is formed on the lateral side surface of the sacrificial semiconductor layer 120 and between the semiconductor layers 118. The internal spacer 192 can be formed by any suitable technique. In some embodiments, the side surface of the sacrificial semiconductor layer 120 is laterally recessed, for example, by an etching process that selectively removes the lateral side portions of the sacrificial semiconductor layer 120 to form a lateral recess in the sacrificial semiconductor layer 120 while retaining the lateral side edges of the semiconductor layer 118. An internal spacer dielectric layer can then be formed on the recessed side surface of the sacrificial semiconductor layer 120 and the side surface of the semiconductor layer 118. The internal spacer dielectric layer can then be removed from the side surface of the semiconductor layer 118, with a portion of the internal spacer dielectric layer remaining in the lateral recess, thereby forming the internal spacer 192. The internal spacer dielectric layer can be removed by any suitable technique, for example, by an etching process that selectively etches the internal spacer dielectric layer.

[0063] The internal spacer 192 can be formed of any suitable material. In some embodiments, the internal spacer 192 is formed of a dielectric material. In some embodiments, the internal spacer 192 comprises silicon nitride.

[0064] like Figure 2G As shown, a semiconductor region 308 can be formed on a substrate 102. The semiconductor region 308 can be formed using any suitable technique, including, for example, epitaxial growth or deposition of a semiconductor material. The semiconductor region 308 can be formed of a semiconductor material different from that of the substrate 102. In some embodiments, the semiconductor region 308 is a SiGe region or layer formed on the substrate 102, which can be a silicon substrate. In some embodiments, the semiconductor region 308 may include between 5% and 10% germanium, and in some embodiments may include between 20% and 30% germanium, but other concentrations of germanium may be used without departing from the scope of this disclosure. In some embodiments, the semiconductor region 308 is formed of the same material as the buried semiconductor layer 306. In some embodiments, the semiconductor region 308 has a thickness in the range of 5 nm to 30 nm.

[0065] In some embodiments, the semiconductor region 308 may be formed at least partially within the source / drain recess 302.

[0066] As will be described in more detail later herein, semiconductor region 308 can improve etch selectivity in one or more subsequent processes. For example, semiconductor region 308 can be more easily removed by etchant than the surrounding portion of sacrificial dielectric layer 318, thus substantially or completely exposing the upper surface of the underlying source / drain region 194, allowing the back-side source / drain contact 340 to be formed entirely over the source / drain region 194. Furthermore, the height of the back-side source / drain contact 340 can be based on or otherwise related to the height of semiconductor region 308. Therefore, semiconductor region 308 can be formed with a specific height desired based on design considerations of the desired height of the back-side source / drain contact 340.

[0067] like Figure 2H As shown, a dielectric layer 310 can be formed on device 100. The dielectric layer 310 can be formed by any suitable technique. In some embodiments, the dielectric layer 310 is formed by one or more of deposition, etching, masking, or any photolithography process. The dielectric layer can be formed on the upper surface of the shallow trench isolation structure 126 and on the semiconductor region 308.

[0068] The dielectric layer 310 can be formed of any suitable dielectric material. In some embodiments, the dielectric layer 310 includes one or more of SiO, AlO, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, SiN, SiOCN, or SiCN. Other materials may be used without departing from the scope of this disclosure. In some embodiments, the dielectric layer 310 has a thickness in the range of 1 nm to 10 nm.

[0069] The dielectric layer 310 may advantageously insulate, isolate, or otherwise protect the source / drain regions of the device 100, which are subsequently formed. For example, the dielectric layer 310 may be an insulating layer that serves as a barrier layer between portions of the source / drain regions and other layers or materials, such as semiconductor regions 308 and internal spacers 192. In some embodiments, the dielectric layer 310 contacts one or more internal spacers 192. In some embodiments, the upper surface of the dielectric layer 310 is coplanar or substantially coplanar with the corresponding upper surface of the internal spacer 192, wherein the dielectric layer 310 contacts the internal spacer 192.

[0070] like Figure 2I As shown, a source / drain region 194 is formed on the semiconductor region 308. In some embodiments, the source / drain region 194 contacts the semiconductor region 308 and can be directly disposed on the semiconductor region 308. In some embodiments, for example, in the case of including a dielectric layer 310, the source / drain region 194 can be separated from the semiconductor region 308 through the dielectric layer 310.

[0071] The source / drain region 194 comprises a semiconductor material. In some embodiments, the source / drain region 194 may be epitaxially grown, for example, from the semiconductor layer 118 or the substrate 102. In embodiments where a dielectric layer 310 is provided and the source / drain region 194 is epitaxially grown from the semiconductor layer 118, since the epitaxially grown source / drain region 194 is formed by a lateral merging process, voids 193 may be formed in the source / drain region 194, for example, at the bottom of the source / drain region 194. In the case of an N-type transistor, the source / drain region 194 may be doped with an N-type dopant. In the case of a P-type transistor, the source / drain region 194 may be doped with a P-type dopant. Doping can be performed in situ during epitaxial growth.

[0072] The source / drain region 194 can extend and contact between the side surfaces of the semiconductor layer 118 of the adjacent stack of semiconductor nanostructures, and the adjacent stack of semiconductor nanostructures can form the channel region of the corresponding transistor.

[0073] like Figure 2JAs shown, substrate 102, buried semiconductor layer 306, semiconductor region 308, shallow trench isolation structure 126, and dielectric layer 310 can be applied to Figure 2J The structure may be at least partially removed by any suitable technique on the back or underside, including, for example, chemical mechanical polishing. However, the embodiments are not limited thereto, and in various embodiments, one or more etching processes, one or more cutting or excision processes, or any other suitable process may be used to at least partially remove the individual components or layers.

[0074] In some embodiments, for example, an isolation structure 226 is formed over dielectric layer 310, and shallow trench isolation structure 126 is substantially or completely removed.

[0075] In some embodiments, a dielectric layer 312 is formed on the shallow trench isolation structure 126, and an isolation structure 226 is formed on the dielectric layer. The shallow trench isolation structure 126 can be removed. The dielectric layer 312 can be formed of any suitable material. In some embodiments, the dielectric layer 312 is a contact etch stop layer (CESL).

[0076] like Figure 2J As shown, a portion of dielectric layer 310 can be removed. For example, dielectric layer 310 can be removed so that only a portion of dielectric layer 310 on semiconductor region 308 remains.

[0077] In addition, such as Figure 2J As shown, a portion of the spacer 174 is removed, as well as the corresponding material disposed between the spacers 174. In some embodiments, the portion of the spacer 174 and the corresponding material disposed between the spacers 174 are removed by a cutting process, which may include one or more of dry etching, wet etching, and chemical mechanical planarization (CMP).

[0078] In some embodiments, the polysilicon layer 138, dielectric layer 140, dielectric layer 142, dielectric layer 143, oxide layer 117, and upper semiconductor layer 119 are removed. Additionally, the sacrificial semiconductor layer 120 may be removed. The sacrificial semiconductor layer 120 may be removed using an etching process that selectively etches the material relative to the semiconductor layer 118. After the etching process, the semiconductor layer 118 is no longer covered by the sacrificial semiconductor structure.

[0079] like Figure 2JAs shown, a gate electrode 216 is formed. In some embodiments, a gate structure may be formed, including the gate electrode 216 and one or more gate dielectric layers. For example, in some embodiments, a gate dielectric 214 is formed on an exposed surface of the semiconductor layer 118. The gate dielectric 214 is shown as a single layer. However, in practice, the gate dielectric 214 may include multiple dielectric layers. For example, the gate dielectric 214 may include an interface dielectric layer in direct contact with the semiconductor layer 118. The gate dielectric 214 may include a high-k gate dielectric layer located on the interface dielectric layer. The interface dielectric layer and the high-k gate dielectric layer together form the gate dielectric 214 of a transistor for the semiconductor device 100.

[0080] The interface dielectric layer may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interface dielectric layer may include a relatively low-k dielectric relative to a high-k dielectric, such as hafnium oxide or other high-k dielectric materials that can be used in the gate dielectric of a transistor.

[0081] The interface dielectric layer can be formed by thermal oxidation, chemical vapor deposition (CVD), or atomic layer deposition (ALD). In some embodiments, the interface dielectric layer can have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses can be used for the interface dielectric layer without departing from the scope of this disclosure.

[0082] The high-k gate dielectric layer and the interface dielectric layer physically separate the semiconductor layer 118 from the gate metal that will be deposited in subsequent steps. The high-k gate dielectric layer and the interface dielectric layer isolate the gate metal from the semiconductor layer 118 corresponding to the channel region of the transistor.

[0083] The high-k gate dielectric layer comprises one or more dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The high-k gate dielectric layer can be formed by CVD, ALD, or any suitable method. In one embodiment, the high-k gate dielectric layer is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer with a uniform thickness is formed around each semiconductor layer 118. In one embodiment, the thickness of the high-k dielectric is in the range of about 1 nm to about 3 nm. Other thicknesses, deposition processes, and materials may be used for the high-k gate dielectric layer without departing from the scope of this disclosure. The high-k gate dielectric layer may include a first layer comprising HfO2 with dipole doping, the dipole doping including La and Mg, and a second layer comprising a crystalline high-k ZrO layer.

[0084] After forming, for example, a gate dielectric 214, a gate metal is deposited. The gate metal forms a gate electrode 216 around the semiconductor nanostructure or layer 118. In some embodiments, the gate metal is in contact with the gate dielectric 214. The gate metal is located between the semiconductor layers 118. In other words, the gate metal is located around the semiconductor nanostructure or layer 118. For this purpose, the transistor of the semiconductor device 100, such as the first transistor 104 formed in relation to the semiconductor nanostructure 118, is referred to as a full-ring gate transistor.

[0085] Although gate electrodes 216 are shown as single metal layers, in practice, each gate electrode 216 may comprise multiple metal layers. For example, gate electrode 216 may comprise one or more very thin work function layers in contact with gate dielectric 214. The thin work function layers may comprise titanium nitride, tantalum nitride, or other conductive materials suitable for providing a selected work function to the transistor. Gate electrode 216 may also comprise a gate fill material corresponding to the majority of gate electrode 216. The gate fill material may comprise cobalt, tungsten, aluminum, or other suitable conductive materials. The layers of gate electrode 216 may be deposited by PVD, ALD, CVD, or other suitable deposition processes. In some embodiments, gate electrode 216 is formed of one or more of titanium (Ti), titanium nitride (TiN), or tungsten (W), and in some embodiments, gate electrode 216 may comprise one or more dopant materials, such as lanthanum (La), zirconium (Zr), or hafnium (Hf).

[0086] In some embodiments, a dielectric pad layer 212 may be formed on or adjacent to an exposed top portion of, for example, the gate electrode 216. In some embodiments, a dielectric cap layer 218 is formed on the gate electrode 216 or on the dielectric pad layer. Furthermore, in some embodiments, the dielectric cap layer 218 may be formed on one or more portions of the source / drain region 194. The dielectric cap layer 218 may comprise silicon oxide or other suitable dielectric material. The dielectric cap layer 218 may comprise a plurality of dielectric strips that generally extend in the same direction and are substantially parallel to each other. The dielectric strips may extend over the gate electrode 216, the source / drain region 194, and other structures of the device 100.

[0087] In some embodiments, a silicide layer may be formed on the top surface of the source / drain region 194. The silicide layer may include titanium silicide, aluminum silicide, nickel silicide, tungsten silicide, or other suitable silicides.

[0088] In addition, such as Figure 2JAs shown, a front-side source / drain contact 220 is formed on the source / drain region 194, and in some embodiments, the front-side source / drain contact 220 may be formed on any silicide layer that may be present on the source / drain region 194. The source / drain contact 220 may include a conductive material, such as tungsten, titanium, aluminum, tantalum, or other suitable conductive materials.

[0089] An isolation structure, such as a dielectric breakdown 223, can be selectively inserted into the source / drain contacts 220 to isolate some transistors from other transistors. The dielectric breakdown 223 may include an oxide such as silicon oxide, a nitride such as silicon nitride, or other dielectric materials. In some embodiments, the dielectric breakdown 223 is formed over one or more of the isolation structures 226.

[0090] In some embodiments, one or more dielectric layers are formed on one side or surface of the device 100, such as on the upper surface of the gate electrode 216, the dielectric breakdown 223, and the source / drain contact 220, as shown below. Figure 2J As shown. In some embodiments, dielectric layer 160 comprises silicon oxide. However, dielectric layer 160 may comprise silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or other dielectric materials without departing from the scope of this disclosure. In some embodiments, dielectric layer 160 is a multilayer comprising a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer may be formed of different materials, such as silicon oxide and silicon nitride.

[0091] In some embodiments, dielectric layer 160 may be a hard mask layer.

[0092] like Figure 2K As shown, device 100 can be flipped such that the back surface 311 of device 100 is oriented upwards as shown, while the front surface 313 of the device is oriented downwards. As part of a thinning process, device 100 can be flipped, wherein the back surface 311 of the device is thinned, for example, by removing one or more components at the back surface 311 of the device using any suitable thinning technique, including, for example, chemical mechanical polishing. For example, as referenced above... Figure 2J The substrate 102, buried semiconductor layer 306, semiconductor region 308, shallow trench isolation structure 126, and dielectric layer 310 can be at least partially removed by any suitable technique, including, for example, by chemical mechanical polishing, which can be performed after the device 100 has been flipped, for example after the front-side source / drain contacts 220 have been formed, as per [reference to...]. Figure 2J As described. In some embodiments, device 100 as Figure 2K The image is flipped as a representation of... Figure 2JThe parts shown and described are the parts to be removed or the parts to be removed regarding Figure 2J This can be performed as part of a thinning process before the components shown and described.

[0093] like Figure 2L As shown, a recess 316 is formed at the back surface 311 of device 100. The recess 316 can be formed, for example, by removing a portion of the substrate 102 disposed between adjacent semiconductor regions 308. The recess 316 can be formed by any suitable technique, any suitable technique may include one or more patterning, etching, deposition or photolithography processes.

[0094] In some embodiments, an etching process is performed to form the groove 316. The etching process may include forming or using one or more hard mask layers or photoresist layers, which may be patterned by selective etching and removal of portions of the substrate 10 to form the groove 316.

[0095] In some embodiments, the groove 316 is formed by removing portions of the substrate 102 through an etching process. In some embodiments, the etching process is an isotropic process in which the etchant flow rate is provided in the range of 5 sccm to 200 sccm. In some embodiments, the etching process is performed in a chamber having a chamber pressure in the range of 1-100 mTorr and a plasma power in the range of 50-250 W. In various embodiments, the pre-cleaning gas or etching gas may be one or more of H2, CHF3, CH3F, CF4, Cl2 or other gases or mixtures thereof. These etching parameters can advantageously facilitate the selective removal of portions of the substrate 102 while retaining portions of adjacent components, such as portions of the semiconductor region 308. In some embodiments, one or more parameters of the etching process, such as the etchant gas chemistry, may be selected to produce high etch selectivity between the substrate 102 and the semiconductor region 308. For example, an etchant gas or other etching parameters may be used that selectively removes material (e.g., silicon) from the substrate 102 while retaining or otherwise inactively removing material (e.g., SiGe) from the semiconductor region 308.

[0096] In some embodiments, the remaining portion 171 of the substrate 102 may be retained at the bottom of the recess 316, for example, above the gate electrode 216. In some embodiments, the remaining portion 171 may have a thickness between 0.5 nm and 20 nm. In some embodiments, the remaining portion 171 has a thickness of less than 0.5 nm, and in other embodiments, layer 171 is absent.

[0097] like Figure 2MAs shown, a sacrificial dielectric layer 318 is formed in the recess 316. In some embodiments, the sacrificial dielectric layer 318 may be formed on a pad layer 320, and the pad layer 320 may be formed directly on the semiconductor material of the transistor 104, such as in the channel region or on the semiconductor layer 118. The pad layer 320 may be formed of any material, such as a dielectric material. In some embodiments, the pad layer 320 may be a silicon nitride layer.

[0098] The sacrificial dielectric layer 318 can be formed of any dielectric material, and in some embodiments, it is formed of a material different from that of the padding layer 320. In some embodiments, the sacrificial dielectric layer 318 is an oxide layer. In some embodiments, the sacrificial dielectric layer 318 includes one or more of SiO, SiOC, AlO, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, SiOCN, SiOCN, or SiCN. In some embodiments, the sacrificial dielectric layer 318 has a thickness in the range of 1 to 50 nm. In some embodiments, the sacrificial dielectric layer 318 has a thickness of less than 20 nm. In some embodiments, the sacrificial dielectric layer 318 has a width in the range of 5 nm to 30 nm.

[0099] In some embodiments, such as after depositing the pad layer 320 and the sacrificial dielectric layer 318, a chemical mechanical polishing process is performed on the back side 311 of the device 100.

[0100] The sacrificial dielectric layer 318 may be formed of a material that produces high etch selectivity between the sacrificial dielectric layer 318 and the semiconductor region 308 (in some embodiments, the semiconductor region 308 may be SiGe).

[0101] like Figure 2N As shown, a recess 322 is formed at the back surface 311 of device 100. In some embodiments, a hard mask layer 324 is formed on the back surface of device 100, and the hard mask layer 324 can be patterned, for example, by photolithography. In some embodiments, a photoresist layer (not shown) can be formed on the hard mask layer 324. The photoresist layer can be patterned by photolithography, and an etching process can be performed to etch the hard mask layer 324 in the pattern of the photoresist layer. The hard mask layer 324 may include a dielectric material, a metal, or other types of materials. In some embodiments, the hard mask layer 324 includes one or more of SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, or SiCN. In some embodiments, the hard mask layer 324 has a thickness in the range of 5 nm to 40 nm.

[0102] The hard mask layer 324 can be patterned to form an opening 326 that extends through the hard mask layer 324. A groove 322 can be formed, for example, in an etching process, in which the hard mask layer 324 protects the underside of the device 100 while allowing etchant to remove exposed portions of the device 100 through the opening 326.

[0103] For example, in some embodiments, the recess 322 is formed by at least partially removing one or more semiconductor regions 308 exposed through the opening 326. In some embodiments, an etching process is used that is highly selective for the material of the semiconductor region 308 (e.g., SiGe) relative to the material of the sacrificial dielectric layer 318 (e.g., oxide) or the sacrificial pad 320 (e.g., SiN). Therefore, the etching process can selectively etch or remove the exposed semiconductor region 308 while retaining the exposed portions of the sacrificial dielectric layer 318 or the sacrificial pad 320.

[0104] As shown in the figure, one or more of the source / drain regions 194 are exposed through the recess 322.

[0105] like Figure 2O As shown, a back-side source / drain contact 340 is formed in the opening 326 and can extend into and partially or completely fill the recess 322. The back-side source / drain contact 340 may comprise the same material as the source / drain contact 220. Alternatively, the source / drain contact 340 may comprise a different material, such as a conductive material different from that used for the source / drain contact 220. In some embodiments, the back-side source / drain contact 340 comprises one or more of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, and Ni. In some embodiments, the back-side source / drain contact 340 may have a thickness in the range of 1 nm to 50 nm.

[0106] In some embodiments, a silicide layer may be formed or otherwise disposed between the source / drain contact 340 and the source / drain region 194. The back-side source / drain contact 340 may be electrically coupled to one or more of the source / drain regions 194.

[0107] In some embodiments, a dielectric pad 181 may be formed in the groove 322 (see...). Figure 3B Source / drain contacts 340 can be formed on dielectric pad 181. In some embodiments, dielectric pad 181 can be deposited in groove 322. Dielectric pad 181 can be formed of any suitable material, and in some embodiments, includes one or more of SiO, SiOC, Al2O3, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, SiOCN, and SiCN.

[0108] The dielectric pad 181 can be etched to remove the bottom and top portions of the sidewalls of the dielectric pad 181, thereby at least partially exposing one or more source / drain regions 194. The source / drain contact 340 can be formed by forming a first metal layer, for example, forming a first metal layer at the lower portion 371 of the source / drain contact 340. A silicide layer 348 can then be formed, for example, by an annealing process in which the first metal layer reacts with the semiconductor material of the source / drain region 194 to form the silicide layer 348. A second metal layer can be formed on the first metal layer, for example, at the upper portion 372 of the source / drain contact 340. In some embodiments, the first metal layer and the second metal layer are formed of different materials or different metals.

[0109] like Figure 2P As shown, a back metallization structure is formed at the back surface 311 of device 100. The back metallization structure may include, for example, electrical contacts, wires, any other conductive components, and may further include one or more electrically insulating layers. In some embodiments, the back metallization structure includes a hard mask layer 342 and an etch stop layer 344. For example, the back metallization contact 346 can be formed by patterning the hard mask layer 342 using the etch stop layer 344, for example, to define an opening. The back metallization structure, such as the back metallization contact 346, can be formed by depositing a conductive or metallic material in the opening. Figure 2P It is shown that a portion of dielectric layer 310 is not as described above. Figure 2J The part that was removed and retained Figure 2P The embodiment below the isolation structure 226 in the middle.

[0110] The back contact 346 may be electrically connected to or coupled to one or more electrical contacts of the transistor 104 of the device 100. For example, in some embodiments, the back contact 346 is electrically connected to one or more of the back source / drain contacts 340 or the gate electrode 216.

[0111] Figure 3A It is shown, for example, as Figure 2O A cross-sectional view of a portion of the semiconductor device 100 shown. Figure 3B It is shown Figure 3A A cross-sectional view of the magnified region "A" of the semiconductor device 100 shown.

[0112] like Figure 3BAs shown, the source / drain contact 340 may have a dual-layer structure, wherein a first portion (e.g., a lower portion) has a first width 371 that is smaller than a second width 372 of a second portion (e.g., an upper portion). In some embodiments, the first width 371 is in the range of 5 nm to 30 nm, and the second width 372 is in the range of 10 nm to 60 nm. In some embodiments, the second width 372 is at least twice as large as the first width 371.

[0113] In some embodiments, a first portion (e.g., a lower portion) of the source / drain contact 340 has a first height 373 and a second portion (e.g., an upper portion) has a second height 374. In some embodiments, the first height 373 is in the range of 5 nm to 30 nm, and the second height 374 is in the range of 5 nm to 30 nm. In some embodiments, the first height 373 is greater than the second height 374.

[0114] In some embodiments, the first portion (e.g., the lower portion) of the source / drain contact 340 may be formed of a different material (e.g., a different metal or conductive material) than the second portion (e.g., the upper portion) of the source / drain contact 340.

[0115] In some embodiments, the silicide layer 348 may have a thickness in the range of 1 nm to 10 nm. In some embodiments, the silicide layer 348 may include one or more of the following: for example, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, or YbSi, wherein the source / drain region 194 is formed of an N-type material. In some embodiments, the silicide layer 348 may include one or more of the following: for example, NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, wherein the source / drain region 194 is formed of a P-type material.

[0116] In some embodiments, the dielectric pad 181 may, for example, be in Figure 3B It has a thickness in the horizontal direction ranging from 0 to 10 nm.

[0117] like Figure 3BAs shown, in some embodiments, the sacrificial dielectric layer 318 may be at least partially recessed, for example, having a first surface 381 and a second surface 382 that is perpendicularly recessed relative to the first surface 381. The height or distance 383 between the first surface 381 and the second surface 382 may be in the range of 0 nm to 20 nm. The sacrificial dielectric layer 318 may be recessed, for example, due to etching to form an opening 326. In some embodiments, the sacrificial dielectric layer 318 has a substantially flat or non-recessed upper surface.

[0118] Figure 3C This is an illustration based on some embodiments. Figure 3B A cross-sectional view of an additional component of the semiconductor device 100 shown. Figure 3C As shown, the upper portion of the source / drain contact 340 may extend laterally by a first distance 391 between the edge of the dielectric pad 181 and the edge of the hard mask layer 324 at the first side of the source / drain contact 340. Similarly, the upper portion of the source / drain contact 340 may extend laterally by a second distance 392 between the edge of the dielectric pad 181 and the edge of the hard mask layer 324 at the second side of the source / drain contact 340. In some embodiments, each of the first distance 391 and the second distance 392 is in the range of 5 nm to 40 nm. In some embodiments, the first distance 391 and the second distance 392 are different. In some embodiments, the difference between the first distance 391 and the second distance 392 is in the range of 0 to 10 nm, which may be due to the coverage characteristics or coverage offset of the photolithography process or tooling used to form the source / drain contact 340.

[0119] Figure 4 This is a perspective view of a semiconductor device 200 according to some embodiments. Figure 4 Semiconductor devices 200 and Figure 2O The semiconductor device 100 shown is substantially the same or similar, except that the dielectric layer 310 extends over the isolation structure 226 and the semiconductor region 308 (e.g., between the source / drain region 194 and the semiconductor region 308). Conversely, as described herein... Figure 2O As described in the semiconductor device 100, a portion of the dielectric layer 310 can be removed, such that only a portion of the dielectric layer 310 on the semiconductor region 308 remains. In some embodiments, the dielectric layer 310 may be omitted or may be completely removed.

[0120] The semiconductor device 200 can be further processed to include a back-side metallization structure, for example, as Figure 2P As shown.

[0121] Figure 5 This is a cross-sectional view of a portion of a semiconductor device 300 according to some embodiments. Figure 5Semiconductor device 300 and, for example, Figure 3C The semiconductor device 100 shown is substantially the same as or similar to the semiconductor device 300, except that the pad 320 and sacrificial dielectric layer 318 are not partially removed in the semiconductor device 300. For example, during a process (e.g., etching) to form the opening 326, the pad 320 and sacrificial dielectric layer 318 of the semiconductor device 300 are not partially recessed or removed at the inner portion of the source / drain contact 340. Figure 5 In the embodiments and Figure 3C Similar to the embodiments, the dielectric pad 181 is not recessed.

[0122] Figure 6 This is a cross-sectional view of a portion of a semiconductor device 400 according to some embodiments. Figure 6 Semiconductor device 400 and, for example Figure 3C The semiconductor device 100 shown is substantially the same as or similar to the semiconductor device 400, except that the side portion of the sacrificial dielectric layer 318 is removed in the semiconductor device 400. That is, the dielectric layer 318 of the semiconductor device 400 has a width that is less than... Figure 3C The width of the sacrificial dielectric layer 318 of the semiconductor device 100 shown. Sidewalls or side portions of the sacrificial dielectric layer 318 may be removed, for example, during a process (e.g., etching) to form the opening 326.

[0123] In addition, such as Figure 6 As shown, the inner sidewall of the gasket 320 can be removed at the interface with the source / drain contact 340. For example, as Figure 6 As shown, pad 320 may have only the outer and lower sides, with the inner side completely removed. Similarly, as... Figure 6 As shown, the upper portion of dielectric pad 181 can be removed. In some embodiments, the upper surface of dielectric pad 181 is coplanar with the upper surface of a portion of pad 320 adjacent to dielectric pad 181. For example, the inner sidewalls of pad 320 and the upper portion of dielectric pad 181 can be removed during a process (e.g., etching) to form opening 326.

[0124] Embodiments of this disclosure provide a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device including a back-side self-aligned source / drain contact that completely falls on or contacts an epitaxial source / drain region. A sacrificial dielectric structure or layer is formed on the gate region or the metal gate electrode and protects or otherwise reduces or prevents damage to the gate region during the formation of the back-side source / drain contact, for example, during an etching process that may be used to form the back-side source / drain contact. As part of the process for forming the back-side source / drain contact, including the sacrificial dielectric structure is advantageous for enlarging the patterned window or opening formed in a hard mask or other layer, because an etching process that selectively removes the underlying portion of the semiconductor region can be employed while retaining the sacrificial dielectric structure.

[0125] In some embodiments, the semiconductor device includes a first dielectric layer and a first plurality of nanostructures on the first dielectric layer. The first plurality of nanostructures overlap each other. A first source / drain region is disposed laterally adjacent to a first side of the first plurality of nanostructures, and a second dielectric layer is disposed on the first side of the first source / drain region. A front source / drain contact is disposed on a second side of the first source / drain region opposite to the first side. A back source / drain contact is disposed on the first side of the first source / drain region and extends through the second dielectric layer.

[0126] In the aforementioned semiconductor device, the semiconductor device further includes: a second source / drain region disposed laterally adjacent to a second side of the first plurality of nanostructures; and a semiconductor layer on the second source / drain region.

[0127] In the aforementioned semiconductor device, the semiconductor device further includes: a second source / drain region disposed laterally adjacent to a second side of the first plurality of nanostructures; a semiconductor layer on the second source / drain region; and a second plurality of nanostructures on the first dielectric layer, the second plurality of nanostructures overlapping each other, the first source / drain region extending between the first plurality of nanostructures and the second plurality of nanostructures, wherein the back-side source / drain contact has a lower portion and an upper portion, the lower portion being disposed between the first source / drain region and the upper portion, and the upper portion having a width greater than the width of the lower portion.

[0128] In the aforementioned semiconductor device, the semiconductor device further includes: a second source / drain region disposed laterally adjacent to a second side of the first plurality of nanostructures; a semiconductor layer on the second source / drain region; and a second plurality of nanostructures on the first dielectric layer, the second plurality of nanostructures overlapping each other, the first source / drain region extending between the first plurality of nanostructures and the second plurality of nanostructures, wherein the back-side source / drain contact has a lower portion and an upper portion, the lower portion being disposed between the first source / drain region and the upper portion, and the upper portion having a width greater than the width of the lower portion. The second dielectric layer defines a laterally recessed portion, and the upper portion of the back-side source / drain contact extends into and onto the laterally recessed portion.

[0129] In the aforementioned semiconductor device, the semiconductor device further includes: a second source / drain region laterally disposed adjacent to a second side of the first plurality of nanostructures; a semiconductor layer on the second source / drain region; and a second plurality of nanostructures on the first dielectric layer, the second plurality of nanostructures overlapping each other, the first source / drain region extending between the first plurality of nanostructures and the second plurality of nanostructures, wherein a back-side source / drain contact has a lower portion and an upper portion, the lower portion being disposed between the first source / drain region and the upper portion, and the upper portion having a width greater than the width of the lower portion. The second dielectric layer defines a laterally recessed portion, and the upper portion of the back-side source / drain contact extends into and onto the laterally recessed portion. The recessed portion of the second dielectric layer extends from the upper surface of the second dielectric layer to a depth in the range of 1 nm to 20 nm.

[0130] In the aforementioned semiconductor device, the semiconductor device further includes: a second source / drain region disposed laterally adjacent to a second side of the first plurality of nanostructures; a semiconductor layer on the second source / drain region; and a second plurality of nanostructures on the first dielectric layer, the second plurality of nanostructures overlapping each other, the first source / drain region extending between the first plurality of nanostructures and the second plurality of nanostructures, wherein the back-side source / drain contact has a lower portion and an upper portion, the lower portion being disposed between the first source / drain region and the upper portion, and the upper portion having a width greater than the width of the lower portion. The lower portion of the back-side source / drain contact includes a first metal, and the upper portion of the back-side source / drain contact includes a second metal different from the first metal.

[0131] In the aforementioned semiconductor device, the semiconductor device further includes: a second source / drain region disposed laterally adjacent to a second side of the first plurality of nanostructures; a semiconductor layer on the second source / drain region; and a second plurality of nanostructures on the first dielectric layer, the second plurality of nanostructures overlapping each other, the first source / drain region extending between the first plurality of nanostructures and the second plurality of nanostructures, wherein the back-side source / drain contact has a lower portion and an upper portion, the lower portion being disposed between the first source / drain region and the upper portion, and the upper portion having a width greater than the width of the lower portion. The width of the lower portion of the back-side source / drain contact is in the range of 5 nm to 30 nm, and the width of the upper portion of the back-side source / drain contact is in the range of 10 nm to 60 nm.

[0132] In the aforementioned semiconductor device, the semiconductor device further includes: a second source / drain region disposed laterally adjacent to a second side of the first plurality of nanostructures; a semiconductor layer on the second source / drain region; and a second plurality of nanostructures on the first dielectric layer, the second plurality of nanostructures overlapping each other, the first source / drain region extending between the first plurality of nanostructures and the second plurality of nanostructures, wherein the back-side source / drain contact has a lower portion and an upper portion, the lower portion being disposed between the first source / drain region and the upper portion, and the upper portion having a width greater than the width of the lower portion. Each of the lower and upper portions of the back-side source / drain has a height in the range of 5 nm to 30 nm.

[0133] In the aforementioned semiconductor device, the semiconductor device further includes a silicide layer between the first source / drain region and the back source / drain contact.

[0134] In the aforementioned semiconductor device, the semiconductor device further includes a dielectric pad layer between the first plurality of nanostructures and the first dielectric layer.

[0135] In the aforementioned semiconductor device, the semiconductor device further includes a dielectric pad layer between the first plurality of nanostructures and the first dielectric layer. The dielectric pad layer includes a first side portion that contacts the back source / drain contacts and a second side portion that is opposite to the first side portion, wherein the first side portion has a height smaller than that of the second side portion.

[0136] In the aforementioned semiconductor device, the semiconductor device further includes a third dielectric layer laterally disposed between at least a portion of the first plurality of nanostructures and the back-side source / drain contacts.

[0137] In some embodiments, a device includes a channel region and a first source / drain region disposed laterally adjacent to a first side of the channel region. A second source / drain region is disposed laterally adjacent to a second side of the channel region opposite to the first side. A gate electrode at least partially surrounds the channel region. A dielectric layer is disposed on the first side of the first source / drain region. A front source / drain contact is disposed on the second side of the first source / drain region opposite to the first side. A back source / drain contact has a first portion on the first side of the first source / drain region and a second portion on the first portion. The second portion has a wider width than the first portion.

[0138] In the aforementioned semiconductor device, the second portion of the back-side source / drain contact is laterally contacted with the dielectric layer.

[0139] In the aforementioned semiconductor device, the first and second portions of the back-side source / drain contacts are formed of different conductive materials.

[0140] In the aforementioned semiconductor device, the semiconductor device further includes a silicide layer between a first portion of the back source / drain contact and a first side of the first source / drain region.

[0141] In some embodiments, a method includes forming a channel region of a transistor overlying a first dielectric layer. A source / drain region is formed laterally adjacent to a first side of the channel region. A second dielectric layer is formed on the first side of the source / drain region. A front source / drain contact is formed on a second side of the source / drain region opposite to the first side. A back source / drain contact is formed on the first side of the source / drain region, extending through the second dielectric layer.

[0142] In the above method, the method further includes: forming a semiconductor layer on the source / drain region; forming a hard mask layer on the semiconductor layer and a second dielectric layer; forming an opening in the hard mask layer that at least partially exposes the source / drain region and the second dielectric layer; and removing the semiconductor layer at least partially through the opening, wherein forming a back source / drain contact includes forming a back source / drain contact in the opening.

[0143] In the above method, the method further includes: forming a semiconductor layer on the source / drain region; forming a hard mask layer on the semiconductor layer and a second dielectric layer; forming an opening in the hard mask layer that at least partially exposes the source / drain region and the second dielectric layer; and at least partially removing the semiconductor layer through the opening, wherein forming a back-side source / drain contact includes forming a back-side source / drain contact in the opening. At least partially removing the semiconductor layer includes etching the semiconductor layer with an etchant that has higher selectivity for the semiconductor layer than for the second dielectric layer.

[0144] In the above method, the method further includes: forming a semiconductor layer on the source / drain region; forming a hard mask layer on the semiconductor layer and a second dielectric layer; forming an opening in the hard mask layer that at least partially exposes the source / drain region and the second dielectric layer; and at least partially removing the semiconductor layer through the opening, wherein forming a back source / drain contact includes forming a back source / drain contact in the opening. At least partially removing the semiconductor layer includes etching the semiconductor layer with an etchant that has higher selectivity for the semiconductor layer than for the second dielectric layer. Forming the back source / drain contact includes forming a back source / drain contact covering a first side of the source / drain region.

[0145] The foregoing disclosure has outlined components of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: First dielectric layer; A plurality of nanostructures are provided on the first dielectric layer, wherein the nanostructures overlap each other and gate electrodes are disposed between the nanostructures. The first source / drain region is laterally adjacent to the first side of the first plurality of nanostructures; The second dielectric layer is on the first side of the first source / drain region; A front-facing source / drain contact is located on the second side of the first source / drain region opposite to the first side. as well as A back-side source / drain contact, located on the first side of the first source / drain region, extends through the second dielectric layer. The back-side source / drain contact has a lower portion and an upper portion with a width greater than the lower portion. A sacrificial dielectric layer is disposed above the first plurality of nanostructures. The upper portion extends laterally outward to overlap with the first plurality of nanostructures in the longitudinal direction, and in the overlapping area, the back source / drain contact is spaced apart from the gate electrode by the sacrificial dielectric layer.

2. The semiconductor device according to claim 1, further comprising: The second source / drain region is laterally adjacent to the second side of the first plurality of nanostructures; as well as Semiconductor layer on the second source / drain region.

3. The semiconductor device according to claim 2, further comprising: A second plurality of nanostructures are provided on the first dielectric layer, the second plurality of nanostructures overlapping each other, and the first source / drain region extends between the first plurality of nanostructures and the second plurality of nanostructures. The back-side source / drain contact has a lower portion and an upper portion, with the lower portion disposed between the first source / drain region and the upper portion.

4. The semiconductor device according to claim 3, wherein, The sacrificial dielectric layer defines a lateral recess, and the upper portion of the back source / drain contact extends into and onto the lateral recess.

5. The semiconductor device of claim 4, wherein the recessed portion of the second dielectric layer extends from the upper surface of the second dielectric layer to a depth in the range of 1 nm to 20 nm.

6. The semiconductor device of claim 3, wherein the lower portion of the back source / drain contact comprises a first metal, and the upper portion of the back source / drain contact comprises a second metal different from the first metal.

7. The semiconductor device according to claim 3, wherein, The width of the lower portion of the back source / drain contact is in the range of 5 nm to 30 nm, and the width of the upper portion of the back source / drain contact is in the range of 10 nm to 60 nm.

8. The semiconductor device according to claim 3, wherein, Each of the lower and upper portions of the back-side source / drain contacts has a height in the range of 5 nm to 30 nm.

9. The semiconductor device of claim 1, further comprising a silicide layer between the first source / drain region and the back source / drain contact.

10. The semiconductor device of claim 1, further comprising a dielectric pad layer between the first plurality of nanostructures and the first dielectric layer.

11. The semiconductor device of claim 10, wherein the dielectric pad layer includes a first side portion in contact with the back source / drain contact and a second side portion opposite to the first side portion, wherein the first side portion has a height less than the height of the second side portion.

12. The semiconductor device of claim 1, further comprising a third dielectric layer laterally disposed between at least a portion of the first plurality of nanostructures and the back source / drain contacts.

13. A semiconductor device, comprising: Channel area; The first source / drain region is laterally adjacent to the first side of the channel region; The second source / drain region is laterally adjacent to the second side of the channel region opposite to the first side; The gate electrode at least partially surrounds the channel region; A dielectric layer is located on the first side of the first source / drain region; A front-facing source / drain contact is located on the second side of the first source / drain region opposite to the first side. as well as The back-side source / drain contact has a first portion on the first side of the first source / drain region and a second portion on the first portion, the second portion having a wider width than the first portion. A sacrificial dielectric layer is disposed above the channel region and the gate electrode. The second portion extends laterally outward to overlap with the channel region in the longitudinal direction, and in the overlapping region, the back source / drain contact is spaced apart from the gate electrode by the sacrificial dielectric layer.

14. The semiconductor device of claim 13, wherein the second portion of the back source / drain contact laterally contacts the dielectric layer.

15. The semiconductor device according to claim 13, wherein, The first and second portions of the back-side source / drain contacts are formed of different conductive materials.

16. The semiconductor device of claim 13, further comprising a silicide layer between the first portion of the back source / drain contact and the first side of the first source / drain region.

17. A method of forming a semiconductor device, comprising: A channel region of a transistor is formed covering the first dielectric layer, and a gate electrode is disposed around the channel region; A source / drain region is formed laterally adjacent to the first side of the channel region; A second dielectric layer is formed on the first side of the source / drain region; A front-side source / drain contact is formed on the second side of the source / drain region opposite to the first side; as well as A back-side source / drain contact is formed on the first side of the source / drain region, the back-side source / drain contact extending through the second dielectric layer. The method further includes: A semiconductor layer is formed on the source / drain region; A sacrificial dielectric layer is formed above the channel region; A hard mask layer is formed on the semiconductor layer and the sacrificial dielectric layer; An opening is formed in the hard mask layer to at least partially expose the source / drain regions and the sacrificial dielectric layer; and The semiconductor layer is at least partially removed through the opening. The formation of the back source / drain contact includes forming the back source / drain contact in the opening. The back-side source / drain contact includes a lower portion and an upper portion that is wider than the lower portion. The upper portion extends laterally outward to overlap with the channel region in the longitudinal direction. In the overlapping region, the back-side source / drain contact is spaced apart from the gate electrode by the sacrificial dielectric layer.

18. The method according to claim 17, wherein, The sacrificial dielectric layer has a lateral recess, and the upper portion of the back source / drain contact extends into the lateral recess.

19. The method of claim 17, wherein removing at least partially the semiconductor layer comprises etching the semiconductor layer with an etchant that has higher selectivity for the semiconductor layer than for the sacrificial dielectric layer.

20. The method of claim 19, wherein forming the back source / drain contact comprises forming the back source / drain contact covering the first side of the source / drain region.

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