A multi-channel adaptive calibration super regenerative transceiver

Abstract

The present invention discloses a multi-channel adaptive calibration super-regenerative transceiver, which belongs to the field of integrated circuits. The structure includes: a single-pole double-throw switch, a low-noise amplifier, a power amplifier, a differential-to-single-ended circuit, a digitally controlled oscillator, an envelope detector, a comparator, a frequency calibration / control circuit module, and a sensitivity calibration / automatic amplitude control module. The structure is applied to a low-power radio frequency front end, and improves the sensitivity through a calibration loop while achieving low-power communication. The present invention is improved and optimized on the basis of the existing circuit structure, including: using a digitally controlled oscillator to solve the frequency drift problem of the super-regenerative oscillator during the quenching operation; the proposed multi-loop collaborative frequency calibration method can solve the problem of mutual influence between frequency adjustment and amplitude adjustment in traditional frequency calibration; the sensitivity calibration and automatic amplitude control circuit components are shared to reduce calibration errors, and the receiver sensitivity can be dynamically calibrated without interrupting the receiving state.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and in particular relates to a multi-channel adaptive calibration super-regenerative transceiver. Background Art

[0002] Among the various structures of the receiver, the mixing structure sacrifices complexity and power consumption in exchange for good sensitivity and stability, and has been widely used; the direct RF tuning structure abandons performance in exchange for low energy consumption, and is often used as a wake-up receiver; the super-regenerative structure utilizes the high gain of the super-regenerative oscillator to combine the advantages of low power consumption and high performance, and has good application prospects.

[0003] The core of the super regenerative receiver is a super regenerative oscillator controlled by a quenching signal and an injection signal. Figure 1 As shown in the figure, the low noise amplifier initially amplifies the RF signal transmitted from the antenna into an injection signal for the oscillator. This signal determines the start-up speed of the super-regenerative oscillator, while the quenching circuit generates a quenching signal to control whether the oscillator starts. The result of the injection signal and the quenching signal acting on the super-regenerative oscillator at the same time is the generation of oscillation signals of varying sizes. The envelope is extracted by the envelope detector, and the data can be obtained by the post-stage demodulation circuit. Although the super-regenerative receiver has a simple structure, it has poor robustness, so some technologies are needed to give full play to its advantages of high sensitivity and energy efficiency.

[0004] Current research on super-regenerative receivers focuses on the input circuit. The use of a Q-enhanced low-noise amplifier in the receiver can improve the receiver sensitivity, but an off-chip balun is required to convert the single-ended signal to differential, and the additional resonant network consumes more area when the frequency band is low. On the other hand, although the super-regenerative oscillator provides a very high gain for the amplification of weak signals, the cost is that it is very sensitive to the mismatch of the LC resonant network. Therefore, a phase-locked loop is often used to calibrate the frequency of the oscillator.

[0005] CN114006584A discloses a tail current circuit of a super regenerative oscillator, a super regenerative oscillator and a super regenerative receiver. The tail current circuit of the super regenerative oscillator comprises a comparison module, a control module and a tail current adjustment module. When the preset oscillation voltage is less than the target voltage, the control module controls the tail current adjustment module to increase the tail current provided to the tail current input terminal of the super regenerative oscillator, thereby increasing the preset oscillation voltage until the preset oscillation voltage of the super regenerative oscillator is just greater than the target voltage, so that the starting time of the super regenerative oscillator is maintained at a relatively fixed time.

[0006] However, for super-regenerative oscillators that need to be quenched continuously, the use of analog phase-locked loops will cause the problem of capacitor tuning voltage leakage, and the receiving state can only be interrupted frequently for calibration, which reduces the receiving efficiency. In addition, although the automatic amplitude calibration method based on the error amplifier can ensure the constant oscillation envelope during frequency calibration, it is independent of the sensitivity calibration loop and will cause certain frequency calibration errors. Summary of the invention

[0007] In view of the shortcomings of the above-mentioned background technology, the present invention provides a multi-channel adaptive calibration super-regenerative transceiver.

[0008] A multi-channel adaptive calibration super-regenerative transceiver, characterized in that it includes a single-pole double-throw switch, a low-noise amplifier, a power amplifier, a differential-to-single-ended circuit, a digitally controlled oscillator, an envelope detector, a comparator, a frequency calibration / control circuit module and a sensitivity calibration / automatic amplitude control module;

[0009] The input end of the single-pole double-throw switch is connected to an external antenna, and the output end of the single-pole double-throw switch is respectively connected to the input end of a low-noise amplifier and the output end of a power amplifier; the output end of the low-noise amplifier is connected to the output end of a digitally controlled oscillator; the input end of the power amplifier is connected to the output end of a differential-to-single-ended circuit; the input end of the differential-to-single-ended circuit is connected to the output end of a digitally controlled oscillator; the output end of the digitally controlled oscillator is respectively connected to the input end of an envelope detector and the input end of a frequency calibration / control circuit; the output end of the envelope detector is connected to the input end of a demodulation circuit; the output end of the demodulation circuit is connected to the input end of a sensitivity calibration circuit, and a comparator generates a system output signal; the output end of the sensitivity calibration / automatic amplitude control module is connected to the tail current input end of the digitally controlled oscillator; the output end of the frequency calibration / control circuit module is connected to the capacitor array of the digitally controlled oscillator.

[0010] Furthermore, the multi-channel adaptive calibration super-regenerative transceiver has three feedback loops: a frequency calibration loop, an amplitude calibration loop and a sensitivity calibration loop, wherein the frequency calibration loop is composed of a digitally controlled oscillator and a frequency calibration / control circuit module, the sensitivity calibration loop is composed of a digitally controlled oscillator, an envelope detector, a comparator and a sensitivity calibration / amplitude control module, and the difference between the amplitude calibration loop and the sensitivity calibration loop is that the working state and control signal of some circuits in the sensitivity calibration / amplitude control module are different. The three working modes of the multi-calibration super-regenerative transceiver are realized through the coordinated work of the three feedback loops: calibration mode, receiving mode and transmitting mode. In the calibration mode, the frequency calibration loop and the amplitude calibration loop work together to calibrate the frequency and amplitude of the digitally controlled oscillator. When the calibration is completed, the system decides whether to enter the receiving mode or the transmitting mode according to the control signal. In the receiving mode, the frequency calibration loop is closed, and the amplitude calibration loop is switched to the sensitivity calibration loop to realize dynamic calibration of the receiver sensitivity without interrupting the receiving state. In the transmitting mode, all loops are closed and opened again when a channel change is detected.

[0011] Furthermore, the calibration mode uses an amplitude calibration loop and a frequency calibration loop to work together to achieve frequency calibration. The loop working order is frequency coarse adjustment, amplitude coarse adjustment, frequency medium adjustment, amplitude fine adjustment and frequency fine adjustment. During the calibration process, it is ensured that the calibration range of the next stage covers the frequency or amplitude deviation caused by the previous stage. The calibration method can solve the problem of mutual influence between frequency adjustment and amplitude adjustment in traditional frequency calibration, thereby improving the calibration accuracy.

[0012] Furthermore, the low noise amplifier includes NMOS tubes Mn1 to Mn4, resistors R1 and R2, capacitors C1 to C3, inductor L1, input signal VRX, output signals VOUTP and VOUTN, and bias voltages VB1 and VB2. The input end of L1 is connected to VRX, and the output end is connected to ground; the input end of C1 is connected to VRX, and the output end is connected to ground; the source of Mn1 is connected to VRX, the gate is connected to the input end of C3, and the drain is connected to the source of Mn2; the gate of Mn2 is connected to VB2, and the drain is connected to VOUTP; the input end of C2 is connected to VRX, and the output end is connected to the gate of Mn3; the source of Mn3 is connected to ground, and the drain is connected to the source of Mn4; the gate of Mn4 is connected to VB2, and the drain is connected to VOUTN; the output end of C3 is connected to ground; the input end of R1 is connected to VB1, and the output end is connected to the gate of Mn1; the input end of R2 is connected to VB1, and the output end is connected to the gate of Mn3.

[0013] Furthermore, the digitally controlled oscillator and its tail current bias circuit include NMOS tubes Mn5, Mn6, Mn14 and Mn15, PMOS tubes Mp5 and Mp6, inductors L2 and L3, reference current source IREF, coarse adjustment capacitor array basic units include NMOS tubes Mn7~Mn9, capacitors C4 and C5, a total of 5 groups; mid-adjustment capacitor array basic units include PMOS tubes Mp1 and Mp2, a total of 5 groups; fine-adjustment capacitor array basic units include NMOS tubes Mn10~Mn13 and inverter INV1, a total of 4 groups; current steering current source array basic units include PMOS tubes Mp3 and Mp4, a total of 9 groups.

[0014] The input end of L2 is connected to the power supply, and the output end is connected to VOUTP; the input end of L3 is connected to the power supply, and the output end is connected to VOUTN; the drain of Mn5 is connected to VOUTP, the gate is connected to VOUTN, and the source is connected to the drain of Mn14; the drain of Mn6 is connected to VOUTN, the gate is connected to VOUTP, and the source is connected to the drain of Mn14; the input end of C4 is connected to VOUTP, and the output end is connected to the drain of Mn8; the drain of Mn7 is connected to the drain of Mn8, the gate is connected to the coarse adjustment control word [0], and the source is connected to the ground; the gate of Mn8 is connected to the coarse adjustment control word [0], and the source is connected to the drain of Mn9; the gate of Mn9 is connected to the coarse adjustment control word, and the source is connected to the ground; the input end of C5 is connected to VOUTN, and the output end is connected to the source of Mn8. The gate of Mp1 is connected to the mid-adjustment control word [0], and the source, substrate and drain are all connected to VOUTP; the gate of Mp2 is connected to the mid-adjustment control word [0], and the source, substrate and drain are all connected to VOUTN; the gate of Mn10 is connected to VOUTP, and the source, substrate and drain are all connected to the fine-adjustment control word [0]; the gate of Mn11 is connected to VOUTN, and the source, substrate and drain are all connected to the fine-adjustment control word [0]; the input end of INV1 is connected to the fine-adjustment control word [0], and the output end is connected to the drain of Mn12; the gate of Mn12 is connected to VOUTP, and the source, substrate and drain are all connected to the drain of Mn13; The gate of Mn13 is connected to VOUTN, and the source, substrate and drain are all connected to the drain of Mn12; the gate of Mn14 is connected to the gate of Mn15, and the source is connected to ground; the gate of Mn15 is connected to the drain, and the source is connected to ground; the gate of Mp3 is connected to the current source control word [0], the drain is connected to the drain of Mn15, and the source is connected to the drain of Mp4; the gate of Mp4 is connected to the gate of Mp6, and the source is connected to the power supply; the gate of Mp5 is connected to the quenching signal, the drain is connected to the gate of Mp6, and the source is connected to the power supply; the drain of Mp6 is connected to the positive terminal of IREF, and the source is connected to the power supply; the negative terminal of IREF is connected to ground.

[0015] Furthermore, the envelope detector includes NMOS tubes Mn16 to Mn29, PMOS tubes Mp7 and Mp8, and capacitor C6. The DC load array includes Mn25, Mn26, Mn28, and Mn29, a total of 2 groups. The input is VOUTP, VOUTN, and the amplitude modulation control signal, the bias current is IB_ED, and the output is ED_OUTP, ED_OUTN1, and ED_OUTN2.

[0016] The gate of Mn16 is connected to VOUTP, the drain is connected to the power supply, and the source is connected to ED_OUTP; the gate of Mn17 is connected to VOUTN, the drain is connected to the power supply, and the source is connected to ED_OUTP; the gate of Mn18 is connected to the gate of Mn19, the drain is connected to ED_OUTP, and the source is connected to ground; the input end of C6 is connected to ED_OUTP, and the output end is connected to ground; the source of Mn19 is connected to ground; the gate of Mp7 is connected to ED_OUTP, the drain is connected to the drain of Mn19, and the source is connected to IB_ED; the gate of Mp8 is connected to the drain of Mn21, the drain is connected to the drain of Mn20, and the source is connected to IB_ED; the gate and drain of Mn20 are connected to the gate of Mn21, and the source is connected to ground; the source of Mn21 The gate and drain of Mn22 are connected to the power supply, and the source is connected to the gate of Mp8; the gate and drain of Mn23 are connected to the power supply, and the source is connected to the gate of Mp8; the gate of Mn24 is connected to the gate of Mn21, the drain is connected to the source of Mn22, and the source is connected to the ground; the gate and drain of Mn25 are connected to the amplitude modulation control signal, and the source is connected to ED_OUTN1; the gate and drain of Mn26 are connected to the amplitude modulation control signal, and the source is connected to ED_OUTN1; the gate of Mn27 is connected to the gate of Mn20, the drain is connected to the source of Mn28, and the source is connected to the ground; the gate and drain of Mn28 are connected to the power supply, and the source is connected to ED_OUTN2; the gate and drain of Mn29 are connected to the power supply, and the source is connected to ED_OUTN2.

[0017] Furthermore, the differential-to-single-ended circuit includes NMOS tubes Mn30 and Mn31, PMOS tube Mp9, capacitors C9 and C10, resistors R3 and R4, input signals are VOUTP and VOUTN, bias voltages are VA, VB2 and VB3, and the output signal is Vsig.

[0018] The gate of Mp9 is connected to VA, the drain is connected to the drain of Mn31, and the source is connected to the power supply; the input of C10 is connected to VOUTP, and the output is connected to the gate of Mn31; the input of R4 is connected to VB2, and the output is connected to the gate of Mn31; the source and substrate of Mn31 are connected to Vsig; the input of C9 is connected to VOUTN, and the output is connected to the gate of Mn30; the input of R3 is connected to VB3, and the output is connected to the gate of Mn30; the drain of Mn30 is connected to Vsig, and the source and substrate are connected to ground.

[0019] Furthermore, the power amplifier includes an inductor L4, an NMOS tube Mn33, and a capacitor C12, and the power amplifier array unit includes a capacitor C11, a resistor R5, and an NMOS tube Mn32, a total of three groups. The input signal is Vsig, the bias voltage is VB6, and the output signal is VTX; the power amplifier array bias voltage is VB5, a total of three groups.

[0020] The input end of L4 is connected to the power supply, and the output end is connected to VTX; the gate of Mn33 is connected to VB6, the drain is connected to VTX, and the source is connected to the drain of Mn32; the input end of C12 is connected to VTX, and the output end is connected to the ground; the input end of C11 is connected to Vsig, and the output end is connected to the gate of Mn32; the input end of R5 is connected to VB5, and the output end is connected to the gate of Mn32; the source of Mn32 is grounded.

[0021] Furthermore, the frequency calibration / control circuit module includes a lookup table, a three-to-one data selector, a digital comparator, a state machine, a 16-bit counter, a divider, a clock, a mode switch, and a coarse / medium / fine digital code generation circuit. The input signals are the channel selection code, the reference frequency, the reset signal, the amplitude modulation feedback signal, and the oscillator output, and the output signals are the amplitude modulation control signal, the coarse control word, the medium control word, and the fine control word.

[0022] The input end of the lookup table is connected to the channel selection code, and the output end is connected to the input end of the three-selection data selector; the output end of the three-selection data selector is connected to the input end of the digital comparator, and the clock module provides the clock signal of each small module; the input end of the digital comparator is connected to the output end of the 16-bit counter and the clock signal, and the output end is connected to the input end of the state machine; the input end of the state machine is connected to the clock signal, and the output end is connected to the coarse / medium / fine adjustment digital code generation circuit; the output end of the coarse / medium / fine adjustment digital code generation circuit is connected to the capacitor array of the digital control oscillator; the input signal of the clock circuit is the reference frequency and the reset signal, and the output end is connected to each digital circuit; the input end of the mode switching circuit is connected to the amplitude modulation feedback signal, and the output signal is the amplitude modulation control signal.

[0023] Furthermore, the sensitivity calibration / automatic amplitude control module includes an averager, a numerical comparator, a two-choice data selector, a state machine, a dynamic successive approximation circuit, and a current steering digital-to-analog converter. The input signal is the comparator input and the amplitude modulation control signal, and the output signal is the amplitude modulation feedback signal and the oscillator tail current.

[0024] The averager input signal is the comparator output, and the output four-bit digital code is connected to the input of the numerical comparator; the output of the numerical comparator is connected to the input of a two-to-one data selector; the other input of the two-to-one data selector is connected to the comparator output, and the output is connected to the state machine input; the state machine output is connected to the dynamic successive approximation circuit input; the dynamic successive approximation circuit outputs a 9-bit digital code connected to the current steering digital-to-analog converter input; the digital-to-analog converter output is connected to the tail current input of the digitally controlled oscillator.

[0025] The present invention improves and optimizes the existing technology and circuit structure, and provides a multi-channel adaptive calibration super regenerative transceiver, the main advantages of which are: the use of a digitally controlled oscillator solves the frequency drift problem of the super regenerative oscillator during the quenching operation; the proposed multi-loop collaborative frequency calibration method can solve the problem of mutual influence between frequency adjustment and amplitude adjustment in traditional frequency calibration; the sensitivity calibration and automatic amplitude control circuit components are shared to reduce calibration errors, and the receiver sensitivity can be dynamically calibrated without interrupting the receiving state. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of the structure of a super regenerative receiver;

[0027] Figure 2 is a structural block diagram of a multi-channel adaptive calibration super-regenerative transceiver of the present invention;

[0028] Figure 3 This is the circuit diagram of the balun low noise amplifier;

[0029] Figure 4 It is the circuit diagram of the digital controlled oscillator and bias circuit;

[0030] Figure 5 It is the circuit diagram of the envelope detector;

[0031] Figure 6 This is the circuit diagram of the differential to single-ended circuit;

[0032] Figure 7 It is the circuit diagram of the power amplifier;

[0033] Figure 8 is the schematic diagram of the frequency calibration / control circuit;

[0034] Fig. 9It is a schematic diagram of the structure of sensitivity calibration / automatic amplitude control;

[0035] Fig.10 It is the timing diagram of frequency calibration. DETAILED DESCRIPTION

[0036] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0037] like Figure 2 As shown, an embodiment of the present invention provides a multi-channel adaptive calibration super regenerative transceiver, a multi-channel adaptive calibration super regenerative transceiver, including a single-pole double-throw switch, a low noise amplifier, a power amplifier, a differential-to-single-ended circuit, a digitally controlled oscillator, an envelope detector, a comparator, a frequency calibration / control circuit module and a sensitivity calibration / automatic amplitude control module; the input end of the single-pole double-throw switch is connected to an external antenna, and the output end of the single-pole double-throw switch is respectively connected to the input end of the low noise amplifier and the output end of the power amplifier; the output end of the low noise amplifier is connected to the output end of the digitally controlled oscillator; the input end of the power amplifier is connected to the output end of the differential-to-single-ended circuit; the input end of the differential-to-single-ended circuit is connected to the digitally controlled oscillator The output end of the digital controlled oscillator is connected to the input end of the envelope detector and the input end of the frequency calibration / control circuit respectively; the output end of the envelope detector is connected to the input end of the demodulation circuit; the output end of the demodulation circuit is connected to the input end of the sensitivity calibration circuit, and the comparator generates a system output signal; the output end of the sensitivity calibration / automatic amplitude control module is connected to the tail current input end of the digital controlled oscillator; the output end of the frequency calibration / control circuit module is connected to the capacitor array of the digital controlled oscillator; the receiving path of the super regenerative receiver includes a low noise amplifier, an envelope detector and a comparator, and the transmitting path includes a differential to single-ended circuit and a power amplifier, wherein both the receiving and transmitting paths include digital controlled oscillators.

[0038] In the above embodiment of the present invention, the multi-channel adaptive calibration super-regenerative transceiver has three feedback loops: a frequency calibration loop, an amplitude calibration loop and a sensitivity calibration loop, wherein the frequency calibration loop is composed of a digitally controlled oscillator and a frequency calibration / control circuit module, the sensitivity calibration loop is composed of a digitally controlled oscillator, an envelope detector, a comparator and a sensitivity calibration / amplitude control module, and the difference between the amplitude calibration loop and the sensitivity calibration loop is that the working state and control signal of some circuits in the sensitivity calibration / amplitude control module are different. The three working modes of the multi-calibration super-regenerative transceiver are realized by the coordinated work of the three feedback loops: calibration mode, receiving mode and transmitting mode. In the calibration mode, the frequency calibration loop and the amplitude calibration loop work together to calibrate the frequency and amplitude of the digitally controlled oscillator, at which time the transmitting path does not work, and only the low noise amplifier in the receiving path does not work. When the calibration is completed, the system decides whether to enter the receiving mode or the transmitting mode according to the control signal. In the receiving mode, the frequency calibration loop is closed, and the amplitude calibration loop is switched to the sensitivity calibration loop to realize dynamic calibration of the receiver sensitivity without interrupting the receiving state, at which time the transmitting path does not work. In the transmit mode, all loops are closed and reopened when a channel change is detected. At this time, the receive path is not working.

[0039] In the above embodiment of the present invention, the calibration mode uses the amplitude calibration loop and the frequency calibration loop to work together to achieve frequency calibration. The loop working order is frequency coarse adjustment, amplitude coarse adjustment, frequency medium adjustment, amplitude fine adjustment and frequency fine adjustment. During the calibration process, it is ensured that the calibration range of the next stage covers the frequency or amplitude deviation caused by the previous stage. The calibration method can solve the problem of mutual influence between frequency adjustment and amplitude adjustment in traditional frequency calibration, thereby improving the calibration accuracy.

[0040] like Figure 3As shown, in the above embodiment of the present invention, the low noise amplifier includes NMOS tubes Mn1~Mn4, resistors R1 and R2, capacitors C1~C3, inductor L1, input signal VRX, output signals VOUTP and VOUTN, and bias voltages VB1 and VB2. The input end of L1 is connected to VRX, and the output end is connected to ground; the input end of C1 is connected to VRX, and the output end is connected to ground; the source of Mn1 is connected to VRX, the gate is connected to the input end of C3, and the drain is connected to the source of Mn2; the gate of Mn2 is connected to VB2, and the drain is connected to VOUTP; the input end of C2 is connected to VRX, and the output end is connected to the gate of Mn3; the source of Mn3 is connected to ground, and the drain is connected to the source of Mn4; the gate of Mn4 is connected to VB2, and the drain is connected to VOUTN; the output end of C3 is connected to ground; the input end of R1 is connected to VB1, and the output end is connected to the gate of Mn1; the input end of R2 is connected to VB1, and the output end is connected to the gate of Mn3. Mn1 is a common gate amplifier, and Mn3 is a common source amplifier to achieve noise cancellation. Mn2 and Mn4 form a cascode structure with Mn1 and Mn3 respectively to improve gain and increase isolation. The R1 and R2 are bias resistors, and C2 and C3 are cross-coupling capacitors to reduce amplifier noise. The L1 and C1 are input impedance matching networks, and consume very little DC voltage drop when providing a DC path for the common gate, thereby adapting to low-voltage operation. The low-noise amplifier uses fewer passive components to achieve input impedance matching and can convert single-ended signals into differential signals.

[0041] like Figure 4 As shown, in the above embodiment of the present invention, the digitally controlled oscillator and its tail current bias circuit include NMOS tubes Mn5, Mn6, Mn14 and Mn15, PMOS tubes Mp5 and Mp6, inductors L2 and L3, reference current source IREF, the basic unit of the coarse adjustment capacitor array includes NMOS tubes Mn7~Mn9, capacitors C4 and C5, a total of 5 groups; the basic unit of the medium adjustment capacitor array includes PMOS tubes Mp1 and Mp2, a total of 5 groups; the basic unit of the fine adjustment capacitor array includes NMOS tubes Mn10~Mn13 and inverter INV1, a total of 4 groups; the basic unit of the current steering current source array includes PMOS tubes Mp3 and Mp4, a total of 9 groups.

[0042] The input end of L2 is connected to the power supply, and the output end is connected to VOUTP; the input end of L3 is connected to the power supply, and the output end is connected to VOUTN; the drain of Mn5 is connected to VOUTP, the gate is connected to VOUTN, and the source is connected to the drain of Mn14; the drain of Mn6 is connected to VOUTN, the gate is connected to VOUTP, and the source is connected to the drain of Mn14; the input end of C4 is connected to VOUTP, and the output end is connected to the drain of Mn8; the drain of Mn7 is connected to the drain of Mn8, the gate is connected to the coarse adjustment control word [0], and the source is connected to the ground; the gate of Mn8 is connected to the coarse adjustment control word [0], and the source is connected to the drain of Mn9; the gate of Mn9 is connected to the coarse adjustment control word, and the source is connected to the ground; the input end of C5 is connected to VOUTN, and the output end is connected to the source of Mn8. The gate of Mp1 is connected to the mid-adjustment control word [0], and the source, substrate and drain are all connected to VOUTP; the gate of Mp2 is connected to the mid-adjustment control word [0], and the source, substrate and drain are all connected to VOUTN; the gate of Mn10 is connected to VOUTP, and the source, substrate and drain are all connected to the fine-adjustment control word [0]; the gate of Mn11 is connected to VOUTN, and the source, substrate and drain are all connected to the fine-adjustment control word [0]; the input end of INV1 is connected to the fine-adjustment control word [0], and the output end is connected to the drain of Mn12; the gate of Mn12 is connected to VOUTP, and the source, substrate and drain are all connected to the drain of Mn13; The gate of Mn13 is connected to VOUTN, and the source, substrate and drain are all connected to the drain of Mn12; the gate of Mn14 is connected to the gate of Mn15, and the source is connected to the ground; the gate of Mn15 is connected to the drain, and the source is connected to the ground; the gate of Mp3 is connected to the current source control word [0], the drain is connected to the drain of Mn15, and the source is connected to the drain of Mp4; the gate of Mp4 is connected to the gate of Mp6, and the source is connected to the power supply; the gate of Mp5 is connected to the quenching signal, the drain is connected to the gate of Mp6, and the source is connected to the power supply; the drain of Mp6 is connected to the positive end of IREF, and the source is connected to the power supply; the negative end of IREF is connected to the ground. The digitally controlled oscillator uses a digitally controlled switched capacitor array to achieve frequency tuning, and works as a super-regenerative oscillator in the receiving mode, which solves the frequency drift problem caused by charge leakage of traditional voltage-controlled capacitors. The fine-tuning capacitor array uses a one-bit control word to control two pairs of MOS capacitors to achieve a capacitance change smaller than the minimum size of the process library, thereby improving the frequency resolution. The tail current of the digital controlled oscillator is controlled by a 9-bit current rudder digital-to-analog converter. In the calibration mode and the transmission mode, the quenching signal is at a high level, and the tail current of the oscillator is a constant level current; in the receiving mode, the quenching signal is a square wave signal far lower than the oscillator frequency, and the tail current of the oscillator is also approximately a square wave. The oscillator uses the same tail current control circuit in the calibration mode and the receiving mode to ensure the consistency of the tail current accuracy, thereby reducing the frequency calibration error.

[0043] like Figure 5 As shown, in the above embodiment of the present invention, the envelope detector includes NMOS tubes Mn16 to Mn29, PMOS tubes Mp7 and Mp8, and capacitor C6. Among them, the DC load array includes Mn25, Mn26, Mn28 and Mn29, a total of 2 groups. The input is VOUTP, VOUTN and the amplitude modulation control signal, the bias current is IB_ED, and the output is ED_OUTP, ED_OUTN1 and ED_OUTN2.

[0044] The gate of Mn16 is connected to VOUTP, the drain is connected to the power supply, and the source is connected to ED_OUTP; the gate of Mn17 is connected to VOUTN, the drain is connected to the power supply, and the source is connected to ED_OUTP; the gate of Mn18 is connected to the gate of Mn19, the drain is connected to ED_OUTP, and the source is connected to ground; the input end of C6 is connected to ED_OUTP, and the output end is connected to ground; the source of Mn19 is connected to ground; the gate of Mp7 is connected to ED_OUTP, the drain is connected to the drain of Mn19, and the source is connected to IB_ED; the gate of Mp8 is connected to the drain of Mn21, the drain is connected to the drain of Mn20, and the source is connected to IB_ED; the gate and drain of Mn20 are connected to the gate of Mn21, and the source is connected to ground; the source of Mn21 The gate and drain of Mn22 are connected to the power supply, and the source is connected to the gate of Mp8; the gate and drain of Mn23 are connected to the power supply, and the source is connected to the gate of Mp8; the gate of Mn24 is connected to the gate of Mn21, the drain is connected to the source of Mn22, and the source is connected to the ground; the gate and drain of Mn25 are connected to the amplitude modulation control signal, and the source is connected to ED_OUTN1; the gate and drain of Mn26 are connected to the amplitude modulation control signal, and the source is connected to ED_OUTN1; the gate of Mn27 is connected to the gate of Mn20, the drain is connected to the source of Mn28, and the source is connected to the ground; the gate and drain of Mn28 are connected to the power supply, and the source is connected to ED_OUTN2; the gate and drain of Mn29 are connected to the power supply, and the source is connected to ED_OUTN2. The input end of the envelope detector is a source follower composed of Mn16 and Mn17, wherein Mn16 and Mn17 work in the subthreshold region, and Mn17 acts as a MOS current source. The time difference between Mn15 and Mn16 and Mn17 in charging and discharging capacitor C6 is used to extract the oscillator envelope. The differential amplifier composed of Mp7, Mp8, Mn19 and Mn20 can improve the gain of the envelope detector and shorten the settling time. Mn21 to Mn29 form a voltage replication circuit, which is output to the subsequent comparator as a threshold voltage.

[0045] like Figure 6As shown, in the above embodiment of the present invention, the differential to single-ended circuit includes NMOS tubes Mn30 and Mn31, PMOS tube Mp9, capacitors C9 and C10, resistors R3 and R4, input signals are VOUTP and VOUTN, bias voltages are VA, VB2 and VB3, and the output signal is Vsig.

[0046] The gate of Mp9 is connected to VA, the drain is connected to the drain of Mn31, and the source is connected to the power supply; the input of C10 is connected to VOUTP, and the output is connected to the gate of Mn31; the input of R4 is connected to VB2, and the output is connected to the gate of Mn31; the source and substrate of Mn31 are connected to Vsig; the input of C9 is connected to VOUTN, and the output is connected to the gate of Mn30; the input of R3 is connected to VB3, and the output is connected to the gate of Mn30; the drain of Mn30 is connected to Vsig, and the source and substrate are connected to the ground. Mn30 and Mn31 need to be implemented using a deep well process to ensure that the threshold voltages are equal, so as to obtain good balance. C9 and C10 are DC blocking capacitors, and R3 and R4 are bias resistors. Mp9 is a switch that controls the differential to single-ended circuit to be closed in non-transmitting mode.

[0047] like Figure 7 As shown, further, in the above embodiment of the present invention, the power amplifier includes an inductor L4, an NMOS tube Mn33, and a capacitor C12, and the power amplifier array unit includes a capacitor C11, a resistor R5, and an NMOS tube Mn32, a total of three groups. The input signal is Vsig, the bias voltage is VB6, and the output signal is VTX; the power amplifier array bias voltage is VB5, a total of three groups.

[0048] The input end of L4 is connected to the power supply, and the output end is connected to VTX; the gate of Mn33 is connected to VB6, the drain is connected to VTX, and the source is connected to the drain of Mn32; the input end of C12 is connected to VTX, and the output end is connected to the ground; the input end of C11 is connected to Vsig, and the output end is connected to the gate of Mn32; the input end of R5 is connected to VB5, and the output end is connected to the gate of Mn32; the source of Mn32 is grounded. C11 is a DC blocking capacitor, R5 is a bias resistor, L4 is a choke inductor, and C12 is an output impedance matching capacitor. Mn32 and Mn33 form a cascode power amplifier. In the transmission mode, the control of the output signal power by the transmission data signal is realized through three groups of gain units composed of Mn32, C11 and R5.

[0049] like Figure 8As shown, further, in the above embodiment of the present invention, the frequency calibration / control circuit module includes a lookup table, a three-to-one data selector, a digital comparator, a state machine, a 16-bit counter, a divider, a clock, a mode switch, and a coarse / medium / fine digital code generation circuit. The input signals are the channel selection code, the reference frequency, the reset signal, the amplitude modulation feedback signal, and the oscillator output, and the output signals are the amplitude modulation control signal, the coarse control word, the medium control word, and the fine control word.

[0050] The input end of the lookup table is connected to the channel selection code, and the output end is connected to the input end of the three-selection data selector; the output end of the three-selection data selector is connected to the input end of the digital comparator, and the clock module provides the clock signal of each small module; the input end of the digital comparator is connected to the output end of the 16-bit counter and the clock signal, and the output end is connected to the input end of the state machine; the input end of the state machine is connected to the clock signal, and the output end is connected to the coarse adjustment / medium adjustment / fine adjustment digital code generation circuit; the output end of the coarse adjustment / medium adjustment / fine adjustment digital code generation circuit is connected to the capacitor array of the digital control oscillator; the input signal of the clock circuit is the reference frequency and the reset signal, and the output end is connected to each digital circuit; the input end of the mode switching circuit is connected to the amplitude modulation feedback signal, and the output signal is the amplitude modulation control signal. The frequency calibration / control module is used to realize the frequency tuning of the digital control oscillator, and control the sensitivity calibration / automatic amplitude control loop to work together. The lookup table receives the channel selection code and generates reference channel codes corresponding to three frequency accuracies. Then the clock module controls the three-selection data selector to select the required reference channel code according to the current working mode. At the same time, the oscillator outputs the digital code generated by the two-frequency division and the 16-bit counter. The digital comparator compares the reference channel code with the digital code obtained by counting. The state machine processes the comparison result and controls the coarse adjustment / medium adjustment / fine adjustment digital code generation circuit to output the control word of the corresponding mode. The mode switching circuit is used to control the switching frequency calibration accuracy and the switching of frequency modulation and amplitude modulation.

[0051] like Fig. 9 As shown, in the above embodiment of the present invention, the sensitivity calibration / automatic amplitude control module includes an averager, a numerical comparator, a two-choice data selector, a state machine, a dynamic successive approximation circuit, and a current steering digital-to-analog converter. The input signal is the comparator input and the amplitude modulation control signal, and the output signal is the amplitude modulation feedback signal and the oscillator tail current.

[0052] The averager input signal is the comparator output, and the output four-bit digital code is connected to the input end of the numerical comparator; the output end of the numerical comparator is connected to the input end of the two-choice data selector; the other input end of the two-choice data selector is connected to the comparator output, and the output end is connected to the state machine input end; the state machine output end is connected to the dynamic successive approximation circuit input end; the dynamic successive approximation circuit outputs a 9-bit digital code connected to the current steering digital-to-analog converter input end; the digital-to-analog converter output end is connected to the tail current input end of the digital control oscillator. In the receiving mode of the sensitivity calibration / amplitude control module, the receiver output passes through the averager circuit to generate a 4-bit digital code, which is compared with 1000 in the numerical comparator, and the state machine outputs the comparison result to the dynamic successive approximation module, thereby generating a 9-bit digital code to control the current steering digital-to-analog converter to generate the required current. In the calibration mode of the sensitivity calibration / amplitude control module, the averager and the numerical comparator do not work, and the receiver output signal is directly input into the state machine to generate a control signal to control the dynamic successive approximation module to generate a 9-bit digital code, thereby controlling the current steering digital-to-analog converter to generate the oscillator tail current. The advantage of the sensitivity calibration / amplitude control module is that it ensures that the accuracy of the tail current control circuit in the calibration mode and the receiving mode is consistent, thereby reducing the frequency calibration error.

[0053] Fig.10 The timing diagram of the frequency calibration / control circuit module and the sensitivity calibration / amplitude control module working together in the calibration mode. In the calibration mode, the frequency is coarsely adjusted first, followed by the amplitude coarse adjustment, the frequency mid-adjustment, the amplitude fine adjustment and the frequency fine adjustment. The signals from top to bottom are the reference frequency, the coarse / mid-adjustment clock, the fine adjustment clock, the amplitude modulation control signal and the amplitude modulation feedback signal, the coarse adjustment control word, the mid-adjustment control word, the fine adjustment control word and the oscillator oscillation frequency. The frequency calibration method can solve the problem of mutual influence between frequency adjustment and amplitude adjustment in traditional frequency calibration, and improve the calibration accuracy.

[0054] The above is only a preferred embodiment of the present invention. It should be pointed out that the protection scope of the present invention cannot be limited to this. Without departing from the principle of the present invention, ordinary technicians in this technical field can also make several improvements and modifications, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A multi-channel adaptive calibration super regenerative transceiver, characterized in that: It includes a single-pole double-throw switch, a low-noise amplifier, a power amplifier, a differential-to-single-ended circuit, a digitally controlled oscillator, an envelope detector, a comparator, a frequency calibration / control circuit module, and a sensitivity calibration / automatic amplitude control module; The input end of the single-pole double-throw switch is connected to an external antenna, and the output end of the single-pole double-throw switch is respectively connected to the input end of a low-noise amplifier and the output end of a power amplifier; the output end of the low-noise amplifier is connected to the output end of a digitally controlled oscillator; the input end of the power amplifier is connected to the output end of a differential-to-single-ended circuit; the input end of the differential-to-single-ended circuit is connected to the output end of a digitally controlled oscillator; the output end of the digitally controlled oscillator is respectively connected to the input end of an envelope detector and the input end of a frequency calibration / control circuit; the output end of the envelope detector is connected to the input end of a demodulation circuit; the output end of the demodulation circuit is connected to the input end of a sensitivity calibration circuit, and a comparator generates a system output signal; the output end of the sensitivity calibration / automatic amplitude control module is connected to the tail current input end of the digitally controlled oscillator; the output end of the frequency calibration / control circuit module is connected to the capacitor array of the digitally controlled oscillator; The multi-channel adaptive calibration super-regenerative transceiver has three feedback loops: a frequency calibration loop, an amplitude calibration loop and a sensitivity calibration loop. The frequency calibration loop is composed of a digitally controlled oscillator and a frequency calibration / control circuit module, and the sensitivity calibration loop is composed of a digitally controlled oscillator, an envelope detector, a comparator and a sensitivity calibration / amplitude control module. In the calibration mode, the frequency calibration loop and the amplitude calibration loop work together to calibrate the frequency and amplitude of the digitally controlled oscillator; when the calibration is completed, the system decides to enter the receiving mode or the transmitting mode according to the control signal; in the receiving mode, the frequency calibration loop is closed, and the amplitude calibration loop is switched to the sensitivity calibration loop to realize dynamic calibration of the receiver sensitivity without interrupting the receiving state; in the transmitting mode, all loops are closed and reopened when a channel change is detected.

2. The multi-channel adaptive calibration super regenerative transceiver according to claim 1, characterized in that: The calibration mode uses an amplitude calibration loop and a frequency calibration loop to work together to achieve frequency calibration. The loop working order is frequency coarse adjustment, amplitude coarse adjustment, frequency medium adjustment, amplitude fine adjustment and frequency fine adjustment. During the calibration process, it is ensured that the calibration range of the next stage covers the frequency or amplitude deviation caused by the previous stage.

3. The multi-channel adaptive calibration super regenerative transceiver according to claim 1, characterized in that: The low noise amplifier includes NMOS tubes Mn1-Mn4, resistors R1 and R2, capacitors C1-C3, inductor L1, input signal VRX, output signals VOUTP and VOUTN, bias voltages VB1 and VB2, The input end of L1 is connected to VRX, and the output end is connected to ground; the input end of C1 is connected to VRX, and the output end is connected to ground; the source of Mn1 is connected to VRX, the gate is connected to the input end of C3, and the drain is connected to the source of Mn2; the gate of Mn2 is connected to VB2, and the drain is connected to VOUTP; the input end of C2 is connected to VRX, and the output end is connected to the gate of Mn3; the source of Mn3 is connected to ground, and the drain is connected to the source of Mn4; the gate of Mn4 is connected to VB2, and the drain is connected to VOUTN; the output end of C3 is connected to ground; the input end of R1 is connected to VB1, and the output end is connected to the gate of Mn1; the input end of R2 is connected to VB1, and the output end is connected to the gate of Mn3.

4. The multi-channel adaptive calibration super regenerative transceiver according to claim 1, characterized in that: The tail current bias circuit of the digital controlled oscillator includes NMOS tubes Mn5, Mn6, Mn14 and Mn15, PMOS tubes Mp5 and Mp6, inductors L2 and L3, a reference current source IREF, a coarse adjustment capacitor array basic unit includes NMOS tubes Mn7-Mn9, capacitors C4 and C5, a total of 5 groups; a medium adjustment capacitor array basic unit includes PMOS tubes Mp1 and Mp2, a total of 5 groups; a fine adjustment capacitor array basic unit includes NMOS tubes Mn10-Mn13 and an inverter INV1, a total of 4 groups; a current steering current source array basic unit includes PMOS tubes Mp3 and Mp4, a total of 9 groups; The input end of L2 is connected to the power supply, and the output end is connected to VOUTP; the input end of L3 is connected to the power supply, and the output end is connected to VOUTN; the drain of Mn5 is connected to VOUTP, the gate is connected to VOUTN, and the source is connected to the drain of Mn14; the drain of Mn6 is connected to VOUTN, the gate is connected to VOUTP, and the source is connected to the drain of Mn14; the input end of C4 is connected to VOUTP, and the output end is connected to the drain of Mn8; the drain of Mn7 is connected to the drain of Mn8, the gate is connected to the coarse adjustment control word [0], and the source is connected to the ground; the gate of Mn8 is connected to the coarse adjustment control word [0], and the source is connected to the drain of Mn9; the gate of Mn9 is connected to the coarse adjustment control word, and the source is connected to the ground; the input end of C5 is connected to VOUTN, and the output end is connected to the source of Mn8; the gate of Mp1 is connected to the medium adjustment control word [0], and the source, substrate and drain are all connected to VOUTP; the gate of Mp2 is connected to the medium adjustment control word [0], and the source, substrate and drain are all connected to VOUTP. The gate of Mn10 is connected to VOUTP, and the source, substrate and drain are all connected to the fine-tuning control word [0]; the gate of Mn11 is connected to VOUTN, and the source, substrate and drain are all connected to the fine-tuning control word [0]; the input of INV1 is connected to the fine-tuning control word [0], and the output is connected to the drain of Mn12; the gate of Mn12 is connected to VOUTP, and the source, substrate and drain are all connected to The drain of Mn13 is connected; the gate of Mn13 is connected to VOUTN, and the source, substrate and drain are all connected to the drain of Mn12; the gate of Mn14 is connected to the gate of Mn15, and the source is connected to ground; the gate of Mn15 is connected to the drain, and the source is connected to ground; the gate of Mp3 is connected to the current source control word [0], the drain is connected to the drain of Mn15, and the source is connected to the drain of Mp4; the gate of Mp4 is connected to the gate of Mp6, and the source is connected to the power supply; The gate of Mp5 is connected to the quenching signal, the drain is connected to the gate of Mp6, and the source is connected to the power supply; the drain of Mp6 is connected to the positive end of IREF, and the source is connected to the power supply; the negative end of IREF is connected to the ground.

5. The multi-channel adaptive calibration super regenerative transceiver according to claim 1, characterized in that: The envelope detector includes NMOS tubes Mn16 to Mn29, PMOS tubes Mp7 and Mp8, and capacitor C6; wherein the DC load array includes Mn25, Mn26, Mn28 and Mn29, a total of 2 groups; the input is VOUTP, VOUTN and amplitude modulation control signal, the bias current is IB_ED, and the output is ED_OUTP, ED_OUTN1 and ED_OUTN2; The gate of Mn16 is connected to VOUTP, the drain is connected to the power supply, and the source is connected to ED_OUTP; the gate of Mn17 is connected to VOUTN, the drain is connected to the power supply, and the source is connected to ED_OUTP; the gate of Mn18 is connected to the gate of Mn19, the drain is connected to ED_OUTP, and the source is connected to ground; the input end of C6 is connected to ED_OUTP, and the output end is connected to ground; the source of Mn19 is connected to ground; the gate of Mp7 is connected to ED_OUTP, the drain is connected to the drain of Mn19, and the source is connected to IB_ED; the gate of Mp8 is connected to the drain of Mn21, the drain is connected to the drain of Mn20, and the source is connected to IB_ED; the gate and drain of Mn20 are connected to the gate of Mn21, and the source is connected to ground; the source of Mn21 The gate and drain of Mn22 are connected to the power supply, and the source is connected to the gate of Mp8; the gate and drain of Mn23 are connected to the power supply, and the source is connected to the gate of Mp8; the gate of Mn24 is connected to the gate of Mn21, the drain is connected to the source of Mn22, and the source is connected to the ground; the gate and drain of Mn25 are connected to the amplitude modulation control signal, and the source is connected to ED_OUTN1; the gate and drain of Mn26 are connected to the amplitude modulation control signal, and the source is connected to ED_OUTN1; the gate of Mn27 is connected to the gate of Mn20, the drain is connected to the source of Mn28, and the source is connected to the ground; the gate and drain of Mn28 are connected to the power supply, and the source is connected to ED_OUTN2; the gate and drain of Mn29 are connected to the power supply, and the source is connected to ED_OUTN2.

6. The multi-channel adaptive calibration super regenerative transceiver according to claim 1, characterized in that: The differential-to-single-ended circuit includes NMOS tubes Mn30 and Mn31, PMOS tube Mp9, capacitors C9 and C10, resistors R3 and R4, input signals are VOUTP and VOUTN, bias voltages are VA, VB2 and VB3, and the output signal is Vsig; The gate of Mp9 is connected to VA, the drain is connected to the drain of Mn31, and the source is connected to the power supply; the input of C10 is connected to VOUTP, and the output is connected to the gate of Mn31; the input of R4 is connected to VB2, and the output is connected to the gate of Mn31; the source and substrate of Mn31 are connected to Vsig; the input of C9 is connected to VOUTN, and the output is connected to the gate of Mn30; the input of R3 is connected to VB3, and the output is connected to the gate of Mn30; the drain of Mn30 is connected to Vsig, and the source and substrate are connected to ground.

7. The multi-channel adaptive calibration super regenerative transceiver according to claim 1, characterized in that: The power amplifier includes an inductor L4, an NMOS tube Mn33, and a capacitor C12. The power amplifier array unit includes a capacitor C11, a resistor R5, and an NMOS tube Mn32, which are three groups in total. The input signal is Vsig, the bias voltage is VB6, and the output signal is VTX. The power amplifier array bias voltage is VB5, which is three groups in total. The input end of L4 is connected to the power supply, and the output end is connected to VTX; the gate of Mn33 is connected to VB6, the drain is connected to VTX, and the source is connected to the drain of Mn32; the input end of C12 is connected to VTX, and the output end is connected to the ground; the input end of C11 is connected to Vsig, and the output end is connected to the gate of Mn32; the input end of R5 is connected to VB5, and the output end is connected to the gate of Mn32; the source of Mn32 is grounded.

8. The multi-channel adaptive calibration super regenerative transceiver according to claim 1, characterized in that: The frequency calibration / control circuit module includes a lookup table, a three-to-one data selector, a digital comparator, a state machine, a 16-bit counter, a two-frequency divider, a clock, a mode switch, and a coarse / medium / fine adjustment digital code generation circuit; the input signals are a channel selection code, a reference frequency, a reset signal, an amplitude modulation feedback signal, and an oscillator output, and the output signals are an amplitude modulation control signal, a coarse adjustment control word, a medium adjustment control word, and a fine adjustment control word; The input end of the lookup table is connected to the channel selection code, and the output end is connected to the input end of the three-selection data selector; the output end of the three-selection data selector is connected to the input end of the digital comparator, and the clock module provides the clock signal of each small module; the input end of the digital comparator is connected to the output end of the 16-bit counter and the clock signal, and the output end is connected to the input end of the state machine; the input end of the state machine is connected to the clock signal, and the output end is connected to the coarse adjustment / medium adjustment / fine adjustment digital code generation circuit; The output end of the coarse / medium / fine adjustment digital code generating circuit is connected to the capacitor array of the digitally controlled oscillator; the input signal of the clock circuit is the reference frequency and the reset signal, and the output end is connected to each digital circuit; the input end of the mode switching circuit is connected to the amplitude modulation feedback signal, and the output signal is the amplitude modulation control signal.

9. The multi-channel adaptive calibration super regenerative transceiver according to claim 1, characterized in that: The sensitivity calibration / automatic amplitude control module includes an averager, a numerical comparator, a two-choice data selector, a state machine, a dynamic successive approximation circuit, and a current steering digital-to-analog converter; the input signal is the comparator input and the amplitude modulation control signal, and the output signal is the amplitude modulation feedback signal and the oscillator tail current; The averager input signal is the comparator output, and the output four-bit digital code is connected to the input of the numerical comparator; the output of the numerical comparator is connected to the input of a two-choice data selector; the other input of the two-choice data selector is connected to the comparator output, and the output is connected to the state machine input; the state machine output is connected to the dynamic successive approximation circuit input; the dynamic successive approximation circuit outputs a 9-bit digital code connected to the current steering digital-to-analog converter input; the digital-to-analog converter output is connected to the tail current input of the digitally controlled oscillator.

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