A resonant fiber-optic gyroscope signal processing system based on FPGA and ARM

Abstract

This invention provides a resonant fiber optic gyroscope signal processing system based on FPGA and ARM, including an A / D converter, an FPGA terminal, an ARM terminal, a D / A converter, and a resonant fiber optic gyroscope. The resonant fiber optic gyroscope includes a tunable semiconductor laser, an optical isolator, a beam splitter, a first phase modulator, a second phase modulator, a first circulator, a second circulator, a coupler, a fiber optic ring resonant cavity, a first photodetector, and a second photodetector. The A / D converter receives the photodetector signals from the gyroscope system; the D / A converter outputs the phase modulation signals and laser control signals; and the AXI bus protocol, UART protocol, and TLV protocol are used to control the FPGA output signals, transmit signals from the ARM terminal, and process the gyroscope output data. This invention allows for the control of required parameters and the acquisition, processing, and observation of gyroscope output signals on a host computer, simplifying the parameter debugging process and improving system debugging efficiency.

Description

Technical Field

[0001] This invention relates to the field of fiber optic gyroscope technology, and more specifically to a resonant fiber optic gyroscope signal processing system based on FPGA and ARM. Background Technology

[0002] A gyroscope is a device used to detect inertial angular motion, measuring the angular velocity and displacement of a vehicle. It has wide applications in military, aerospace, and guidance fields. Resonant fiber optic gyroscopes use a fiber optic ring resonant cavity as their core sensing element. Based on the Sagnac effect, they detect angular velocity by detecting the resonant frequency difference in the optical path. However, because the frequency difference signal is extremely weak, precise signal detection can be achieved by applying phase modulation and demodulation techniques as well as PID frequency locking technology.

[0003] By applying FPGA and ARM to the signal processing system of resonant fiber optic gyroscope, the input of photodetector signals of the gyroscope system is completed through A / D converter, and the output of phase modulation signals and laser control signals is completed through D / A converter. At the same time, the control of FPGA output signals, the transmission of ARM signals, and the processing of gyroscope output data are completed through AXI bus protocol, UART protocol, and TLV protocol. It is possible to realize the control of the required parameters and the acquisition, processing and observation of gyroscope output signals on the host computer, which facilitates system debugging. Summary of the Invention

[0004] This invention addresses the issues of control parameter adjustment and output data processing in resonant fiber optic gyroscope systems by establishing a resonant fiber optic gyroscope signal processing system based on FPGA and ARM. This simplifies the parameter debugging process in the system and provides convenience for researchers in the field.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] This invention discloses a resonant fiber optic gyroscope signal processing system based on FPGA and ARM, mainly comprising an A / D converter, an FPGA terminal, an ARM terminal, a D / A converter, and a resonant fiber optic gyroscope. The resonant fiber optic gyroscope is composed of the following components: a tunable semiconductor laser, an optical isolator, a beam splitter, a first phase modulator, a second phase modulator, a first circulator, a second circulator, a coupler, a fiber optic ring resonant cavity, a first photodetector, and a second photodetector.

[0007] The tunable semiconductor laser, the first phase modulator, and the second phase modulator are connected to the D / A converter, and the first photodetector and the second photodetector are connected to the A / D converter. The FPGA inputs and outputs signals through the A / D converter and the D / A converter, respectively. The FPGA sends data to the host computer through UART. The ARM communicates with the FPGA through the AXI protocol and sends control parameters through the serial port.

[0008] The FPGA-side IP core structure includes an AXI module, a PL control parameter adjustment module, a waveform control module, a first modulation signal generation module, a second modulation signal generation module, a first demodulation module, a second demodulation module, a first filtering module, a second filtering module, a PID control module, a laser voltage control module, and a UART transmission module.

[0009] The implementation steps of this invention are as follows:

[0010] Step 1: The linearly transformed voltage signal generated by the FPGA is converted into D / A output 3 by the D / A converter and input to the tunable semiconductor laser to realize the frequency sweep function of the tunable semiconductor laser.

[0011] Step 2: The phase modulation signal 1 and phase modulation signal 2 generated by the FPGA are converted into D / A output 1 and D / A output 2 by the D / A converter, and then input to the first phase modulator and the second phase modulator.

[0012] Step 3: The laser signal output from the tunable semiconductor laser is input to the beam splitter via an optical isolator, splitting the beam into two beams with equal intensity and frequency. Beam 1 is input to the first phase modulator for modulation. The modulated optical signal 1 is input from end 1 and output from end 2 of the first circulator, and then enters the fiber optic ring resonator through a 95:5 coupler to propagate counterclockwise around the cavity. It is then input to end 2 of the second circulator through the coupler and output from end 3 of the second circulator to the first photodetector, where it is converted into electrical signal 1. Beam 2 is input to the second phase modulator for modulation. The modulated optical signal 2 is input from end 1 and output from end 2 of the second circulator, and then enters the fiber optic ring resonator through the coupler to propagate clockwise around the cavity. It is then input to end 2 of the first circulator through the coupler and output from end 3 of the first circulator to the second photodetector, where it is converted into electrical signal 2.

[0013] Step 4: Electrical signals 1 and 2 are converted into A / D input 1 and A / D input 2 by an A / D converter and then input to the FPGA for processing to obtain the required output signal.

[0014] Step 5: The voltage control signal obtained by the FPGA in Step 4 is output by the D / A converter to obtain D / A output 3 and input to the tunable semiconductor laser end to complete the locking of the frequency of the tunable semiconductor laser with the resonant frequency of one optical wave of the fiber ring resonator.

[0015] Step 6: After the system enters the locked state, the host computer can observe the waveform changes of the gyroscope speed and other signals in real time.

[0016] Step 7: When control parameters need to be adjusted, the adjusted parameters are input to the ARM terminal via the serial port transmission assistant using the TLV protocol to complete real-time control of the system.

[0017] The beneficial effects of this invention are as follows:

[0018] This invention provides a resonant fiber optic gyroscope signal processing system based on FPGA and ARM, which realizes the generation of phase modulation signals on the FPGA side, the processing of output signals of the resonant fiber optic gyroscope, the transmission of system control signals on the ARM side, and the real-time observation of output signals by the host computer, thereby improving the debugging efficiency of the system. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the system structure of a resonant fiber optic gyroscope signal processing system based on FPGA and ARM according to the present invention.

[0020] Figure 2 This is a schematic diagram of the IP core used in the FPGA of this invention.

[0021] Figure 3 This is a schematic diagram of the data processing flow from the FPGA serial port output to the host computer.

[0022] Figure 4 This is a schematic diagram showing the real-time waveform display of the gyroscope output signal on the host computer.

[0023] Figure 5 A flowchart illustrating the process of sending control parameters.

[0024] List of reference numerals in the attached diagram:

[0025] 1-Tunable semiconductor laser, 2-Optical isolator, 3-Optical splitter, 4-First phase modulator, 5-Second phase modulator, 6-First circulator, 7-Second circulator, 8-Coupler, 9-Fiber optic ring resonator, 10-First photodetector, 11-Second photodetector. Detailed Implementation

[0026] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] like Figure 1 As shown, this invention provides a resonant fiber optic gyroscope signal processing system based on FPGA and ARM, mainly including an A / D converter, an FPGA terminal, an ARM terminal, a D / A converter, and a resonant fiber optic gyroscope. The resonant fiber optic gyroscope is composed of the following components: a tunable semiconductor laser 1, an optical isolator 2, a beam splitter 3, a first phase modulator 4, a second phase modulator 5, a first circulator 6, a second circulator 7, a coupler 8, a fiber optic ring resonant cavity 9, a first photodetector 10, and a second photodetector 11. The tunable semiconductor laser 1, the first phase modulator 4, and the second phase modulator 5 are connected to a D / A converter to perform the following functions: the phase modulation signal output from the FPGA is input to the first phase modulator 4 and the second phase modulator 5 through the D / A converter; the laser control signal output from the FPGA is input to the tunable semiconductor laser 1 through the D / A converter to control the laser frequency. The first photodetector 10 and the second photodetector 11 are connected to the A / D converter to realize the conversion of optical signal → electrical signal → digital signal, and input the data to the FPGA for data processing. The processed data is then input to the host computer via the UART protocol for real-time observation. The ARM terminal can realize real-time debugging of the control parameters in the FPGA system.

[0028] like Figure 2 The IP core modules used on the FPGA side include: AXI module, PL control parameter adjustment module, waveform control module, first modulation signal generation module, second modulation signal generation module, first demodulation module, second demodulation module, first filtering module, second filtering module, PID control module, laser voltage control module, and UART transmission module.

[0029] Combination Figure 2 In the embodiments provided by this invention, the process of FPGA and ARM implementing signal processing of resonant fiber optic gyroscope is as follows:

[0030] Step 1: The voltage signal generated by the linear transformation of the FPGA is converted into D / A output 3 by the D / A converter and input to the tunable semiconductor laser 1 to realize the frequency sweep function of the tunable semiconductor laser 1.

[0031] Step 2: The phase modulation signal 1 and phase modulation signal 2 generated by the FPGA are converted into D / A output 1 and D / A output 2 by the D / A converter, and then input to the first phase modulator 4 and the second phase modulator 5.

[0032] Specifically, the phase modulation signals that can be generated in the FPGA include arbitrarily frequency-adjustable sine waves, square waves, sawtooth waves, and triangle waves. Sine waves are generated using the Cordicip core; by adjusting the input values ​​of the Cordicip core, the frequency and initial phase of the sine wave signal can be controlled. Square waves, sawtooth waves, and triangle waves achieve frequency adjustment through an accumulation function. Real-time adjustment of the phase modulation waveform's frequency and initial phase can be achieved through communication between the ARM and FPGA ends; the voltage of the phase modulation waveform can be adjusted by adjusting the sliding rheostat at the D / A output circuit.

[0033] Step 3: The laser signal output from the tunable semiconductor laser 1 is input to the beam splitter 3 via the optical isolator 2, splitting the beam into two beams with equal intensity and frequency. Beam 1 is input to the first phase modulator 4 for modulation. The modulated optical signal 1 is input from end 1 and output from end 2 of the first circulator 6, and then enters the fiber optic ring resonator 9 via the 95:5 coupler 8 to propagate around the cavity in a counterclockwise direction. It is then input to end 2 of the second circulator 7 via the coupler 8, and output from end 3 of the second circulator 7 to the first photodetector 10 to be converted into electrical signal 1. Beam 2 is input to the second phase modulator 5 for modulation. The modulated optical signal 2 is input from end 1 and output from end 2 of the second circulator 7, and then enters the fiber optic ring resonator 9 via the coupler 8 to propagate around the cavity in a clockwise direction. It is then input to end 2 of the first circulator 6 via the coupler 8, and output from end 3 of the first circulator 6 to the second photodetector 11 to be converted into electrical signal 2.

[0034] Step 4: Electrical signals 1 and 2 are converted into A / D input 1 and A / D input 2 by an A / D converter and then input to the FPGA for processing to obtain the required output signal.

[0035] The specific signal processing procedure is as follows: A / D input 1 and A / D input 2 are input to the FPGA terminal and demodulated by a signal that is in phase and frequency with the phase modulation signal. The demodulated signal is then filtered by a four-stage cascaded filter. One of the processed signals is used as an error signal and input to the PID control module to obtain a control signal. The control signal is then input to the scanning voltage control module of the tunable semiconductor laser 1 to control the output voltage signal in step 1. Simultaneously, the two demodulated signals, the difference between the two demodulated signals, the voltage control signal, and the error signal are input to the serial port via the UART protocol and transmitted to the host computer for observation, facilitating real-time adjustment of system parameters.

[0036] The output signals are all 32-bit signed data, with a frame format of: start bit 0, 8 data bits, end flag bit 1, and no parity bit. Each 32-bit data is divided into 4 frames for transmission, in the following order: bits 24-31, bits 16-23, bits 8-15, and bits 0-7. The format and order of each data group are: 4 start frames AAAAAAAA, 4 demodulated signal frames (1 frame), 4 demodulated signal frames (2 frames), 4 demodulated signal difference frames, 4 voltage control signal frames, 4 error signal frames, and 4 end frames EEEEEEEE. The transmission frequency trans_fre is defined as the frequency at which each data group is acquired. During the acquisition of each data group, the data validity signal tx_data_valid is set to 0, and after data acquisition is complete, tx_data_valid is set to 1. Simultaneously, the data transmission rate is defined by adjusting the baud rate. The state machine for data transmission is defined as follows:

[0037] S_IDLE: Data transmission initialization state. When tx_data_valid is 1, the parameters within the FPGA are assigned values, and the state machine enters the S_SEND state; when tx_data_valid is 0, it remains in the S_IDLE state.

[0038] S_SEND: Data transmission status. Each group of data is transmitted according to the baud rate, for a total of 28 data frames. After all frames of the current data group have been transmitted, the system returns to the S_IDLE state, waiting for the next group of data to be valid.

[0039] like Figure 3 As shown, after the above data is transmitted to the host computer via serial port, it is deframed by MATLAB: the baud rate in MATLAB is set to be the same as that on the FPGA side; for the data sent to the host computer via serial port, the frame header AA AAAAAA is first checked; when the frame header is detected, the frame header and frame tail are removed, and the received data is converted into a frame received by the anonymous host computer; the frame header, target address, function code and a set of data bytes 20 are sent to the anonymous host computer; then, the 5 data bytes are sent to the anonymous host computer in sequence in the low byte-first format; finally, after the corresponding baud rate is set on the anonymous host computer, the real-time output waveforms of the 5 signals can be observed in real time.

[0040] The above control parameter settings are only for this embodiment. In actual system applications, the signals and quantities to be observed can be adjusted, and the above code can be adjusted accordingly.

[0041] Step 5: The voltage control signal obtained by the FPGA in Step 4 is output by the D / A converter to obtain D / A output 3 and input to the tunable semiconductor laser 1 to complete the locking of the frequency of the tunable semiconductor laser 1 with the resonant frequency of one optical wave of the fiber ring resonator 9.

[0042] Step 6: After the system enters the locked state, the host computer can observe the waveform changes of the gyroscope speed and other signals in real time.

[0043] Step 7: When control parameters need to be adjusted, the adjusted parameters are input to the ARM terminal via the serial port transmission assistant using the TLV protocol to complete real-time control of the system.

[0044] Specifically, the FPGA-side system parameters controllable by the ARM side include: the modulation waveform selection signal Wave_control, the clockwise and counterclockwise modulation signal frequencies Modu_fre_cw and Modu_fre_ccw, the clockwise and counterclockwise modulation signal initial phases Modu_phase_cw and Modu_phase_ccw, the clockwise and counterclockwise demodulation signal frequencies Demodu_fre_cw and Demodu_fre_ccw, the PID controller control parameters Kp, Ki, and Kd, and the clockwise optical path four-stage cascaded filter parameters B10_cw, B11_cw, and B12_cw. A11_cw, A12_cw, B20_cw, B21_cw, B22_cw, A21_cw, A22_cw, parameters of the counterclockwise optical path four-stage cascaded filter B10_ccw, B11_ccw, B12_ccw, A11_ccw, A12_ccw, B20_ccw, B21_ccw, B22_ccw, A21_ccw, A22_ccw, transmission frequency Trans_Fre, serial communication baud rate Baud_Rate, transmission end signal trans_end, and FPGA reset signal PL_rst. These parameters are initially set on the FPGA side, and the ARM side, based on the TLV protocol, can realize the real-time adjustment and transmission of the above parameters, as follows:

[0045] The system achieves high-speed communication and data exchange between the ARM and FPGA sides via the AXI bus protocol. The FPGA side first uses the AXI protocol as its architecture, defining custom IP cores for receiving and transmitting data, and specifying the storage addresses and initial values ​​of the aforementioned parameters. When control parameters need adjustment, they are adjusted using a serial port debugging assistant with the TLV protocol input frame format shown below:

[0046] Packet header value AA AAAAAA + total buffer length (including packet header length, packet tail length, and data pool length) + TLV + data + packet tail value EE EEEEEE.

[0047] The TLV format is: ID number + data type + data length. The ID number is defined according to the data type, including waveform selection, PID, clockwise signal filtering, counter-clockwise signal filtering, modulation frequency, demodulation frequency, modulation phase, and communication parameters. The data type includes unsigned 1-byte integer, unsigned 2-byte integer, unsigned 4-byte integer, and unsigned 8-byte integer. The data length is the number of parameters to be transmitted in this data set.

[0048] In one specific embodiment, a set of transmitted data is defined as: AAAAAAAA 000000200000000200000004 00000002 000003E8 0000000A EEEEEEEE. The second to seventh bytes respectively represent the total buffer length as 32 bits, the PID function ID number as 2, the data type as an unsigned 4-byte integer, the parameters to be transmitted in this set of data as 2, the Kp parameter value as 1000, and the Ki parameter value as 10.

[0049] The system allocates a certain amount of space to store the serial port input in the form of a circular queue. After the ARM receives the data from the serial port, it performs frame decoding. When the packet header value is detected, the subsequent data is extracted until the packet tail value is detected. Then, the address is performed according to the information of the extracted data, and the parameter value is stored in the corresponding address in the DMA mode. After the storage is completed, the ARM simultaneously stores the high-order write_end signal in the specified address.

[0050] When the FPGA detects the high-order `write_end` signal stored via the AXI bus, it enters data transmission mode, extracts all data values ​​corresponding to the specified address, uses them as outputs of the PL control parameter adjustment IP core, and inputs them to the corresponding IP core whose parameters need modification. After data transmission is complete, it outputs the high-order `trans_end` signal to the GPIO interface to inform the ARM that this data reception is finished. At this time, the ARM sends a control parameter modification completion message to the serial port and displays it in the serial port debugging assistant window, indicating that the control parameter modification process is complete. The flowchart is as follows. Figure 5 As shown.

[0051] The above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description, which do not affect the essential content of the present invention. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A resonant fiber optic gyroscope signal processing system based on FPGA and ARM, characterized in that, The system includes an A / D converter, an FPGA, an ARM, a D / A converter, and a resonant fiber optic gyroscope. The resonant fiber optic gyroscope is composed of the following components: a tunable semiconductor laser (1), an optical isolator (2), a beam splitter (3), a first phase modulator (4), a second phase modulator (5), a first circulator (6), a second circulator (7), a coupler (8), a fiber optic ring resonant cavity (9), a first photodetector (10), and a second photodetector (11). Among these, the tunable semiconductor laser (1), the first phase modulator (4), and the second phase modulator (5) are connected to the D / A converter, and the first photodetector (10) and the second photodetector (11) are connected to the A / D converter. The FPGA inputs and outputs signals through the A / D converter and the D / A converter, respectively. The FPGA sends data to the host computer via UART. The ARM communicates with the FPGA via the AXI protocol and sends control parameters via a serial port. The FPGA terminal transmits data to the host computer via UART, specifically as follows: The two demodulated signals, their difference, voltage control signal, and error signal, processed by the FPGA, are transmitted via serial communication using the UART protocol to the serial port for observation by the host computer. The format and order of each data set are as follows: 4 start frames (AA AAAAAA), 4 demodulated signal frames (1 frame), 4 demodulated signal frames (2 frames), 4 demodulated signal difference frames, 4 voltage control signal frames, 4 error signal frames, and 4 end frames (EE EEEEEE). The transmission frequency is defined, and the data transmission rate is defined by adjusting the baud rate. After the above data is transmitted to the host computer via serial port, it is deframed by MATLAB: MATLAB is set to the same baud rate as the FPGA; for data sent to the host computer via serial port, the frame header AA AAAAAA is first checked; when the frame header is detected, the frame header and frame tail are removed, and the received data is converted into a frame received by the anonymous host computer; the frame header, target address, function code, and a set of 20 data bytes are sent to the anonymous host computer; then, the 5 data bytes are sent to the anonymous host computer in sequence with the least significant byte first; finally, after setting the corresponding baud rate on the anonymous host computer, the real-time output waveforms of the 5 signals can be observed in real time. The ARM terminal communicates with the FPGA terminal via the AXI protocol and transmits control parameters via a serial port, specifically as follows: The FPGA architecture is based on the AXI protocol. Custom IP cores for receiving and transmitting data are defined, specifying the storage addresses and initial values ​​of the required control parameters. When control parameters need adjustment, they are adjusted using a serial port debugging assistant with the TLV protocol and the frame format shown below: Packet header value AA AAAAAA + Total buffer length + TLV + Data + Packet tail value EE EEEEEE; where the total buffer length includes the packet header length, packet tail length, and data pool length; The system allocates a certain space to store the serial port input in the form of a circular queue. After the ARM receives the data from the serial port, it performs frame decomposition. When the packet header value is detected, the subsequent data is extracted until the packet tail value is detected. Then, the address is performed according to the information of the extracted data, and the parameter value is stored in the corresponding address in the DMA mode. After the storage is completed, the ARM simultaneously stores the high-order write_end signal in the specified address. When the FPGA detects the high-order write_end signal stored via the AXI bus, it enters the data transmission state, extracts all data values ​​corresponding to the specified address, uses them as PL control parameters to adjust the output of the IP core, and inputs them to the corresponding IP core whose parameters need to be modified. After the data transmission is complete, it outputs the high-order trans_end signal to the GPIO interface to inform the ARM that the data reception is over. At this time, the ARM sends the control parameter modification completion information to the serial port and displays it in the serial port debugging assistant window, indicating that the control parameter modification is complete.

2. The resonant fiber optic gyroscope signal processing system based on FPGA and ARM according to claim 1, characterized in that, The IP core components on the FPGA side include: The system includes an AXI module, a PL control parameter adjustment module, a waveform control module, a first modulation signal generation module, a second modulation signal generation module, a first demodulation module, a second demodulation module, a first filtering module, a second filtering module, a PID control module, a laser voltage control module, and a UART transmission module.

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