Bus arbitration method, electronic device, and graphics processor
By reallocating memory access permissions when the data at the end of the access request aligns with the memory page boundary in the GPU, the memory access efficiency problem caused by frequent switching is solved, and more efficient memory access is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING XIANGDIXIAN COMPUTING TECH CO LTD
- Filing Date
- 2023-01-12
- Publication Date
- 2026-06-26
AI Technical Summary
Existing bus arbitration strategies result in decreased memory access efficiency due to frequent memory page switching when multiple master devices access memory, with a particularly significant impact on GPU memory access.
By determining whether the data at the end of the current access request of the target master device is aligned with the storage boundary of the target memory page, if they are aligned, memory access permissions are reallocated, reducing the number of memory page switches and improving memory access efficiency.
It significantly reduces the number of memory page switches, improves memory access efficiency, and especially avoids introducing other negative effects during GPU memory access.
Smart Images
Figure CN116303158B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of data processing technology, specifically to a bus arbitration method, electronic device, and graphics processor. Background Technology
[0002] In a CPU, when multiple master devices access memory, the bus schedules their access requests to select one master device to allocate memory access permissions. Existing scheduling strategies focus on ensuring timely responses to each master device's access requests. These strategies include round-robin scheduling and QoS-based scheduling. In round-robin scheduling, access permissions are automatically passed to the next master device after the current master device's access request is completed. In QoS-based scheduling, higher-priority master devices are given priority access. However, since the addresses accessed by each master device are typically located in different memory pages, frequent switching of master device access permissions inevitably leads to frequent memory page switching, thus impacting memory access efficiency. Summary of the Invention
[0003] The purpose of this disclosure is to provide a bus arbitration method, electronic device, and graphics processor designed to improve memory access efficiency.
[0004] According to one aspect of this disclosure, a bus arbitration method is provided, the method comprising:
[0005] Determine whether the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page; the target master device is the master device currently allocated memory access permissions among multiple master devices, the last data is the last data in the data segment accessed by the current access request, and the target memory page is the memory page currently being accessed;
[0006] Memory access permissions are reallocated if the data at the end aligns with the storage boundary of the target memory page.
[0007] In one feasible implementation of this disclosure, determining whether the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page includes:
[0008] Based on the access address information and the size of the accessed data carried in the current access request, as well as the total storage space size of the target memory page, calculate the first remaining space of the target memory page after the current access request is executed;
[0009] If the first remaining space is equal to 0, determine that the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page.
[0010] In one feasible implementation of this disclosure, the current access request is a burst transmission request, and the size of the accessed data is equal to the product of the burst length and the burst size carried by the burst transmission request.
[0011] In one feasible implementation of this disclosure, the bus arbitration method further includes:
[0012] The information of the first remaining space is sent to the target master device, so that the target master device can send the next access request based on the first remaining space.
[0013] In one feasible implementation of this disclosure, the bus arbitration method further includes:
[0014] If the first remaining space is negative, calculate the second remaining space of the next memory page after the current access request is executed, based on the access address information and the size of the accessed data carried by the current access request, as well as the total storage space size of the next memory page of the target memory page.
[0015] The information of the second remaining space is sent to the target master device, so that the target master device can send the next access request based on the second remaining space.
[0016] In one feasible implementation of this disclosure, the bus arbitration method further includes:
[0017] Start timing when the current access request is received, or start timing when the current access request is completed;
[0018] If no further access request is received from the target master device when the timer value exceeds the preset threshold, memory access permissions are reallocated.
[0019] In one feasible implementation of this disclosure, the reallocation of memory access permissions includes:
[0020] In a round-robin fashion, a master device is selected from multiple master devices, and memory access permissions are allocated to the selected master device.
[0021] Alternatively, based on the QoS of the pending access requests for each master device, select one master device from multiple master devices and assign memory access permissions to the selected master device.
[0022] According to another aspect of this disclosure, an electronic device is also provided, the device comprising: a comparator and a bus arbitration module;
[0023] The comparator is configured to determine whether the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page; the target master device is the master device currently allocated memory access permissions among multiple master devices, the last data is the last data in the data segment accessed by the current access request, and the target memory page is the memory page currently being accessed;
[0024] The bus arbitration module is configured to reallocate memory access permissions when the last data is aligned with the storage boundary of the target memory page.
[0025] In one feasible implementation of this disclosure, the comparator is specifically configured to: calculate the first remaining space of the target memory page after the current access request is executed, based on the access address information and the size information of the accessed data carried by the current access request, as well as the total storage space size of the target memory page; and if the first remaining space is equal to 0, determine that the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page.
[0026] In one feasible implementation of this disclosure, the current access request is a burst transmission request, and the size of the accessed data is equal to the product of the burst length and the burst size carried by the burst transmission request.
[0027] In one feasible implementation of this disclosure, the comparator is further configured to: send information about the first remaining space to the target master device, so that the target master device can send the next access request based on the first remaining space.
[0028] In one feasible implementation of this disclosure, the bus arbitration device further includes multiple address calculation modules, each address calculation module corresponding to a master device, and the transmission delay between each address calculation module and the corresponding master device is less than the transmission delay between the comparator and the master device;
[0029] Each address calculation module is configured to: calculate the first remaining space of the target memory page after the current access request is executed, based on the access address information and the size of the accessed data carried in the current access request, as well as the total storage space size of the target memory page; and send the information of the first remaining space to the target master device, so that the target master device can send the next access request based on the first remaining space.
[0030] In one feasible implementation of this disclosure, the bus arbitration device further includes multiple master devices. After receiving the first remaining space, the target master device among the multiple master devices determines whether the first remaining space is greater than a preset data size. If it is, it sends the next access request according to the preset data size; otherwise, it sends the next access request according to the first remaining space.
[0031] In one feasible implementation of this disclosure, the comparator is further configured to: when the first remaining space is negative, calculate the second remaining space of the next memory page after the current access request is executed, based on the access address information and the size information of the accessed data carried by the current access request, as well as the total storage space size of the next memory page of the target memory page; send the information of the second remaining space to the target master device, so that the target master device sends the next access request based on the second remaining space.
[0032] In one feasible implementation of this disclosure, the bus arbitration module is further configured to: start timing when a current access request is received, or start timing when the current access request is processed; and reallocate memory access permissions if no next access request from the target master device is received when the timing value exceeds a preset threshold.
[0033] In one feasible implementation of this disclosure, the bus arbitration module is specifically configured to: select one master device from multiple master devices in a round-robin manner and allocate memory access permissions to the selected master device; or, select one master device from multiple master devices based on the QoS of the pending access requests of each master device and allocate memory access permissions to the selected master device.
[0034] According to another aspect of this disclosure, a graphics processor is also provided, including the electronic device described in any of the foregoing embodiments. Attached Figure Description
[0035] Figure 1 This is a schematic flowchart of a bus arbitration method provided in an embodiment of this disclosure;
[0036] Figure 2 This is a schematic diagram of the structure of a bus arbitration device provided in an embodiment of this disclosure. Detailed Implementation
[0037] Before introducing the embodiments of this disclosure, it should be noted that:
[0038] Some embodiments of this disclosure are described as processing flows. Although the various operational steps of the flow may be numbered sequentially, the operational steps may be performed in parallel, concurrently, or simultaneously.
[0039] The embodiments disclosed herein may use terms such as "first," "second," etc., to describe various features, but these features should not be limited by these terms. These terms are used merely to distinguish one feature from another.
[0040] The term “and / or” may be used in embodiments of this disclosure, and “and / or” includes any and all combinations of one or more of the associated features listed.
[0041] It should be understood that when describing the connection or communication relationship between two components, unless it is explicitly stated that the two components are directly connected or communicate directly, the connection or communication between the two components can be understood as a direct connection or communication, or it can be understood as an indirect connection or communication through an intermediate component.
[0042] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the exemplary embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be combined with each other.
[0043] In existing technologies, to ensure timely responses to access requests from each master device, memory access permissions are typically switched frequently between multiple master devices. However, since the addresses accessed by each master device are usually located in different pages of memory, frequent switching of master device access permissions inevitably leads to frequent switching of memory pages, thus affecting memory access efficiency.
[0044] This disclosure proposes a bus arbitration method, electronic device, and graphics processor to improve memory access efficiency. (Reference) Figure 1 , Figure 1 This is a schematic flowchart of a bus arbitration method provided in an embodiment of this disclosure. Figure 1 As shown, the bus arbitration method includes the following steps:
[0045] S110: Determine whether the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page; the target master device is the master device currently allocated memory access permissions among multiple master devices, the last data is the last data in the data segment accessed by the current access request, and the target memory page is the currently accessed memory page.
[0046] In this disclosure, the current access request of the target master device accesses (e.g., reads) a segment of data in the target memory page. The last data corresponding to the current access request is aligned with the storage boundary of the target memory page, specifically meaning that the last data in the data segment accessed by the current access request is exactly the last data in the target memory page.
[0047] The bus arbitration method disclosed herein can be specifically applied to GPUs, where the accessed memory can be GDDR memory. Compared to CPUs, GPU memory access processes have the following main characteristics: 1) The data that the host device needs to read from memory is usually large, and this data usually fills one or more memory pages; 2) The host device does not have high requirements for the timeliness of its response to access requests. Due to these characteristics of GPU memory access processes, the bus arbitration method disclosed herein can significantly improve memory access efficiency when implemented in GPUs without causing other negative effects.
[0048] In this disclosure, multiple master devices can be multiple GPUs in a multi-core GPU graphics card, or multiple modules in a single GPU. This disclosure does not limit the specific type of master device.
[0049] In some specific embodiments of this disclosure, step S110 specifically includes the following sub-steps:
[0050] S110-1: Based on the access address information and the size of the accessed data carried in the current access request, as well as the total storage space size of the target memory page, calculate the first remaining space of the target memory page after the current access request is executed.
[0051] S110-2: If the first remaining space is equal to 0, determine that the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page.
[0052] The first remaining space refers to the storage space between the last data in the data segment accessed by the current access request and the last data in the target memory page.
[0053] When calculating the first remaining space based on the access address information and the size of the accessed data carried by the current access request, as well as the total storage space size of the target memory page, the first remaining space is obtained by summing the access address and the size of the accessed data, and then subtracting the summation result from the total storage space.
[0054] If the bit width M of the access address is greater than the bit width N of the target memory page's storage space, then when calculating the first remaining space based on the access address information and the size information of the accessed data carried in the current access request, as well as the total storage space size of the target memory page, the lower N+1 bits of the access address are taken, the size information of the accessed data is represented as N bits, the lower N+1 bits of the access address and the N bits of the size information of the accessed data are summed, and then the total storage space of N bits is subtracted from the summation result to obtain the first remaining space.
[0055] In some specific embodiments of this disclosure, the current access request is a burst transmission request, and the size of the accessed data is equal to the product of the burst length and the burst size carried by the burst transmission request.
[0056] For ease of understanding, taking the AMBA AXI bus as an example, when the initiated transfer request address is Request_Addr[31:0], the burst length is 16, and the burst size is 256 bits, the size of the accessed data Transfer_Size[11:0] is 16*256 / 8=512B. Taking Request_Addr as the access address (i.e., the starting address), the address at the end of this transfer is Request_Addr[31:0]+Transfer_Size[11:0]. Assuming the total storage space size of the target memory page is Page_Size is 4KB, that is, the bit width is 12 bits, represented as Page_Size[11:0], then the first remaining space is: Page_Size[11:0]- (Request_Addr[31:0] + Transfer_Size[11:0]). In hardware implementation, to prevent overflow, the calculation formula is: Rest_Addr[12:0]={1'b0,Page_Size[11:0]}-(Request_Addr[12:0]+{1'b0,Transfer_Size[11:0]}), where Rest_Addr is the first remaining space.
[0057] S120: Reallocate memory access permissions when the last data is aligned with the storage boundary of the target memory page.
[0058] In some specific embodiments of this disclosure, when it is necessary to reallocate memory access permissions, a master device can be selected from multiple master devices in a round-robin manner, and memory access permissions can be allocated to the selected master device; or, a master device can be selected from multiple master devices according to the QoS of the pending access requests of each master device, and memory access permissions can be allocated to the selected master device.
[0059] Specifically, when allocating memory access permissions using a round-robin method, each master device can be traversed in a preset order. If an unprocessed access request exists on a traversed master device, memory access permissions are allocated to that master device. When allocating memory access permissions based on the QoS of pending access requests for each master device, the highest priority access request can be determined from multiple cached pending access requests, and then memory access permissions are allocated to the master device corresponding to that access request.
[0060] In this disclosure, if the last data aligns with the storage boundary of the target memory page (i.e., the currently accessed memory page), it indicates that the currently accessed memory page has just been read. If the access request to the target master device continues to be processed at this point, it will be necessary to switch to another memory page. In this disclosure, when a memory page switch is necessary, memory access permissions are reallocated, which can reduce the number of memory page switches and improve memory access efficiency.
[0061] Alternatively, from another perspective, this disclosure reallocates memory access permissions only when the end data is aligned with the storage boundary of the target memory page, and does not reallocate memory access permissions when the end data is not aligned with the storage boundary of the target memory page. This allows multiple consecutive access requests for the same memory page on a master device to be processed continuously, which can significantly reduce the number of memory page switches and improve memory access efficiency.
[0062] In some specific embodiments of this disclosure, the bus arbitration method further includes the following steps: sending information about the first remaining space to the target master device, so that the target master device sends the next access request based on the first remaining space.
[0063] In this disclosure, by sending the first remaining space information to the target master device, the target master device can generate the next access request based on the first remaining space information, rather than blindly generating the next access request without the first remaining space information as a reference, which would cause the next access request to require cross-domain memory pages. For example, in some specific embodiments of this disclosure, when the master device generates a new access request, it first determines whether the first remaining space is greater than a preset data size based on the first remaining space after the previous access request has been processed. If it is greater, a new access request is generated based on the preset data size, and the data size required by the new access request is equal to the preset data size. If it is not greater, a new access request is generated based on the first remaining space, and the data size required by the new access request is equal to the size of the first remaining space.
[0064] In some specific embodiments of this disclosure, considering that the master device does not have a first remaining space as a reference when generating the first access request, the generated first access request may involve cross-domain memory pages. In this case, the first remaining space calculated according to the above sub-step S110-1 is a negative value. To deal with this situation, the bus arbitration method of this disclosure further includes the following steps: when the first remaining space is negative, calculate the second remaining space of the next memory page after the current access request is executed, based on the access address information and the size information of the accessed data carried in the current access request, as well as the total storage space size of the next memory page of the target memory page; send the information of the second remaining space to the target master device, so that the target master device sends the next access request based on the second remaining space.
[0065] The second remaining space refers to the storage space between the last data in the data segment accessed by the current access request and the last data in the next memory page of the target memory page.
[0066] The second remaining space is calculated by summing the access address and the size of the accessed data carried in the current access request, as well as the total storage space of the next memory page of the target memory page. The second remaining space is obtained by subtracting the sum from the total storage space of the next memory page.
[0067] If the bit width M of the access address is greater than the bit width N of the target memory page's storage space, then when calculating the second remaining space based on the access address information and the size information of the accessed data carried by the current access request, as well as the total storage space size of the next memory page, the lower N+1 bits of the access address are taken, the size information of the accessed data is represented as N bits, then the lower N+1 bits of the access address and the N bits of the accessed data size information are summed, and then the N bits of the total storage space of the next memory page are subtracted from the summation result to obtain the second remaining space.
[0068] In some specific embodiments of this disclosure, the current access request is a burst transmission request, and the size of the accessed data is equal to the product of the burst length and the burst size carried by the burst transmission request.
[0069] For ease of understanding, taking the AMBA AXI bus as an example, when the initiated transfer request address is Request_Addr[31:0], the burst length is 16, and the burst size is 256 bits, the size of the accessed data Transfer_Size[11:0] is 16*256 / 8=512B. Taking Request_Addr as the access address (i.e., the starting address), the address at the end of this transfer is Request_Addr[31:0]+Transfer_Size[11:0]. Assuming the total storage space size of the target memory page is Page_Size is 4KB, that is, the bit width is 12 bits, represented as Page_Size[11:0], then the first remaining space is: Page_Size[11:0]- (Request_Addr[31:0] + Transfer_Size[11:0]). In hardware implementation, to prevent overflow, the calculation formula is: Rest_Addr[12:0]={1'b0,Page_Size[11:0]}-(Request_Addr[12:0]+{1'b0,Transfer_Size[11:0]}), where Rest_Addr is the first remaining space. If the first remaining space is negative, the second remaining space needs to be calculated based on the total storage space size of the next memory page, Page_Size'. The calculation formula is Rest_Addr[12:0]'={1'b0,Page_Size[11:0]'}-(Request_Addr[12:0]+{1'b0,Transfer_Size[11:0]}), where Rest_Addr' is the second remaining space.
[0070] In this disclosure, by sending the second remaining space information to the target master device, the target master device can generate the next access request based on the second remaining space information, so as not to blindly generate the next access request without the second remaining space information as a reference, which would cause the next access request to need to cross memory pages.
[0071] In some specific embodiments of this disclosure, if multiple access requests from the target master device have been processed, but the last data corresponding to the last access request is not aligned with the boundary of the target memory page, it is necessary to wait for the target master device to initiate a new access request until the last data corresponding to an access request is aligned with the boundary of the target memory page before switching memory access permissions. In the above situation, memory may be inaccessible for a relatively long period of time. To address this situation, the bus arbitration method of this disclosure further includes the following steps: starting a timer when the current access request is received, or starting a timer when the current access request is processed; and reallocating memory access permissions if no next access request from the target master device is received when the timer value exceeds a preset threshold.
[0072] In this disclosure, if the timer value exceeds a preset threshold and no further access request is received from the target master device, it indicates that the target master device has likely completed the data reading task for the current task (such as image rendering, image display, or model training). Before the target master device begins processing the next task, no new access request will be initiated. Therefore, to promptly transfer memory access permissions to other master devices, this disclosure reallocates memory access permissions if the timer value exceeds the preset threshold and no further access request is received from the target master device.
[0073] The present disclosure provides a bus arbitration method. Based on the same inventive concept, the present disclosure also proposes an electronic device. (Reference) Figure 2 , Figure 2 This is a schematic diagram of the structure of a bus arbitration device provided in an embodiment of this disclosure. Figure 2 As shown, the bus arbitration device includes a comparator and a bus arbitration module.
[0074] The comparator is configured to determine whether the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page; the target master device is the master device currently allocated memory access permissions among multiple master devices, the last data is the last data in the data segment accessed by the current access request, and the target memory page is the currently accessed memory page.
[0075] The bus arbitration module is configured to reallocate memory access permissions when the last data is aligned with the storage boundary of the target memory page.
[0076] In this disclosure, if the last data aligns with the storage boundary of the target memory page (i.e., the currently accessed memory page), it indicates that the currently accessed memory page has just been read. If the access request to the target master device continues to be processed at this point, it will be necessary to switch to another memory page. In this disclosure, when a memory page switch is necessary, memory access permissions are reallocated, which can reduce the number of memory page switches and improve memory access efficiency.
[0077] Alternatively, from another perspective, this disclosure reallocates memory access permissions only when the end data is aligned with the storage boundary of the target memory page, and does not reallocate memory access permissions when the end data is not aligned with the storage boundary of the target memory page. This allows multiple consecutive access requests for the same memory page on a master device to be processed continuously, which can significantly reduce the number of memory page switches and improve memory access efficiency.
[0078] In some specific embodiments of this disclosure, the comparator and the bus arbitration module are connected via an arbitration switching signal line. When the comparator determines that the end data corresponding to the current access request is aligned with the storage boundary of the target memory page, the comparator sends an arbitration switching signal to the bus arbitration module at a high level. When the comparator determines that the end data corresponding to the current access request is not yet aligned with the storage boundary of the target memory page, the comparator maintains the arbitration switching signal sent to the bus arbitration module at a low level.
[0079] In some specific embodiments of this disclosure, the comparator is specifically configured to: calculate the first remaining space of the target memory page after the current access request is executed, based on the access address information and the size information of the accessed data carried by the current access request, as well as the total storage space size of the target memory page; and if the first remaining space is equal to 0, determine that the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page.
[0080] In some specific embodiments of this disclosure, the current access request is a burst transmission request, and the size of the accessed data is equal to the product of the burst length and the burst size carried by the burst transmission request.
[0081] For ease of understanding, taking the AMBA AXI bus as an example, when the initiated transfer request address is Request_Addr[31:0], the burst length is 16, and the burst size is 256 bits, the size of the accessed data Transfer_Size[11:0] is 16*256 / 8=512B. Taking Request_Addr as the access address (i.e., the starting address), the address at the end of this transfer is Request_Addr[31:0]+Transfer_Size[11:0]. Assuming the total storage space size of the target memory page is Page_Size is 4KB, that is, the bit width is 12 bits, represented as Page_Size[11:0], then the first remaining space is: Page_Size[11:0]- (Request_Addr[31:0] + Transfer_Size[11:0]). In hardware implementation, to prevent overflow, the calculation formula is: Rest_Addr[12:0]={1'b0,Page_Size[11:0]}-(Request_Addr[12:0]+{1'b0,Transfer_Size[11:0]}), where Rest_Addr is the first remaining space.
[0082] In some specific embodiments of this disclosure, the comparator is further configured to send information about the first remaining space to the target master device, enabling the target master device to send the next access request based on the first remaining space. By sending the first remaining space information to the target master device, the target master device can generate the next access request based on the first remaining space information, rather than blindly generating the next access request without the first remaining space information as a reference, which would cause the next access request to require cross-domain memory pages.
[0083] Alternatively, in some other specific embodiments of this disclosure, the bus arbitration device does not send the first remaining space information to the target master device via a comparator, but rather via an address calculation module with lower latency to the target master device. Specifically, the bus arbitration device further includes multiple address calculation modules ( Figure 2 The diagram only shows the address calculation module corresponding to the target master device. Each address calculation module corresponds to one master device, and the transmission delay between each address calculation module and its corresponding master device is less than the transmission delay between the comparator and the master device.
[0084] Each address calculation module is configured to: calculate the first remaining space of the target memory page after the current access request is executed, based on the access address information and the size of the accessed data carried in the current access request, as well as the total storage space size of the target memory page; and send the information of the first remaining space to the target master device, so that the target master device can send the next access request based on the first remaining space.
[0085] like Figure 2 As shown, the access request from the target master device is sent to the comparator and the address calculation module corresponding to the target master device. The address calculation module calculates the first remaining space based on the access address information and the size of the accessed data carried in the access request, as well as the total storage space size of the target memory page, and sends this first remaining space information to the target master device. The comparator calculates the first remaining space based on the access address information and the size of the accessed data carried in the access request, as well as the total storage space size of the target memory page. If the first remaining space is equal to 0, the arbitration switching signal sent by the comparator to the bus arbitration module is high; if the first remaining space is not equal to 0, the arbitration switching signal sent by the comparator to the bus arbitration module remains low.
[0086] In this disclosure, the address calculation module corresponding to the target master device sends the first remaining space information to the target master device. Since the time delay between the address calculation module and the target master device is small, it can help the target master device receive the corresponding first remaining space information in a timely manner after sending the previous access request, so as to quickly generate the next access request based on the first remaining space.
[0087] In some specific embodiments of this disclosure, the bus arbitration device further includes multiple master devices ( Figure 2 (Only the target master device is shown in the figure). After the target master device among multiple master devices receives the first remaining space, it determines whether the first remaining space is greater than the preset data size. If it is, it sends the next access request according to the preset data size. If not, it sends the next access request according to the first remaining space.
[0088] In practice, the master device determines whether the first remaining space is greater than the preset data size based on the first remaining space after the previous access request has been processed. If it is greater, a new access request is generated based on the preset data size, and the data size to be accessed by the new access request is equal to the preset data size. If it is not greater, a new access request is generated based on the first remaining space, and the data size to be accessed by the new access request is equal to the size of the first remaining space.
[0089] As mentioned earlier, considering that the master device does not have a first remaining space as a reference when generating the first access request, the generated first access request may involve cross-domain memory pages. In this case, the first remaining space calculated by the comparator is a negative value. To address this situation, in some specific embodiments of this disclosure, the comparator is further configured to: when the first remaining space is negative, calculate the second remaining space of the next memory page after the current access request is executed, based on the access address information and the size information of the accessed data carried in the current access request, as well as the total storage space size of the next memory page of the target memory page; and send the information of the second remaining space to the target master device, so that the target master device sends the next access request based on the second remaining space.
[0090] As mentioned earlier, if multiple access requests from the target master device have been processed, but the last data corresponding to the last access request is not aligned with the boundary of the target memory page, it is necessary to wait for the target master device to initiate a new access request until the last data corresponding to an access request is aligned with the boundary of the target memory page before switching memory access permissions. In this case, memory may be inaccessible for a considerable period of time. To address this issue, in some specific embodiments of this disclosure, the bus arbitration module is further configured to: start timing when the current access request is received, or start timing when the current access request is processed; and reallocate memory access permissions if no next access request from the target master device is received when the timing value exceeds a preset threshold.
[0091] In some specific embodiments of this disclosure, the bus arbitration module is specifically configured to: select one master device from multiple master devices in a round-robin manner and allocate memory access permissions to the selected master device; or, select one master device from multiple master devices based on the QoS of the pending access requests of each master device and allocate memory access permissions to the selected master device.
[0092] Based on the same inventive concept, this disclosure also proposes a graphics processor that includes the electronic device described in any of the above embodiments.
[0093] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0094] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.
Claims
1. A bus arbitration method, the method comprising: Determine whether the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page; The target master device is the master device currently allocated memory access permissions among multiple master devices, the last data is the last data in the data segment accessed by the current access request, and the target memory page is the currently accessed memory page; If the last data is aligned with the storage boundary of the target memory page, the memory access permissions are reallocated; The step of determining whether the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page includes: Based on the access address information and the size of the accessed data carried in the current access request, as well as the total storage space size of the target memory page, calculate the first remaining space of the target memory page after the current access request is executed; If the first remaining space is equal to 0, it is determined that the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page.
2. The method according to claim 1, wherein the current access request is a burst transmission request, and the size of the accessed data is equal to the product of the burst length and the burst size carried by the burst transmission request.
3. The method according to claim 1, further comprising: The information of the first remaining space is sent to the target master device, so that the target master device sends the next access request based on the first remaining space.
4. The method according to claim 1, further comprising: If the first remaining space is negative, the second remaining space of the next memory page after the current access request is executed is calculated based on the access address information and the size information of the accessed data carried by the current access request, as well as the total storage space size of the next memory page of the target memory page. The information of the second remaining space is sent to the target master device, so that the target master device sends the next access request based on the second remaining space.
5. The method according to claim 1, further comprising: The timer starts when the current access request is received, or when the current access request is processed. If no further access request is received from the target master device when the timer value exceeds a preset threshold, the memory access permissions are reallocated.
6. The method according to claim 1, wherein the reallocation of memory access permissions comprises: A master device is selected from the plurality of master devices using a polling method, and memory access permissions are allocated to the selected master device. Alternatively, based on the QoS of the pending access requests of each master device, a master device may be selected from the plurality of master devices, and memory access permissions may be assigned to the selected master device.
7. An electronic device, the device comprising: Comparator and bus arbitration module; The comparator is configured to: calculate the first remaining space of the target memory page after the current access request is executed, based on the access address information and the size information of the accessed data carried in the current access request, as well as the total storage space size of the target memory page; and determine that the last data corresponding to the current access request of the target master device is aligned with the storage boundary of the target memory page if the first remaining space is equal to 0. The target master device is the master device currently allocated memory access permissions among multiple master devices, the last data is the last data in the data segment accessed by the current access request, and the target memory page is the currently accessed memory page; The bus arbitration module is configured to reallocate memory access permissions when the last data is aligned with the storage boundary of the target memory page.
8. The apparatus according to claim 7, wherein the current access request is a burst transmission request, and the size of the accessed data is equal to the product of the burst length and the burst size carried by the burst transmission request.
9. The apparatus of claim 7, wherein the comparator is further configured to: send information about the first remaining space to the target master device, causing the target master device to send a next access request based on the first remaining space.
10. The apparatus according to claim 7, further comprising a plurality of address calculation modules, each address calculation module corresponding to a master device, wherein the transmission delay between each address calculation module and the corresponding master device is less than the transmission delay between the comparator and the master device; Each address calculation module is configured to: calculate the first remaining space of the target memory page after the current access request is executed, based on the access address information and the size information of the accessed data carried in the current access request, as well as the total storage space size of the target memory page; and send the information of the first remaining space to the target master device, so that the target master device sends the next access request based on the first remaining space.
11. The apparatus according to claim 9 or 10, further comprising a plurality of master devices, wherein after receiving the first remaining space, the target master device among the plurality of master devices determines whether the first remaining space is greater than a preset data size; if so, it sends the next access request according to the preset data size; if not, it sends the next access request according to the first remaining space.
12. The apparatus of claim 7, wherein the comparator is further configured to: when the first remaining space is negative, calculate the second remaining space of the next memory page after the current access request is executed, based on the access address information and the size information of the accessed data carried in the current access request, and the total storage space size of the next memory page of the target memory page; and send the information of the second remaining space to the target master device, so that the target master device sends the next access request based on the second remaining space.
13. The apparatus according to claim 7, wherein the bus arbitration module is further configured to: start timing when the current access request is received, or start timing when the current access request is processed; and reallocate the memory access permissions if no next access request from the target master device is received when the timing value exceeds a preset threshold.
14. The apparatus according to claim 7, wherein the bus arbitration module is specifically configured to: select a master device from the plurality of master devices in a polling manner and allocate memory access permissions to the selected master device; or, select a master device from the plurality of master devices according to the QoS of the pending access requests of each master device and allocate memory access permissions to the selected master device.
15. A graphics processor comprising the electronic device according to any one of claims 7 to 14.