Clock tree structure and implementation method thereof
By designing the trunk and branch clock networks, the clock tree structure was optimized, solving the problems of high power consumption and difficult timing convergence in the chip, and achieving more efficient clock signal transmission and lower power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI YIJIAXIN INTEGRATED CIRCUIT DESIGN CO LTD
- Filing Date
- 2023-03-27
- Publication Date
- 2026-05-19
AI Technical Summary
Existing clock tree structures in chips suffer from high power consumption, difficulty in timing convergence, clock skew, and insertion delay issues, and are also greatly affected by environmental parameters.
The design employs a trunk clock network and branch clock networks. The trunk clock network is composed of first-level and second-level buffer units. The second-level buffer units are arranged at equal intervals on the central axis. The branch clock network is output from the second-level buffer units. The third-level buffer units are perpendicular to the trunk clock network, driving the fourth-level buffer units to extend in a tree structure, thereby reducing the number of buffer units and levels and optimizing the wiring path.
It reduces chip power consumption, reduces power consumption on the clock network, simplifies the timing convergence process, reduces sensitivity to environmental parameters, and improves the transmission consistency of clock signals.
Smart Images
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Abstract
Description
Technical Field
[0001] This invention relates to the field of clock tree technology, and in particular to a clock tree structure and its implementation method. Background Technology
[0002] With the advancement of process technology, the size of chips is getting larger and larger, and clock signals have a significant impact on the performance and power consumption of integrated circuits.
[0003] Traditional clock tree structures are tree-like structures that run from a clock source to the clock sink of a sequential device. They address issues like high fan-out and high load on the clock source by inserting buffers or inverters, ensuring the clock signal is transmitted completely and without deviation to the clock signal terminals of the sequential devices. However, due to the inconsistent physical locations of sequential devices, the clock signals arriving at any number of sequential devices from the same clock source will inevitably be inconsistent, leading to clock skew and insertion delay. Furthermore, transistors are inherently sensitive to environmental parameters; a large number of buffers or inverter stages results in a short common path, making them highly susceptible to on-chip error (OCV), which can lead to overly pessimistic prediction.
[0004] This has led to various clock network structures: tree structures, network structures, and spine structures. While tree structures are simple and elegant, and beneficial for controlling clock skew and overall clock delay, they either have high routing requirements and low flexibility, or too many levels of buffer cells, making them highly susceptible to OCV (Optical Character Volume). Network structures typically have smaller clock skew and better anti-interference capabilities, but the numerous redundant interconnects increase power consumption and are also limited by chip layout, potentially leading to implementation failures. Spine structures typically have smaller clock skew and better anti-interference capabilities, but the leaf nodes at the back of the clock spine require additional wiring optimization to reach the flip-flops to meet clock skew requirements. Furthermore, in advanced processes, the parasitic capacitance and resistance of interconnects are increasingly significant. To ensure clock signal integrity, the trunk and branches of the spine structure require shielding nets on all sides, consuming considerable routing resources. Summary of the Invention
[0005] The technical problem to be solved by this invention is to improve the existing clock tree construction method, reduce chip power consumption, and reduce the difficulty of timing convergence by providing a new clock tree and implementation method, thereby reducing chip power consumption and the difficulty of timing convergence.
[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0007] A clock tree structure includes a trunk clock network and branch clock networks. The trunk clock network is introduced from the outside and consists of a first-level buffer unit and a second-level buffer unit. The first-level buffer unit is located at the external input port, and the second-level buffer units are arranged at equal intervals on the central axis. The branch clock network is led out from the output of the second-level buffer unit and consists of buffer units from the second-level buffer unit to the third-level buffer unit. The third-level buffer unit is placed perpendicular to the trunk clock network. The third-level buffer unit pushes the fourth-level buffer unit in a tree structure, and so on, up to the nth-level buffer unit and the gated clock unit.
[0008] As a further preferred embodiment of the clock tree structure of the present invention, the direction of the trunk clock network is horizontal or vertical, and there are one or more trunk clock networks; the third-level buffer units drive the loads of L*L-sized windows respectively; wherein, the number of loads of L*L-sized windows is less than or equal to N, and N is the maximum fan-out limit specified by the design requirements.
[0009] As a further preferred embodiment of the clock tree structure of the present invention, the first-level buffer unit, the second-level buffer unit, the third-level buffer unit and the nth-level buffer unit can all be replaced with an even number of inverters.
[0010] An implementation method based on a clock tree structure includes the following steps:
[0011] Step 1: Determine if there are multiple levels of gated clocks after the clock root node, and flatten the gated clock unit into a single level.
[0012] Step 2: Obtain the layout of the registers directly connected after the clock root node, cut the logic unit module into L*L windows, group the registers in the window into N groups, use buffer units to push them, and set this level of buffer unit as the nth level buffer unit.
[0013] Step 3: Obtain the layout of the gated clock unit and the nth level buffer unit connected after the clock root node. Cut the logic unit module into an L*L window. Group the gated clock units and the nth level buffer unit in the window into N groups and use the buffer unit to push them. This level of buffer unit is the (n-1)th level buffer unit.
[0014] Step 4: Based on the clock root node obtained in Steps 1 to 3, connect the fourth-level buffer unit in groups of N and use the buffer unit buffer to drive it. This level of buffer unit is the third-level buffer unit.
[0015] Step 5: Connect the first-level buffer unit from the clock port to drive the second-level buffer unit as the main clock network. The second-level buffer units are arranged at equal intervals on the central axis, and the equal interval is denoted as a.
[0016] Step 6: Divide the logic unit module into multiple rectangular regions with height 'a', perpendicular to the main clock network. Each rectangular region has a second-level buffer unit at its center. Connect the output of the second-level buffer unit in the rectangular region to the input of all the third-level buffer units in that rectangular region.
[0017] As a further preferred embodiment of the clock tree structure implementation method of the present invention, the value of the equal spacing 'a' depends on the driving capability of the second-level buffer unit and the physical distance and number of the third-level buffer units in the rectangular area with height 'a'. The number of the third-level buffer units is less than or equal to N, where N is the maximum fan-out limit specified by the design requirements.
[0018] As a further preferred embodiment of the clock tree structure implementation method of the present invention, the L*L-sized window is obtained by dividing the logic unit module from the middle to the surrounding area, that is, cutting the entire logic unit into several L*L-sized windows, and the value of L depends on the driving capability of the driving unit connected to the load in the window.
[0019] As a further preferred embodiment of the clock tree structure of the present invention, the direction of the main clock network is determined by minimizing the distance from the load to the main network; the branch clock network is shorter than the main clock network to minimize the distance from the load to the main network and reduce propagation delay; the main clock network tree is set on the central axis of the logic unit module.
[0020] As a further preferred embodiment of the clock tree structure implementation method of the present invention, the next level is driven by a tree structure after the third level buffer. This tree structure has N branches to ensure that the number of loads is maximized so as to reduce the number of levels of the clock tree. N is the maximum fan-out limit value specified by the design requirements.
[0021] As a further preferred embodiment of the clock tree structure implementation method of the present invention, the physical location of the nth level buffer unit is determined by the layout of the registers, which drives the registers within the L*L window, and the value of L is determined by the driving capability of the nth level buffer unit.
[0022] As a further preferred embodiment of the clock tree structure implementation method of the present invention, if there are multiple levels of gated clock units after the root node, the clock ports of the multiple registers connected after the nth level gated clock unit need to be flattened. The flattened gated clock units are used to make their levels the same, that is, to flatten the multiple levels of gated clock units after the root node into one level.
[0023] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:
[0024] This invention discloses a clock tree structure and its implementation method, which reduces the number of buffer units and stages between the clock root node and the register clock terminal, saves routing resources, and reduces power consumption on the clock network; the trunk clock tree and branch clock trees also serve as common paths, reducing the impact of OCV, preventing overly pessimistic problems, and making timing more easy to converge. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic diagram of a traditional clock tree structure;
[0027] Figure 2 This is a schematic diagram of a clock tree layout for the chip logic unit module of the present invention;
[0028] Figure 3 This is a schematic diagram showing the layout of the chip logic unit module of the present invention, which is divided into an nth-level buffer unit within an L*L window, driving multiple registers.
[0029] Figure 4 This is a schematic diagram showing the layout of the chip logic unit module of the present invention divided into multiple rectangular areas with height 'a'.
[0030] Figure 5 This is a schematic diagram of the special clock structure after preprocessing of the chip logic unit module of the present invention;
[0031] Figure 6 This is a simplified dual-trunk clock tree diagram of the chip logic unit module of the present invention;
[0032] Figure 7 This is a simplified four-trunk clock tree diagram of the chip logic unit module of the present invention. Detailed Implementation
[0033] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings:
[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The specific implementation methods of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. The following embodiments are used to illustrate the present invention, but are not intended to limit the scope of the present invention.
[0035] Example 1:
[0036] like Figures 2 to 7 As shown, a clock tree structure includes a trunk and branch clock networks. The trunk clock network is introduced from the outside and consists of a first-level buffer unit and a second-level buffer unit. The trunk direction can be horizontal or vertical, and there can be one or more trunks. The branch clock networks are led out from the trunk clock network and consist of second-level to third-level buffer units. The branch clock networks drive the load within an L*L window, that is, the third-level buffer unit drives the fourth-level buffer unit in a tree structure, and so on, up to the nth-level buffer unit and the gated clock unit.
[0037] In this embodiment, the L*L-sized window is obtained by dividing the logic unit module from the middle to the surrounding area, that is, cutting the entire logic unit into several L*L-sized windows. The value of L depends on the driving capability of the driving unit connected to the load in the window. Here, by constraining the size of the window, the problem of the transition time of the clock unit is prevented from being caused by the excessively long traces connecting the driving unit to the fan-out unit.
[0038] In this embodiment, the main clock network consists of a larger first-level buffer unit driving multiple second-level buffer units. The branch clock network is led out from the output of multiple second-level buffer units and driven by multiple third-level buffer units. The third-level buffer units drive loads of L*L size windows respectively. The number of loads in the L*L size window is less than or equal to N, where N is the maximum fan-out limit specified by the design requirements. Furthermore, by constraining the number of fan-out units connected to the driving unit, the problem of transition time default of the middle unit is prevented from being caused by too many fan-out units connected to the driving unit.
[0039] In this embodiment, the choice of the main trunk direction is to minimize the distance from the load to the main trunk. Generally, the main trunk is longer than the branches. This is to minimize the distance between the load and the main trunk, thereby reducing propagation delay.
[0040] In this embodiment, the master clock tree is positioned on the central axis of the logic unit module. By positioning the master clock tree on its central axis according to the physical layout of the clock sinks after the clock root node, the clock sink points are distributed as evenly as possible on both sides of the master clock tree, which can reduce the length and number of wiring connections in terms of physical distance.
[0041] In this embodiment, the first-level buffer unit is located near the external input port, the second-level buffer units are arranged at equal intervals on the central axis, and the third-level buffer unit is placed perpendicular to the main clock and on a horizontal line, which is beneficial for routing and makes the wiring simple and neat.
[0042] In this embodiment, the third-level buffer drives the next level in a tree structure. This tree structure has N branches to maximize the number of loads, thereby reducing the number of levels in the clock tree, reducing the impact of OCV, and preventing excessive pessimism. N is the maximum fan-out limit specified by the design requirements.
[0043] In this embodiment, the first-level buffer unit can be one or split into multiple main branches. The number of main branches is determined by the size of the physical layout of the chip logic unit modules, such as... Figure 6 It is a clock tree structure with two main branches, such as Figure 7 It is a clock tree structure with four main branches.
[0044] In this embodiment, the number of cache units at each level is determined by the number of cache units at the next level and the physical distance between them. The number of cache units at each level meets the design requirements. Typically, the first and second levels use cache units with larger drives to drive more cache units at the next level. The third level and subsequent levels use relatively smaller cache units to meet the clock transition time requirements.
[0045] In this embodiment, the cache units at each level can be replaced with an even number of inverters, which consume less power.
[0046] Example 2:
[0047] This invention also provides a method for implementing a clock tree, comprising the following steps:
[0048] Step 1: Analyze the clock structure, determine whether there are multiple levels of gated clocks after the clock root node, and flatten the gated clock units into a single level.
[0049] Step Two, as follows Figure 3As shown, the layout of the registers directly connected after the clock root node is obtained. The logic unit module is cut into an L*L window. The registers in the window are grouped into N groups and pushed by a buffer unit. For ease of description, this level of buffer unit is set as the nth level buffer unit.
[0050] Step 3: Obtain the layout of the gated clock units and the nth-level buffer units connected after the clock root node. Cut the logic unit module into L*L windows. Group the gated clock units and the nth-level buffer units within the window into groups of N, and use the buffer unit to drive them. This level of buffer unit is the (n-1)th-level buffer unit. Similarly, obtain the fourth-level buffer units connected after the clock root node into groups of N, and use the buffer unit to drive them. This level of buffer unit is the third-level buffer unit.
[0051] Step 4: Connect a larger driver from the clock port to drive the first-stage buffer unit to drive multiple second-stage buffer units as the backbone clock network. The second-stage buffer units are arranged at equal intervals on the central axis, and the equal interval is denoted as a.
[0052] Step 5: Divide the logic unit module into multiple rectangular regions with height 'a', perpendicular to the main axis. Each rectangular region should have a second-level buffer unit at its center. Connect the output of each second-level buffer unit within a rectangular region to the input of all third-level buffer units within that region, as follows: Figure 4 As shown; combined Figure 6 Understandably, if the load capacitance of the second-stage buffer unit is too large, a second-stage buffer unit can be cloned and placed close to the original second-stage buffer unit, symmetrically driving the third-stage buffer units on both sides.
[0053] In step one, the multi-level gated clock is used because some chip designs incorporate integrated gated clocks (ICGs) to control power consumption. When a module is not needed, the power supply to the registers after the ICG is cut off to reduce power consumption. However, due to logic or other reasons, some registers in a clock domain may not be able to cut off power consumption, such as... Figure 5 FF1 in the registers; while some registers may be controlled by two levels of ICG, such as Figure 5 FF31 and FF32 in the code. To ensure that the loads after the clock root node are of the same type, for registers like FF1 that are directly connected to the clock signal, you can try adding a virtual ICG of the same type as the ICG or a buffer unit with a similar device delay value to achieve a rough balance in their structure. Figure 5 Structures like ICG B and ICG C need to be flattened. Flattening means making their series the same. This eliminates the clock skew caused by their inherent structure.
[0054] In step five, the value of the equal spacing 'a' depends on the driving capability of the second-level buffer unit and the physical distance and number of the third-level buffer units within the rectangular area with height 'a'. The number of third-level buffer units is less than or equal to N, where N is the maximum fan-out limit specified by the design requirements.
[0055] Example 3:
[0056] Based on Example 2, when the physical layout of the chip logic unit module is relatively large, in order to meet the clock electrical performance (clock transition time), the first-level buffer unit can be split into multiple units, or the second-level buffer unit can be split into multiple units. The split layout is determined according to the size of the physical layout of the chip logic unit module. Figure 6 , Figure 7 These are two cases of deformation.
[0057] In this embodiment, multiple first-level buffer units drive multiple second-level buffer units, forming multiple trunk clock networks. The multiple trunk clocks and multiple branch clocks constitute a fishbone-shaped clock structure, which is modified according to the actual situation to achieve a better clock tree structure.
[0058] like Figure 1 If the chip logic unit structure directly adopts the traditional clock tree connection method, then its connection method will be problematic. Too many clock buffers will result in a long clock tree, many levels, and a large number of buffer units used, leading to high clock tree power consumption, easy channel routing congestion, high clock tree routing resource consumption, and high noise on the clock tree. At the same time, a large number of buffer units on the clock tree will also cause the clock tree to branch early, have few common paths, and have more clock cycles occupied by OCV, ultimately making timing convergence difficult.
[0059] In summary, the clock tree structure and implementation method provided by this invention, compared with the prior art, reduces the number of buffer units and lowers chip power consumption by establishing a clock tree structure with a master clock tree and a sub-clock tree. The master clock tree and the sub-clock tree also serve as a common path, reducing the number of clock stages, minimizing the impact of OCV, and facilitating the final timing convergence.
[0060] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.
Claims
1. A clock tree structure, characterized in that, It includes a trunk clock network and branch clock networks. The trunk clock network is introduced from the outside and consists of a first-level buffer unit and a second-level buffer unit. The first-level buffer unit is located at the external input port, and the second-level buffer units are arranged at equal intervals 'a' on the central axis. The branch clock network is led out from the output of the second-level buffer unit and consists of buffer units from the second-level to the third-level buffer unit. The third-level buffer unit is placed perpendicular to the trunk clock network, and the third-level buffer unit pushes the fourth-level buffer unit in a tree structure, and so on. The process extends to the nth-level buffer unit and the gated clock unit. The value of the equal spacing 'a' depends on the driving capability of the second-level buffer unit and the physical distance and number of the third-level buffer units within a rectangular area with height 'a'. The direction of the main clock network is determined by minimizing the distance from the load to the main network. The branch clock network is shorter than the main clock network to minimize the distance from the load to the main network and reduce propagation delay. After the third-level buffer, the next level is driven by a tree structure with N branches to maximize the number of loads and reduce the number of levels in the clock tree.
2. A clock tree structure according to claim 1, characterized in that, The trunk clock network is horizontal or vertical, and there are one or more trunk clock networks; the third-level buffer unit drives the load of an L*L window; wherein, the number of loads in the L*L window is less than or equal to N, and N is the maximum fan-out limit specified by the design requirements.
3. A clock tree structure according to claim 1, characterized in that, The first-level buffer unit, the second-level buffer unit, the third-level buffer unit, and the nth-level buffer unit can all be replaced with an even number of inverters.
4. A method for implementing a clock tree structure based on any one of claims 1 to 3, characterized in that, Specifically, it includes the following steps: Step 1: Determine if there are multiple levels of gated clocks after the clock root node. If there are multiple levels of gated clock units after the root node, flatten the multiple levels of gated clock units after the root node into a single level. Step 2: Obtain the layout of the registers directly connected after the clock root node, cut the logic unit module into L*L windows, group the registers in the window into N groups, use buffer units to push them, and set this level of buffer unit as the nth level buffer unit. Step 3: Obtain the layout of the gated clock unit and the nth level buffer unit connected after the clock root node. Cut the logic unit module into an L*L window. Group the gated clock units and the nth level buffer unit in the window into N groups and use the buffer unit to push them. This level of buffer unit is the (n-1)th level buffer unit. Step 4: Based on the clock root node obtained in Steps 1 to 3, connect the fourth-level buffer unit in groups of N and use the buffer unit buffer to drive it. This level of buffer unit is the third-level buffer unit. Step 5: Connect the first-level buffer unit from the clock port to drive the second-level buffer unit as the main clock network. The second-level buffer units are arranged at equal intervals on the central axis, and the equal interval is denoted as a. Step 6: Divide the logic unit module into multiple rectangular regions with height 'a', perpendicular to the main clock network. Each rectangular region has a second-level buffer unit at its center. Connect the output of the second-level buffer unit in the rectangular region to the input of all the third-level buffer units in that rectangular region.
5. The method for implementing a clock tree structure according to claim 4, characterized in that, The value of the equal spacing 'a' depends on the driving capability of the second-level buffer unit and the physical distance and number of the third-level buffer units within the rectangular area with height 'a'. The number of third-level buffer units is less than or equal to N, where N is the maximum fan-out limit specified by the design requirements.
6. The method for implementing a clock tree structure according to claim 4, characterized in that, The L*L-sized window is obtained by dividing the logic unit module from the middle outwards, that is, cutting the entire logic unit into several L*L-sized windows. The value of L depends on the driving capability of the driving unit connected to the load within the window.
7. The method for implementing a clock tree structure according to claim 4, characterized in that, The direction of the main clock network is determined by minimizing the distance from the load to the main network; the branch clock network is shorter than the main clock network to minimize the distance from the load to the main network and reduce propagation delay. The main clock network tree is set on the central axis of the logic unit module.
8. The method for implementing a clock tree structure according to claim 4, characterized in that, After the third-level buffer, the next level is driven by a tree structure. This tree structure has N branches to ensure that the number of loads is maximized in order to reduce the number of levels in the clock tree. N is the maximum fan-out limit specified by the design requirements.
9. The method for implementing a clock tree structure according to claim 4, characterized in that, The physical location of the nth-level buffer unit is determined by the layout of the registers, and it drives the registers within the L*L window. The value of L is determined by the driving capability of the nth-level buffer unit.