Display panel and display device

Abstract

The present invention provides a display panel and a display device. By overlapping M0 signal lines with the first driving circuit and overlapping N0 signal lines with the second driving circuit, the occupied area of some signal lines can be reduced, and the border width of the display device can be decreased. Moreover, in the present invention, the relationship between the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D1 of M0 signal lines, and the total width D2 of N0 signal lines is set as W2 > W1, D2 > D1, and D2 / W2 > D1 / W1, further optimizing the overlapping arrangement of the shift register with a larger width and the shift register with a smaller width with the total widths of their respective corresponding signal lines, fully reducing the occupied area of the driving circuit and the signal lines, and further decreasing the border width of the display device.

Description

[0001] This application is a divisional application of the patent with the application date of September 10, 2021, application number: 202111063932.7, and invention title: Display Panel and Display Device. Technical Field

[0002] The present invention relates to the field of display technologies, and more specifically, to a display panel and a display device. Background Art

[0003] In the existing display device, the border area includes a peripheral driving circuit for providing driving signals to the pixel units in the display area. In the display device, a plurality of pixel units are arranged in the display area, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected to the peripheral driving circuit at the border area, and the peripheral driving circuit provides a scan control signal and a light emission control signal to the pixel circuit to control the pixel circuit to provide a driving current to the light emitting element. However, the existing driving circuit occupies a large space, resulting in difficulty in reducing the border width of the display device. Summary of the Invention

[0004] In view of this, the present invention provides a display panel and a display device, which effectively solve the technical problems existing in the prior art and ensure that the border width of the display device is small.

[0005] To achieve the above object, the technical solutions provided by the present invention are as follows:

[0006] A display panel includes:

[0007] A driving circuit and a pixel circuit, the driving circuit provides a control signal to the pixel circuit, and the pixel circuit provides a driving current to the light emitting element of the display panel;

[0008] The driving circuit includes a first driving circuit and a second driving circuit;

[0009] A signal line group, the signal line group includes a first signal line group and a second signal line group, the first signal line group includes M signal lines for providing signals to the first driving circuit, the second signal line group includes N signal lines for providing signals to the second driving circuit, M≥1, N≥1;

[0010] In a direction perpendicular to the surface of the display panel, M0 signal lines in the first signal line group overlap with the first driving circuit, and N0 signal lines in the second signal line group overlap with the second driving circuit, 1≤M0≤M, 1≤N0≤N;

[0011] The first driving circuit includes an S1-stage shift register extending in a first direction, and the second driving circuit includes an S2-stage shift register extending in the first direction. A second direction is parallel to the plane where the display panel surface is located and perpendicular to the first direction, where S1≥2 and S2≥2; wherein,

[0012] In the second direction, the width of the first driving circuit is W1, the width of the second driving circuit is W2, the total width of the M0 signal lines in the first signal line group is D1, and the total width of the N0 signal lines in the second signal line group is D2;

[0013] W2>W1, D2>D1, and D2 / W2>D1 / W1.

[0014] Correspondingly, the present invention further provides a display device including the above-mentioned display panel.

[0015] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0016] The present invention provides a display panel and a display device. By overlapping the M0 signal lines with the first driving circuit and overlapping the N0 signal lines with the second driving circuit, the occupied area of some signal lines can be reduced, and the border width of the display device can be reduced. Moreover, in the present invention, the relationship between the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D1 of the M0 signal lines, and the total width D2 of the N0 signal lines is set as W2>W1, D2>D1, and D2 / W2>D1 / W1, further optimizing the overlapping setting of the shift register with a larger width and the shift register with a smaller width with the total widths of their respective corresponding signal lines, fully reducing the occupied area of the driving circuit and the signal lines, and further reducing the border width of the display device. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0018] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0019] Figure 2 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 3Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0021] Figure 4 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0022] Figure 5 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0023] Figure 6 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0024] Figure 7 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0025] Figure 8 A structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0026] Figure 9 is Figure 8 The structural layout of the shift register shown;

[0027] Figure 10 Another structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0028] Figure 11 is Figure 10 The structural layout of the shift register shown;

[0029] Figure 12 Another structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0030] Figure 13 is Figure 12 The structural layout of the shift register shown;

[0031] Figure 14 A structural schematic diagram of a shift register of a first driving circuit provided by an embodiment of the present invention;

[0032] Figure 15 A structural schematic diagram of a shift register of a second driving circuit provided by an embodiment of the present invention;

[0033] Figure 16 A structural schematic diagram of a signal line provided by an embodiment of the present invention;

[0034] Figure 17 Another structural schematic diagram of a signal line provided by an embodiment of the present invention;

[0035] Figure 18 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0036] Figure 19 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0037] Figure 20 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0038] Figure 21 A schematic structural diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0040] As described in the background art, the existing display device border area includes a peripheral driving circuit for providing driving signals for the pixel units in the display area. In a display device, a plurality of pixel units are arranged in its display area, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected to the peripheral driving circuit in the border area, and the peripheral driving circuit provides a scan control signal and a light emission control signal for the pixel circuit to control the pixel circuit to provide a driving current for the light emitting element. However, the existing driving circuit occupies a large space, resulting in difficulty in reducing the border width of the display device.

[0041] Based on this, the embodiments of the present invention provide a display panel and a display device, which effectively solve the technical problems existing in the prior art and ensure that the border width of the display device is small.

[0042] To achieve the above object, the technical solutions provided by the embodiments of the present invention are as follows, specifically combined with Figures 1 to 21 The technical solutions provided by the embodiments of the present invention are described in detail.

[0043] Referring to Figure 1 shown, a schematic structural diagram of a display panel provided by an embodiment of the present invention, wherein the display panel includes: a driving circuit and a pixel circuit 20, the driving circuit provides a control signal for the pixel circuit 20, and the pixel circuit 20 provides a driving current for the light emitting element 30 of the display panel.

[0044] The display panel includes a display area AA and a border area NA. The pixel circuit 20 and the light emitting element 30 can be arranged in the display area AA, and the driving circuit is arranged in the border area NA. The driving circuit includes a first driving circuit 11 and a second driving circuit 12.

[0045] Located in the border area NA, the display panel includes a signal line group, the signal line group includes a first signal line group and a second signal line group, the first signal line group includes M signal lines that provide signals for the first driving circuit 11, the second signal line group includes N signal lines that provide signals for the second driving circuit 12, M≥1, N≥1. And, in the direction perpendicular to the surface of the display panel (i.e., in the direction perpendicular to the light-emitting direction of the display panel), M0 signal lines 110 in the first signal line group overlap with the first driving circuit 11, and N0 signal lines 120 in the second signal line group overlap with the second driving circuit 12, 1≤M0≤M, 1≤N0≤N.

[0046] The first driving circuit 11 includes an S1-stage shift register extending along the first direction Y, the second driving circuit 12 includes an S2-stage shift register extending along the first direction Y, and the first driving circuit 11 and the second driving circuit 12 can be arranged along the second direction X. Wherein, the second direction X is parallel to the plane where the surface of the display panel is located and perpendicular to the first direction Y, S1≥2, S2≥2; wherein,

[0047] Along the second direction X, the width of the first driving circuit 11 is W1, the width of the second driving circuit 12 is W2, the total width of the M0 signal lines 110 in the first signal line group is D1, and the total width of the N0 signal lines 120 in the second signal line group is D2; W2>W1, D2>D1, and D2 / W2>D1 / W1.

[0048] It can be understood that by overlapping the M0 signal lines with the first driving circuit and overlapping the N0 signal lines with the second driving circuit, wherein the extending directions of the M0 signal lines and the N0 signal lines are the first direction, the occupied area of some signal lines can be reduced, and the border width of the display device can be reduced.

[0049] In the second direction, when the width of the driving circuit is wider and the width of the signal line is wider, the border of the display panel is larger. To reduce the border, generally, the signal line and the driving circuit can be set to overlap each other to reduce the border. When there is more than one set of driving circuits in the border, how to set it to sufficiently reduce the border becomes a problem. Based on this problem, the inventors of the present application found that when W2 > W1 and D2 > D1, by setting D2 / W2 > D1 / W1, the width of the signal line overlapped by the driving circuit with a larger width is also larger, so as to sufficiently reduce the width occupied by the driving circuit with a larger width and the signal line connected thereto on the display panel, so that the driving circuit with a larger width and the driving circuit with a smaller width both achieve a better overlapping relationship with their respective signal lines, and the border is sufficiently reduced. Therefore, in the embodiment of the present application, by setting the relationship between the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D1 of M0 signal lines, and the total width D2 of N0 signal lines as W2 > W1, D2 > D1, and D2 / W2 > D1 / W1, the overlapping setting of the shift register with a larger width and the shift register with a smaller width with the total width of their respective corresponding signal lines is further optimized, the occupied area of the driving circuit and the signal line is sufficiently reduced, and the border width of the display device is further reduced.

[0050] In an embodiment of the present invention, the display panel provided by the present invention may be a single-sided driving panel structure. For example, Figure 1 as described, the first driving circuit 11 and the second driving circuit 12 of the driving circuit are located on one side of the display area AA, and the pixel circuit 20 is driven by a single-sided driving circuit. Alternatively, the display panel provided by the present invention may also be a double-sided driving panel structure. For example, Figure 2 as shown, the driving circuit includes the first driving circuit 11 located on both sides of the display area AA, and the driving circuit includes the second driving circuit 12 located on both sides of the display area AA, and then the pixel circuit 20 is driven by a double-sided driving circuit.

[0051] For example, Figure 2 as shown, in the double-sided driving panel structure provided by the embodiment of the present invention, the pixel circuits 20 in the same row can be simultaneously driven by two first driving circuits 11 located on different sides of the display area AA, and the pixel circuits 20 in the same row can be simultaneously driven by two second driving circuits 12 located on different sides of the display area AA.

[0052] It can be understood that the first driving circuits (defined as the first-side first driving circuit and the second-side first driving circuit) on different sides of the display area each include a plurality of cascaded shift registers. The first-stage shift register of the first-side first driving circuit and the first-stage shift register of the second-side first driving circuit are both electrically connected to the pixel circuits in the first row. The second-stage shift register of the first-side first driving circuit and the second-stage shift register of the second-side first driving circuit are both electrically connected to the pixel circuits in the second row, and so on. The last-stage shift register of the first-side first driving circuit and the last-stage shift register of the second-side first driving circuit are both electrically connected to the pixel circuits in the last row. Similarly, the second driving circuits (defined as the first-side second driving circuit and the second-side second driving circuit) on different sides of the display area each include a plurality of cascaded shift registers. The first-stage shift register of the first-side second driving circuit and the first-stage shift register of the second-side second driving circuit are both electrically connected to the pixel circuits in the first row. The second-stage shift register of the first-side second driving circuit and the second-stage shift register of the second-side second driving circuit are both electrically connected to the pixel circuits in the second row, and so on. The last-stage shift register of the first-side second driving circuit and the last-stage shift register of the second-side second driving circuit are both electrically connected to the pixel circuits in the last row.

[0053] Alternatively, as Figure 3 shown, in the panel structure with bilateral driving provided by the embodiment of the present invention, the pixel circuits 20 in different rows can be respectively driven by two first driving circuits 11 located on different sides of the display area AA, and the pixel circuits 20 in different rows can be respectively driven by two second driving circuits 12 located on different sides of the display area AA.

[0054] It can be understood that the odd-stage first driving circuits in the first driving circuit are located on the first side of the display area, while the even-stage first driving circuits in the first driving circuit are located on the second side of the display area. Among them, the odd-stage first driving circuits are correspondingly electrically connected to the pixel circuits in the odd rows, and the even-stage first driving circuits are correspondingly electrically connected to the pixel circuits in the even rows. Similarly, the odd-stage second driving circuits in the second driving circuit are located on the first side of the display area, while the even-stage second driving circuits in the second driving circuit are located on the second side of the display area. Among them, the odd-stage second driving circuits are correspondingly electrically connected to the pixel circuits in the odd rows, and the even-stage second driving circuits are correspondingly electrically connected to the pixel circuits in the even rows.

[0055] In an embodiment of the present invention, the display panel provided by the present invention includes a substrate, and the driving circuit and the pixel circuit are located on the substrate; the M0 signal lines are located on a side of the first driving circuit away from the substrate, the N0 signal lines are located on a side of the second driving circuit away from the substrate, and the M0 signal lines are located on the same layer, and / or the N0 signal lines are located on the same layer. As Figure 4 As shown, it is a schematic structural diagram of another display panel provided by an embodiment of the present invention. The display panel includes a substrate 100. A transistor array layer located on the substrate 100, the transistor array layer includes a semiconductor layer 210 located on the substrate 100, and the semiconductor layer 210 includes a plurality of active regions; a gate insulating layer 220 located on a side of the semiconductor layer 210 away from the substrate 100; a gate metal layer 230 located on a side of the gate insulating layer 220 away from the substrate 100, and the gate metal layer 230 includes a plurality of gates and a plurality of first capacitor plates; an interlayer insulating layer 240 located on a side of the gate metal layer 230 away from the substrate 100; a capacitor metal layer 250 located on a side of the interlayer insulating layer 240 away from the substrate 100, and the capacitor metal layer 250 includes second capacitor plates that are disposed opposite and overlapping the first capacitor plates; an isolation layer 260 located on a side of the capacitor metal layer 250 away from the substrate 100; a source-drain metal layer 270 located on a side of the isolation layer 260 away from the substrate 100, and the source-drain metal layer 270 includes a plurality of source electrodes and drain electrodes, and the source electrodes and drain electrodes are in contact connection with the active regions through their respective corresponding vias; wherein, the transistor array layer includes a driving circuit and a pixel circuit. A first insulating layer 310 located on a side of the source-drain metal layer 270 away from the substrate 100. M0 signal lines 110 located on a side of the first insulating layer 310 away from the substrate 100, and the M0 signal lines 110 can be prepared from the same conductive layer. And, the display panel further includes N0 signal lines 120 located on a side of the first insulating layer 310 away from the substrate 100, and the N0 signal lines 120 can be prepared from the same conductive layer.

[0056] As Figure 4 As shown, the M0 signal lines 110 and the N0 signal lines 120 provided by the embodiment of the present invention can be prepared from the same conductive layer, that is, the M0 signal lines 110 and the N0 signal lines 120 are located on the same layer. Or, as Figure 5As shown, it is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Among them, the M0 signal lines 110 and the N0 signal lines 120 provided by the embodiment of the present invention can be prepared from different conductive layers, that is, there is a second insulating layer 320 between the M0 signal lines 110 and the N0 signal lines 120. Among them, the M0 signal lines 110 or the N0 signal lines 120 can be located on the side of the second insulating layer 320 close to the first insulating layer 310. The present invention does not make specific limitations on this.

[0057] In an embodiment of the present invention, the present invention can further optimize the widths of the signal lines and the driving circuit, and then optimize the width of the border area of the display panel to achieve the trend of narrow borders. Among them, along the second direction, the total width of the M signal lines is D11, and the total width of the N signal lines is D22; where [(W1 - D11) - (W2 - D22)] × [(D11 - D1) - (D22 - D2)] ≤ 0.

[0058] It can be understood that among the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D11 of the M signal lines, the total width D1 of the M0 signal lines, the total width D22 of the N signal lines, and the total width D2 of the N0 signal lines provided by the embodiment of the present invention, the larger one of (W1 - D11) and (W2 - D22) indicates that the difference between the total width of the signal lines and the width of the corresponding driving circuit is larger, and the total width of the signal lines is smaller than the width of the corresponding driving circuit. At this time, there is more space in the area where the driving circuit is located to set the signal lines that overlap with the driving circuit. Furthermore, since the area where the corresponding driving circuit (the first driving circuit or the second driving circuit) is located can overlap more signal lines, then the driving circuit corresponds to the smaller one of (D11 - D1) and (D22 - D2). By setting like this, it can fully save the border area of the display panel, avoid waste of extra space, and conform to the narrow border design. Optionally, (D11 - D1) = (D22 - D2) = 0 provided by the embodiment of the present invention, that is, all M signal lines overlap with the first driving circuit, and all N signal lines overlap with the second driving circuit, maximizing the reduction of the width of the border area of the display panel and ensuring that the border of the display panel is narrower.

[0059] As Figure 6 As shown, it is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Among them, the relationship between the number of the N0 signal lines 120 and the number of the M0 signal lines 110 provided by the embodiment of the present invention can be: N0 - M0 ≥ 1.

[0060] It can be understood that for the first driving circuit provided in the embodiment of the present invention, the width W1, the width W2 of the second driving circuit, the total width D1 of the M0 signal lines, and the total width D2 of the N0 signal lines satisfy the relationship: W2 > W1, D2 > D1, and D2 / W2 > D1 / W1. Therefore, by setting the number of the N0 signal lines and the number of the M0 signal lines such that N0 - M0 ≥ 1, the number of overlaps between the N0 signal lines and the second driving circuit is increased, achieving the purpose of reducing the width of the border area.

[0061] As Figure 7 shown, it is a schematic structural diagram of another display panel provided in the embodiment of the present invention. Among them, the i-th signal line 11i in the M0-th signal line 120 and the j-th signal line 12j in the N0 signal lines are signal lines for transmitting the same functional signal; along the second direction X, the width of the i-th signal line 11i is Di, and the width of the j-th signal line 12j is Dj; where Dj > Di. Here, the i-th signal line is any signal line among the M0 signal lines, and the j-th signal line is any signal line among the N0 signal lines.

[0062] It should be noted that the i-th signal line and the j-th signal line provided in the embodiment of the present invention can be a single signal line or a combination of multiple signal lines, and the present invention does not make specific limitations in this regard. Among them, when the i-th signal line and the j-th signal line are a combination of multiple signal lines, the widths of the i-th signal line and the j-th signal line are the total widths of the signal lines included respectively.

[0063] It can be understood that the width W2 of the second driving circuit is greater than the width W1 of the first driving circuit. Compared with the transistors in the shift register of the first driving circuit, the occupied area of the transistors in the shift register of the second driving circuit is larger, and in many cases, the output requirements of the shift register in the second driving circuit may be higher. Therefore, in order to ensure the accuracy and stability of signal transmission and output of the second driving circuit, the second driving circuit needs to be connected to wider signal lines to reduce the voltage drop on the signal lines and avoid large fluctuations in the signals transmitted on the signal lines. Thus, for the technical solution provided in the embodiment of the present invention, the width W2 of the second driving circuit is larger, and at the same time, the j-th signal line with a larger width is overlapped with the second driving circuit in the light-emitting direction of the display panel, which can, on the premise of ensuring the normal output of the second driving circuit, avoid the j-th signal line from affecting the width of the border area of the display panel and ensure that the width of the display panel is smaller.

[0064] In an embodiment of the present invention, the i-th signal line 11i and the j-th signal line 12j provided by the present invention can both be clock signal lines; the first driving circuit 11 provides a light-emitting control signal for the light-emitting control transistor of the pixel circuit 20, and the second driving circuit 12 provides a control signal for the PMOS transistor in the pixel circuit 20; where Dj / W2 > Di / W1.

[0065] Specific combination Figure 8 and Figure 9 as shown Figure 8 FIG. is a schematic structural diagram of a shift register provided by an embodiment of the present invention Figure 9 is Figure 8 a structural layout of the shift register shown Figure 8 It may be a schematic structural diagram of a shift register in a first driving circuit. Among them, the shift register in the first driving circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a first capacitor C11, a second capacitor C12, and a third capacitor C13. Among them, the first signal line group includes a start signal line STV1 (where the start signal line STV1 provides an enable signal for the shift register at the end in the cascaded shift register of the first driving circuit), a clock signal line CK1, a clock signal line XCK1 (the pulse signals transmitted by the clock signal line CK1 and the clock signal line XCK1 are in opposite phases), a low-level voltage signal line VGL, and a high-level voltage signal line VGH. Among them, signals are provided for the shift register in the first driving circuit through the first signal line group, and then through the cooperation of the first transistor M1 to the thirteenth transistor M13 and the first capacitor C11 to the third capacitor C13, finally enabling the shift register to output a light emission control signal for controlling the light emission control transistor in the pixel circuit 20. The start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-level voltage signal line VGL, and the high-level voltage signal line VGH provided by the embodiment of the present invention can all overlap with the first driving circuit. That is, the M0 signal lines include the start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-level voltage signal line VGL, and the high-level voltage signal line VGH, ensuring that the width of the border area of the display panel is small.

[0066] And in combination with Figure 10 and Figure 11 as shown Figure 10 FIG. is a schematic structural diagram of another shift register provided by an embodiment of the present invention Figure 11 is Figure 10 a structural layout of the shift register shown Figure 10It may be a schematic structural diagram of a shift register in the second driving circuit. Optionally, the second driving circuit is used to control PMOS transistors in the pixel circuit. The shift register in the second driving circuit includes a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a fifth transistor P5, a sixth transistor P6, a seventh transistor P7, an eighth transistor P8, a first capacitor C21, and a second capacitor C22. The second signal line group includes a start signal line STV2 (where the start signal line STV2 provides an enable signal for the shift register at the end in the cascaded shift registers in the second driving circuit), a clock signal line CK2, a clock signal line XCK2, a low-level voltage signal line VGL, and a high-level voltage signal line VGH. Signals are provided to the shift register in the second driving circuit through the second signal line group. Then, through the cooperation of the first transistor P1 to the eighth transistor P8, the first capacitor C21, and the second capacitor C23, finally, the shift register outputs a control signal for controlling the operation of the PMOS transistor in the pixel circuit 20. The start signal line STV2, the clock signal line CK2, the clock signal line XCK2 (the pulse signals transmitted by the clock signal line CK2 and the clock signal line XCK2 are out of phase), the low-level voltage signal line VGL, and the high-level voltage signal line VGH provided in the embodiments of the present invention can all overlap with the second driving circuit. That is, the N0 signal lines include the start signal line STV2, the clock signal line CK2, the clock signal line XCK2, the low-level voltage signal line VGL, and the high-level voltage signal line VGH, ensuring a smaller width of the border area of the display panel.

[0067] Combined Figure 11 As shown, the j signal lines provided in the embodiments of the present invention include a j1 signal line CK2 and a j2 signal line XCK2. Along the second direction X, the j2 signal line XCK2 is located on the side of the j1 signal line CK2 facing the display area AA of the display panel. The width of the j1 signal line CK2 is Dj1, and the width of the j2 signal line XCK2 is Dj2, where Dj2 > Dj1; among them, Dj1 ≥ Di, and / or, Dj2 ≥ Di. Optionally, Dj = Dj1 + Dj2.

[0068] It can be understood that the j signal line provided in the embodiment of the present invention is related to the output control of the second driving circuit and other related control processes of the circuit. Therefore, the j signal line can be substantially set as a combination of a j1 signal line and a j2 signal line, and the j2 signal line can be disposed on the side of the j1 signal line facing the display area. Moreover, since the output end of the driving circuit is generally disposed on the side facing the display area to facilitate electrical connection with the pixel circuit in the display area, and the j2 signal line may be connected to the output module of the shift register. In this regard, the width of the j2 signal line is designed to be larger to ensure the transmission stability of the signal accessed by the output module. Thus, Dj2 can be designed to be greater than Dj1; and on this basis, the width relationship can also be set as Dj1≥Di, and / or, Dj2≥Di, so as to further meet the high transmission stability of the signal accessed by the shift register of the second driving circuit with a larger width. At the same time, the width W2 of the second driving circuit provided in the embodiment of the present invention is larger. Therefore, a wider j signal line can be set to overlap with it to achieve a narrow border design.

[0069] In an embodiment of the present invention, the i signal line and the j signal line provided by the present invention can also be other types of signal lines. That is, the i signal line 11i and the j signal line provided by the present invention can also be the same high-level voltage signal line or low-level voltage signal line; the first driving circuit 11 provides a light emission control signal for the light emission control transistor of the pixel circuit 20. Optionally, the second driving circuit 12 provides a control signal for the NMOS transistor in the pixel circuit 20, and the NMOS transistor is connected to the gate of the driving transistor; wherein, Dj / W2>Di / W1. Wherein, the driving transistor is the transistor in the pixel circuit 20 for providing a driving current, and the light emitting element in the pixel circuit 20 emits light in response to the driving current.

[0070] The shift register of the first driving circuit provided in the embodiment of the present invention can be as Figure 8 and Figure 9 shown in the circuit structure of the shift register. And in combination with Figure 12 and Figure 13 shown, Figure 12 is a schematic structural diagram of another shift register provided in the embodiment of the present invention, Figure 13 is Figure 12 shown in the layout of the shift register. Figure 12It can be a schematic structural diagram of a shift register in the second driving circuit. Optionally, the second driving circuit is used to control the NMOS transistors in the pixel circuit. The shift register in the second driving circuit includes a first transistor N1, a second transistor N2, a third transistor N3, a fourth transistor N4, a fifth transistor N5, a sixth transistor N6, a seventh transistor N7, an eighth transistor N8, a ninth transistor N9, a tenth transistor N10, an eleventh transistor N11, a twelfth transistor N12, a thirteenth transistor N13, a first capacitor C31, a second capacitor C32, and a third capacitor C33. The second signal line group includes a start signal line STV3 (where the start signal line STV3 provides an enabling signal for the shift register at the end in the cascaded shift registers of the second driving circuit), a clock signal line CK3, a clock signal line XCK3 (the pulse signals transmitted by the clock signal line CK3 and the clock signal line XCK3 are in opposite phases), a low-level voltage signal line VGL, and a high-level voltage signal line VGH. Signals are provided to the shift register in the second driving circuit through the second signal line group. Then, through the cooperation of the first transistor N1 to the thirteenth transistor N13 and the first capacitor C31 to the third capacitor C33, finally, the shift register outputs a control signal for controlling the operation of the NMOS transistors in the pixel circuit 20. The start signal line STV3, the clock signal line CK3, the clock signal line XCK3, the low-level voltage signal line VGL, and the high-level voltage signal line VGH provided in the embodiments of the present invention can all overlap with the second driving circuit. That is, the N0 signal lines include the start signal line STV3, the clock signal line CK3, the clock signal line XCK3, the low-level voltage signal line VGL, and the high-level voltage signal line VGH, ensuring that the width of the border area of the display panel is small.

[0071] Combined with Figure 8 and Figure 12As shown, when the i signal line and the j signal line are both the high-level voltage signal line VGH or the low-level voltage signal line VGL, in the shift register of the first driving circuit and the shift register of the second driving circuit, the output transistors (the ninth transistor M9 and the tenth transistor M10) of the shift register of the first driving circuit and the output transistors (the ninth transistor N9 and the tenth transistor N10) of the shift register of the second driving circuit are connected to the high-level voltage signal line VGH and the low-level voltage signal line VGL; since the gate potential of the driving transistor in the pixel circuit is closely related to the magnitude of the driving current, the NMOS transistor connecting the gate of the driving transistor has relatively high requirements for the stability and leakage current of the NMOS transistor to ensure high stability of the potential of the gate of the driving transistor. Therefore, in the embodiment of the present invention, by designing the width W2 of the second driving circuit to be larger, the output stability of the shift register in the second driving circuit can be made higher; and since the width W2 of the second driving circuit is designed to be larger, a larger Dj parameter can be designed, and finally the purpose of reducing the voltage drop of the transmitted signal and ensuring the stability of the transmitted signal can be achieved, and at the same time, a narrow bezel design can be realized, and the width relationship is further optimized to Dj / W2 > Di / W1.

[0072] As Figure 13 shown, the j signal line includes a j1 signal line VGL and a j2 signal line VGH. Along the second direction X, the j2 signal line VGH is located on the side of the j1 signal line VGL facing the display area AA of the display panel. The width of the j1 signal line VGL is Dj1, and the width of the j2 signal line VGH is Dj2, and Dj2 > Dj1; wherein, Dj1 ≥ Di, and / or, Dj2 ≥ Di. Optionally, Dj = Dj1 + Dj2.

[0073] It can be understood that the j signal line provided in the embodiment of the present invention is related to the output of the second driving circuit and other related control processes of other circuits. Therefore, the j signal line can be substantially set as a combination of the j1 signal line and the j2 signal line, and the j2 signal line can be arranged on the side of the j1 signal line facing the display area. And since the output end of the driving circuit is on the side facing the display area to facilitate electrical connection with the pixel circuit in the display area, and the j2 signal line is connected to the output module of the shift register. For this reason, the width of the j2 signal line is designed to be larger to ensure the transmission stability of the signal accessed by the output module. Thus, Dj2 can be designed to be greater than Dj1; and on this basis, the width relationship can also be set as Dj1 ≥ Di, and / or, Dj2 ≥ Di, so as to meet the high transmission stability of the signal accessed by the shift register of the second driving circuit with a larger width. At the same time, the width W2 of the second driving circuit provided in the embodiment of the present invention is larger, so a wider j signal line can be arranged to overlap with it to realize the narrow bezel design.

[0074] In an embodiment of the present invention, the first-stage shift register of the first driving circuit provided by the present invention includes x1 transistors and y1 capacitors, where x1 ≥ 1 and y1 ≥ 1; the first-stage shift register of the second driving circuit includes x2 transistors and y2 capacitors, where x1 ≥ 1 and y2 ≥ 1; at least one of the M0 signal lines overlaps with at least one of the x1 transistors and does not overlap with any of the y1 capacitors; and / or, at least one of the N0 signal lines overlaps with at least one of the x2 transistors and does not overlap with any of the y2 capacitors.

[0075] It can be understood that the signal line is used to transmit signals. When the signal line overlaps with the capacitor, it is equivalent to a new capacitor being connected to the original capacitor, which will cause the capacitance value to change, not only affecting the capacitor, but also affecting the stability of signal transmission on the signal line. Therefore, the shift registers in the first driving circuit and the second driving circuit provided in the embodiments of the present invention both include multiple transistors and at least one capacitor. Among the signal lines overlapping with the driving circuit (the first driving circuit and / or the second driving circuit), at least one signal line only overlaps with the transistors and does not overlap with the capacitors, ensuring the stability of signal transmission on the signal line and the reliability of the capacitors in the driving circuit.

[0076] Specifically, as Figure 14 and Figure 15 shown, Figure 14 FIG. is a schematic structural diagram of a shift register of a first driving circuit provided by an embodiment of the present invention, Figure 15 FIG. is a schematic structural diagram of a shift register of a second driving circuit provided by an embodiment of the present invention. Among them, the M0 signal lines in the shift register of the first driving circuit include a start signal line STV1, a clock signal line CK1, a clock signal line XCK1, a low-level voltage signal line VGL, and a high-level voltage signal line VGH. Among them, the start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-level voltage signal line VGL, and the high-level voltage signal line VGH all overlap with the transistors included in the shift register, and the start signal line STV1, the clock signal line CK1, and the clock signal line XCK1 do not overlap with the capacitors included in the shift register, thereby being able to improve the situation where the capacitance value of the capacitors in the shift register changes, and at the same time being able to ensure high stability of signal transmission on the signal line.

[0077] Moreover, among the N0 signal lines in the shift register of the second driving circuit, there are a start signal line STV2, a clock signal line CK2, a clock signal line XCK2, a low-level voltage signal line VGL, and a high-level voltage signal line VGH. Among them, the start signal line STV2, the clock signal line CK2, the clock signal line XCK2, the low-level voltage signal line VGL, and the high-level voltage signal line VGH all overlap with the transistors included in the shift register, and the start signal line STV2, the clock signal line CK2, the low-level voltage signal line VGL, and the clock signal line XCK2 do not overlap with the capacitors included in the shift register. Therefore, the situation where the capacitance value of the capacitors in the shift register changes can be improved, and at the same time, the stability of the signals transmitted on the signal lines can be ensured to be high.

[0078] Furthermore, among the M0 signal lines provided in the embodiment of the present invention, at least one clock signal line does not overlap with any one of the y1 capacitors; and / or, among the N0 signal lines, at least one clock signal line does not overlap with any one of the y2 capacitors. It can be understood that since the pulse signal is transmitted on the clock signal line, the pulse signal is not only easily affected by the capacitor, but also the pulse signal can affect the charging and discharging process of the capacitor. The non-overlapping design of the clock signal line and the capacitor in the present invention can effectively ensure the high stability of the pulse signal transmission on the clock signal line and ensure the high reliability of the capacitor. Specifically, as Figure 14 and Figure 15 shown, the clock signal line CK1 and the clock signal line XCK1 do not overlap with the capacitors of the corresponding shift register, that is, the clock signal line CK2 and the clock signal line XCK2 do not overlap with the capacitors of the corresponding shift register.

[0079] In an embodiment of the present invention, among the M0 signal lines provided by the present invention, the signal line with the largest width in the second direction does not overlap with any one of the y1 capacitors; and / or, among the N0 signal lines, the signal line with the largest width in the second direction does not overlap with any one of the y2 capacitors. Since the size of the capacitor is proportional to the relative area of the electrodes, the method of setting the signal line with a larger width not to overlap with the capacitor is adopted to avoid a large change in the capacitance value of the capacitor in the driving circuit, ensure the high stability of the signal transmitted on the signal line, and ensure the high reliability of the capacitor.

[0080] Such as Figure 16As shown in the figure, it is a schematic structural diagram of a signal line provided by an embodiment of the present invention. Among them, the M0 signal lines or the N0 signal lines provided by the embodiment of the present invention include a first clock signal line CKL for transmitting a first clock signal and a second clock signal line XCKL for transmitting a second clock signal (the pulse signals transmitted by the clock signal line CKL and the clock signal line XCKL are in opposite phases), and a first voltage signal line VG1 for transmitting a constant first voltage signal; the first clock signal line CKL and the first voltage signal line VG1 are respectively located on both sides of the second clock signal line XCKL; wherein, the distance L1 between the first clock signal line CKL and the second clock signal line XCKL is greater than the distance L2 between the first voltage signal line VG1 and the second clock signal line XCKL. Among them, the first voltage signal line VG1 can be a low-level voltage signal line or a high-level voltage signal line.

[0081] It can be understood that the pulse signals transmitted by the clock signal line CKL and the clock signal line XCKL provided by the embodiment of the present invention are in opposite phases. Therefore, a relatively large distance needs to be set between the clock signal line CKL and the clock signal line XCKL to avoid a large impact on their respective pulse signals caused by the electric field generated between them when the signals on the clock signal line CKL and the clock signal line XCKL undergo signal transitions. The first voltage signal line VG1 transmits a constant voltage signal, which has no rising edge and falling edge. Therefore, the impact is relatively small when its distance from the clock signal line is small. The distance L2 between it and the second clock signal line XCKL can be set to be less than the distance L1 between the first clock signal line CKL and the second clock signal line XCKL to optimize the layout space of the circuit.

[0082] As Figure 17 As shown in the figure, it is another schematic structural diagram of a signal line provided by an embodiment of the present invention. Among them, the M0 signal lines or the N0 signal lines include a first voltage signal line VG1 for transmitting a constant first voltage signal, a second voltage signal line VG2 for transmitting a constant second voltage signal, and a first clock signal line CK for transmitting a first clock signal; the first voltage signal line VG1 and the first clock signal line CK are respectively located on both sides of the second voltage signal line VG2; wherein, the distance L3 between the first voltage signal line VG1 and the second voltage signal line VG2 is greater than the distance L4 between the first clock signal line CK and the second voltage signal line VG2.

[0083] It can be understood that the first voltage signal line VG1 and the second voltage signal line VG2 provided in the embodiments of the present invention transmit different level voltage signals. That is, when the first voltage signal line VG1 is a high-level voltage signal line, the second voltage signal line VG2 is a low-level voltage signal line; and when the first voltage signal line VG1 is a low-level voltage signal line, the second voltage signal line VG2 is a high-level voltage signal line. Therefore, it is required that the voltage signal lines VG1 and VG2 have high signal transmission stability. In the present invention, the distance between the first voltage signal line VG1 and the second voltage signal line VG2 is set to be relatively large to avoid mutual influence between the two, resulting in poor signal stability of their respective transmissions and unstable output signals of the driving circuit.

[0084] As Figure 18 shown, it is a schematic structural diagram of another display panel provided by the embodiments of the present invention. Among them, the driving circuit further includes a third driving circuit 13, the signal line group further includes a third signal line group, and the third signal line group includes P signal lines that provide signals for the third driving circuit 13, where P≥1; in the direction perpendicular to the surface of the display panel, P0 signal lines 130 in the third signal line group intersect with the third driving circuit 13, where 1≤P0≤P; the third driving circuit 13 includes an S3-stage shift register extending along the first direction Y, where S3≥2; among them, in the second direction X, the width of the third driving circuit 13 is W3, and the total width of the P0 signal lines 130 in the third signal line group is D3; W2>W3, and D3 / W3>D2 / W2>D1 / W1.

[0085] It can be understood that the driving circuit provided by the embodiments of the present invention may include a first driving circuit, a second driving circuit, and a third driving circuit. The width W2 of the second driving circuit is greater than the width W3 of the third driving circuit, and the width W3 of the third driving circuit provided by the embodiments of the present invention may be located between the width W1 of the first driving circuit and the width W2 of the second driving circuit. Among them, the total width D3 of the P0 signal lines 130 provided by the embodiments of the present invention is relatively large, such that D3 / W3>D2 / W2>D1 / W1.

[0086] When the width W3 of the third driving circuit is relatively small compared to the width W2 of the second driving circuit and the output requirements for it are relatively high, on the one hand, the widths of some of the P signal lines corresponding to it are relatively wide. In order not to affect the border space, it needs to be set to intersect with the third driving circuit as much as possible. In this case, the situation that may occur is that W3 is not too large, but D3 is relatively large, so the situation of D3 / W3>D2 / W2>D1 / W1 may occur. At this time, because D3 is relatively large, that is, P0 signal lines with relatively wide widths among the P signal lines are all set to intersect with the third driving circuit, so as not to increase the border area additionally.

[0087] As shown in Figure 18 the figure, for the technical solution provided by the embodiment of the present invention, optionally, the first driving circuit 11, the third driving circuit 13, and the second driving circuit 12 may be arranged side by side along the second direction X, so as to facilitate providing different driving signals for each row of pixel circuits. Further optionally, along the second direction X, the first driving circuit 11, the third driving circuit 13, and the second driving circuit 12 are sequentially arranged from the frame N1 of the display panel towards the display area AA of the display panel; the first driving circuit 11 provides a light emission control signal for the light emission control transistor of the pixel circuit 20; the second driving circuit 12 provides a control signal for the PMOS transistor in the pixel circuit 20; the third driving circuit 13 provides a control signal for the NMOS transistor in the pixel circuit 20, and the NMOS transistor is connected to the gate of the driving transistor.

[0088] It should be noted that the pixel circuit provided by the embodiment of the present invention may include a driving transistor, a light emission control transistor, and the remaining NMOS transistors and PMOS transistors. Among them, the driving transistor is used to generate a driving current, and the light emitting element in the pixel circuit emits light in response to the driving circuit; and, the light emission control transistor is used to transmit the driving current to the light emitting element according to the control of the light emission control signal. And, the remaining NMOS transistors and PMOS transistors are used to perform controls such as resetting the pixel circuit and threshold capture of the driving transistor, which are the same as the prior art, and the present invention will not elaborate further.

[0089] In an embodiment of the present invention, the display panel provided by the present invention may be a single-sided driving panel structure, as Figure 18 described, the first driving circuit 11, the second driving circuit 12, and the third driving circuit of the driving circuit are located on one side of the display area AA, and the pixel circuit 20 is driven by the single-sided driving circuit. Or, the display panel provided by the present invention may also be a double-sided driving panel structure, as Figure 18 shown in the figure, the driving circuit includes the first driving circuit 11 located on both sides of the display area AA, the driving circuit includes the second driving circuit 12 located on both sides of the display area AA, and the driving circuit includes the third driving circuit 13 located on both sides of the display area AA, and then the pixel circuit 20 is driven by the double-sided driving circuit.

[0090] As shown in Figure 19As shown, in the panel structure with bilateral driving provided by the embodiments of the present invention, the pixel circuits 20 in the same row can be simultaneously driven by two first driving circuits 11 located on different sides of the display area AA, the pixel circuits 20 in the same row can be simultaneously driven by two second driving circuits 12 located on different sides of the display area AA, and the pixel circuits 20 in the same row can be simultaneously driven by two third driving circuits 13 located on different sides of the display area AA.

[0091] Alternatively, as Figure 20 shown, in the panel structure with bilateral driving provided by the embodiments of the present invention, the pixel circuits 20 in different rows can be respectively driven by two first driving circuits 11 located on different sides of the display area AA, the pixel circuits 20 in different rows can be respectively driven by two second driving circuits 12 located on different sides of the display area AA, and the pixel circuits 20 in different rows can be respectively driven by two third driving circuits 13 located on different sides of the display area AA.

[0092] In an embodiment of the present invention, along the second direction X, the width of the output transistor of the first driving circuit 11 is smaller than the width of the output transistor of the third driving circuit 13, and the width of the output transistor of the third driving circuit 13 is smaller than the width of the output transistor of the second driving circuit 12. Herein, the output transistor is the transistor connected to the output end of the shift register, and is used to output relevant control signals to the output end of the shift register. Specifically, in combination with Figures 8 to 13 shown, where Figure 8 and Figure 9 shown can be the shift register of the first driving circuit 11. Herein, the output transistors of the shift register of the first driving circuit are the ninth transistor M9 and the tenth transistor M10. The ninth transistor M9 is used to transmit the output signal of the high-level voltage signal line VGH to the output end OUT1 of the shift register, and the tenth transistor M10 is used to transmit the output signal of the low-level voltage signal line VGL to the output end OUT1 of the shift register. Figure 10 and Figure 11 shown can be the shift register of the second driving circuit 12. Herein, the output transistors of the shift register of the second driving circuit are the seventh transistor P7 and the eighth transistor P8. The seventh transistor P7 is used to transmit the output signal of the high-level voltage signal line VGH to the output end OUT2 of the shift register, and the eighth transistor P8 is used to transmit the pulse signal of the clock signal line XCK2 to the output end OUT2 of the shift register. And Figure 12 and Figure 13It may be the shift register of the third driving circuit 13. The output transistors of the shift register of the third driving circuit are the ninth transistor N9 and the tenth transistor N10. The ninth transistor N9 is used to transmit the output signal of the high-level voltage signal line VGH to the output terminal OUT3 of the shift register, and the tenth transistor N10 is used to transmit the output signal of the low-level voltage signal line VGL to the output terminal OUT3 of the shift register.

[0093] It should be noted that the shift registers shown in the first driving circuit, the second driving circuit, and the third driving circuit provided in the embodiments of the present invention are not limited to Figures 8 to 13 the shift register shown. It may also be other types of shift register structures, and the present invention does not make specific limitations thereto.

[0094] In an embodiment of the present invention, the relationship between the width W1 of the first driving circuit, the width W2 of the second driving circuit, the width W3 of the third driving circuit, the total width D1 of M0 signal lines, the total width D2 of N0 signal lines, and the total width D3 of P0 signal lines may be D3 / W3 - D2 / W2 < D2 / W2 - D1 / W1. Among them, the shift registers in the second driving circuit and the third driving circuit have relatively high requirements for the output signal, while the shift register in the first driving circuit has relatively low requirements for the output signal. Therefore, the present invention can design the values of D3 / W3 and D2 / W2 to be relatively close to fully avoid the problem of increased border area caused by the relatively wide width of their corresponding signal lines, and the difference between the former two and the value of D1 / W1 is designed to be relatively large.

[0095] In an embodiment of the present invention, the relationship between the number of M0 signal lines, the number of N0 signal lines, and the number of P0 signal lines provided by the present invention may be set as M0 < P0 < N0. The width of the second driving circuit provided in the embodiments of the present invention is greater than the width of the third driving circuit, and the width of the third driving circuit is greater than the width of the first driving circuit. Furthermore, by setting the number of signal lines as M0 < P0 < N0, because the number of signal lines corresponding to the second driving circuit is relatively large, or the width of the signal lines corresponding to the second driving circuit is relatively wide. Therefore, setting N0 to be relatively large can fully avoid the second driving circuit and its corresponding signal lines from occupying too much border area; the width of the third driving circuit is smaller than the width of the second driving circuit. If the output requirements for the third driving circuit are relatively high, the number of its corresponding signal lines may also be relatively large, or the width of the signal lines may be relatively large. Therefore, setting P0 to be relatively large can fully avoid the second driving circuit and its corresponding signal lines from occupying too much border area; the first driving circuit itself has a relatively small width and may not have enough space to overlap the corresponding signal lines. Therefore, M0 can be set relatively small; such a setting can ensure the optimization of the overlap between the signal lines and the driving circuit and reduce the border width of the display panel.

[0096] In an embodiment of the present invention, the M0 signal lines provided by the present invention include third clock signal lines for transmitting a third clock signal; the N0 signal lines include fourth clock signal lines for transmitting a fourth clock signal; the P0 signal lines include fifth clock signal lines for transmitting a fifth clock signal; wherein, the width of the third clock signal line is less than the width of the fifth clock signal line, and the width of the fifth clock signal line is less than the width of the fourth clock signal line. The width of the second driving circuit provided by the embodiment of the present invention is greater than the width of the third driving circuit, and the width of the third driving circuit is greater than the width of the first driving circuit. Furthermore, by designing the width of the third clock signal line to be less than the width of the fifth clock signal line, and designing the width of the fifth clock signal line to be less than the width of the fourth clock signal line, it is ensured that the clock signal lines corresponding to different driving circuits are matched, thereby improving the stability and reliability of signal transmission of different clock signal lines.

[0097] In an embodiment of the present invention, the M0 signal lines provided by the present invention include third voltage signal lines for transmitting a third voltage signal; the N0 signal lines include fourth voltage signal lines for transmitting a fourth voltage signal; the P0 signal lines include fifth voltage signal lines for transmitting a fifth voltage signal; wherein, the width of the third voltage signal line is less than the width of the fourth voltage signal line, and the width of the fourth voltage signal line is less than the width of the fifth voltage signal line. The width of the second driving circuit provided by the embodiment of the present invention is greater than the width of the third driving circuit, and the width of the third driving circuit is greater than the width of the first driving circuit. Furthermore, by designing the width of the third voltage signal line to be less than the width of the fourth voltage signal line, and designing the width of the fourth voltage signal line to be less than the width of the fifth voltage signal line, it is ensured that the voltage signal lines corresponding to different driving circuits are matched, thereby improving the stability and reliability of signal transmission of different voltage signal lines.

[0098] Correspondingly, an embodiment of the present invention further provides a display device, including the display panel provided in any of the above embodiments.

[0099] As Figure 21 shown, it is a schematic structural diagram of a display device provided by an embodiment of the present invention. Among them, the display device 1000 provided by the embodiment of the present invention may be a mobile terminal device.

[0100] In other embodiments of the present invention, the display device provided by the present invention may also be an electronic display device such as a mobile phone, a computer, a vehicle-mounted terminal, etc., and the present invention does not make specific limitations thereto.

[0101] Embodiments of the present invention provide a display panel and a display device. By overlapping M0 signal lines with a first driving circuit and overlapping N0 signal lines with a second driving circuit, the occupied area of some signal lines can be reduced, and the border width of the display device can be reduced. Moreover, in the embodiments of the present invention, the relationship between the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D1 of M0 signal lines, and the total width D2 of N0 signal lines is set as W2>W1, D2>D1, and D2 / W2>D1 / W1, further optimizing the overlapping setting of the shift register with a larger width and the shift register with a smaller width with the total widths of their respective corresponding signal lines, fully reducing the occupied areas of the driving circuit and the signal lines, and further reducing the border width of the display device.

[0102] The foregoing description of the disclosed embodiments enables those skilled in the art to practice or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, it includes: a substrate substrate; a driving circuit and a pixel circuit, the driving circuit and the pixel circuit being located on the substrate substrate; the driving circuit includes a first driving circuit and a second driving circuit; a signal line group, the signal line group includes a first signal line group and a second signal line group, the first signal line group includes M signal lines for providing signals to the first driving circuit, the second signal line group includes N signal lines for providing signals to the second driving circuit, M≥1, N≥1; in a direction perpendicular to the surface of the display panel, M0 signal lines in the first signal line group overlap with the first driving circuit and are located on a side of the first driving circuit away from the substrate substrate, N0 signal lines in the second signal line group overlap with the second driving circuit and are located on a side of the second driving circuit away from the substrate substrate, 1≤M0≤M, 1≤N0≤N; the first driving circuit includes an S1-stage shift register extending in a first direction, and / or, the second driving circuit includes an S2-stage shift register extending in the first direction, a second direction is parallel to a plane where the surface of the display panel is located and perpendicular to the first direction, S1≥2, S2≥2; the first driving circuit provides a light emission control signal for a light emission control transistor in the pixel circuit; the second driving circuit provides a control signal for a PMOS transistor in the pixel circuit, or the second driving circuit provides a control signal for an NMOS transistor in the pixel circuit; the M0 signal lines include third voltage signal lines for transmitting a third voltage signal, the N0 signal lines include fourth voltage signal lines for transmitting a fourth voltage signal, along the second direction, the width of the third voltage signal line is less than the width of the fourth voltage signal line; and / or, the M0 signal lines include third clock signal lines for transmitting a third clock signal, the N0 signal lines include fourth clock signal lines for transmitting a fourth clock signal, along the second direction, the width of the third clock signal line is less than the width of the fourth clock signal line.

2. The display panel according to claim 1, characterized in that, the display panel includes a transistor array layer, the transistor array layer includes the driving circuit and / or the pixel circuit; the transistor array layer includes: a semiconductor layer, the semiconductor layer includes an active region; a gate metal layer, the gate metal layer includes a plurality of gates; a source-drain metal layer, the source-drain metal layer includes a plurality of sources and a plurality of drains; wherein, the M0 signal lines are located on a side of the source-drain metal layer away from the substrate substrate, and the N0 signal lines are located on a side of the source-drain metal layer away from the substrate substrate.

3. The display panel according to claim 1 or 2, characterized in that, the M0 signal lines are located in the same layer, and / or, the N0 signal lines are located in the same layer.

4. The display panel according to claim 1 or 2, characterized in that, The M0 signal lines and the N0 signal lines are on the same layer; or, The M0 signal lines and the N0 signal lines are on different layers.

5. The display panel according to claim 2, characterized in that a first insulating layer is included between the source-drain metal layer and the film layer where the M0 signal lines are located, or a first insulating layer is included between the source-drain metal layer and the film layer where the N0 signal lines are located; a second insulating layer is included between the film layer where the M0 signal lines are located and the film layer where the N0 signal lines are located.

6. The display panel according to claim 1, characterized in that the driving circuit further includes a third driving circuit, the signal line group further includes a third signal line group, the third signal line group includes P signal lines for providing signals to the third driving circuit, P≥1; in a direction perpendicular to the surface of the display panel, P0 signal lines in the third signal line group intersect with the third driving circuit and are located on a side of the third driving circuit away from the substrate, 1≤P0≤P; the third driving circuit includes an S3-stage shift register, S3≥2; wherein, the P0 signal lines include fifth voltage signal lines for transmitting a fifth voltage signal, and along the second direction, the width of the fourth voltage signal line is smaller than the width of the fifth voltage signal line; and / or, the P0 signal lines include fifth clock signal lines for transmitting a fifth clock signal, and along the second direction, the width of the fifth clock signal line is smaller than the width of the fourth clock signal line.

7. The display panel according to claim 6, characterized in that the first driving circuit provides a light emission control signal for the light emission control transistor of the pixel circuit; the second driving circuit provides a control signal for the PMOS transistor in the pixel circuit; the third driving circuit provides a control signal for the NMOS transistor in the pixel circuit.

8. The display panel according to claim 6, characterized in that along the second direction, the width of the output transistor of the first driving circuit is smaller than the width of the output transistor of the third driving circuit, and the width of the output transistor of the third driving circuit is smaller than the width of the output transistor of the second driving circuit.

9. A display panel, characterized in that comprises: a substrate; a driving circuit, the driving circuit is located on the substrate, and the driving circuit includes a first driving circuit and a second driving circuit; a signal line group, the signal line group includes a first signal line group and a second signal line group, the first signal line group includes M signal lines for providing signals to the first driving circuit, the second signal line group includes N signal lines for providing signals to the second driving circuit, M≥1, N≥1; In a direction perpendicular to the surface of the display panel, M0 signal lines in the first signal line group intersect with the first driving circuit and are located on a side of the first driving circuit away from the substrate, and N0 signal lines in the second signal line group intersect with the second driving circuit and are located on a side of the second driving circuit away from the substrate, where 1 ≤ M0 ≤ M and 1 ≤ N0 ≤ N; The first driving circuit includes an S1-stage shift register extending in a first direction, and / or the second driving circuit includes an S2-stage shift register extending in the first direction. A second direction is parallel to the plane where the surface of the display panel is located and perpendicular to the first direction, where S1 ≥ 2 and S2 ≥ 2; The M0 signal lines include third voltage signal lines for transmitting a third voltage signal, and the N0 signal lines include fourth voltage signal lines for transmitting a fourth voltage signal. Along the second direction, the width of the third voltage signal lines is smaller than the width of the fourth voltage signal lines; and / or The M0 signal lines include third clock signal lines for transmitting a third clock signal, and the N0 signal lines include fourth clock signal lines for transmitting a fourth clock signal. Along the second direction, the width of the third clock signal lines is smaller than the width of the fourth clock signal lines.

10. The display panel according to claim 1, wherein, the display panel includes a transistor array layer, and the transistor array layer includes the driving circuit; The transistor array layer includes: a semiconductor layer, and the semiconductor layer includes an active region; a gate metal layer, and the gate metal layer includes a plurality of gates; a source-drain metal layer, and the source-drain metal layer includes a plurality of sources and a plurality of drains; wherein, the M0 signal lines are located on a side of the source-drain metal layer away from the substrate, and the N0 signal lines are located on a side of the source-drain metal layer away from the substrate.

11. The display panel according to claim 9 or 10, wherein, the M0 signal lines are located in the same layer, and / or the N0 signal lines are located in the same layer.

12. The display panel according to claim 9 or 10, wherein, the M0 signal lines and the N0 signal lines are located in the same layer; or, the M0 signal lines and the N0 signal lines are located in different layers.

13. The display panel according to claim 10, wherein, a first insulating layer is included between the source-drain metal layer and the film layer where the M0 signal lines are located, or a first insulating layer is included between the source-drain metal layer and the film layer where the N0 signal lines are located; a second insulating layer is included between the film layer where the M0 signal lines are located and the film layer where the N0 signal lines are located.

14. The display panel according to claim 9, wherein, the driving circuit further includes a third driving circuit, the signal line group further includes a third signal line group, and the third signal line group includes P signal lines for providing signals to the third driving circuit, where P ≥ 1; In a direction perpendicular to the surface of the display panel, P0 signal lines in the third signal line group overlap with the third driving circuit and are located on a side of the third driving circuit away from the substrate; 1 ≤ P0 ≤ P. The third driving circuit includes an S3-stage shift register, S3 ≥ 2; wherein, The P0 signal lines include fifth voltage signal lines for transmitting a fifth voltage signal. Along the second direction, the width of the fourth voltage signal line is smaller than the width of the fifth voltage signal line; and / or, The P0 signal lines include fifth clock signal lines for transmitting a fifth clock signal. Along the second direction, the width of the fifth clock signal line is smaller than the width of the fourth clock signal line.

15. The display panel according to claim 14, wherein, The display panel further includes a pixel circuit; The first driving circuit provides a light emission control signal for a light emission control transistor of the pixel circuit; The second driving circuit provides a control signal for a PMOS transistor in the pixel circuit; The third driving circuit provides a control signal for an NMOS transistor in the pixel circuit.

16. The display panel according to claim 14, wherein, Along the second direction, the width of the output transistor of the first driving circuit is smaller than the width of the output transistor of the third driving circuit, and the width of the output transistor of the third driving circuit is smaller than the width of the output transistor of the second driving circuit.

17. A display device, wherein, It includes the display panel according to any one of claims 1-16.

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