Display panel and display device

Abstract

The present invention provides a display panel and a display device, which can reduce the occupied area of ​​some signal lines and reduce the border width of the display device by overlapping the M0 signal lines with the first drive circuit and overlapping the N0 signal lines with the second drive circuit. In addition, the present invention further optimizes the overlapping arrangement of the shift register with a larger width and the shift register with a smaller width and the total width of the corresponding signal lines by setting the relationship between the width W1 of the first drive circuit, the width W2 of the second drive circuit, the total width D1 of the M0 signal lines and the total width D2 of the N0 signal lines to W2>W1, D2>D1, and D2 / W2>D1 / W1, thereby fully reducing the occupied area of ​​the drive circuit and the signal lines and further reducing the border width of the display device.

Description

[0001] This application is a divisional application of a patent for display panel and display device, with application date of September 10, 2021, application number: 202111063932.7, and invention name: Technical Field

[0002] The present invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Art

[0003] The border area of ​​the existing display device includes a peripheral driving circuit for providing a driving signal to the pixel unit in the display area. In the display device, a plurality of pixel units are arranged in the display area, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected to the peripheral driving circuit in the border area, and the peripheral driving circuit provides a scanning control signal and a light-emitting control signal to the pixel circuit to control the pixel circuit to provide a driving current to the light-emitting element. However, the existing driving circuit occupies a large space, which makes it difficult to reduce the border width of the display device. Summary of the invention

[0004] In view of this, the present invention provides a display panel and a display device, which effectively solve the technical problems existing in the prior art and ensure that the border width of the display device is small.

[0005] To achieve the above purpose, the technical solution provided by the present invention is as follows:

[0006] A display panel, comprising:

[0007] A driving circuit and a pixel circuit, wherein the driving circuit provides a control signal to the pixel circuit, and the pixel circuit provides a driving current to the light-emitting element of the display panel;

[0008] The driving circuit includes a first driving circuit and a second driving circuit;

[0009] a signal line group, the signal line group comprising a first signal line group and a second signal line group, the first signal line group comprising M signal lines providing signals to the first drive circuit, the second signal line group comprising N signal lines providing signals to the second drive circuit, M≥1, N≥1;

[0010] In a direction perpendicular to the surface of the display panel, M0 signal lines in the first signal line group overlap with the first drive circuit, and N0 signal lines in the second signal line group overlap with the second drive circuit, 1≤M0≤M, 1≤N0≤N;

[0011] The first driving circuit includes an S1-level shift register extending along a first direction, and the second driving circuit includes an S2-level shift register extending along the first direction. The second direction is parallel to the plane where the display panel surface is located and perpendicular to the first direction. S1≥2, S2≥2; wherein,

[0012] Along the second direction, the width of the first driving circuit is W1, the width of the second driving circuit is W2, the total width of the M0 signal lines in the first signal line group is D1, and the total width of the N0 signal lines in the second signal line group is D2;

[0013] W2>W1, D2>D1, and D2 / W2>D1 / W1.

[0014] Correspondingly, the present invention also provides a display device, comprising the above-mentioned display panel.

[0015] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0016] The present invention provides a display panel and a display device, which can reduce the occupied area of ​​some signal lines and reduce the border width of the display device by overlapping the M0 signal lines with the first drive circuit and overlapping the N0 signal lines with the second drive circuit. In addition, the present invention further optimizes the overlapping arrangement of the shift register with a larger width and the shift register with a smaller width and the total width of the corresponding signal lines by setting the relationship between the width W1 of the first drive circuit, the width W2 of the second drive circuit, the total width D1 of the M0 signal lines and the total width D2 of the N0 signal lines to W2>W1, D2>D1, and D2 / W2>D1 / W1, thereby fully reducing the occupied area of ​​the drive circuit and the signal lines and further reducing the border width of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0020] Figure 3A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0021] Figure 4 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0022] Figure 5 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0024] Figure 7 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0025] Figure 8 A schematic diagram of the structure of a shift register provided by an embodiment of the present invention;

[0026] Fig. 9 for Figure 8 The structural layout of the shift register shown;

[0027] Fig.10 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0028] Fig.11 for Fig.10 The structural layout of the shift register shown;

[0029] Fig.12 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0030] Fig.13 for Fig.12 The structural layout of the shift register shown;

[0031] Fig.14 A schematic structural diagram of a shift register of a first driving circuit provided by an embodiment of the present invention;

[0032] Fig.15 A schematic structural diagram of a shift register of a second driving circuit provided by an embodiment of the present invention;

[0033] Fig.16 A schematic diagram of the structure of a signal line provided by an embodiment of the present invention;

[0034] Fig.17 A schematic diagram of the structure of another signal line provided by an embodiment of the present invention;

[0035] Fig.18 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0036] Fig.19 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0037] Fig. 20 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0038] Fig.21 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] As described in the background technology, the border area of ​​the existing display device includes a peripheral driving circuit for providing a driving signal to the pixel unit in the display area. In the display device, a plurality of pixel units are arranged in the display area, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected to the peripheral driving circuit in the border area, and the peripheral driving circuit provides a scanning control signal and a light-emitting control signal to the pixel circuit to control the pixel circuit to provide a driving current for the light-emitting element. However, the existing driving circuit occupies a large space, which makes it difficult to reduce the border width of the display device.

[0041] Based on this, the embodiments of the present invention provide a display panel and a display device, which effectively solve the technical problems existing in the prior art and ensure that the border width of the display device is small.

[0042] To achieve the above purpose, the technical solution provided by the embodiment of the present invention is as follows, specifically combined with Figures 1 to 21 The technical solution provided by the embodiment of the present invention is described in detail.

[0043] refer to Figure 1 As shown, it is a structural schematic diagram of a display panel provided in an embodiment of the present invention, wherein the display panel includes: a driving circuit and a pixel circuit 20, the driving circuit provides a control signal for the pixel circuit 20, and the pixel circuit 20 provides a driving current for the light-emitting element 30 of the display panel.

[0044] The display panel includes a display area AA and a frame area NA. The pixel circuit 20 and the light emitting element 30 can be arranged in the display area AA, and the driving circuit is arranged in the frame area NA. The driving circuit includes a first driving circuit 11 and a second driving circuit 12 .

[0045] Located at the frame area NA, the display panel includes a signal line group, the signal line group includes a first signal line group and a second signal line group, the first signal line group includes M signal lines for providing signals to the first drive circuit 11, and the second signal line group includes N signal lines for providing signals to the second drive circuit 12, M≥1, N≥1. And, in a direction perpendicular to the surface of the display panel (that is, in a light emitting direction perpendicular to the display panel), M0 signal lines 110 in the first signal line group overlap with the first drive circuit 11, and N0 signal lines 120 in the second signal line group overlap with the second drive circuit 12, 1≤M0≤M, 1≤N0≤N.

[0046] The first driving circuit 11 includes an S1-level shift register extending along a first direction Y, the second driving circuit 12 includes an S2-level shift register extending along the first direction Y, and the first driving circuit 11 and the second driving circuit 12 can be arranged along a second direction X. The second direction X is parallel to the plane where the display panel surface is located and perpendicular to the first direction Y, S1≥2, S2≥2;

[0047] Along the second direction X, the width of the first driving circuit 11 is W1, the width of the second driving circuit 12 is W2, the total width of the M0 signal lines 110 in the first signal line group is D1, and the total width of the N0 signal lines 120 in the second signal line group is D2; W2>W1, D2>D1, and D2 / W2>D1 / W1.

[0048] It can be understood that by overlapping the M0 signal lines with the first driving circuit and overlapping the N0 signal lines with the second driving circuit, where the extension direction of the M0 signal lines and the extension direction of the N0 signal lines are the first direction, the area occupied by some signal lines can be reduced and the border width of the display device can be reduced.

[0049] In the second direction, when the width of the driving circuit is wider and the width of the signal line is wider, the border of the display panel is larger. In order to reduce the border, generally, the signal line and the driving circuit can be set to overlap each other to reduce the border; and when there is more than one set of driving circuits in the border, how to set it to fully reduce the border is a problem. Based on this problem, the inventor of the present application found that when W2>W1, D2>D1, by setting D2 / W2>D1 / W1, the width of the signal line overlapped by the driving circuit with a larger width is also larger, thereby fully reducing the width occupied by the driving circuit with a larger width and the signal line connected to it on the display panel, so that the driving circuit with a larger width and the driving circuit with a smaller width both achieve a good overlapping relationship with their respective signal lines, and fully reduce the border. Therefore, the embodiment of the present application further optimizes the overlapping setting of the shift register with a larger width and the shift register with a smaller width and the total width of their respective corresponding signal lines by setting the relationship between the width W1 of the first drive circuit, the width W2 of the second drive circuit, the total width D1 of M0 signal lines, and the total width D2 of N0 signal lines to W2>W1, D2>D1, and D2 / W2>D1 / W1, thereby fully reducing the occupied area of ​​the drive circuit and the signal line, and further reducing the border width of the display device.

[0050] In one embodiment of the present invention, the display panel provided by the present invention may be a panel structure driven by a single side, such as Figure 1 The first driving circuit 11 and the second driving circuit 12 of the driving circuit are located on one side of the display area AA, and the pixel circuit 20 is driven by the unilateral driving circuit. Alternatively, the display panel provided by the present invention can also be a panel structure with bilateral driving, such as Figure 2 As shown, the driving circuit includes a first driving circuit 11 located on both sides of the display area AA, and the driving circuit includes a second driving circuit 12 located on both sides of the display area AA, thereby driving the pixel circuit 20 through the double-sided driving circuit.

[0051] like Figure 2 As shown, in the double-sided driven panel structure provided by an embodiment of the present invention, the pixel circuits 20 in the same row can be driven simultaneously by two first driving circuits 11 located on different sides of the display area AA, and the pixel circuits 20 in the same row can be driven simultaneously by two second driving circuits 12 located on different sides of the display area AA.

[0052] It can be understood that the first driving circuits on different sides of the display area (defined as the first driving circuit on the first side and the first driving circuit on the second side) each include multiple cascaded shift registers, the first-stage shift register of the first driving circuit on the first side and the first-stage shift register of the first driving circuit on the second side are both electrically connected to the pixel circuit of the first row, the second-stage shift register of the first driving circuit on the first side and the second-stage shift register of the first driving circuit on the second side are both electrically connected to the pixel circuit of the second row, and so on, the last-stage shift register of the first driving circuit on the first side and the last-stage shift register of the first driving circuit on the second side are both electrically connected to the pixel circuit of the last row. Similarly, the second driving circuits on different sides of the display area (defined as the second driving circuit on the first side and the second driving circuit on the second side) each include multiple cascaded shift registers, the first-stage shift register of the second driving circuit on the first side and the first-stage shift register of the second driving circuit on the second side are both electrically connected to the pixel circuit of the first row, the second-stage shift register of the second driving circuit on the first side and the second-stage shift register of the second driving circuit on the second side are both electrically connected to the pixel circuit of the second row, and so on, the last-stage shift register of the second driving circuit on the first side and the last-stage shift register of the second driving circuit on the second side are both electrically connected to the pixel circuit of the last row.

[0053] Or, if Figure 3 As shown, in the double-sided driven panel structure provided by an embodiment of the present invention, pixel circuits 20 in different rows can be driven respectively by two first driving circuits 11 located on different sides of the display area AA, and pixel circuits 20 in different rows can be driven respectively by two second driving circuits 12 located on different sides of the display area AA.

[0054] It can be understood that the odd-numbered first driving circuits in the first driving circuits are located on the first side of the display area, and the even-numbered first driving circuits in the first driving circuits are located on the second side of the display area, wherein the odd-numbered first driving circuits are electrically connected to the pixel circuits of the odd rows, and the even-numbered first driving circuits are electrically connected to the pixel circuits of the even rows. Similarly, the odd-numbered second driving circuits in the second driving circuits are located on the first side of the display area, and the even-numbered second driving circuits in the second driving circuits are located on the second side of the display area, wherein the odd-numbered second driving circuits are electrically connected to the pixel circuits of the odd rows, and the even-numbered second driving circuits are electrically connected to the pixel circuits of the even rows.

[0055] In one embodiment of the present invention, the display panel provided by the present invention includes a base substrate, the driving circuit and the pixel circuit are located on the base substrate; the M0 signal lines are located on the side of the first driving circuit away from the base substrate, the N0 signal lines are located on the side of the second driving circuit away from the base substrate, and the M0 signal lines are located on the same layer, and / or the N0 signal lines are located on the same layer. Figure 4 , which is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, wherein the display panel includes a substrate 100. A transistor array layer located on the substrate 100, the transistor array layer includes a semiconductor layer 210 located on the substrate 100, the semiconductor layer 210 includes a plurality of active regions; a gate insulating layer 220 located on a side of the semiconductor layer 210 away from the substrate 100; a gate metal layer 230 located on a side of the gate insulating layer 220 away from the substrate 100, the gate metal layer 230 includes a plurality of gates and a plurality of first capacitor plates; an interlayer insulating layer 240 located on a side of the gate metal layer 230 away from the substrate 100; and an interlayer insulating layer 240 located on a side of the gate metal layer 230 away from the substrate 100. The capacitor metal layer 250 of the insulating layer 240 is located on the side away from the substrate 100, and the capacitor metal layer 250 includes a second capacitor plate that is arranged to overlap with the first capacitor plate; the isolation layer 260 is located on the side of the capacitor metal layer 250 away from the substrate 100; the source-drain metal layer 270 is located on the side of the isolation layer 260 away from the substrate 100, and the source-drain metal layer 270 includes a plurality of source electrodes and drain electrodes, and the source electrodes and drain electrodes are contacted and connected with the active area through respective corresponding vias; wherein the transistor array layer includes a driving circuit and a pixel circuit. The first insulating layer 310 is located on the side of the source-drain metal layer 270 away from the substrate 100. M0 signal lines 110 are located on the side of the first insulating layer 310 away from the substrate 100, wherein the M0 signal lines 110 can be prepared from the same conductive layer. Furthermore, the display panel further includes N0 signal lines 120 located on a side of the first insulating layer 310 away from the base substrate 100 , wherein the N0 signal lines 120 can be made of the same conductive layer.

[0056] like Figure 4 As shown, the M0 signal lines 110 and N0 signal lines 120 provided in the embodiment of the present invention can be prepared from the same conductive layer, that is, the M0 signal lines 110 and N0 signal lines 120 are located in the same layer. Figure 5As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the M0 signal lines 110 and N0 signal lines 120 provided by the embodiment of the present invention can be prepared by different conductive layers, that is, there is a second insulating layer 320 between the M0 signal lines 110 and the N0 signal lines 120, wherein the M0 signal lines 110 or the N0 signal lines 120 can be located on the side of the second insulating layer 320 close to the first insulating layer 310, and the present invention does not make any specific limitation to this.

[0057] In one embodiment of the present invention, the present invention can further optimize the width of the signal line and the driving circuit, thereby optimizing the width of the border area of ​​the display panel to achieve a trend of narrow border. Wherein, along the second direction, the total width of the M signal lines is D11, and the total width of the N signal lines is D22; wherein, [(W1-D11)-(W2-D22)]×[(D11-D1)-(D22-D2)]≤0.

[0058] It can be understood that among the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D11 of the M signal lines, the total width D1 of the M0 signal lines, the total width D22 of the N signal lines, and the total width D2 of the N0 signal lines provided in the embodiment of the present invention, the larger one of (W1-D11) and (W2-D22) indicates that the difference between the total width of the signal line and the width of the corresponding driving circuit is large, and the total width of the signal line is smaller than the width of the corresponding driving circuit. At this time, the area where the driving circuit is located has more space to set the signal line that overlaps with the driving circuit. Furthermore, since the area where the corresponding driving circuit (the first driving circuit or the second driving circuit) is located can overlap more signal lines, the driving circuit corresponds to the smaller one of (D11-D1) and (D22-D2). Such a setting can fully save the border area of ​​the display panel, avoid unnecessary space waste, and comply with the narrow border design. Optionally, an embodiment of the present invention provides (D11-D1)=(D22-D2)=0, that is, M signal lines all overlap with the first driving circuit, and N signal lines all overlap with the second driving circuit, thereby maximizing the reduction in width of the border area of ​​the display panel and ensuring that the border of the display panel is narrower.

[0059] like Figure 6 , which is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, wherein the relationship between the number of N0 signal lines 120 and the number of M0 signal lines 110 provided by the embodiment of the present invention may be: N0-M0≥1.

[0060] It can be understood that the relationship between the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D1 of the M0 signal lines and the total width D2 of the N0 signal lines provided in the embodiment of the present invention is W2>W1, D2>D1, and D2 / W2>D1 / W1. Therefore, by setting the number of N0 signal lines and the number of M0 signal lines to N0-M0≥1, the number of N0 signal lines overlapping with the second driving circuit is greater, thereby achieving the purpose of reducing the width of the border area.

[0061] like Figure 7 , which is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, wherein the i signal line 11i in the M0 signal line 120 and the j signal line 12j in the N0 signal lines are signal lines that transmit signals of the same function; along the second direction X, the width of the i signal line 11i is Di, and the width of the j signal line 12j is Dj; wherein Dj>Di. The i signal line is any signal line in the M0 signal lines, and the j signal line is any signal line in the N0 signal lines.

[0062] It should be noted that the i signal line and the j signal line provided in the embodiment of the present invention may be a single signal line or a combination of multiple signal lines, and the present invention does not impose any specific limitation on this. When the i signal line and the j signal line are a combination of multiple signal lines, the width of the i signal line and the j signal line is the total width of each signal line.

[0063] It can be understood that the width W2 of the second driving circuit is greater than the width W1 of the first driving circuit. Compared with the transistors in the shift register of the first driving circuit, the occupied area of ​​the transistors in the shift register of the second driving circuit is larger, and in many cases, the output requirements of the shift register in the second driving circuit may be higher. Therefore, in order to ensure the accuracy and stability of the signal transmission and output of the second driving circuit, the second driving circuit needs to connect a wider signal line to reduce the voltage drop on the signal line and avoid large fluctuations in the signal transmitted on the signal line. Therefore, the technical solution provided by the embodiment of the present invention has a larger width W2 of the second driving circuit, and at the same time, the j signal line with a larger width is overlapped with the second driving circuit in the light emitting direction of the display panel. It can avoid the j signal line affecting the width of the border area of ​​the display panel while ensuring the normal output of the second driving circuit, and ensure that the width of the display panel is small.

[0064] In one embodiment of the present invention, the i signal line 11i and the j signal line 12j provided by the present invention can both be clock signal lines; the first driving circuit 11 provides a light-emitting control signal for the light-emitting control transistor of the pixel circuit 20, and the second driving circuit 12 provides a control signal for the PMOS transistor in the pixel circuit 20; wherein, Dj / W2>Di / W1.

[0065] Specific combination Figure 8 and Fig. 9 As shown, Figure 8 A schematic diagram of the structure of a shift register provided by an embodiment of the present invention, Fig. 9 for Figure 8 The structural layout of the shift register is shown. Figure 8 It can be a structural schematic diagram of a shift register in a first driving circuit, wherein the shift register in the first driving circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a first capacitor C11, a second capacitor C12 and a third capacitor C13, wherein the first signal line group includes a start signal line STV1 (wherein the start signal line STV1 provides a start signal for a shift register at the end of the cascaded shift register in the first driving circuit), a clock signal line CK1, a clock signal line XCK1 (the phase of the pulse signal transmitted by the clock signal line CK1 and the clock signal line XCK1 is inverted), a low-level voltage signal line VGL and a high-level voltage signal line VGH. Among them, the first signal line group provides a signal to the shift register in the first driving circuit, and then through the cooperation of the first transistor M1 to the thirteenth transistor M13 and the first capacitor C11 to the third capacitor C13, the shift register finally outputs a light-emitting control signal for controlling the operation of the light-emitting control transistor in the pixel circuit 20. The start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-level voltage signal line VGL and the high-level voltage signal line VGH provided in the embodiment of the present invention can all overlap with the first driving circuit, that is, M0 signal lines include the start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-level voltage signal line VGL and the high-level voltage signal line VGH, ensuring that the border area width of the display panel is small.

[0066] And combined Fig.10 and Fig.11 As shown, Fig.10 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention, Fig.11 for Fig.10 The structural layout of the shift register is shown. Fig.10It can be a structural schematic diagram of a shift register in a second driving circuit, wherein, optionally, the second driving circuit is used to control a PMOS transistor in a pixel circuit, and the shift register in the second driving circuit includes a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a fifth transistor P5, a sixth transistor P6, a seventh transistor P7, an eighth transistor P8, a first capacitor C21, and a second capacitor C22, wherein the second signal line group includes a start signal line STV2 (wherein the start signal line STV2 provides a start signal for a shift register at the end of the cascaded shift register in the second driving circuit), a clock signal line CK2, a clock signal line XCK2, a low-level voltage signal line VGL, and a high-level voltage signal line VGH. Wherein, a signal is provided to the shift register in the second driving circuit through the second signal line group, and then through the cooperation of the first transistor P1 to the eighth transistor P8, the first capacitor C21, and the second capacitor C23, the shift register finally outputs a control signal for controlling the operation of the PMOS transistor in the pixel circuit 20. The start signal line STV2, clock signal line CK2, clock signal line XCK2 (the phase of the pulse signal transmitted by the clock signal line CK2 and the clock signal line XCK2 is inverted), low-level voltage signal line VGL and high-level voltage signal line VGH provided in the embodiment of the present invention can all overlap with the second driving circuit, that is, N0 signal lines include the start signal line STV2, the clock signal line CK2, the clock signal line XCK2, the low-level voltage signal line VGL and the high-level voltage signal line VGH, ensuring that the width of the border area of ​​the display panel is small.

[0067] Combination Fig.11 As shown, the j signal line provided in the embodiment of the present invention includes a j1 signal line CK2 and a j2 signal line XCK2. Along the second direction X, the j2 signal line XCK2 is located on the side of the j1 signal line CK2 facing the display area AA of the display panel. The width of the j1 signal line CK2 is Dj1, and the width of the j2 signal line XCK2 is Dj2, Dj2>Dj1; wherein, Dj1≥Di, and / or, Dj2≥Di, wherein, optionally, Dj=Dj1+Dj2.

[0068] It can be understood that the j signal line provided in the embodiment of the present invention is related to the output control of the second driving circuit and other related control processes of the circuit, so the j signal line can be substantially set to a combination of the j1 signal line and the j2 signal line, and the j2 signal line can be set on the side of the j1 signal line facing the display area. In addition, since the output end of the driving circuit is generally set on the side facing the display area, so as to be electrically connected to the pixel circuit at the display area, and the j2 signal line may be connected to the output module of the shift register, in this regard, the width of the j2 signal line is designed to be larger to ensure the transmission stability of the signal connected to the output module, so that Dj2 can be designed to be greater than Dj1; and on this basis, the width relationship can also be set to Dj1≥Di, and / or, Dj2≥Di, so as to meet the high transmission stability of the shift register access signal of the second driving circuit with a larger width. At the same time, the width W2 of the second driving circuit provided in the embodiment of the present invention is larger, so a wider j signal line can be set to overlap with it to achieve a narrow frame design.

[0069] In one embodiment of the present invention, the i signal line and the j signal line provided by the present invention can also be other types of signal lines. That is, the i signal line 11i and the j signal line provided by the present invention can also be high-level voltage signal lines or low-level voltage signal lines; the first driving circuit 11 provides a light-emitting control signal for the light-emitting control transistor of the pixel circuit 20, and optionally, the second driving circuit 12 provides a control signal for the NMOS transistor in the pixel circuit 20, and the NMOS transistor is connected to the gate of the driving transistor; wherein Dj / W2>Di / W1. The driving transistor is a transistor in the pixel circuit 20 for providing a driving current, and the light-emitting element in the pixel circuit 20 emits light in response to the driving current.

[0070] The shift register of the first driving circuit provided in the embodiment of the present invention can be as follows: Figure 8 and Fig. 9 The circuit structure of the shift register shown in FIG. Fig.12 and Fig.13 As shown, Fig.12 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention, Fig.13 for Fig.12 The layout of the shift register is shown. Fig.12It can be a structural schematic diagram of a shift register in a second driving circuit, wherein, optionally, the second driving circuit is used to control an NMOS transistor in a pixel circuit, wherein the shift register in the second driving circuit includes a first transistor N1, a second transistor N2, a third transistor N3, a fourth transistor N4, a fifth transistor N5, a sixth transistor N6, a seventh transistor N7, an eighth transistor N8, a ninth transistor N9, a tenth transistor N10, an eleventh transistor N11, a twelfth transistor N12, a thirteenth transistor N13, a first capacitor C31, a second capacitor C32 and a third capacitor C33, wherein the second signal line group includes a start signal line STV3 (wherein the start signal line STV3 provides a start signal for a shift register at the end of the cascaded shift register in the second driving circuit), a clock signal line CK3, a clock signal line XCK3 (the phase of the pulse signal transmitted by the clock signal line CK3 and the clock signal line XCK3 is inverted), a low-level voltage signal line VGL and a high-level voltage signal line VGH. Among them, the second signal line group provides a signal to the shift register in the second driving circuit, and then through the cooperation of the first transistor N1 to the thirteenth transistor N13 and the first capacitor C31 to the third capacitor C33, the shift register finally outputs a control signal for controlling the operation of the NMOS transistor in the pixel circuit 20. The start signal line STV3, the clock signal line CK3, the clock signal line XCK3, the low-level voltage signal line VGL and the high-level voltage signal line VGH provided in the embodiment of the present invention can all overlap with the second driving circuit, that is, N0 signal lines include the start signal line STV3, the clock signal line CK3, the clock signal line XCK3, the low-level voltage signal line VGL and the high-level voltage signal line VGH, ensuring that the border area width of the display panel is small.

[0071] Combination Figure 8 and Fig.12As shown, when the i signal line and the j signal line are both the high-level voltage signal line VGH or the low-level voltage signal line VGL, in the shift register of the first drive circuit and the shift register of the second drive circuit, the output transistors (the ninth transistor M9 and the tenth transistor M10) of the shift register of the first drive circuit and the output transistors (the ninth transistor N9 and the tenth transistor N10) of the shift register of the second drive circuit are connected to the high-level voltage signal line VGH and the low-level voltage signal line VGL; since the gate potential of the driving transistor in the pixel circuit is closely related to the size of the driving current, the NMOS transistor connected to the gate of the driving transistor has higher requirements on the stability and leakage current of the NMOS transistor to ensure that the potential stability of the gate of the driving transistor is high. Therefore, the embodiment of the present invention can make the output stability of the shift register in the second driving circuit higher by designing the width W2 of the second driving circuit to be larger; and because the width W2 of the second driving circuit is designed to be larger, the Dj parameter with a larger width can be designed, ultimately achieving the purpose of reducing the voltage drop of the transmission signal and ensuring the stability of the transmission signal, while also being able to achieve a narrow bezel design, further optimizing the width relationship to Dj / W2>Di / W1.

[0072] like Fig.13 As shown, the j signal line includes a j1 signal line VGL and a j2 signal line VGH. Along the second direction X, the j2 signal line VGH is located on the side of the j1 signal line VGL facing the display area AA of the display panel. The width of the j1 signal line VGL is Dj1, and the width of the j2 signal line VGH is Dj2, Dj2>Dj1; wherein, Dj1≥Di, and / or, Dj2≥Di, optionally, Dj=Dj1+Dj2.

[0073] It can be understood that the j signal line provided in the embodiment of the present invention is related to the output of the second driving circuit and other related control processes of other circuits, so the j signal line can be substantially set to a combination of the j1 signal line and the j2 signal line, and the j2 signal line can be set on the side of the j1 signal line facing the display area. In addition, since the output end of the driving circuit is on the side facing the display area, so as to be electrically connected to the pixel circuit at the display area, and the j2 signal line is connected to the output module of the shift register, the width of the j2 signal line is designed to be larger to ensure the transmission stability of the signal connected to the output module, so that Dj2 can be designed to be greater than Dj1; and on this basis, the width relationship can also be set to Dj1≥Di, and / or, Dj2≥Di, so as to meet the high transmission stability of the shift register access signal of the second driving circuit with a larger width. At the same time, the width W2 of the second driving circuit provided in the embodiment of the present invention is larger, so a wider j signal line can be set to overlap with it to achieve a narrow frame design.

[0074] In one embodiment of the present invention, the first-level shift register of the first driving circuit provided by the present invention includes x1 transistors and y1 capacitors, x1≥1, y1≥1; the first-level shift register of the second driving circuit includes x2 transistors and y2 capacitors, x1≥1, y2≥1; at least one of the M0 signal lines overlaps with at least one of the x1 transistors, and does not overlap with any of the y1 capacitors; and / or, at least one of the N0 signal lines overlaps with at least one of the x2 transistors, and does not overlap with any of the y2 capacitors.

[0075] It can be understood that the signal line is used to transmit signals. When the signal line overlaps with the capacitor, it is equivalent to connecting the original capacitor to a new capacitor, which causes the capacitance value to change, which not only affects the capacitor, but also affects the stability of signal transmission on the signal line. Therefore, the shift register in the first drive circuit provided by the embodiment of the present invention and the shift register in the second drive circuit both include multiple transistors and at least one capacitor. Among the signal lines overlapping with the drive circuit (the first drive circuit and / or the second drive circuit), at least one signal line only overlaps with the transistor, but does not overlap with the capacitor, thereby ensuring the stability of signal transmission on the signal line and the reliability of the capacitor in the drive circuit.

[0076] Specific as Fig.14 and Fig.15 As shown, Fig.14 A schematic diagram of the structure of a shift register of a first driving circuit provided by an embodiment of the present invention, Fig.15 A schematic diagram of the structure of a shift register of a second driving circuit provided by an embodiment of the present invention. Among them, M0 signal lines in the shift register of the first driving circuit include a start signal line STV1, a clock signal line CK1, a clock signal line XCK1, a low-level voltage signal line VGL and a high-level voltage signal line VGH, wherein the start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-level voltage signal line VGL and the high-level voltage signal line VGH are all overlapped with the transistors included in the shift register, and the start signal line STV1, the clock signal line CK1 and the clock signal line XCK1 do not overlap with the capacitors included in the shift register, thereby improving the situation where the capacitance value of the capacitor in the shift register changes, and at the same time ensuring the high stability of the signal transmitted on the signal line.

[0077] In addition, N0 signal lines in the shift register of the second driving circuit include a start signal line STV2, a clock signal line CK2, a clock signal line XCK2, a low-level voltage signal line VGL and a high-level voltage signal line VGH, wherein the start signal line STV2, the clock signal line CK2, the clock signal line XCK2, the low-level voltage signal line VGL and the high-level voltage signal line VGH all overlap with the transistors included in the shift register, and the start signal line STV2, the clock signal line CK2, the low-level voltage signal line VGL and the clock signal line XCK2 do not overlap with the capacitors included in the shift register, thereby improving the situation in which the capacitance value of the capacitor in the shift register changes, and at the same time ensuring the high stability of the signal transmitted on the signal line.

[0078] Furthermore, among the M0 signal lines provided in the embodiment of the present invention, at least one clock signal line does not overlap with any one of the y1 capacitors; and / or, among the N0 signal lines, at least one clock signal line does not overlap with any one of the y2 capacitors. It is understandable that since the clock signal line transmits a pulse signal, the pulse signal is not only easily affected by the capacitor, but also can affect the charging and discharging process of the capacitor. The present invention designs the clock signal line and the capacitor to be non-overlapping, which can effectively ensure the high stability of the pulse signal transmission on the clock signal line and the high reliability of the capacitor. Specifically, Fig.14 and Fig.15 As shown, the clock signal line CK1 and the clock signal line XCK1 do not overlap with the capacitors of the corresponding shift registers, and the clock signal line CK2 and the clock signal line XCK2 do not overlap with the capacitors of the corresponding shift registers.

[0079] In one embodiment of the present invention, among the M0 signal lines provided by the present invention, the signal line with the largest width along the second direction does not overlap with any of the y1 capacitors; and / or, among the N0 signal lines, the signal line with the largest width along the second direction does not overlap with any of the y2 capacitors. Since the size of the capacitor is proportional to the relative area of ​​the electrode plates, the signal line with a larger width is set to a non-overlapping manner with the capacitor, thereby avoiding a large change in the capacitance value of the capacitor in the driving circuit, ensuring the stability of the signal transmission of the signal line, and ensuring the high reliability of the capacitor.

[0080] like Fig.16As shown, it is a schematic diagram of the structure of a signal line provided by an embodiment of the present invention, wherein the M0 signal lines or the N0 signal lines provided by the embodiment of the present invention include a first clock signal line CKL for transmitting a first clock signal and a second clock signal line XCKL for transmitting a second clock signal (the phases of the pulse signals transmitted by the clock signal line CKL and the clock signal line XCKL are inverted), and a first voltage signal line VG1 for transmitting a constant first voltage signal; the first clock signal line CKL and the first voltage signal line VG1 are respectively located on both sides of the second clock signal line XCKL; wherein the spacing L1 between the first clock signal line CKL and the second clock signal line XCKL is greater than the spacing L2 between the first voltage signal line VG1 and the second clock signal line XCKL. wherein the first voltage signal line VG1 can be a low-level voltage signal line or a high-level voltage signal line.

[0081] It can be understood that the pulse signals transmitted by the clock signal line CKL and the clock signal line XCKL provided in the embodiment of the present invention are in phase with each other, so the spacing between the clock signal line CKL and the clock signal line XCKL needs to be set larger to avoid the electric field generated between the clock signal line CKL and the clock signal line XCKL when the signals on the clock signal line CKL and the clock signal line XCKL jump and have a greater impact on the respective pulse signals. The first voltage signal line VG1 transmits a constant voltage signal, which does not have a rising edge and a falling edge, so the impact is smaller when the spacing between it and the clock signal line is smaller, and the spacing L2 between it and the second clock signal line XCKL can be set to be smaller than the spacing L1 between the first clock signal line CKL and the second clock signal line XCKL, so as to optimize the layout space of the line.

[0082] like Fig.17 As shown, it is a schematic diagram of the structure of another signal line provided in an embodiment of the present invention, wherein the M0 signal lines or the N0 signal lines include a first voltage signal line VG1 for transmitting a constant first voltage signal and a second voltage signal line VG2 for transmitting a constant second voltage signal, and a first clock signal line CK for transmitting a first clock signal; the first voltage signal line VG1 and the first clock signal line CK are respectively located on both sides of the second voltage signal line VG2; wherein the spacing L3 between the first voltage signal line VG1 and the second voltage signal line VG2 is greater than the spacing L4 between the first clock signal line CK and the second voltage signal line VG2.

[0083] It can be understood that the first voltage signal line VG1 and the second voltage signal line VG2 provided in the embodiment of the present invention transmit voltage signals of different levels, that is, when the first voltage signal line VG1 is a high-level voltage signal line, the second voltage signal line VG2 is a low-level voltage signal line; and when the first voltage signal line VG1 is a low-level voltage signal line, the second voltage signal line VG2 is a high-level voltage signal line; therefore, the voltage signal line VG1 and the second voltage signal line VG2 are required to have high stability in signal transmission. The present invention sets a larger distance between the first voltage signal line VG1 and the second voltage signal line VG2 to avoid mutual influence between the two, which makes the stability of the signals transmitted by each of them poor, resulting in unstable output signals of the driving circuit.

[0084] like Fig.18 As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the driving circuit further includes a third driving circuit 13, and the signal line group further includes a third signal line group, and the third signal line group includes P signal lines for providing signals to the third driving circuit 13, P≥1; in the direction perpendicular to the surface of the display panel, P0 signal lines 130 in the third signal line group overlap with the third driving circuit 13, 1≤P0≤P; the third driving circuit 13 includes an S3-level shift register extending along the first direction Y, S3≥2; wherein, in the second direction X, the width of the third driving circuit 13 is W3, and the total width of the P0 signal lines 130 in the third signal line group is D3; W2>W3, and D3 / W3>D2 / W2>D1 / W1.

[0085] It can be understood that the driving circuit provided in the embodiment of the present invention may include a first driving circuit, a second driving circuit and a third driving circuit, the width W2 of the second driving circuit is greater than the width W3 of the third driving circuit, and the width W3 of the third driving circuit provided in the embodiment of the present invention may be between the width W1 of the first driving circuit and the width W2 of the second driving circuit. Among them, the total width D3 of the P0 signal lines 130 provided in the embodiment of the present invention is relatively large, so that D3 / W3>D2 / W2>D1 / W1.

[0086] When the width W3 of the third driving circuit is smaller than the width of the second driving circuit W2, and the output requirement is higher, on the one hand, the width of some of the P signal lines corresponding to it is wider. In order not to affect the frame space, it is necessary to set them to overlap with the third driving circuit as much as possible. At this time, the situation that may occur is that W3 is not too large, but D3 is large, so that D3 / W3>D2 / W2>D1 / W1 may occur. At this time, because D3 is large, the P0 signal lines with a wider width among the P signal lines are all set to overlap with the third driving circuit, so as not to increase the frame area extra.

[0087] like Fig.18 As shown, the technical solution provided by the embodiment of the present invention, optionally, the first driving circuit 11, the third driving circuit 13, and the second driving circuit 12 can be arranged side by side along the second direction X, so as to facilitate providing different driving signals for each row of pixel circuits. Further optionally, along the second direction X, the first driving circuit 11, the third driving circuit 13, and the second driving circuit 12 are sequentially arranged from the frame N1 of the display panel toward the display area AA of the display panel; the first driving circuit 11 provides a light-emitting control signal for the light-emitting control transistor of the pixel circuit 20; the second driving circuit 12 provides a control signal for the PMOS transistor in the pixel circuit 20; the third driving circuit 13 provides a control signal for the NMOS transistor in the pixel circuit 20, and the NMOS transistor is connected to the gate of the driving transistor.

[0088] It should be noted that the pixel circuit provided by the embodiment of the present invention may include a driving transistor, a light-emitting control transistor, and other NMOS transistors and PMOS transistors, wherein the driving transistor is used to generate a driving current, and the light-emitting element in the pixel circuit emits light in response to the driving circuit; and the light-emitting control transistor is used to transmit the driving current to the light-emitting element according to the control of the light-emitting control signal. And the remaining NMOS transistors and PMOS transistors are used to reset the pixel circuit, capture the threshold of the driving transistor, etc., which is the same as the prior art, and the present invention will not be redundantly described.

[0089] In one embodiment of the present invention, the display panel provided by the present invention may be a panel structure driven by a single side, such as Fig.18 As described above, the first driving circuit 11, the second driving circuit 12 and the third driving circuit of the driving circuit are located on one side of the display area AA, and the pixel circuit 20 is driven by the unilateral driving circuit. Alternatively, the display panel provided by the present invention can also be a panel structure with bilateral driving, such as Fig.18 As shown, the driving circuit includes a first driving circuit 11 located on both sides of the display area AA, the driving circuit includes a second driving circuit 12 located on both sides of the display area AA, and the driving circuit includes a third driving circuit 13 located on both sides of the display area AA, thereby driving the pixel circuit 20 through the bilateral driving circuit.

[0090] like Fig.19As shown, in the double-sided driven panel structure provided by an embodiment of the present invention, the pixel circuits 20 in the same row can be driven simultaneously by two first driving circuits 11 located on different sides of the display area AA, the pixel circuits 20 in the same row can be driven simultaneously by two second driving circuits 12 located on different sides of the display area AA, and the pixel circuits 20 in the same row can be driven simultaneously by two third driving circuits 13 located on different sides of the display area AA.

[0091] Or, if Fig. 20 As shown, in the bilaterally driven panel structure provided by an embodiment of the present invention, pixel circuits 20 in different rows can be respectively driven by two first driving circuits 11 located on different sides of the display area AA, pixel circuits 20 in different rows can be respectively driven by two second driving circuits 12 located on different sides of the display area AA, and pixel circuits 20 in different rows can be respectively driven by two third driving circuits 13 located on different sides of the display area AA.

[0092] In one embodiment of the present invention, along the second direction X, the width of the output transistor of the first driving circuit 11 is smaller than the width of the output transistor of the third driving circuit 13, and the width of the output transistor of the third driving circuit 13 is smaller than the width of the output transistor of the second driving circuit 12. The output transistor is a transistor connected to the output end of the shift register, and is used to output the relevant control signal to the output end of the shift register. Figures 8 to 13 As shown, Figure 8 and Fig. 9 The shift register shown may be a first driving circuit 11, wherein the output transistors of the shift register of the first driving circuit are a ninth transistor M9 and a tenth transistor M10, the ninth transistor M9 is used to transmit the output signal of the high-level voltage signal line VGH to the output terminal OUT1 of the shift register, and the tenth transistor M10 is used to transmit the output signal of the low-level voltage signal line VGL to the output terminal OUT1 of the shift register. Fig.10 and Fig.11 The shift register of the second driving circuit 12 is shown, wherein the output transistors of the shift register of the second driving circuit are the seventh transistor P7 and the eighth transistor P8, the seventh transistor P7 is used to transmit the output signal of the high level voltage signal line VGH to the output end OUT2 of the shift register, and the eighth transistor P8 is used to transmit the output pulse signal of the clock signal line XCK2 to the output end OUT2 of the shift register. Fig.12 and Fig.13It can be a shift register of the third driving circuit 13, and the output transistors of the shift register of the third driving circuit are the ninth transistor N9 and the tenth transistor N10. The ninth transistor N9 is used to transmit the output signal of the high-level voltage signal line VGH to the output end OUT3 of the shift register, and the tenth transistor N10 is used to transmit the output signal of the low-level voltage signal line VGL to the output end OUT3 of the shift register.

[0093] It should be noted that the shift registers shown in the first drive circuit, the second drive circuit and the third drive circuit provided in the embodiment of the present invention are not limited to Figures 8 to 13 The shift register shown may also be other types of shift register structures, which are not specifically limited in the present invention.

[0094] In one embodiment of the present invention, the relationship among the width W1 of the first driving circuit, the width W2 of the second driving circuit, the width W3 of the third driving circuit, the total width D1 of M0 signal lines, the total width D2 of N0 signal lines and the total width D3 of P0 signal lines provided by the present invention can be D3 / W3-D2 / W2<D2 / W2-D1 / W1. Among them, the shift registers in the second driving circuit and the third driving circuit have higher requirements for the output signal, while the shift register in the first driving circuit has lower requirements for the output signal. Therefore, the present invention can design the values ​​of D3 / W3 and D2 / W2 to be relatively close, so as to fully avoid the problem of increased border area caused by the wider width of the corresponding signal lines, and the above two are designed to have a relatively large difference from the values ​​of D1 / W1.

[0095] In one embodiment of the present invention, the relationship between the number of M0 signal lines, the number of N0 signal lines and the number of P0 signal lines provided by the present invention can be set to M0<P0<N0. The width of the second driving circuit provided by the embodiment of the present invention is greater than the width of the third driving circuit, and the width of the third driving circuit is greater than the width of the first driving circuit, and then by setting the number of signal lines to M0<P0<N0, because the number of signal lines corresponding to the second driving circuit is large, or the width of the signal lines corresponding to the second driving circuit is wide, therefore, setting N0 to be large can fully avoid the second driving circuit and its corresponding signal lines occupying too much border area; the width of the third driving circuit is smaller than the width of the second driving circuit. If the output requirements of the third driving circuit are high, the number of corresponding signal lines may also be large, or the width of the signal lines may be large, therefore, setting P0 to be large can fully avoid the second driving circuit and its corresponding signal lines occupying too much border area; the first driving circuit itself has a small width, and there may not be too much space to overlap the corresponding signal lines, therefore, M0 can be set to be relatively small; such a setting can ensure the optimization of the overlap between the signal lines and the driving circuit, and reduce the border width of the display panel.

[0096] In one embodiment of the present invention, the M0 signal lines provided by the present invention include a third clock signal line for transmitting a third clock signal; the N0 signal lines include a fourth clock signal line for transmitting a fourth clock signal; the P0 signal lines include a fifth clock signal line for transmitting a fifth clock signal; wherein the width of the third clock signal line is smaller than the width of the fifth clock signal line, and the width of the fifth clock signal line is smaller than the width of the fourth clock signal line. The width of the second driving circuit provided by the embodiment of the present invention is greater than the width of the third driving circuit, and the width of the third driving circuit is greater than the width of the first driving circuit, and then by designing the width of the third clock signal line to be smaller than the width of the fifth clock signal line, and designing the width of the fifth clock signal line to be smaller than the width of the fourth clock signal line, it is ensured that the clock signal lines corresponding to different driving circuits are matched, and the stability and reliability of signal transmission by different clock signal lines are improved.

[0097] In one embodiment of the present invention, the M0 signal lines provided by the present invention include a third voltage signal line for transmitting a third voltage signal; the N0 signal lines include a fourth voltage signal line for transmitting a fourth voltage signal; the P0 signal lines include a fifth voltage signal line for transmitting a fifth voltage signal; wherein the width of the third voltage signal line is smaller than the width of the fourth voltage signal line, and the width of the fourth voltage signal line is smaller than the width of the fifth voltage signal line. The width of the second driving circuit provided by the embodiment of the present invention is greater than the width of the third driving circuit, and the width of the third driving circuit is greater than the width of the first driving circuit, and then by designing the width of the third voltage signal line to be smaller than the width of the fourth voltage signal line, and designing the width of the fourth voltage signal line to be smaller than the width of the fifth voltage signal line, it is ensured that the voltage signal lines corresponding to different driving circuits are matched, and the stability and reliability of signal transmission by different voltage signal lines are improved.

[0098] Correspondingly, an embodiment of the present invention further provides a display device, comprising the display panel provided by any one of the above embodiments.

[0099] like Fig.21 , which is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, wherein the display device 1000 provided in an embodiment of the present invention may be a mobile terminal device.

[0100] In other embodiments of the present invention, the display device provided by the present invention may also be an electronic display device such as a mobile phone, a computer, a vehicle-mounted terminal, etc., and the present invention does not make any specific limitation on this.

[0101] The embodiment of the present invention provides a display panel and a display device, which can reduce the occupied area of ​​some signal lines and reduce the border width of the display device by overlapping the M0 signal lines with the first drive circuit and overlapping the N0 signal lines with the second drive circuit. In addition, the embodiment of the present invention further optimizes the overlapping arrangement of the shift register with a larger width and the shift register with a smaller width and the total width of the corresponding signal lines by setting the relationship between the width W1 of the first drive circuit, the width W2 of the second drive circuit, the total width D1 of the M0 signal lines and the total width D2 of the N0 signal lines to W2>W1, D2>D1, and D2 / W2>D1 / W1, thereby fully reducing the occupied area of ​​the drive circuit and the signal lines and further reducing the border width of the display device.

[0102] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, It is characterized in that include: substrate substrate; A driving circuit and a pixel circuit, wherein the driving circuit and the pixel circuit are located on the substrate; The driving circuit includes a first driving circuit and a second driving circuit; a signal line group, the signal line group comprising a first signal line group and a second signal line group, the first signal line group comprising M signal lines providing signals to the first drive circuit, the second signal line group comprising N signal lines providing signals to the second drive circuit, M≥1, N≥1; In a direction perpendicular to the surface of the display panel, M0 signal lines in the first signal line group overlap with the first drive circuit and are located on a side of the first drive circuit away from the base substrate, and N0 signal lines in the second signal line group overlap with the second drive circuit and are located on a side of the second drive circuit away from the base substrate, 1≤M0≤M, 1≤N0≤N; The first driving circuit includes an S1-level shift register extending along a first direction, and / or the second driving circuit includes an S2-level shift register extending along the first direction, the second direction is parallel to the plane where the display panel surface is located, and is perpendicular to the first direction, S1≥2, S2≥2; The first driving circuit provides a light emitting control signal for the light emitting control transistor in the pixel circuit; The second driving circuit provides a control signal for a PMOS transistor in the pixel circuit, or the second driving circuit provides a control signal for an NMOS transistor in the pixel circuit; Along the second direction, the total width of the M0 signal lines in the first signal line group is D1, and the total width of the N0 signal lines in the second signal line group is D2; M0<N0, and / or, D1<D2.

2. The display panel according to claim 1, It is characterized in that The display panel comprises a transistor array layer, and the transistor array layer comprises the driving circuit and / or the pixel circuit; The transistor array layer comprises: a semiconductor layer, the semiconductor layer comprising an active region; A gate metal layer, wherein the gate metal layer includes a plurality of gate electrodes; A source-drain metal layer, wherein the source-drain metal layer includes a plurality of source electrodes and a plurality of drain electrodes; wherein, The M0 signal lines are located on a side of the source-drain metal layer away from the substrate, and the N0 signal lines are located on a side of the source-drain metal layer away from the substrate.

3. The display panel according to claim 1 or 2, It is characterized in that The M0 signal lines are located on the same layer, and / or the N0 signal lines are located on the same layer.

4. The display panel according to claim 1 or 2, It is characterized in that The M0 signal lines and the N0 signal lines are located in the same layer; or, The M0 signal lines and the N0 signal lines are located in different layers.

5. The display panel according to claim 2, It is characterized in that A first insulating layer is included between the source-drain metal layer and the film layer where the M0 signal lines are located, or a first insulating layer is included between the source-drain metal layer and the film layer where the N0 signal lines are located; A second insulating layer is included between the film layer where the M0 signal lines are located and the film layer where the N0 signal lines are located.

6. The display panel according to claim 1, It is characterized in that The total width of the M signal lines is D11, and the total width of the N signal lines is D22; wherein, (D11-D1)=(D22-D2); and / or, D11-D1=0; and / or, D22-D2=0.

7. The display panel according to claim 1, It is characterized in that N0-M0≥1.

8. The display panel according to claim 1, It is characterized in that The driving circuit further includes a third driving circuit, the signal line group further includes a third signal line group, the third signal line group includes P signal lines providing signals to the third driving circuit, P≥1; In a direction perpendicular to the surface of the display panel, P0 signal lines in the third signal line group overlap with the third driving circuit and are located on a side of the third driving circuit away from the base substrate, 1≤P0≤P; The third driving circuit includes an S3-level shift register, S3≥2; wherein, M0<P0, and / or, P0<N0.

9. The display panel according to claim 8, It is characterized in that Along the second direction, the width of the first driving circuit is W1, the width of the second driving circuit is W2, the width of the third driving circuit is W3, and the total width of the P0 signal lines in the third signal line group is D3; wherein, When W3>W1, D3>D1; and / or, When W3>W2, D3>D2.

10. The display panel according to claim 8, It is characterized in that Along the second direction, a width of the output transistor of the first driving circuit is smaller than a width of the output transistor of the third driving circuit, and a width of the output transistor of the third driving circuit is smaller than a width of the output transistor of the second driving circuit.

11. A display panel, It is characterized in that include: substrate substrate; A driving circuit, the driving circuit is located on the substrate, and the driving circuit includes a first driving circuit and a second driving circuit; a signal line group, the signal line group comprising a first signal line group and a second signal line group, the first signal line group comprising M signal lines providing signals to the first drive circuit, the second signal line group comprising N signal lines providing signals to the second drive circuit, M≥1, N≥1; In a direction perpendicular to the surface of the display panel, M0 signal lines in the first signal line group overlap with the first drive circuit and are located on a side of the first drive circuit away from the base substrate, and N0 signal lines in the second signal line group overlap with the second drive circuit and are located on a side of the second drive circuit away from the base substrate, 1≤M0≤M, 1≤N0≤N; The first driving circuit includes an S1-level shift register extending along a first direction, and / or the second driving circuit includes an S2-level shift register extending along the first direction, the second direction is parallel to the plane where the display panel surface is located, and is perpendicular to the first direction, S1≥2, S2≥2; Along the second direction, the total width of the M0 signal lines in the first signal line group is D1, and the total width of the N0 signal lines in the second signal line group is D2; M0<N0, and / or, D1<D2.

12. The display panel according to claim 11, It is characterized in that The display panel comprises a transistor array layer, and the transistor array layer comprises the driving circuit; The transistor array layer comprises: a semiconductor layer, the semiconductor layer comprising an active region; A gate metal layer, wherein the gate metal layer includes a plurality of gate electrodes; A source-drain metal layer, wherein the source-drain metal layer includes a plurality of source electrodes and a plurality of drain electrodes; wherein, The M0 signal lines are located on a side of the source-drain metal layer away from the substrate, and the N0 signal lines are located on a side of the source-drain metal layer away from the substrate.

13. The display panel according to claim 11 or 12, It is characterized in that The M0 signal lines are located on the same layer, and / or the N0 signal lines are located on the same layer.

14. The display panel according to claim 11 or 12, It is characterized in that The M0 signal lines and the N0 signal lines are located in the same layer; or, The M0 signal lines and the N0 signal lines are located in different layers.

15. The display panel according to claim 12, It is characterized in that A first insulating layer is included between the source-drain metal layer and the film layer where the M0 signal lines are located, or a first insulating layer is included between the source-drain metal layer and the film layer where the N0 signal lines are located; A second insulating layer is included between the film layer where the M0 signal lines are located and the film layer where the N0 signal lines are located.

16. The display panel according to claim 11, It is characterized in that The total width of the M signal lines is D11, and the total width of the N signal lines is D22; wherein, (D11-D1)=(D22-D2); and / or, D11-D1=0; and / or, D22-D2=0.

17. The display panel according to claim 11, It is characterized in that N0-M0≥1.

18. The display panel according to claim 11, It is characterized in that The driving circuit further includes a third driving circuit, the signal line group further includes a third signal line group, the third signal line group includes P signal lines providing signals to the third driving circuit, P≥1; In a direction perpendicular to the surface of the display panel, P0 signal lines in the third signal line group overlap with the third driving circuit and are located on a side of the third driving circuit away from the base substrate, 1≤P0≤P; The third driving circuit includes an S3-level shift register, S3≥2; wherein, M0<P0, and / or, P0<N0.

19. The display panel according to claim 18, It is characterized in that Along the second direction, the width of the first driving circuit is W1, the width of the second driving circuit is W2, the width of the third driving circuit is W3, and the total width of the P0 signal lines in the third signal line group is D3; wherein, When W3>W1, D3>D1; and / or, When W3>W2, D3>D2.

20. The display panel according to claim 18, It is characterized in that Along the second direction, a width of the output transistor of the first driving circuit is smaller than a width of the output transistor of the third driving circuit, and a width of the output transistor of the third driving circuit is smaller than a width of the output transistor of the second driving circuit.

21. A display device, It is characterized in that A display panel comprising any one of claims 1-20.

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