Display substrate, driving method thereof, and display device

Abstract

A display substrate, a driving method thereof and a display device, comprising a plurality of gate driving circuits, each of which comprises a plurality of shift registers connected in cascade, and each of the shift registers comprises a first reset sub-circuit connected with an interframe reset control end, a reset signal end and a first node to be reset respectively, and configured to write a reset signal of the reset signal end into the first node to be reset according to an interframe reset control signal of the interframe reset control end; wherein the interframe reset control end is connected with an interframe reset control line, and the interframe reset control ends of the plurality of gate driving circuits are connected with the same interframe reset control line.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display substrate and a driving method thereof, and a display device. BACKGROUND

[0002] Organic Light-Emitting Diode (OLED) has the advantages of self-illumination, wide viewing angle, fast response time, high luminous efficiency, low working voltage, and simple process, and is known as the next generation of "star" light-emitting devices. SUMMARY

[0003] The present disclosure provides a display substrate, comprising a plurality of gate driving circuits, the gate driving circuit comprising a plurality of shift registers cascaded with each other, the shift register comprising: a first reset sub-circuit, the first reset sub-circuit being connected with an interframe reset control end, a reset signal end and a first node to be reset respectively, for writing a reset signal of the reset signal end into the first node to be reset according to an interframe reset control signal of the interframe reset control end;

[0004] The interframe reset control end is connected with an interframe reset control line, and the interframe reset control ends of the plurality of gate driving circuits are connected with the same interframe reset control line.

[0005] In some embodiments, the interframe reset control line connecting the plurality of gate driving circuits is connected with the same signal input terminal.

[0006] In some embodiments, the interframe reset control line comprises: a first extension line, a second extension line and a lead wire, the first extension line and the second extension line are crossed with each other and connected with each other at the crossing position, one end of the lead wire is connected with the second extension line, and the other end is connected with the interframe reset control end.

[0007] In some embodiments, the interframe reset control line comprises: two first extension lines, one of the two first extension lines is located on the side of the plurality of gate driving circuits close to the signal input terminal, and the other of the two first extension lines is located on the side of the plurality of gate driving circuits away from the signal input terminal, wherein the signal input terminal is connected with the interframe reset control line.

[0008] In some embodiments, the first extension line and the second extension line are arranged in different layers and connected through a via at the crossing position.

[0009] In some embodiments, the display substrate further comprises a first signal line, the first signal line is arranged in a layer different from the first extension line and intersects with the first extension line at a first position;

[0010] The first extension line at the first position is provided with at least one strip-shaped hole, the strip-shaped hole is used to divide the first extension line at the first position into a plurality of extension line segments in parallel with each other, and the extension direction of the extension line segment intersects with the extension direction of the first signal line.

[0011] In some embodiments, the extension direction of the extension line segment is the same as the extension direction of the first extension line.

[0012] In some embodiments, in the extension direction of the first extension line, the size of the extension line segment is greater than the size of the first signal line.

[0013] In some embodiments, the extension direction of the first extension line is the same as the arrangement direction of the plurality of gate drive circuits, and the extension direction of the second extension line is the same as the arrangement direction of the plurality of shift registers in the same gate drive circuit.

[0014] In some embodiments, the display substrate comprises a display area and a frame area located at least one side of the display area, and the interframe reset control line and the plurality of gate drive circuits are located in the frame area.

[0015] The plurality of shift registers in the same gate drive circuit are connected to the same second extension line through a plurality of lead lines, and the same second extension line is located on the side of the plurality of lead lines away from the display area.

[0016] In some embodiments, the display substrate further comprises a pixel circuit and a light emitting device, and the pixel circuit is used to drive the light emitting device to emit light.

[0017] The plurality of gate drive circuits comprise at least one of the following:

[0018] The first gate drive circuit is connected to the write control end of the pixel circuit and is used to provide a write control signal to the pixel circuit.

[0019] The second gate drive circuit is connected to the compensation control end of the pixel circuit and is used to provide a compensation control signal to the pixel circuit.

[0020] The third gate drive circuit is connected to the initialization control end of the pixel circuit and is used to provide an initialization control signal to the pixel circuit.

[0021] In some embodiments, the shift register in the first gate drive circuit further comprises a second reset sub-circuit, connected with the inter-row reset control end, the reset signal end and a second node to be reset respectively, for writing the reset signal of the reset signal end into the second node to be reset according to the inter-row reset control signal of the inter-row reset control end;

[0022] The inter-frame reset control line is further connected with the inter-row reset control end of the last stage shift register in the first gate drive circuit.

[0023] In some embodiments, the display substrate comprises a plurality of pixel circuits arranged in an array, and the plurality of pixel circuits form a plurality of pixel circuit rows.

[0024] One shift register in the first gate drive circuit is connected with one pixel circuit row, one shift register in the second gate drive circuit is connected with one or more pixel circuit rows, and one shift register in the third gate drive circuit is connected with one or more pixel circuit rows.

[0025] In some embodiments, one shift register in the second gate drive circuit is connected with a plurality of pixel circuit rows, and the plurality of pixel circuit rows are respectively connected with different output transistors in the shift register, and the gates of a plurality of output transistors connected with the plurality of pixel circuit rows are connected with the same node.

[0026] One shift register in the third gate drive circuit is connected with a plurality of pixel circuit rows, and the plurality of pixel circuit rows are respectively connected with different output transistors in the shift register, and the gates of a plurality of output transistors connected with the plurality of pixel circuit rows are connected with the same node.

[0027] In some embodiments, the pixel circuit comprises:

[0028] A write sub-circuit connected with the write control end, the data end and a first node, for writing the data signal of the data end into the first node according to the write control signal;

[0029] A compensation sub-circuit connected with the compensation control end, a reference voltage end and the first node, for writing the voltage of the reference voltage end into the first node according to the compensation control signal;

[0030] An initialization sub-circuit connected with the initialization control end, an initialization voltage end and a second node, for writing the voltage of the initialization voltage end into the second node according to the initialization control signal, and the second node is further connected with the first electrode of the light emitting device.

[0031] The storage capacitor has its first electrode connected to the first node and its second electrode connected to the second node.

[0032] A driving sub-circuit, connected to the first node, the second node, and the third node, is used to write the signal from the third node into the second node under the potential control of the first node; and

[0033] The light-emitting sub-circuit, connected to the light-emitting control terminal, the first voltage terminal, and the third node, is used to drive the light-emitting device to emit light in cooperation with the driving sub-circuit according to the light-emitting control signal of the light-emitting control terminal.

[0034] This disclosure provides a display device, including:

[0035] The display substrate as described in any embodiment; and

[0036] A driver chip, connected to the display substrate, is used to provide drive signals to the display substrate.

[0037] This disclosure provides a driving method for a display substrate, used to drive a display substrate as described in any embodiment, the driving method comprising:

[0038] Between two frame periods, an inter-frame reset control signal is provided to the inter-frame reset control line so that the inter-frame reset control signal is input to the inter-frame reset control terminal via the inter-frame reset control line. The first reset sub-circuit writes the reset signal of the reset signal terminal into the first node to be reset according to the inter-frame reset control signal.

[0039] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0041] Figure 1 An exemplary schematic diagram of a planar structure of a display substrate provided in this disclosure is shown;

[0042] Figure 2An exemplary circuit diagram of the first shift register is shown;

[0043] Figure 3 An exemplary circuit diagram of the second shift register is shown;

[0044] Figure 4 An exemplary circuit diagram of the third shift register is shown;

[0045] Figure 5 The timing diagrams of several driving signals for the display substrate are shown as examples;

[0046] Figure 6 An exemplary wiring layout of the display substrate on the Source IN side is shown;

[0047] Figure 7 An exemplary wiring layout of a display substrate on the source end side is shown;

[0048] Figure 8 An exemplary schematic diagram of a pixel circuit is shown;

[0049] Figure 9 The timing diagrams of several control signals for the pixel circuit are shown as examples;

[0050] Figure 10 Simulation results of several signals in the display substrate provided in this disclosure are illustrated by way of example. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0052] This disclosure provides a display substrate, with reference to... Figure 1 An exemplary schematic diagram of a planar structure of a display substrate is shown. The display substrate includes multiple gate drive circuits (GOAs), and each gate drive circuit (GOA) includes multiple shift registers cascaded together.

[0053] For example, such as Figure 1As shown, the display substrate includes three gate driving circuits GOA, namely a first gate driving circuit GOA_G1, a second gate driving circuit GOA_G2, and a third gate driving circuit GOA_G3. The first gate driving circuit GOA_G1 includes multiple cascaded first shift registers G1 GOA Units, the second gate driving circuit GOA_G2 includes multiple cascaded second shift registers G2 GOA Units, and the third gate driving circuit GOA_G3 includes multiple cascaded third shift registers G3 GOA Units.

[0054] Reference Figure 2 An exemplary circuit diagram of the first shift register is shown. (Refer to...) Figure 3 An exemplary circuit diagram of the second shift register is shown. (Refer to...) Figure 4 An exemplary circuit diagram of the third shift register is shown.

[0055] Reference Figures 2 to 4 As shown in any one of the diagrams, the shift register includes a first reset sub-circuit 21, which is connected to the inter-frame reset control terminal TRS, the reset signal terminal RS, and the first node to be reset, respectively. It is used to write the reset signal of the reset signal terminal RS into the first node to be reset according to the inter-frame reset control signal of the inter-frame reset control terminal TRS.

[0056] For example, such as Figures 2 to 4 As shown in any one of the diagrams, the first node to be reset can be the gate of the output transistor Mt, or a node connected to the gate of the output transistor Mt (such as node Q), and this disclosure does not limit this.

[0057] like Figure 1 As shown, the inter-frame reset control terminal TRS is connected to the inter-frame reset control line 10, and the inter-frame reset control terminals TRS of multiple gate drive circuits GOA are connected to the same inter-frame reset control line 10.

[0058] For example, such as Figure 1 As shown, the inter-frame reset control terminals TRS of each first shift register G1 GOAUnit in the first gate drive circuit GOA_G1, the inter-frame reset control terminals TRS of each second shift register G2 GOA Unit in the second gate drive circuit GOA_G2, and the inter-frame reset control terminals TRS of each third shift register G3 GOA Unit in the third gate drive circuit GOA_G3 are all connected to the same inter-frame reset control line 10.

[0059] In practical implementation, an inter-frame reset control signal can be provided to the inter-frame reset control line 10 between two frame cycles. The inter-frame reset control signal is input to the inter-frame reset control terminal TRS of each shift register in multiple gate drive circuits (GOA) via the inter-frame reset control line 10. The first reset sub-circuit 21 in the shift register writes the reset signal of the reset signal terminal RS to the first node to be reset according to the inter-frame reset control signal input from the inter-frame reset control terminal TRS. This can discharge and reduce noise in the first node to be reset, improve the noise immunity of the gate drive circuit (GOA), enhance the functional stability of the gate drive circuit (GOA), and ensure that the display substrate displays the image normally.

[0060] The display substrate provided in this disclosure, by setting the inter-frame reset control terminals (TRS) of multiple gate drive circuits (GOA) to share the same inter-frame reset control line 10, can improve the noise immunity of the GOA while saving wiring space. With reasonable design, it can also save the number of passlines or channels on the driver chip.

[0061] In some implementations, the inter-frame reset control line 10 connecting multiple gate drive circuits (GOAs) is connected to the same signal input terminal PIN. The signal input terminal PIN can be connected to a driver chip to provide an inter-frame reset control signal to the inter-frame reset control line 10.

[0062] like Figure 1 As shown, the inter-frame reset control line 10 of the first gate drive circuit GOA_G1 is connected to the inter-frame reset control terminal TRS of each first shift register G1 GOA Unit. The inter-frame reset control line 10 of the second gate drive circuit GOA_G2 is connected to the inter-frame reset control terminal TRS of each second shift register G2 GOA Unit. The inter-frame reset control line 10 of the third gate drive circuit GOA_G3 is connected to the inter-frame reset control terminal TRS of each third shift register G3 GOA Unit. The inter-frame reset control lines 10 of the first, second, and third gate drive circuits GOA_G1, GOA_G2, and GOA_G3 are all connected to the same signal input terminal PIN.

[0063] In this embodiment, since multiple gate drive circuits (GOAs) share a single signal input terminal PIN, the inter-frame reset control signal is provided to the inter-frame reset control line 10 through this single signal input terminal PIN, which can save the number of passlines or channels on the driver chip and reduce the cost of the driver chip.

[0064] It should be noted that the inter-frame reset control line 10 connecting multiple gate drive circuits GOA can also be connected to multiple signal input terminals PIN, and this disclosure does not limit this.

[0065] It should be noted that the first reset sub-circuit 21 and the first node to be reset can be directly connected, such as... Figure 2 As shown, the first reset sub-circuit 21 and the first node to be reset can also be indirectly connected, such as... Figure 3 or Figure 4 As shown, a normally open transistor Mk is further disposed between the first reset sub-circuit 21 and the first node to be reset. The gate of the normally open transistor Mk is connected to a signal terminal that enables it to conduct, the first terminal is connected to the first reset sub-circuit 21, and the second terminal is connected to the first node to be reset. Exemplarily, in... Figure 3 and Figure 4 In this circuit, the normally open transistor Mk is an N-type transistor, and its gate is connected to a high-level signal VGH, so it is in the on state, thereby turning on the first reset sub-circuit 21 and the first node to be reset.

[0066] Specifically, the interval between two frame cycles can be after the multiple gate drive circuits (GOA) have completed their output in the previous frame cycle and before the multiple gate drive circuits (GOA) begin their output in the next frame cycle.

[0067] For example, such as Figure 5 As shown, one display cycle of a display substrate includes a refresh display phase (such as...). Figure 5 The two frame cycles mentioned above can be between two refresh display phases, i.e., after the previous refresh display phase and before the next refresh display phase, such as the hold display phase.

[0068] For example, such as Figures 2 to 4 As shown in any one of the diagrams, the first reset sub-circuit 21 may include a first reset transistor Mf1, the gate of the first reset transistor Mf1 is connected to the inter-frame reset control terminal TRS, the first pole is connected to the reset signal terminal RS, and the second pole is connected to the first node to be reset.

[0069] In practical implementation, the inter-frame reset control signal provided to the signal input terminal PIN between two frame cycles can be a signal capable of turning on the first reset transistor Mf1. For example... Figures 2 to 4 As shown in either case, when the first reset transistor Mf1 is an N-type transistor, a high-level inter-frame reset control signal (such as...) can be provided to the signal input terminal PIN between two frame cycles. Figure 5 (TRS in the text).

[0070] To enable simultaneous reset of the first reset nodes in multiple gate drive circuits (GOAs), the first reset transistors Mf1 in the first shift register G1 GOA Unit, the second shift register G2 GOA Unit, and the third shift register G3 GOA Unit are of the same type, for example, all being N-type transistors (e.g.,...). Figures 2 to 4 (As shown) or P-type transistor.

[0071] The reset signal at the reset signal terminal RS can be a signal capable of turning off the output transistor Mt. For example... Figures 2 to 4 As shown in either case, when the output transistor Mt is an N-type transistor, a low-level reset signal can be provided to the reset signal terminal RS between two frame cycles.

[0072] For example, in the first shift register G1 GOA Unit, as Figure 2 As shown, the reset signal is a low-level signal VGL. In the second shift register G2 GOA Unit, as... Figure 3 As shown, the reset signal is the clock signal CKA, as... Figure 5 As shown, the clock signal CKA is low between two frame cycles. In the third shift register G3 GOA Unit, as... Figure 4 As shown, the reset signal is the clock signal CKC, as... Figure 5 As shown, the clock signal CKC is low between two frame cycles.

[0073] In some implementations, such as Figure 1 As shown, the inter-frame reset control line 10 includes: a first extension line 11, a second extension line 12, and a lead 13. The first extension line 11 and the second extension line 12 intersect each other and are connected to each other at the intersection. One end of the lead 13 is connected to the second extension line 12, and the other end is connected to the inter-frame reset control terminal TRS.

[0074] In some implementations, such as Figure 1 As shown, the inter-frame reset control line 10 includes: two first extension lines 11, which are arranged in the same gate drive circuit GOA in the direction of the multiple shift registers (in Figure 1 The middle section is vertical), and the two first extension lines 11 are located on opposite sides of the multiple gate drive circuits GOA (e.g., Figure 1 (as shown in the upper and lower sections).

[0075] For example, such as Figure 1 As shown, the two first extension lines 11 are in the arrangement direction of multiple shift registers located within the same gate drive circuit (in... Figure 1(Vertical orientation) One first extension line 11 is located on the side of the multiple gate drive circuits GOA closest to the signal input terminal PIN (i.e., the Source IN side, below the multiple gate drive circuits GOA), and the other first extension line 11 is located on the side of the multiple gate drive circuits GOA furthest from the signal input terminal PIN (i.e., the Source End side, above the multiple gate drive circuits GOA). The signal input terminal PIN is connected to the inter-frame reset control line 10, used to bind the driver chip and provide inter-frame reset control signals to the inter-frame reset control line 10.

[0076] Reference Figure 6 and Figure 7 Exemplary wiring layouts of the display substrate on the Source IN side and Source End side are shown respectively. Figure 6 and Figure 7 In the diagram, figure b is a magnified view of the area within the dashed box in figure a, figure c is a magnified view of the area within the dashed box in figure b, and figure d is a layered diagram corresponding to figure c. Figure 6 As shown, a first horizontal extension line 11 is provided on the Source IN side of the display substrate, as... Figure 7 As shown, another horizontal first extension line 11 is provided on the Source End side of the display substrate.

[0077] By setting multiple first extension lines 11, the voltage drop of the inter-frame reset control signal on the inter-frame reset control line 10 can be reduced, thereby improving the driving capability of the inter-frame reset control signal.

[0078] It should be noted that the inter-frame reset control line 10 may also include a first extension line 11, for example, located on the side of the plurality of gate drive circuits GOA near the signal input terminal PIN (e.g., the lower side of the plurality of gate drive circuits GOA), or on the side of the plurality of gate drive circuits GOA away from the signal input terminal PIN (e.g., the upper side of the plurality of gate drive circuits GOA). The inter-frame reset control line 10 may also have two or more first extension lines 11, with one part located on the side of the plurality of gate drive circuits GOA near the signal input terminal PIN (e.g., the lower side of the plurality of gate drive circuits GOA), and another part located on the side of the plurality of gate drive circuits GOA away from the signal input terminal PIN (e.g., the upper side of the plurality of gate drive circuits GOA).

[0079] In some implementations, such as Figure 6 or Figure 7 As shown, the first extension line 11 and the second extension line 12 are disposed in different layers, and pass through vias (such as...) at their intersections. Figure 7 The via H is shown in Figure c.

[0080] For example, such as Figure 7As shown in Figure d, the transition pattern P1 on the first extension line 11 and the transition pattern P2 on the second extension line 12 overlap through a through hole provided in the insulating layer (not shown in the figure) between the first extension line 11 and the second extension line 12.

[0081] It should be noted that the first extension line 11 and the second extension line 12 can also be set on the same layer, and this disclosure does not limit this. Similarly, the second extension line 12 and the lead line 13 can be set on the same layer or on different layers, and this disclosure does not limit this.

[0082] In some implementations, such as Figure 6 or Figure 7 As shown, the display substrate also includes a first signal line 61, which is disposed on a different layer from the first extension line 11 and intersects with each other at a first position. At least one strip-shaped hole 62 is provided on the first extension line 11 at the first position. The strip-shaped hole 62 is used to divide the first extension line 11 at the first position into multiple parallel extension segments 63, the extension directions of which intersect with the extension direction of the first signal line 61.

[0083] By setting the strip hole 62 to form multiple parallel extension segments 63, it is possible to cut off a short circuit between a certain extension segment 63 and the first signal line 61, so that the short circuit can be repaired, the short circuit can be avoided from affecting the signal transmission on the first extension line 11, the integrity of the signal can be guaranteed, the product yield can be improved, and technical support can be provided for medium and large-sized MNT products.

[0084] In some implementations, such as Figure 6 or Figure 7 As shown, the extension direction of extension segment 63 is the same as the extension direction of the first extension line 11. Figure 6 and Figure 7 In the middle, the extension direction of the extension segment 63 and the extension direction of the first extension line 11 are both horizontal.

[0085] In some implementations, such as Figure 6 As shown, in the extension direction of the first extension line 11, the size w1 of the extension segment 63 is greater than the size w2 of the first signal line 61.

[0086] In some implementations, such as Figure 1 As shown, the extension direction of the first extension line 11 is the same as the arrangement direction of the multiple gate drive circuits GOA, and the extension direction of the second extension line 12 is the same as the arrangement direction of the multiple shift registers located in the same gate drive circuit GOA.

[0087] like Figure 1As shown, the first gate drive circuit GOA_G1, the second gate drive circuit GOA_G2, and the third gate drive circuit GOA_G3 are arranged horizontally, meaning that the multiple gate drive circuits GOA are arranged horizontally, and the extension direction of the first extension line 11 is also horizontal. Figure 1 As shown, the multiple shift registers located within the same gate drive circuit GOA are all arranged vertically, and the extension direction of the second extension line 12 is also vertical. The extension directions of the first extension line 11 and the second extension line 12 can be perpendicular to each other (e.g., ...). Figure 1 (As shown).

[0088] In some implementations, such as Figure 1 As shown, the display substrate includes a display area and a frame area located on at least one side of the display area. The inter-frame reset control line 10 and multiple gate drive circuits GOA are all located in the frame area. Among them, multiple shift registers located in the same gate drive circuit GOA are connected to the same second extension line 12 through multiple leads 13, and the same second extension line 12 is located on the side of the multiple leads 13 away from the display area.

[0089] It should be noted that the inter-frame reset control line 10 and multiple gate drive circuits GOA can be interconnected on one side (such as the left or right side) of the display area, or the inter-frame reset control line 10 and multiple gate drive circuits GOA can be interconnected on both sides (such as the left and right sides) of the display area. For example, Figure 1 The inter-frame reset control line 10 and multiple gate drive circuits GOA shown are located in the left border area of ​​the display area.

[0090] In some embodiments, the display area of ​​the display substrate includes pixel circuitry and light-emitting devices, wherein the pixel circuitry drives the light-emitting devices to emit light. For example, such as... Figure 8As shown, the pixel circuit includes: a write sub-circuit 81, connected to the write control terminal G1, the data terminal Data, and the first node N1, used to write the data signal of the data terminal Data to the first node N1 according to the write control signal of the write control terminal G1; a compensation sub-circuit 82, connected to the compensation control terminal G2, the reference voltage terminal Vref, and the first node N1, used to write the reference voltage of the reference voltage terminal Vref to the first node N1 according to the compensation control signal of the compensation control terminal G2; and an initialization sub-circuit 83, connected to the initialization control terminal G3, the initialization voltage terminal Vini, and the second node N2, used to write the reference voltage of the reference voltage terminal Vref to the first node N1 according to the initialization control signal of the initialization control terminal G3. The initial voltage of the initialization voltage terminal Vini is written into the second node N2, which is also connected to the first terminal of the light-emitting device LD; the storage capacitor Cst has its first terminal connected to the first node N1 and its second terminal connected to the second node N2; the driving sub-circuit 84 is connected to the first node N1, the second node N2 and the third node N3, and is used to write the signal of the third node N3 into the second node N2 under the potential control of the first node N1; and the light-emitting sub-circuit 85 is connected to the light-emitting control terminal EM, the first voltage terminal VDD and the third node N3, and is used to drive the light-emitting device LD to emit light in cooperation with the driving sub-circuit 84 according to the light-emitting control signal of the light-emitting control terminal EM.

[0091] For example, such as Figure 8 As shown, the write sub-circuit 81 includes a first transistor M1, the gate of the first transistor M1 is connected to the write control terminal G1, the first terminal is connected to the data terminal Data, and the second terminal is connected to the first node N1.

[0092] For example, such as Figure 8 As shown, the compensation sub-circuit 82 includes a second transistor M2. The gate of the second transistor M2 is connected to the compensation control terminal G2, the first terminal is connected to the reference voltage terminal Vref, and the second terminal is connected to the first node N1.

[0093] For example, such as Figure 8 As shown, the initialization sub-circuit 83 includes a third transistor M3. The gate of the third transistor M3 is connected to the initialization control terminal G3, the first terminal is connected to the initialization voltage terminal Vini, and the second terminal is connected to the second node N2.

[0094] For example, such as Figure 8 As shown, the driving sub-circuit 84 includes a driving transistor Md, the gate of which is connected to the first node N1, the first electrode of which is connected to the second node N2, and the second electrode of which is connected to the third node N3.

[0095] For example, such as Figure 8As shown, the light-emitting sub-circuit 85 includes a fourth transistor M4. The gate of the fourth transistor M4 is connected to the light-emitting control terminal EM, the first terminal is connected to the first voltage terminal VDD, and the second terminal is connected to the third node N3.

[0096] For example, Figure 8 The transistors in the pixel circuit shown are all N-type transistors. (Refer to...) Figure 9 An example is shown Figure 8 The timing diagram shows several control signals for the pixel circuit. G1 represents the write control signal for write control terminal G1, G2 represents the compensation control signal for compensation control terminal G2, G3 represents the initialization control signal for initialization control terminal G3, and EM represents the light emission control signal for light emission control terminal EM. Figure 9 As shown, the driving process of a pixel circuit can include the following four stages:

[0097] In phase T1, which is the reset phase, the write control signal G1 is low, the compensation control signal G2 and the initialization control signal G3 are high, and the light emission control signal EM is low. Therefore, the second transistor M2 is turned on, the third transistor M3 is turned on, and the fourth transistor M4 is turned off. The second node N2, i.e., the anode of the LD, is reset to the initialization voltage Vini. The gate of the first node N1, i.e., the driving transistor Md, is written with the reference voltage Vref, and the first transistor M1 is turned off.

[0098] In stage T2, which is the compensation stage, the write control signal G1 is low, the compensation control signal G2 is high, the initialization control signal G3 is low, and the light emission control signal EM is high. Therefore, the third transistor M3 is off, the fourth transistor M4 is on, the second transistor M2 remains on, and the first transistor M1 is off. Since the driving transistor Md is on at this time, the source voltage VG of the driving transistor Md rises to VGS = Vth, and the driving transistor Md is off. Here, VGS is the difference between the source voltage VG and the gate voltage VS of the driving transistor Md.

[0099] T3 is the writing stage. The write control signal G1 is high, the compensation control signal G2 is low, the initialization control signal G3 is low, and the light emission control signal EM is low. Therefore, the second transistor M2 is off, the third transistor M3 is off, the fourth transistor M4 is off, and the first transistor M1 is on to write the data voltage Data.

[0100] During stage T4, which is the light-emitting stage, the write control signal G1 is low, the compensation control signal G2 is low, the initialization control signal G3 is low, and the light-emitting control signal EM is high. Therefore, the fourth transistor M4 is turned on, and the first transistor M1, the second transistor M2, and the third transistor M3 are turned off.

[0101] It should be noted that the transistors in the pixel circuit can be oxide transistors, polysilicon transistors, or a combination of oxide transistors and polysilicon transistors connected in series (e.g., ...). Figure 8 The first transistor M1, the second transistor M2, and the third transistor M3 are shown in the diagram.

[0102] In some implementations, the multiple gate drive circuits GOA sharing the inter-frame reset control line 10 include a first gate drive circuit GOA_G1, which is connected to the write control terminal G1 of the pixel circuit and is used to provide write control signals to the pixel circuit.

[0103] In some implementations, the multiple gate drive circuits GOA sharing the inter-frame reset control line 10 include a second gate drive circuit GOA_G2, which is connected to the compensation control terminal G2 of the pixel circuit and is used to provide compensation control signals to the pixel circuit.

[0104] In some implementations, the multiple gate drive circuits GOA sharing the inter-frame reset control line 10 include a third gate drive circuit GOA_G3, which is connected to the initialization control terminal G3 of the pixel circuit and is used to provide initialization control signals to the pixel circuit.

[0105] Reference Figure 10 Simulation results for several signals in the display substrate provided in this disclosure are illustrated as examples. For instance... Figure 10 As shown, the first gate drive circuit GOA_G1 outputs the write control signal G1 to the 2160th row pixel circuit. <2160> The compensation control signal G2 output by the second gate drive circuit GOA_G2 to the 2160th row pixel circuit. <2160> And the initialization control signal G3 output by the third gate drive circuit GOA_G3 to the 2160th row pixel circuit. <2160> The simulation results show that the signal integrity is good and it has strong anti-interference ability. Figure 10 EM in <2160> This is the light emission control signal for the pixel circuit in row 2160.

[0106] In some implementations, such as Figure 2 As shown, the shift register in the first gate drive circuit GOA_G1 also includes a second reset sub-circuit 22. The second reset sub-circuit 22 is connected to the interline reset control terminal CRg1, the reset signal terminal RS, and the second node to be reset, respectively. It is used to write the reset signal of the reset signal terminal RS into the second node to be reset according to the interline reset control signal of the interline reset control terminal CRg1. The inter-frame reset control line 10 is also connected to the interline reset control terminal CRg1 of the last stage shift register in the first gate drive circuit GOA_G1.

[0107] For example, such as Figure 2 As shown, the second node to be reset can be the gate of the output transistor Mt, or a node connected to the gate of the output transistor Mt (such as node Q), and this disclosure does not limit it in this way.

[0108] In the first gate driver circuit GOA_G1, except for the last stage shift register, the output of the lower-level shift register is connected to the inter-row reset control terminal CRg1 of the upper-level shift register, thereby resetting the upper-level shift register. That is, in the first gate driver circuit GOA_G1, the inter-row reset control terminal CRg1 of the Nth-level shift register is connected to the output of the (N+M)th-level shift register, where 1 ≤ N < H, N+M ≤ H, M ≥ 1, and both M and N are positive integers. H is the total number of shift registers in the first gate driver circuit GOA_G1. For example, M can be 1, 2, 3, or 4, etc.

[0109] like Figure 1 As shown, the inter-line reset control terminal CRg1 of the last stage shift register in the first gate drive circuit GOA_G1 is connected to the inter-frame reset control line 10, meaning the inter-frame reset control signal is multiplexed into an inter-line reset control signal. In a specific implementation, an inter-frame reset control signal can be provided to the inter-frame reset control line 10 between two frame periods (such as during image cancellation). The inter-frame reset control signal is input to the inter-line reset control terminal CRg1 of the last stage shift register in the first gate drive circuit GOA_G1 via the inter-frame reset control line 10. The second reset sub-circuit 22 therein writes the reset signal of the reset signal terminal RS to the second node to be reset according to the inter-frame reset control signal, thereby resetting the second node to be reset.

[0110] In this way, while resetting the first node to be reset in multiple gate drive circuits GOA, the second node to be reset in the last stage shift register of the first gate drive circuit GOA_G1 can be reset simultaneously using the inter-frame reset control signal. By connecting the inter-frame reset control line 10 to the inter-line reset control terminal CRg1 of the last stage shift register in the first gate drive circuit GOA_G1, there is no need to additionally set up an inter-line reset control line to connect to the aforementioned last stage shift register, thereby saving wiring space and simplifying design and driving complexity.

[0111] For example, such as Figure 2 As shown, the second reset sub-circuit 22 may include a second reset transistor Mf2. The gate of the second reset transistor Mf2 is connected to the inter-row reset control terminal CRg1, the first terminal is connected to the reset signal terminal RS, and the second terminal is connected to the second node to be reset.

[0112] In practical implementation, the inter-frame reset control signal provided to the signal input terminal PIN between two frame cycles can be a signal capable of turning on the second reset transistor Mf2. For example... Figure 2 As shown, when the second reset transistor Mf2 is an N-type transistor, a high-level inter-frame reset control signal (such as...) can be provided to the signal input terminal PIN between two frame cycles. Figure 5 (TRS in the text).

[0113] In order to enable the inter-frame reset control signal to be reused as the inter-line reset control signal, the first reset transistor Mf1 and the second reset transistor Mf2 are of the same type, for example, both are N-type transistors or P-type transistors.

[0114] In some implementations, such as Figures 2 to 4 As shown, the display substrate includes multiple pixel circuits arranged in an array, forming multiple pixel circuit rows. Specifically, a shift register in the first gate driving circuit GOA_G1 is connected to one pixel circuit row, a shift register in the second gate driving circuit GOA_G2 is connected to one or more pixel circuit rows, and a shift register in the third gate driving circuit GOA_G3 is connected to one or more pixel circuit rows.

[0115] For example, such as Figure 2 As shown, a shift register in the first gate drive circuit GOA_G1 is connected to a pixel circuit row, for example, Figure 2 The output terminal OUTg1 of the shift register shown <n>connects the (N+1)th row of pixel circuits (i.e., the (N+1)th row of pixel circuits). Figure 2 In this case, the output terminal OUTg1 of the shift register <n>The first electrode or the second electrode of the output transistor Mt is connected.

[0116] As shown in the example of Fig. 6, the second gate drive circuit GOA_G2 is connected to the first gate drive circuit GOA_G1. Figure 3 As shown in the example of Fig. 6, the second gate drive circuit GOA_G2 is connected to the first gate drive circuit GOA_G1. Figure 3 As shown in the example of Fig. 6, the second gate drive circuit GOA_G2 is connected to the first gate drive circuit GOA_G1. <n>The other output terminal OUTg2<N> is connected to the Nth row of pixel circuits (i.e., the Nth row of pixel circuits), and the other output terminal OUTg2<N+1> is connected to the N+1th row of pixel circuits (i.e., the N+1th row of pixel circuits). Figure 3 In this case, the output terminal OUTg2 <n>The first electrode or the second electrode of the output transistor Mt1 is connected to the first electrode or the second electrode of the output transistor Mt2.

[0117] As shown exemplarily, one shift register in the third gate drive circuit GOA_G3 connects two pixel circuit rows, for example, Figure 4 As shown exemplarily, one shift register in the third gate drive circuit GOA_G3 connects two pixel circuit rows, for example, Figure 4 One output terminal OUTg3 of the shift register shown <n>The other output end OUTg3<N> is connected to the Nth row of pixel circuits (i.e., the Nth row of pixel circuits), and the other output end OUTg3<N+1> is connected to the N+1th row of pixel circuits (i.e., the N+1th row of pixel circuits). Figure 4 In the case of the output end OUTg3 <n>Connect the first or second terminal of the output transistor Mt1, and the output terminal OUTg3.<N+1> Connect the first or second terminal of the output transistor Mt2.

[0118] In some implementations, such as Figure 3 As shown, in the second gate driving circuit GOA_G2, a shift register connects to multiple pixel circuit rows. These pixel circuit rows are each connected to different output transistors Mt within the shift register. The gates of the multiple output transistors Mt connected to the multiple pixel circuit rows are connected to the same node. In this way, one output transistor Mt corresponds to one pixel circuit row. Compared to a scheme where one output transistor Mt connects to multiple pixel circuit rows, this reduces the size of the output transistors Mt in the second gate driving circuit GOA_G2 and decreases the impact of parasitic capacitance on the output transistors Mt.

[0119] For example, such as Figure 3 As shown, a shift register in the second gate drive circuit GOA_G2 is connected to two pixel circuit rows (i.e., the Nth pixel circuit row and the N+1th pixel circuit row). The two pixel circuit rows are connected to the output transistor Mt1 and the output transistor Mt2, respectively. The gates of the output transistor Mt1 and the output transistor Mt2 are connected to the same node Q.

[0120] In some implementations, such as Figure 4 As shown, in the third gate driving circuit GOA_G3, a shift register connects to multiple pixel circuit rows. These pixel circuit rows are each connected to different output transistors Mt within the shift register. The gates of the multiple output transistors Mt connected to the multiple pixel circuit rows are connected to the same node. In this way, one output transistor Mt corresponds to one pixel circuit row. Compared to a scheme where one output transistor Mt connects to multiple pixel circuit rows, this reduces the size of the output transistors Mt in the third gate driving circuit GOA_G3 and decreases the impact of parasitic capacitance on the output transistors Mt.

[0121] For example, such as Figure 4 As shown, a shift register in the third gate drive circuit GOA_G3 is connected to two pixel circuit rows (i.e., the Nth pixel circuit row and the N+1th pixel circuit row). The two pixel circuit rows are connected to the output transistor Mt1 and the output transistor Mt2, respectively. The gates of the output transistor Mt1 and the output transistor Mt2 are connected to the same node Q.

[0122] This disclosure also provides a display device, including: a display substrate as described in any embodiment; and a driver chip connected to the display substrate for providing a drive signal to the display substrate.

[0123] It can be understood that the display device provided by the present disclosure has the advantages of the display substrate described above, which will not be repeated here. The display device provided by the present disclosure can be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.

[0124] In a specific implementation, the driving chip can be connected with the signal input terminal in the display substrate.

[0125] The present disclosure also provides a driving method of the display substrate, for driving the display substrate according to any one of the embodiments, the driving method comprising:

[0126] Between two frame periods, the inter-frame reset control line 10 is provided with an inter-frame reset control signal, so that the inter-frame reset control signal is input to the inter-frame reset control end TRS through the inter-frame reset control line 10, and the first reset sub-circuit 21 writes the reset signal of the reset signal end RS to the first to-be-reset node according to the inter-frame reset control signal.

[0127] It should be noted that the driving method of the display substrate can further include more steps, which can be determined according to actual needs, and the present disclosure does not limit this. The detailed description and technical effects of the driving method can be referred to the description of the display substrate in the foregoing, which will not be repeated here.

[0128] In the present disclosure, the meaning of "a plurality of" is two or more than two, and the meaning of "at least one" is one or more than one, unless otherwise explicitly specified.

[0129] In the present disclosure, the terms "upper", "lower", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0130] In this document, the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, product or device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0131] As used herein, the terms "one embodiment", "some embodiments", "certain embodiments", "one or more embodiments", "some examples", "one example", "an example", "embodiments", etc., mean incorporating at least the featured feature, structure, material, or characteristic since the disclosure is written in the broadest form to include at least one of the appropriate features, structures, materials, or characteristics in at least one embodiment or example. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be included in any appropriate manner in any one or more embodiments or examples.

[0132] In this document, relational terms such as first and second, and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0133] In describing some embodiments, the expressions "coupled" and "connected" can be used. For example, the term "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. However, the terms "coupled" or "communicatively coupled" can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the context.

[0134] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", both of which include the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0135] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0136] As used herein, the term "if' is optionally interpreted as meaning "when" or "upon" or "in response to a determination" or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if detecting [stated condition or event]" is optionally interpreted as meaning "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]" depending on the context.

[0137] The use of "for" or "configured to" herein means open and inclusive language that does not exclude devices suitable for or configured to perform additional tasks or steps.

[0138] The use of "based on" or "according to" herein means open and inclusive. A process, step, calculation or other action that is based on one or more recited conditions or values, can in practice be based on other conditions or values beyond those that are recited. A process, step, calculation or other action that is according to one or more recited conditions or values, can in practice be according to other conditions or values beyond those that are recited.

[0139] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0140] As used herein, "parallel," "perpendicular," "equal," "flush," includes the recited condition and conditions that approximate the recited condition, within an acceptable range of approximation, where the acceptable range of approximation is determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of approximation for near parallel can be, for example, within 5° of deviation; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of approximation for near perpendicular can also be, for example, within 5° of deviation. "Equal" includes absolute equality and near equality, where the acceptable range of approximation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either. "Flush" includes absolute flush and near flush, where the acceptable range of approximation for near flush can be, for example, a distance between the two that is less than or equal to 5% of either of the dimensions.

[0141] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0142] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layer and regions are shown in the drawings with the same dimensions. For example, the thickness of layers and regions can be exaggerated in the drawings. Thus, the exemplary embodiments are not intended to be limited to the illustrations as shown in the drawings, but include variations as would be known to one of ordinary skill in the art. For example, etched regions shown as rectangular can typically have curved features. Thus, the regions illustrated in the drawings are schematic and not intended to be exact representations of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0143] It should be finally pointed out that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A display substrate comprising a plurality of gate driving circuits, wherein the gate driving circuits include a plurality of shift registers cascaded together, the shift registers comprising: The first reset sub-circuit is connected to the inter-frame reset control terminal, the reset signal terminal, and the first node to be reset, respectively, and is used to write the reset signal of the reset signal terminal into the first node to be reset according to the inter-frame reset control signal of the inter-frame reset control terminal. The inter-frame reset control terminal is connected to the inter-frame reset control line, and the inter-frame reset control terminals of multiple gate drive circuits are connected to the same inter-frame reset control line; the inter-frame reset control signal is provided to the inter-frame reset control line between two frame periods. The inter-frame reset control line includes: a first extension line, a second extension line, and a lead wire. The first extension line and the second extension line intersect each other and are connected to each other at the intersection. One end of the lead wire is connected to the second extension line, and the other end is connected to the inter-frame reset control terminal.

2. The display substrate according to claim 1, wherein, The inter-frame reset control lines connecting multiple gate drive circuits are connected to the same signal input terminal.

3. The display substrate according to claim 1, wherein, The inter-frame reset control line includes two first extension lines. In the arrangement direction of multiple shift registers located in the same gate drive circuit, one of the first extension lines is located on the side of the multiple gate drive circuits closer to the signal input terminal, and the other first extension line is located on the side of the multiple gate drive circuits away from the signal input terminal. The signal input terminal is connected to the inter-frame reset control line.

4. The display substrate according to claim 1, wherein, The first extension line and the second extension line are disposed in different layers and are connected by vias at their intersections.

5. The display substrate according to claim 1, wherein the display substrate further comprises a first signal line, the first signal line and the first extension line being disposed in different layers and intersecting each other at a first position; in, At least one strip hole is provided on the first extension line at the first position. The strip hole is used to divide the first extension line at the first position into multiple extension segments connected in parallel. The extension direction of the extension segments intersects with the extension direction of the first signal line.

6. The display substrate according to claim 5, wherein, The extension direction of the extension segment is the same as the extension direction of the first extension line.

7. The display substrate according to claim 6, wherein, In the extension direction of the first extension line, the size of the extension segment is larger than the size of the first signal line.

8. The display substrate according to claim 1, wherein, The first extension line extends in the same direction as the arrangement of the plurality of gate driving circuits, and the second extension line extends in the same direction as the arrangement of the plurality of shift registers within the same gate driving circuit.

9. The display substrate according to claim 1, wherein, The display substrate includes a display area and a frame area located on at least one side of the display area, and the inter-frame reset control line and the plurality of gate driving circuits are all located in the frame area; Multiple shift registers located within the same gate drive circuit are connected to the same second extension line via multiple leads, and the same second extension line is located on the side of the multiple leads away from the display area.

10. The display substrate according to any one of claims 1 to 9, wherein the display substrate further comprises a pixel circuit and a light-emitting device, the pixel circuit being used to drive the light-emitting device to emit light; in, The plurality of gate drive circuits include at least one of the following: A first gate driving circuit is connected to the write control terminal of the pixel circuit and is used to provide a write control signal to the pixel circuit. The second gate driving circuit is connected to the compensation control terminal of the pixel circuit and is used to provide compensation control signals to the pixel circuit. as well as The third gate driving circuit is connected to the initialization control terminal of the pixel circuit and is used to provide initialization control signals to the pixel circuit.

11. The display substrate according to claim 10, wherein, The shift register in the first gate drive circuit further includes a second reset sub-circuit. The second reset sub-circuit is connected to the inter-row reset control terminal, the reset signal terminal, and the second node to be reset, respectively, and is used to write the reset signal of the reset signal terminal into the second node to be reset according to the inter-row reset control signal of the inter-row reset control terminal. The inter-frame reset control line is also connected to the inter-line reset control terminal of the last stage shift register in the first gate drive circuit.

12. The display substrate according to claim 10, wherein, The display substrate includes a plurality of pixel circuits arranged in an array, and the plurality of pixel circuits form a plurality of pixel circuit rows; In this circuit, a shift register in the first gate driving circuit is connected to one pixel circuit row, a shift register in the second gate driving circuit is connected to one or more pixel circuit rows, and a shift register in the third gate driving circuit is connected to one or more pixel circuit rows.

13. The display substrate according to claim 12, wherein, In the second gate driving circuit, a shift register is connected to multiple pixel circuit rows, and the multiple pixel circuit rows are respectively connected to different output transistors in the shift register. The gates of the multiple output transistors connected to the multiple pixel circuit rows are connected to the same node. A shift register in the third gate driving circuit is connected to multiple pixel circuit rows, and the multiple pixel circuit rows are respectively connected to different output transistors in the shift register. The gates of the multiple output transistors connected to the multiple pixel circuit rows are connected to the same node.

14. The display substrate according to claim 10, wherein, The pixel circuit includes: A write sub-circuit, connected to the write control terminal, the data terminal, and the first node, is used to write the data signal from the data terminal to the first node according to the write control signal. A compensation sub-circuit, connected to the compensation control terminal, the reference voltage terminal, and the first node, is used to write the voltage of the reference voltage terminal into the first node according to the compensation control signal. An initialization sub-circuit is connected to the initialization control terminal, the initialization voltage terminal, and the second node. It is used to write the voltage of the initialization voltage terminal into the second node according to the initialization control signal. The second node is also connected to the first electrode of the light-emitting device. The storage capacitor has its first electrode connected to the first node and its second electrode connected to the second node. A driving sub-circuit, connected to the first node, the second node, and the third node, is used to write the signal from the third node into the second node under the potential control of the first node; and The light-emitting sub-circuit, connected to the light-emitting control terminal, the first voltage terminal, and the third node, is used to drive the light-emitting device to emit light in cooperation with the driving sub-circuit according to the light-emitting control signal of the light-emitting control terminal.

15. A display device, comprising: The display substrate as described in any one of claims 1 to 14; as well as A driver chip, connected to the display substrate, is used to provide drive signals to the display substrate.

16. A driving method for a display substrate, used to drive the display substrate as described in any one of claims 1 to 14, the driving method comprising: Between two frame periods, an inter-frame reset control signal is provided to the inter-frame reset control line so that the inter-frame reset control signal is input to the inter-frame reset control terminal via the inter-frame reset control line. The first reset sub-circuit writes the reset signal of the reset signal terminal into the first node to be reset according to the inter-frame reset control signal.

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