Method of improving stress in metal hard mask

Abstract

The application provides a method for improving stress of a metal hard mask, a substrate is provided, a back-end metal interconnection layer structure is formed on the substrate, a barrier layer and a low-K dielectric layer on the barrier layer are formed on the back-end metal interconnection layer structure; a stack is formed on the low-K dielectric layer, the stack is at least composed of a first oxide layer, a metal hard mask layer and a second oxide layer stacked in turn from bottom to top; a first trench is formed on the stack by using photolithography and etching, so that the first oxide layer is exposed; a second trench in communication with the metal interconnection layer structure is formed at the bottom of the first trench by using photolithography and etching. The method reduces the stress of the metal hard mask and improves the line fluctuation or line swing phenomenon caused by stress when the metal hard mask layer is used for patterning the low-K dielectric layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the stress of a metal hard mask. Background Technology

[0002] Hard metal mask layers (such as titanium nitride) are widely used in high aspect ratio etching because they provide good critical dimension and profile control due to their high hardness and excellent etch selectivity. However, the residual stress of TiN can cause deformation of the metal line pattern, resulting in voids in the fill metal of trenches and contact holes.

[0003] As the size continues to shrink to nodes of 14nm and below, the line undulation or line wiggling phenomenon caused by stress during the patterning of low-K dielectric layers by the hard metal mask layer in the back-end metal interconnect layer process becomes increasingly significant.

[0004] To address the aforementioned issues, a novel method for improving the stress of metal hard masks is needed. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the stress of a metal hard mask, which solves the problem of line undulation or line wiggling caused by stress when the metal hard mask layer patterns the low-K dielectric layer in the back-end metal interconnect layer process of the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for improving the stress of a metal hard mask, comprising: Step 1: Provide a substrate on which a back-end metal interconnect layer structure is formed, and a barrier layer and a low-k dielectric layer are formed on the barrier layer. Step 2: Form a stack on the low-k dielectric layer, the stack consisting of at least a first oxide layer, a metal hard mask layer, and a second oxide layer stacked sequentially from bottom to top; Step 3: Form the first trench on the stacked layers using photolithography and etching to expose the first oxide layer; Step 4: Using photolithography and etching, a second trench communicating with the metal interconnect layer structure is formed at the bottom of the first trench.

[0007] Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator substrate.

[0008] Preferably, the back-end metal interconnect layer structure in step one is a back-end copper interconnect layer structure.

[0009] Preferably, the material of the barrier layer in step one is SiCN.

[0010] Preferably, the material of the low-k dielectric layer in step one is SiCOH.

[0011] Preferably, the material of the metal hard mask layer in step two is TiN.

[0012] Preferably, the stack in step two further includes a first and a second buffer layer, and the stack consists of a first oxide layer, a first buffer layer, a metal hard mask layer, a second buffer layer, and a second oxide layer stacked sequentially from bottom to top.

[0013] Preferably, the materials of the first and second buffers in step two are any one of amorphous silicon, TiON, WN, TiSiN, AlO, AlN, and AlON.

[0014] Preferably, in step three, after forming the first trench on the stacked layers using photolithography and etching to expose the first oxide layer, the metal hard mask is further subjected to an annealing process.

[0015] Preferably, the method for annealing the metal hard mask in step three includes: using a low-temperature hydrogen sintering process, with an annealing time of 15 to 60 minutes and an annealing temperature of 250 to 400 degrees Celsius.

[0016] Preferably, the photolithography and etching method in step three includes: sequentially forming an organic underlayer structure layer, an antireflective coating, and a photoresist layer on the second oxide layer; then opening the photoresist layer to expose the antireflective coating underneath; and then etching the exposed antireflective coating and the organic underlayer structure layer and the stacked layers underneath.

[0017] Preferably, before forming the first trench in step three, the method further includes: after forming the first trench on the stacked layers using photolithography and etching to expose the second oxide layer, the method further includes forming a third trench on the metal hard mask using photolithography and etching, wherein the depth of the third trench is less than the thickness of the metal hard mask layer.

[0018] Preferably, the photolithography and etching method in step four includes: forming an organic underlying structure layer covering the stacked layers, then forming an anti-reflective coating and a photoresist layer on the organic underlying structure, then opening the photoresist layer to expose the anti-reflective coating underneath it, and then etching the exposed anti-reflective coating and the bottom of the first trench underneath it.

[0019] As described above, the method for improving the stress of a metal hard mask according to the present invention has the following beneficial effects: The method of the present invention reduces the stress of the metal hard mask and improves the line undulation or line wiggling phenomenon caused by stress when the metal hard mask layer is patterned on the low-K dielectric layer. Attached Figure Description

[0020] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention. Figures 2A to 2F The diagram shows a semiconductor structure schematic of each step in the process flow of Embodiment 1 of the present invention; Figures 3A to 3F The diagram shows a semiconductor structure schematic of each step in the process flow of Embodiment 1 of the present invention; Figures 4A to 4E The diagram shows a semiconductor structure schematic of a portion of the process flow of Embodiment 1 of the present invention. Figure 4F and Figure 4G The first and third groove diagrams of the present invention are shown respectively. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. Example 1

[0022] Please see Figure 1 The present invention provides a method for improving the stress of a metal hard mask, comprising: Step 1: Provide a substrate (not shown in the figure), on which a back-end metal interconnect layer structure 101 is formed, and a barrier layer 102 and a low-k dielectric layer 103 located on the barrier layer 102 are formed on the back-end metal interconnect layer structure 101. In embodiments of the present invention, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0023] In an embodiment of the present invention, the back-end metal interconnect layer structure 101 in step one is a back-end copper interconnect layer structure. The method for forming the metal interconnect layer structure is generally as follows: forming an interlayer dielectric layer covering the semiconductor structure on a substrate, then forming contact holes or trenches on the interlayer dielectric layer, and then forming a metal interconnect layer on the contact holes or trenches.

[0024] In an embodiment of the present invention, the material of the barrier layer 102 in step one is SiCN.

[0025] In an embodiment of the present invention, the material of the low-k dielectric layer 103 in step one is SiCOH.

[0026] Step 2: Form a stack on the low-k dielectric layer 103. The stack consists of at least a first oxide layer 104, a metal hard mask layer 106, and a second oxide layer 108 stacked sequentially from bottom to top. The material of the first and second oxide layers is silicon dioxide.

[0027] In an embodiment of the present invention, the material of the metal hard mask layer 106 in step two is TiN.

[0028] In an embodiment of the present invention, the stack in step two further includes first and second buffer layers. The stack consists of a first oxide layer 104, a first buffer layer 105, a metal hard mask layer 106, a second buffer layer 107, and a second oxide layer 108 stacked sequentially from bottom to top. That is, by adding buffer layers, the degree of stress variation in the metal hard mask layer 106 is reduced.

[0029] In the embodiments of the present invention, the materials of the first and second buffers in step two are any one of amorphous silicon, TiON, WN, TiSiN, AlO, AlN, and AlON. It should be noted that the materials of the first and second buffer layers can also be other materials well known to those skilled in the art, and are not specifically limited here.

[0030] Step 3: The first trench is formed on the stacked layers using photolithography and etching, exposing the first oxide layer 104; In an embodiment of the present invention, the photolithography and etching method in step three includes: sequentially forming an organic underlayer structure layer 109, an anti-reflection coating 110, and a photoresist layer 111 on the second oxide layer 108; then opening the photoresist layer 111 to expose the underlying anti-reflection coating 110, forming a structure as shown below. Figure 2A The structure shown is then etched using a dry etching method, exposing the anti-reflective coating 110 and the underlying organic substructure layer 109, and stacked onto the first oxide layer 104 to form the structure shown. Figure 2B The structure shown.

[0031] Step 4: Using photolithography and etching, a second trench is formed at the bottom of the first trench, which is connected to the metal interconnect layer structure.

[0032] In an embodiment of the present invention, the photolithography and etching method in step four includes: forming an organic underlayer structure 109 covering the stack, then forming an antireflective coating 110 and a photoresist layer 111 on the organic underlayer structure 109, and then opening the photoresist layer 111 to expose the antireflective coating 110 underneath, forming a layer as shown in the figure. Figure 2C The structure shown is followed by dry etching of the exposed antireflective coating 110 and the bottom of the first trench beneath it. Specifically, the bottom of the first trench is first etched down to the low-k dielectric layer 103 to form a structure as shown. Figure 2D The structure shown is then processed by removing the remaining anti-reflective coating 110, photoresist layer 111, and organic underlayer structure layer 109 to form a structure as shown. Figure 2E The structure shown is then etched to remove the first oxide layer 104 and form a second trench as shown in 2F that communicates with the metal interconnect layer structure. Example 2

[0033] Please see Figure 1 The present invention provides a method for improving the stress of a metal hard mask, comprising: Step 1: Provide a substrate, on which a back-end metal interconnect layer structure 101 is formed, and a barrier layer 102 and a low-k dielectric layer 103 located on the barrier layer 102 are formed on the back-end metal interconnect layer structure 101. In embodiments of the present invention, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0034] In an embodiment of the present invention, the back-end metal interconnect layer structure 101 in step one is a back-end copper interconnect layer structure. The method for forming the metal interconnect layer structure is generally as follows: forming an interlayer dielectric layer covering the semiconductor structure on a substrate, then forming contact holes or trenches on the interlayer dielectric layer, and then forming a metal interconnect layer on the contact holes or trenches.

[0035] In an embodiment of the present invention, the material of the barrier layer 102 in step one is SiCN.

[0036] In an embodiment of the present invention, the material of the low-k dielectric layer 103 in step one is SiCOH.

[0037] Step 2: A stack is formed on the low-k dielectric layer 103. The stack consists of a first oxide layer 104, a metal hard mask layer 106, and a second oxide layer 108 stacked sequentially from bottom to top. The material of the first oxide layer is silicon dioxide.

[0038] In an embodiment of the present invention, the material of the metal hard mask layer 106 in step two is TiN.

[0039] Step 3: The first trench is formed on the stacked layers using photolithography and etching, exposing the first oxide layer 104; In an embodiment of the present invention, the photolithography and etching method in step three includes: sequentially forming an organic underlayer structure layer 109, an anti-reflection coating 110, and a photoresist layer 111 on the second oxide layer 108; then opening the photoresist layer 111 to expose the underlying anti-reflection coating 110, forming a structure as shown below. Figure 3A The structure shown is then etched using a dry etching method, exposing the anti-reflective coating 110 and the underlying organic substructure layer 109, and stacked onto the first oxide layer 104 to form the structure shown. Figure 3B The structure shown.

[0040] In an embodiment of the present invention, after forming the first trench on the stacked layers using photolithography and etching to expose the first oxide layer 104 in step three, an annealing process is also included for the metal hard mask. That is, annealing is performed after etching the metal hard mask to relieve some of the stress in the metal hard mask layer 106.

[0041] In an embodiment of the present invention, the method for annealing the metal hard mask in step three includes: using a low-temperature hydrogen sintering process (H2 Sinter), with an annealing time of 15 to 60 minutes and an annealing temperature of 250 to 400 degrees Celsius.

[0042] Step 4: Using photolithography and etching, a second trench is formed at the bottom of the first trench, which is connected to the metal interconnect layer structure.

[0043] In an embodiment of the present invention, the photolithography and etching method in step four includes: forming an organic underlayer structure 109 covering the stack, then forming an antireflective coating 110 and a photoresist layer 111 on the organic underlayer structure 109, and then opening the photoresist layer 111 to expose the antireflective coating 110 underneath, forming a layer as shown in the figure. Figure 3C The structure shown is followed by dry etching of the exposed antireflective coating 110 and the bottom of the first trench beneath it. Specifically, the bottom of the first trench is first etched down to the low-k dielectric layer 103 to form a structure as shown. Figure 3D The structure shown is then processed by removing the remaining anti-reflective coating 110, photoresist layer 111, and organic underlayer structure layer 109 to form a structure as shown. Figure 3E The structure shown is then etched to remove the first oxide layer 104 and form a second trench as shown in 3F that communicates with the metal interconnect layer structure. Example 3

[0044] Please see Figure 1 The present invention provides a method for improving the stress of a metal hard mask, comprising: Step 1: Provide a substrate, on which a back-end metal interconnect layer structure 101 is formed, and a barrier layer 102 and a low-k dielectric layer 103 located on the barrier layer 102 are formed on the back-end metal interconnect layer structure 101. In embodiments of the present invention, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0045] In an embodiment of the present invention, the back-end metal interconnect layer structure 101 in step one is a back-end copper interconnect layer structure. The method for forming the metal interconnect layer structure is generally as follows: forming an interlayer dielectric layer covering the semiconductor structure on a substrate, then forming contact holes or trenches on the interlayer dielectric layer, and then forming a metal interconnect layer on the contact holes or trenches.

[0046] In an embodiment of the present invention, the material of the barrier layer 102 in step one is SiCN.

[0047] In an embodiment of the present invention, the material of the low-k dielectric layer 103 in step one is SiCOH.

[0048] Step 2: A stack is formed on the low-k dielectric layer 103. The stack consists of a first oxide layer 104, a metal hard mask layer 106, and a second oxide layer 108 stacked sequentially from bottom to top. The material of the first oxide layer is silicon dioxide.

[0049] In an embodiment of the present invention, the material of the metal hard mask layer 106 in step two is TiN.

[0050] In an embodiment of the present invention, before forming the first trench in step three, the method further includes: sequentially forming an organic underlayer structure layer 109, an anti-reflective coating 110, and a photoresist layer 111 on the second oxide layer 108; then opening the photoresist layer 111 to expose the underlying anti-reflective coating 110, forming a structure as shown below. Figure 4A The structure shown includes, after forming a first trench on the stacked layers using photolithography and etching to expose the second oxide layer 108, forming a third trench on a metal hard mask using photolithography and etching. The depth of the third trench is less than the thickness of the metal hard mask layer 106, forming a structure as shown in the diagram. Figure 4B The structure shown is such that the stress on the metal hard mask layer 106 is reduced by forming multiple third trenches on the metal hard mask layer 106.

[0051] For example, the contact hole pattern 201 to be etched on the stack is as follows: Figure 4F As shown, the third trench pattern 202 on the metal hard mask layer 106 is as follows: Figure 4G As shown, the third trench pattern 202 and the contact hole pattern 201 can be transferred sequentially onto the substrate using a mask. It should be noted that the distribution of the third trench pattern 202 can also be any other than perpendicular to the third trench pattern 202; no specific limitation is made here.

[0052] Step 3: The first trench is formed on the stacked layers using photolithography and etching, exposing the first oxide layer 104; In an embodiment of the present invention, the photolithography and etching method in step three includes: sequentially forming an organic underlayer structure layer 109, an anti-reflection coating 110, and a photoresist layer 111 on a stack, and then opening the photoresist layer 111 to expose the underlying anti-reflection coating 110, forming a structure as shown below. Figure 4C The structure shown is similar to Figure 4C The cross-sectional structure diagram perpendicular to the shown cross-section is as follows Figure 4D As shown, the exposed anti-reflective coating 110 and the underlying organic substructure layer 109 are then etched using a dry etching method and stacked onto the first oxide layer 104 to form a layer as shown. Figure 4E The structure shown.

[0053] Step 4: Using photolithography and etching, a second trench is formed at the bottom of the first trench, which is connected to the metal interconnect layer structure.

[0054] In an embodiment of the present invention, the photolithography and etching method in step four includes: forming an organic underlayer structure layer 109 overlay, then forming an antireflective coating 110 and a photoresist layer 111 on the organic underlayer structure layer 109, then opening the photoresist layer 111 to expose the antireflective coating 110 underneath, and then etching the exposed antireflective coating 110 and the bottom of the first trench below it using a dry etching method. Specifically, firstly, the bottom of the first trench is etched down to the low-k dielectric layer 103, then the remaining antireflective coating 110, photoresist layer 111, and organic underlayer structure layer 109 are removed, and then the first oxide layer 104 is removed by etching, and a second trench communicating with the metal interconnect layer structure as shown in 4F is formed.

[0055] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0056] In summary, the method of this invention reduces the stress of the hard metal mask and improves the line undulation or line wiggling phenomena caused by stress when the hard metal mask layer patterns a low-K dielectric layer. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0057] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the stress of a metal hard mask, characterized in that, At least including: Step 1: Provide a substrate on which a back-end metal interconnect layer structure is formed, and a barrier layer and a low-k dielectric layer are formed on the barrier layer. Step 2: Form a stack on the low-k dielectric layer, the stack consisting of at least a first oxide layer, a metal hard mask layer, and a second oxide layer stacked sequentially from bottom to top; Step 3: An organic underlayer structure layer, an anti-reflective coating, and a photoresist layer are sequentially formed on the second oxide layer. Then, the photoresist layer is opened to expose the anti-reflective coating underneath it. The exposed anti-reflective coating and the organic underlayer structure layer and the stacked layer are then etched to form a first trench on the stacked layer, thereby exposing the first oxide layer. Step 4: Form an organic underlayer structure layer covering the stacked layers, then form an anti-reflective coating and a photoresist layer on the organic underlayer structure, then open the photoresist layer to expose the anti-reflective coating underneath, then etch the exposed anti-reflective coating and the bottom of the first trench below it to form a second trench communicating with the metal interconnect layer structure.

2. The method for improving the stress of a metal hard mask according to claim 1, characterized in that: The substrate in step one includes a bulk semiconductor substrate or a silicon-on-insulator substrate.

3. The method for improving the stress of a metal hard mask according to claim 1, characterized in that: The back-end metal interconnect layer structure mentioned in step one is a back-end copper interconnect layer structure.

4. The method for improving the stress of a metal hard mask according to claim 1, characterized in that: The material of the barrier layer in step one is SiCN.

5. The method for improving the stress of a metal hard mask according to claim 1, characterized in that: The material of the low-k dielectric layer in step one is SiCOH.

6. The method for improving the stress of a metal hard mask according to claim 1, characterized in that: The material of the metal hard mask layer in step two is TiN.

7. The method for improving the stress of a metal hard mask according to claim 1, characterized in that: The stack in step two also includes a first and a second buffer layer. The stack consists of a first oxide layer, a first buffer layer, a metal hard mask layer, a second buffer layer, and a second oxide layer stacked sequentially from bottom to top.

8. The method for improving the stress of a metal hard mask according to claim 7, characterized in that: The materials of the first and second buffer layers in step two are any one of amorphous silicon, TiON, WN, TiSiN, AlO, AlN, and AlON.

9. The method for improving the stress of a metal hard mask according to claim 1, characterized in that: Step three, after forming the first trench on the stacked layers using photolithography and etching to expose the first oxide layer, also includes an annealing process for the metal hard mask.

10. The method for improving the stress of a metal hard mask according to claim 9, characterized in that: The method for annealing the metal hard mask in step three includes: using a low-temperature hydrogen sintering process, with an annealing time of 15 to 60 minutes and an annealing temperature of 250 to 400 degrees Celsius.

11. The method for improving the stress of a metal hard mask according to claim 1, characterized in that: Before forming the first trench in step three, the method further includes: after forming the first trench on the stacked layer by photolithography and etching to expose the second oxide layer, the method further includes forming a third trench on the metal hard mask by photolithography and etching, wherein the depth of the third trench is less than the thickness of the metal hard mask layer.

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