Bottom exit non-hermetic package SiP module

Abstract

This invention provides a bottom-lead non-hermetic SiP module, comprising: a package base including pins and a base plate, with one end of the pins fixed to the upper surface of the base plate and the other end extending from the lower surface of the base plate; an adapter board including a wiring layer, a substrate layer, and a first electrical interconnect structure, the substrate layer being bonded to the surface of the package base, the wiring layer being fabricated on the upper surface of the substrate layer, and the wiring layer and pins being interconnected through the first electrical interconnect structure; a chip stack including bare chips, an adhesive layer, and a second interconnect structure, the bottom bare chip being formed on the upper surface of the adapter board through the adhesive layer, the second layer of bare chips and higher layers of bare chips being formed on the upper surface of the next layer of bare chips through the adhesive layer, and the bare chips being interconnected with each other and with the wiring layer through the second electrical interconnect structure; and a molding compound encapsulating the upper half of the pins, the adapter board, and the chip stack, and forming an integral part with the base plate. This invention can improve the reliability between the SiP module and the circuit board.

Description

Technical Field

[0001] This invention relates to the field of system-in-package and advanced packaging technology, specifically to a bottom-lead-out non-hermetic SiP module. Background Technology

[0002] With the rapid development of electronic products towards miniaturization and integration, System-in-Package (SiP) technology has become one of the important directions for the future development of the microelectronics industry. SiP technology utilizes various advanced packaging techniques to achieve high-density integrated processing of multiple heterogeneous bare chips or devices within a single package. Therefore, SiP module products not only have advantages such as miniaturization, multifunctionality, and high reliability, but also reduce the design complexity of backend processes, shorten product development cycles, and lower supply chain management costs.

[0003] Currently, SiP module products are primarily evaluated for quality using device-grade standards, and their interface types are consistent with or compatible with those of conventionally packaged devices. A large portion of the electrical interconnections in SiP modules are already completed within the package; interactions with external functions are subsystem-to-subsystem interactions. Therefore, SiP modules typically require only tens to hundreds of I / O interfaces, with I / O interface spacing generally ranging from sub-millimeter to millimeter. Based on these I / O interface quantity and size characteristics, SiP modules are typically available in two package types: pinned packages, typified by SOP (Surface Mount Technology), and pinless packages, typified by BGA (Browser Grid Interface). In harsh environments such as aerospace and weaponry, SiP modules must withstand not only severe mechanical shocks but also thermal stress from extreme temperature changes. In such harsh application environments, SiP products protected by patents such as CN202011323589, CN202110140717, CN201810154887, and CN201420433174, which employ BGA and QFN packaging interfaces, face serious electrical interconnect reliability issues. However, SiP products with pins can significantly improve the overall system reliability because the metal pins between the device package and the PCB board can buffer stress.

[0004] If a SiP module uses a conventional leaded package structure such as SOP or QFP, the lead-out terminals are on the side of the device, and the area where the lead contacts the PCB pads is typically only 0.5mm to 1mm long, far from meeting the requirements of high-reliability applications. Increasing the soldering length between the lead and the PCB pads would significantly increase the overall area of ​​the SiP module, making true miniaturization impossible. Therefore, extending the lead-out terminals from the bottom of the module allows for a several-fold increase in the soldering length between the lead and the PCB pads without increasing the SiP module area, thus achieving a truly reliable mechanical connection between the SiP module and the PCB pads.

[0005] Currently, French company 3D plus and Zhuhai Orbita are stacking multiple SOP packaged devices with a bottom-leaded pin frame and encapsulating them in a single unit. They then interconnect the components using thin-film metal wiring on the sides of the encapsulation, ultimately obtaining a bottom-leaded, non-hermetic SiP module based on PoP packaging technology, which has already been applied in aerospace products. However, because PoP packaging technology involves stacking components, the thickness of the PoP packaged SiP module is very large, generally equal to 1 to 1.5 times the sum of the thicknesses of all components. This results in a relatively large SiP module mass, which can exert significant impact on the bottom leads in vibration environments. This can cause cracks in the pin soldering, leading to abnormal electrical interconnections, or even the entire SiP module detaching from the PCB module, causing the entire system to malfunction. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a bottom-lead-out non-hermetic SiP module that can stack multiple bare chips internally. It also employs an adapter board with a high-density wiring layer to resolve the contradiction between the complex electrical interconnection requirements of stacked bare chips and the simple interconnection capability of the pin frame. Furthermore, it can further reduce the overall size and weight, and significantly improve the interconnection reliability between the SiP module and the stand-alone PCB motherboard.

[0007] The bottom-lead-out non-hermetic SiP module provided by the present invention includes: a packaging base, an adapter board, a chip stack, and a potting compound;

[0008] The packaging base includes pins and a base plate. The pins pass through a through slot or through hole in the base plate, with one end fixed to the upper surface of the base plate and the other end leading out from the lower surface of the base plate.

[0009] The adapter board includes a wiring layer, a substrate layer, and a first electrical interconnect structure. The substrate layer is bonded to the surface of the package base. The wiring layer is fabricated on the upper surface of the substrate layer. The wiring layer and the pins are electrically interconnected through the first electrical interconnect structure.

[0010] A chip stack includes multiple bare chips, an adhesive layer, and a second electrical interconnect structure. The bare chips at the bottom layer are formed on the surface of an adapter board through the adhesive layer. The second layer of bare chips and the higher-layer bare chips are all formed on the surface of the next layer of bare chips through the adhesive layer. The bare chips are electrically interconnected with each other and with the wiring layer through the second electrical interconnect structure.

[0011] The molding compound encapsulates the upper half of the pins, the adapter plate, and the chip stack within itself, and is integrated with the base plate.

[0012] Preferably, the pin material is at least one of copper alloy and iron-nickel alloy.

[0013] Preferably, the substrate is at least one of the following: chip carrier board, PCB board, ceramic substrate, co-fired ceramic substrate, glass substrate and quartz substrate.

[0014] Preferably, the wiring layer adopts any one of PI / Cu thin film wiring, BCB / Cu wiring and SiO2 / Cu wiring.

[0015] Preferably, the substrate of the adapter plate is made of any one of silicon, glass, quartz and organic substrate.

[0016] Preferably, the first electrical interconnect structure employs either wire bonding or solder interconnect.

[0017] Preferably, the bare chip type of the chip stack is any one of digital chips, analog chips, radio frequency chips, hybrid integrated bare chips, and MEMS chips.

[0018] Preferably, the stacking structure of the chip stack is a staggered stack, a pyramidal stack, or a stepped stack;

[0019] The bonding method between bare chips within the chip stack is either die-attach film or epoxy film.

[0020] Preferably, the second electrical interconnect structure is either wire bonding or solder interconnect.

[0021] Preferably, the potting compound is made of any one of epoxy resin, silicone, and polyurethane.

[0022] The surface of the potting compound is covered with a grounded metal film layer, and the metal film layer structure adopts any one of Ni / Au alloy, Ni / Pb / Au alloy, Cr / Au alloy and Ti / Au alloy.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. This invention selects an adapter board as an intermediate transition layer between the stack and the pins. The high-density thin-film interconnect layer of the adapter board can integrate the large number of electrical interconnect requirements of the stack and form a simple interface for electrical interconnection with the pins, thereby solving the contradiction between the complex electrical interconnect requirements of the stack and the simple wiring capability of the pins, and realizing a smaller package size.

[0025] 2. In this invention, all electrical interconnections are contained within the potting compound, and there are no metal wirings on the surface of the potting compound. Therefore, problems such as open circuits caused by impacts to metal wiring and short circuits caused by solder accidentally splashing onto the wiring area during module assembly can be avoided.

[0026] 3. In this invention, if there are chips or functional circuits within the SiP module that require electromagnetic compatibility (EMC) treatment, a grounded metal film layer can be easily prepared on the surface of the potting compound, without the need for secondary potting as required for side-interconnected SiP modules before the surface metal shielding layer can be prepared. Therefore, the bottom-pin non-hermetic SiP module provided by this invention has a smaller size, higher integration density, lower cost, and better electrical assembly. Attached Figure Description

[0027] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0028] Figure 1 This is a schematic diagram of the structure of the bottom lead-out non-hermetic SiP module in the first embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of a non-hermetically sealed SiP module with a surface metal shielding film layer at the bottom lead-out end in the second embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the packaging base structure in the third embodiment of the present invention, in which the pins are directly attached to the base plate;

[0031] Figure 4 This is a schematic diagram of the adapter board structure using solder as a low-density electrical interconnect structure in the fourth embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of a chip stack structure using solder balls as a high-density electrical interconnect structure in the fifth embodiment of the present invention.

[0033] In the diagram: 1 is the packaging base, 2 is the adapter board, 3 is the chip stack, 4 is the potting compound, 11 is the pin, 12 is the base plate, 21 is the substrate, 22 is the high-density wiring layer, 23 is the low-density electrical interconnect structure, 31 is the bare chip, 32 is the adhesive layer, 33 is the high-density electrical interconnect structure, and 4 is the potting compound. Detailed Implementation

[0034] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0035] Example 1

[0036] Figure 1 This is a schematic diagram of the structure of a non-hermetically sealed SiP module with a bottom lead-out end in an embodiment of the present invention, as shown below. Figure 1 As shown, the bottom lead-out non-hermetic SiP module provided by the present invention includes: a packaging base 1, an adapter board 2, a chip stack 3, and a potting body 4.

[0037] The packaging base 1 includes pins 11 and a base plate 12;

[0038] The base plate 12 has through slots or through holes on both sides or around the perimeter. The pins 11 pass through the slots or holes of the base plate 12 to form the inner pins of the upper part and the outer pins of the lower part. The inner pins are fixed to the upper surface of the base plate 12.

[0039] The adapter board 2 includes a high-density wiring layer 21, a substrate layer 22, and a low-density electrical interconnect structure 23.

[0040] The substrate layer 22 is formed on the surface of the package base 1, the high-density wiring layer 21 is formed on the surface of the substrate layer 22, and the low-density electrical interconnect structure 23 is formed between the high-density wiring layer 21 and the upper surface of the pin 11 by wire bonding.

[0041] The chip stack 3 includes multiple stacked bare chips 31, an adhesive layer 32, and a high-density electrical interconnect structure 33;

[0042] The bare chips 31 are stacked on the upper surface of the adapter board 2. The adhesive layer 32 is located between the bare chips 31 and between the bare chips 31 and the high-density wiring layer 21, and plays a bonding role. The high-density electrical interconnect structure 33 is formed between the bare chips 31 and between the bare chips 31 and the high-density wiring layer 21 by wire bonding, and forms an electrical interconnect function.

[0043] The potting compound 4 encapsulates the upper half of the pin 11, the adapter plate 2, and the chip stack 3 inside it, and forms an integral part with the base plate 12.

[0044] In this embodiment of the invention, preferably, the material of pin 11 is including but not limited to copper alloy and iron-nickel alloy.

[0045] Preferably, the substrate 12 is, but is not limited to, a chip carrier board, a PCB board, a ceramic substrate, a co-fired ceramic substrate, a glass substrate, and a quartz substrate.

[0046] Preferably, the density wiring layer 21 employs, but is not limited to, PI / Cu thin film wiring, BCB / Cu wiring, and SiO2 / Cu wiring.

[0047] Preferably, the substrate 22 is, but is not limited to, silicon, glass, quartz and organic substrate.

[0048] Preferably, the 31 types of bare chips include, but are not limited to, digital chips, analog chips, radio frequency chips, hybrid integrated bare chips, and MEMS chips.

[0049] Preferably, the stacking structure of the multiple bare chips 31 includes, but is not limited to, staggered stacking, pyramidal stacking, and stepped stacking.

[0050] Preferably, the adhesive layer 32 is made of, but not limited to, adhesive film and epoxy resin.

[0051] Preferably, the potting compound 4 is made of materials including but not limited to epoxy resin, silicone and polyurethane.

[0052] In the bottom-lead-out non-hermetic SiP module provided in this embodiment of the invention, the preferred packaging structure in which the pin 11 is led out from the bottom 1 of the packaging base can greatly improve the connection reliability between the SiP module and the PCB motherboard. At the same time, the adapter board 2 is used as a transition between the chip stack 3 and the pin 11. The electrical interconnection between the bare chips 31 inside the chip stack 3 is completed in the high-density wiring layer 21 of the adapter board 2. The electrical interconnection requirements between multiple stacked bare chips 31 and the outside of the module are also achieved through the optimized rewiring of the high-density wiring layer 21 and then through the low-density electrical interconnection structure 23 and the pin 11.

[0053] Therefore, in this embodiment of the invention, an adapter board 2 is set inside the SiP module as a transition between multiple stacked bare chips 31 and pins 11, which creatively solves the problem that the lead frame package structure with simple wiring capability cannot meet the high number of electrical interconnection requirements of the SiP module.

[0054] Furthermore, by controlling the thickness of the bare chip 31, not only can the SiP module be made thinner and lighter, but the thermal stress caused by the CTE mismatch of various heterogeneous materials inside the potting compound 4 can also be reduced, greatly improving the reliability of SiP module products.

[0055] Example 2

[0056] Figure 2 This is a schematic diagram of a non-hermetic SiP module with a surface metal shielding film layer at the bottom lead-out end, as shown in the second embodiment of the present invention. Figure 2 As shown, the surface of the potting body 4 can be covered with a grounded metal film layer 5, which serves as an electromagnetic shielding function and improves the electromagnetic interference resistance of the SiP module. The structure of the metal film layer includes, but is not limited to, Ni / Au, Ni / Pb / Au, Cr / Au and Ti / Au.

[0057] Example 3

[0058] Figure 3 This is a schematic diagram of the package base structure in the third embodiment of the present invention, in which the pins are directly attached to the base plate. Figure 3 As shown, pin 11 is electrically interconnected with metal via 13 in base plate 12 through bonding structure 14, and metal via 13 is electrically interconnected with high-density wiring layer 21. Bonding structure 14 is solder or conductive epoxy.

[0059] Example 4

[0060] Figure 4 This is a schematic diagram of an adapter board structure using solder as a low-density electrical interconnect structure in the fourth embodiment of the present invention, as shown below. Figure 4 As shown, the low-density electrical interconnect structure 23 of the adapter board 2 is in the form of metal vias and solder balls.

[0061] Example 5

[0062] Figure 5 This is a schematic diagram of a chip stack structure using solder balls as a high-density electrical interconnect structure in the fifth embodiment of the present invention, as shown below. Figure 5 As shown, the internal structure of the multiple bare chips 31 and the high-density electrical interconnection structure 33 between the bare chips 31 and the adapter board 2 are in the form of solder balls.

[0063] In this embodiment of the invention, the bottom lead-out non-hermetic SiP module provided by the present invention can be used in various types of stand-alone, secondary packaged devices or modules.

[0064] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A bottom-lead-out non-hermetic SiP module, characterized in that, include: Packaging base, adapter board, chip stack and potting compound; The packaging base includes pins and a base plate. The pins pass through a through slot or through hole in the base plate, with one end fixed to the upper surface of the base plate and the other end leading out from the lower surface of the base plate. The adapter board includes a wiring layer, a substrate layer, and a first electrical interconnect structure. The substrate layer is bonded to the surface of the package base. The wiring layer is fabricated on the upper surface of the substrate layer. The wiring layer and the pins are electrically interconnected through the first electrical interconnect structure. A chip stack includes multiple bare chips, an adhesive layer, and a second electrical interconnect structure. The bare chips at the bottom layer are formed on the surface of an adapter board through the adhesive layer. The second layer of bare chips and the higher-layer bare chips are all formed on the surface of the next layer of bare chips through the adhesive layer. The bare chips are electrically interconnected with each other and with the wiring layer through the second electrical interconnect structure. A molding compound encapsulates the upper half of the pins, the adapter plate, and the chip stack within itself, and is integrally formed with the base plate; The surface of the potting compound is covered with a grounded metal film layer, and the metal film layer structure adopts any one of Ni / Au alloy, Ni / Pb / Au alloy, Cr / Au alloy and Ti / Au alloy.

2. The bottom-lead-out non-hermetic SiP module according to claim 1, characterized in that, The pins are made of at least one of copper alloy and iron-nickel alloy.

3. The bottom-lead-out non-hermetic SiP module according to claim 1, characterized in that, The base plate is at least one of the following: chip carrier board, PCB board, ceramic substrate, co-fired ceramic substrate, glass substrate and quartz substrate.

4. The bottom-lead-out non-hermetic SiP module according to claim 1, characterized in that, The wiring layer adopts any one of PI / Cu thin film wiring, BCB / Cu wiring and SiO2 / Cu wiring.

5. The bottom-lead-out non-hermetic SiP module according to claim 1, characterized in that, The substrate of the adapter plate is made of any one of silicon, glass, quartz and organic substrate.

6. The bottom-lead-out non-hermetic SiP module according to claim 1, characterized in that, The first electrical interconnect structure employs either wire bonding or solder interconnect.

7. The bottom-lead-out non-hermetic SiP module according to claim 1, characterized in that, The bare chip type of the chip stack can be any one of digital chips, analog chips, radio frequency chips, hybrid integrated bare chips, and MEMS chips.

8. The bottom-lead-out non-hermetic SiP module according to claim 1, characterized in that, The stacking structure of the chip stack can be staggered stacking, pyramidal stacking, or stepped stacking.

9. The bonding method between bare chips within the chip stack according to claim 8 is either a die-attach film or an epoxy die-attachment.

10. The bottom-lead-out non-hermetic SiP module according to claim 1, characterized in that, The second electrical interconnect structure can be either wire bonding or solder interconnect.

11. The bottom-lead-out non-hermetic SiP module according to claim 1, characterized in that, The potting compound is made of any one of epoxy resin, silicone, and polyurethane.

Images