Display backplane and display device

Abstract

The application provides a display backboard and a display device, and relates to the technical field of display. The display backboard comprises a plurality of pixel circuits arranged at intervals, a light transmission area between the pixel circuits, a plurality of first connecting lines extending along a first direction, and two adjacent pixel circuits connected by the first connecting lines. The pixel circuit comprises a first gate line, a first channel line and a second gate line arranged in sequence. The first channel line extends along the first direction as a whole. The first gate line and the second gate line extend along a second direction as a whole. The first gate line, the first channel line and the second gate line form a first transistor at an overlapping position. The second direction intersects the first direction. The first gate line and the second gate line are connected by a first lap joint line. The first lap joint line is connected to the first connecting line by a via hole.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display backplane and a display device. Background Technology

[0002] To reduce the number of holes in the display panel and make electronic devices more aesthetically pleasing, some electronic devices place their optical sensors below the display panel, capturing light through the gap between adjacent sub-pixels within the display panel. Therefore, it is necessary to compress the projected area of ​​the pixel circuitry in the sub-pixels, thereby reducing light obstruction. Summary of the Invention

[0003] Embodiments of this application provide a display back panel and a display device, wherein the light occlusion between two adjacent sub-pixels is minimal.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] On one hand, embodiments of this application provide a display back panel, including a plurality of pixel circuits arranged at intervals, a light-transmitting area located between the pixel circuits, and a plurality of first connecting lines extending along a first direction, wherein the first connecting lines connect two adjacent pixel circuits;

[0006] The pixel circuit includes a first gate line, a first channel line, and a second gate line stacked sequentially. The first channel line extends entirely along the first direction, and the first gate line and the second gate line extend entirely along the second direction. The first gate line, the first channel line, and the second gate line form a first transistor at their overlap. The second direction intersects the first direction.

[0007] The first gate line and the second gate line are connected by a first bonding wire, and the first bonding wire is connected to the first connecting line through a via.

[0008] In some embodiments, the pixel circuit further includes an initialization signal line and a seventh transistor, both of which are connected to the initialization signal line.

[0009] In some embodiments, the seventh transistor includes a seventh channel line, the first channel line including opposing first and second ends, the first end of the seventh channel line being disposed adjacent to the second end of the first channel line;

[0010] The initialization signal line connects the first end of the first channel line and the first end of the seventh channel line, and the initialization signal line extends along the routing path of the first channel line.

[0011] In some embodiments, the pixel circuit further includes a fourth channel line and a third gate line stacked together, wherein the third gate line and the fourth channel line form a fourth transistor at their overlap, and the third gate line forms the gate of the fourth transistor and the seventh transistor.

[0012] In some embodiments, the third gate line has a first lap pad at its end, and the third gate line is connected to at least one of the first connection lines through the first lap pad.

[0013] In some embodiments, the pixel circuit further includes a fifth gate line; in a projection perpendicular to the light-emitting surface, the fifth gate line is located between the first channel line and the third gate line, and the end of the fifth gate line is provided with a second overlap plate;

[0014] The third gate line is bent away from the position opposite to the second lap pad in the direction away from the fifth gate line.

[0015] In some embodiments, the pixel circuit further includes a fourth gate line, a second channel line, and a fifth gate line stacked sequentially, wherein the fourth gate line, the second channel line, and the fifth gate line form a second transistor at their overlap.

[0016] One end of the fourth gate line and one end of the fifth gate line are connected by a second connection wire, and the second connection wire is connected to a first connection line through a via; the other end of the fourth gate line or the other end of the fifth gate line is connected to the first connection line through a via.

[0017] In some implementations, the first connection line is located on a layer away from the fourth gate line of the fifth gate line, and the two ends of the fifth gate line are connected to the first connection line through vias.

[0018] In some embodiments, the pixel circuit further includes a third channel line and a first electrode plate, a second electrode plate, and a third bonding wire stacked sequentially.

[0019] The third channel line and the first electrode plate form a third transistor at their overlap.

[0020] The second electrode plate has a notched structure. One end of the third connecting wire passes through the notched structure and connects to the first electrode plate. The other end of the third connecting wire connects to the first channel line and the second channel line.

[0021] In some embodiments, the pixel circuit further includes a fifth channel line, a sixth channel line, and a sixth gate line, wherein the sixth gate line and the fifth channel line form a fifth transistor at their overlap, and the sixth gate line and the sixth channel line form a sixth transistor at their overlap, and the sixth transistor is connected to the first electrode of the light-emitting device.

[0022] The sixth gate line is connected to at least one of the first connection lines via a via.

[0023] In some embodiments, in a projection perpendicular to the light-emitting surface along the second direction, the seventh transistor is located between the sixth transistor and the first transistor.

[0024] In some embodiments, the pixel circuit further includes data signal lines and voltage signal lines;

[0025] One end of the fifth channel line and the second electrode plate are connected by a fourth bonding wire, and the voltage signal line is connected to the fourth bonding wire through a via.

[0026] The data signal line is connected to one end of the fourth channel line, and the other end of the fourth channel line is connected to the other end of the fifth channel line.

[0027] In some embodiments, the system further includes multiple second connection lines extending along the second direction, at least one of which connects to the data signal lines in two adjacent pixel circuits, and at least one of which connects to the voltage signal lines in two adjacent pixel circuits.

[0028] In some implementations, the first connecting line and / or the second connecting line are transparent connecting lines.

[0029] On the other hand, this application provides a display device, including:

[0030] The aforementioned display back panel; and

[0031] A light-emitting device is disposed on one side of the display back panel and connected to a pixel circuit, which is used to drive the light-emitting device to emit light.

[0032] The display backplane and display device provided in this application embodiment have a first gate line and a second gate line extending along a second direction, making the dimensions of the first gate line and the second gate line smaller along a first direction. This results in a smaller dimension of the first lap joint used to connect the first gate line and the second gate line along the first direction, reducing the number of lap joints required to connect the first lap joint and the first connecting line. Reducing the number of lap joints shrinks the projected area of ​​the pixel circuit, thereby increasing the light-transmitting area between the pixel circuits. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A schematic diagram of a pixel circuit layout provided in an embodiment of this application;

[0035] Figure 2 A circuit schematic diagram of a pixel circuit provided in an embodiment of this application;

[0036] Figure 3 for Figure 2 The signal timing diagram of the pixel circuit shown is shown.

[0037] Figure 4 This is a circuit layout design for a pixel circuit in an embodiment of this application;

[0038] Figures 5 to 34 It shows Figure 4 The diagram shows the schematic diagrams of each film layer of the pixel circuit and a partial diagram of the film layer stacking structure.

[0039] Figure label:

[0040] 100 - First connecting line; 200 - Second connecting line;

[0041] 3-Third channel line; 4-Fourth channel line; 5-Fifth channel line; 6-Sixth channel line; 7-Seventh channel line;

[0042] 11-Third gate line; 12-First electrode plate; 13-Sixth gate line; 14-First lap plate;

[0043] 21-First gate line; 22-Fourth gate line; 23-Second electrode; 24-Cut corner structure;

[0044] 31 - First trench line; 32 - Second trench line;

[0045] 41 - Second gate line; 42 - Fifth gate line; 43 - Second lap plate;

[0046] 51 - First connection wire; 52 - Second connection wire; 53 - Third connection wire; 54 - Fourth connection wire; 55 - Fifth connection wire; 56 - Initialization signal wire;

[0047] 61-First lap joint; 62-Second lap joint; 63-Third lap joint; 64-Fourth lap joint; 65-Fifth lap joint; 66-Sixth lap joint; 67-Seventh lap joint; 68-Eighth lap joint; 69-Ninth lap joint; 70-Tenth lap joint; 71-Eleventh lap joint; 72-Twelfth lap joint;

[0048] 81 - Data signal connection cable; 82 - Lower section; 83 - Upper section; 84 - Connection structure;

[0049] 91 - SD2 line; 92 - Anode adapter structure; 93 - Anode. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0051] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0052] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0053] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0054] This application provides a display device, which can be a mobile phone, laptop computer, ultra-large mobile personal computer (UMPC), netbook, personal digital assistant (PDA), wearable device, virtual reality device, or other mobile computing device with a panel. This application does not limit the scope of the application to this type of device. For ease of description, this application uses a mobile phone as an example.

[0055] The display device may include a housing and a display panel, with the display panel disposed on the housing so that the display panel and the housing together form a cavity, in which components such as batteries and motherboards may be installed.

[0056] The display panel can be an OLED display panel, which includes a display backplane and light-emitting devices disposed on one side of the display backplane. The display backplane has pixel circuits connected to the light-emitting devices, enabling the pixel circuits to drive the light-emitting devices to emit light. The display backplane can have multiple pixel circuits arranged at intervals, and also multiple light-emitting devices. Each light-emitting device corresponds to and is electrically connected to a pixel circuit; one light-emitting device and one pixel circuit form one pixel.

[0057] For example, the display panel includes a plurality of pixels arranged in a rectangular array, forming a plurality of pixel rows and a plurality of pixel columns. A pixel row includes a plurality of pixels spaced apart along a first direction, and a pixel column includes a plurality of pixels spaced apart along a second direction. The first and second directions intersect and are both parallel to the display back panel. Correspondingly, the display back panel includes a plurality of pixel circuits arranged in a rectangular array, forming a plurality of pixel circuit rows and a plurality of pixel circuit columns; light-emitting devices are also arranged in a rectangular array, forming a plurality of light-emitting device rows and a plurality of light-emitting device columns.

[0058] Optical devices such as cameras and fingerprint recognition devices can also be installed in the cavity located below the display panel. These optical devices can be located below the display area of ​​the display panel. The display area contains pixel circuits and optical devices for displaying images, and a non-display area can also be provided around the display area. The area in the display area directly opposite the optical devices is the first area, and the area outside the first area is the second area.

[0059] A light-transmitting area can be provided between two adjacent pixel circuits in the first region, allowing light to pass through. During operation, light from outside the display device can pass through the light-transmitting area and enter an optical device located below the display panel (e.g., light from outside the display device passes through the light-transmitting area and enters a camera located below the display panel); or, light emitted from the optical device passes through the light-transmitting area and exits from the display panel (e.g., light emitted from a fingerprint recognition device passes through the light-transmitting area, exits from the display panel, enters the user's fingerprint, and is reflected back to the fingerprint recognition device).

[0060] To ensure the proper functioning of the optical components located beneath the display panel, it is necessary to increase the area of ​​the light-transmitting zone or reduce its obstruction of light, thereby allowing a sufficient amount of light to enter the optical components. Furthermore, to guarantee the display effect of the display panel, it is essential to maintain a certain pixel density, i.e., the number of pixel circuits and the center-to-center distance between adjacent pixel circuits. This application's embodiments, while maintaining a constant pixel density, improve the pixel circuitry to enhance the light transmittance of the first region.

[0061] In this embodiment, the pixel circuits are independent islands, and adjacent pixel circuits are connected by connecting lines, which can be at least partially located within the light-transmitting area. To reduce the light obstruction caused by the connecting lines, the connecting lines can be transparent or semi-transparent, for example, indium tin oxide (ITO) connecting lines. Of course, the connecting lines can also be made of other conductive materials.

[0062] For example, such as Figure 1 As shown, the display backplane includes multiple pixel circuits, including a first pixel circuit for driving red pixels, a second pixel circuit for driving green pixels, and a third pixel circuit for driving blue pixels. Adjacent pixel circuits are connected by connecting lines. The connecting lines include a first connecting line 100 along the horizontal direction and a second connecting line 200 along the vertical direction. The signals transmitted by the first connecting line 100 are different from those transmitted by the second connecting line 200. For example, the first connecting line 100 can transmit Vinit, EM, Gate, Gate, and Reset signals, while the second connecting line 200 can transmit VDD and Data signals.

[0063] in, Figure 1 The illustration shows a pixel comprising three sub-pixels: red, green, and blue, arranged in an RGB pattern. In practical applications, arrangements such as GRIB can also be used. This application does not limit the pixel arrangement. Furthermore, the number and color of the sub-pixels within a pixel are not limited.

[0064] A first connecting line extends along a first direction and electrically connects two adjacent pixel circuits along the first direction. For example, the first connecting line is parallel to a pixel row.

[0065] The pixel circuit includes a first gate line, a first channel line, and a second gate line stacked sequentially. The first channel line extends entirely along a first direction, and the first and second gate lines extend entirely along a second direction. A first transistor is formed at the intersection of the first gate line, the first channel line, and the second gate line. The first gate line and the second gate line are connected by a first bonding wire, which is connected to a first connecting line through a via. The first and second directions can be perpendicular or at an angle, and this is not limited thereto.

[0066] The first transistor is a dual-gate transistor. The intersection of the first gate line and the first channel line is the bottom gate of the first transistor, and the intersection of the second gate line and the first channel line is the top gate of the first transistor. The bottom gate and the top gate are connected.

[0067] The first connection line is connected to the first bridging wire, and the first bridging wire is connected to the first gate line and the second gate line, so that the signal in the first connection line can be written into the top gate and bottom gate of the first transistor, thereby controlling the on and off of the first transistor.

[0068] For ease of description, the pixel circuit is assumed to include a first side and a second side along the first direction. The end of the traces (e.g., gate lines, channel lines, connecting lines, etc.) in the pixel circuit facing the first side is the first end, and the end facing the second side is the second end.

[0069] Extending along the first direction means roughly following the first direction. It can be parallel to the first direction as a whole, or it can be at a small angle to the first direction as a whole; or, most of the area is parallel to the first direction, and a small part of the area is at a certain angle to the first direction. Extending along the second direction is similar and will not be elaborated further.

[0070] When the transistor channel line extends along the second direction and the gate line extends along the first direction, the distance between the first and second ends of the gate line within the pixel circuit is relatively long. In this case, it is typically necessary to configure the connection line as a segmented structure. For example, the connection line may include a first sub-connection line located on the first side of the pixel circuit and a second sub-connection line located on the second side of the pixel circuit. The first sub-connection line is connected to the first end of the gate line through a via, and the second sub-connection line is connected to the second end of the gate line through a via. However, when connecting through vias, a bonding pad is required, and the projected area of ​​the bonding pad is relatively large, resulting in a larger projected area of ​​the pixel circuit and increased light shading by the pixel circuit. It should be noted that in the embodiments of this application, projection refers to projection onto the substrate.

[0071] For example, when both the first gate line and the second gate line extend along the first direction, both the first and second gate lines have a lap pad at their first ends. The lap line is connected to the two lap pads through a via, thereby connecting the first gate line and the second gate line. The lap line has a lap pad, and the first sub-connecting line is connected to the lap pad on the lap line through a via. The second end of either the first or second gate line has a lap pad, and the second sub-connecting line is connected to the first or second gate line through a via. In other words, when the gate line of the transistor extends along the first direction, at least four lap pads are required in a pixel circuit to achieve the connection between the connecting line and the transistor.

[0072] In this embodiment, the first gate line and the second gate line extend along a second direction, making their dimensions along the first direction smaller. This results in a smaller dimension along the first direction for the first lap joint used to connect the first gate line and the second gate line, reducing the number of lap pads required to connect the first lap joint and the first connecting line. Reducing the number of lap pads shrinks the projected area of ​​the pixel circuit, thereby increasing the light-transmitting area between the pixel circuits.

[0073] For example, both the first gate line and the second gate line have overlapping pads on the same side. The first overlapping line is connected to the two overlapping pads through a via, and the first overlapping line has one overlapping pad. The first connecting line is connected to the overlapping pad of the first overlapping line through a via. In other words, only three overlapping pads are needed, instead of four overlapping pads extending along the first direction relative to the gate line, reducing one overlapping pad.

[0074] A pixel circuit may include multiple transistors, with the first transistor being one of the multiple transistors.

[0075] Figure 2 This is a circuit schematic diagram of a pixel circuit in an embodiment of this application, such as... Figure 2 As shown, the pixel circuit can be a 7T1C structure, that is, the pixel circuit includes seven transistors and one capacitor. Figure 3 for Figure 2 The signal timing diagram of the pixel circuit is shown. T1 and T2 are NMOS transistors, and T3, T4, T5, T6, and T7 are PMOS transistors.

[0076] For example, the operation of a pixel circuit includes the following stages:

[0077] In the first stage, EM and Gate_P are supplied with high-level signals, Reset_N and Gate_N are supplied with low-level signals, and T1, T2, T4, T5, T6, and T7 are not conducting, thus writing the VDD signal into capacitor Cst.

[0078] In the second stage, EM, Reset_N, and Gate_P are supplied with high-level signals, Gate_N is supplied with low-level signals, and T2, T4, T5, T6, and T7 are not conducting. The Vinit signal is written to capacitor Cst.

[0079] In the third stage, EM and Gate_N are supplied with high-level signals, Gate_P and Reset_N are supplied with low-level signals, T1, T5, T6 and T7 are not turned on, the light-emitting element is initialized, and the VDD signal is written to capacitor Cst.

[0080] In the fourth stage, EM and Gate_P are supplied with high-level signals, Gate_N and Reset_N are supplied with low-level signals, and T1, T2, T4, T5, T6, and T7 are not turned on.

[0081] In the fifth stage, EM, Reset_N, and Gate_N are supplied with low-level signals, and Gate_P is supplied with a high-level signal. T1, T2, T4, and T7 are not conducting, while the others are conducting, and the light-emitting device emits light.

[0082] For example, the first transistor is Figure 2 In the T1 transistor, the first connection line is connected to the first gate line and the second gate line, and a reset signal (Reset_N) is applied. Of course, the first transistor can also be other transistors.

[0083] For example, the first channel line can be a metal oxide, such as indium gallium zinc oxide (IGZO). Of course, the first channel line can also be low-temperature polysilicon (LTPS).

[0084] The first transistor can be located at the edge of the pixel circuit, so that the first connection line is also located at the edge of the pixel circuit, thereby reducing mutual interference between the first connection line and other traces in the pixel circuit. Here, "edge" refers to the edge of the pixel circuit projection.

[0085] During the operation of a display panel, the pixel circuit and the light-emitting device need to be initialized. Therefore, the pixel circuit in related technologies usually has two traces for initializing the pixel circuit and two traces for initializing the light-emitting device. That is, the pixel circuit has two traces to initialize the light-emitting device and the pixel circuit, and the two traces can be used with different initialization signals.

[0086] In this embodiment, the pixel circuit may further include an initialization signal line and a seventh transistor, both of which are connected to the initialization signal line. An initialization signal can be passed through the initialization signal line, configured to initialize the pixel circuit and the light-emitting device. Since the pixel circuit in this embodiment only requires one initialization signal line to initialize the light-emitting device and the pixel circuit, compared to the two traces used in related technologies, the number of traces is reduced, and the projected area of ​​the pixel circuit is decreased.

[0087] For example, continue to refer to Figure 2The first transistor can be a T1 transistor, and the seventh transistor can be a T7 transistor. The first terminal of the seventh transistor is connected to the light-emitting device, and the second terminal of the seventh transistor is connected to the initialization signal line. The first terminal of the first transistor is also connected to the initialization signal line. The first and second terminals of the seventh transistor are either the source or the drain of the transistor.

[0088] The first channel line includes a first end and a second end, and the seventh transistor includes a seventh channel line, with the first end of the seventh channel line disposed adjacent to the second end of the first channel line. The initialization signal line is disposed on a different layer from the first channel line and the second channel line, and the initialization signal line extends along the trace path of the first channel line, and the initialization signal line connects the first end of the first channel line and the first end of the seventh channel line.

[0089] The initialization signal line extends along the trace path of the first channel line, meaning that the projection of the initialization signal line and the projection of the first channel line at least partially overlap. Because the projection of the initialization signal line and the projection of the first channel line at least partially overlap, the projected area of ​​the pixel circuit is smaller.

[0090] Here, overlap is distinguished from cross overlap (e.g., the intersection of the first channel line and the first gate line). At least partial overlap between the projections of the initialization signal line and the first channel line means that most or all of their projections overlap. For example, the initialization signal line may be located directly above the first channel line and have the same or approximately the same orientation.

[0091] The first channel line and the seventh channel line can be disposed in different layers. For example, the first channel line belongs to the IGZO layer, and the seventh channel line belongs to the polysilicon layer.

[0092] The display backplane may include multiple strobe signal connection lines, each connected to a pixel circuit row. When one of the strobe signal connection lines is activated, the pixel circuit row connected to that strobe signal connection line can be written with data signals or initialization signals, while other pixel circuit rows cannot be written with data signals or initialization signals. The strobe signal connection lines are connected to the strobe signal lines in the pixel circuits.

[0093] In related technologies, the pixel circuit includes a gating signal line for controlling the writing of data signals and another gating signal line for controlling the writing of initialization signals.

[0094] In this embodiment, the pixel circuit may further include a fourth channel line and a third gate line stacked together. A fourth transistor is formed at the intersection of the third gate line and the fourth channel line. The third gate line forms the gates of both the fourth and seventh transistors. The gates of both the fourth and seventh transistors are formed through the third gate line. One of the fourth and seventh transistors is used to control the writing of a data signal, and the other is used to control the writing of an initialization signal. That is, the signal in the third gate line can simultaneously control the writing of both the data signal and the initialization signal. Compared to using two different selection signal lines, this saves one line, resulting in a smaller projected area for the pixel circuit.

[0095] For example, continue to refer to Figure 2 The fourth transistor is a T4 transistor, and its gate is connected to the first strobe signal line to receive the Gate_P signal. The seventh transistor is a T7 transistor, and its gate is also connected to the first strobe signal line to receive the Gate_P signal.

[0096] Since the gates of the fourth transistor and the seventh transistor are supplied with the same signal, the third gate line can simultaneously form the gates of both the fourth and seventh transistors, making the routing of the pixel circuit simpler.

[0097] The third gate line has a first lap pad at its end. The third gate line is connected to at least one first connection line through the first lap pad. It is connected to the gate of the fourth transistor through a via and to the gate of the seventh transistor through a via, thereby reducing the number of vias and thus reducing the projected area of ​​the pixel circuit.

[0098] The pixel circuit may also include a fifth gate line, the projection of which is located between the projections of the first channel line and the third gate line. The fifth gate line is used to form the gate of some transistors in the pixel circuit. In order to connect the fifth gate line to the vias of other film layers, a second lap pad is provided at the end of the fifth gate line, the width of which is greater than the linewidth of the fifth gate line.

[0099] In order to minimize the projected area of ​​the pixel circuit, the projection of the fifth gate line and the projection of the third gate line can be set close to each other. Since the width of the overlap plate is greater than the line width of the fifth gate line, the position on the third gate line opposite to the second overlap plate is bent away from the fifth gate line to avoid the second overlap plate.

[0100] The pixel circuit also includes a fourth gate line, a second channel line, and a fifth gate line stacked sequentially, with the fourth gate line, the second channel line, and the fifth gate line forming a second transistor at their overlap. One end of the fourth gate line and one end of the fifth gate line are connected by a second connection wire, which is connected to at least one first connection line via a via; the other end of the fourth gate line or the other end of the fifth gate line is connected to the first connection line via a via.

[0101] The fourth and fifth gate lines are connected only at one end via a via, while the other end remains unconnected. Therefore, the fourth and fifth gate lines can have a connection pad at only one end, reducing the number of connection pads and thus lowering the projected area of ​​the pixel circuitry.

[0102] For example, each of the first ends of the fourth gate line and the fifth gate line is provided with a lap pad, the second lap line is connected to the two lap pads, the second lap line is provided with a lap pad for connecting to the first connecting line, and the second end of the fourth gate line or the fifth gate line is provided with a lap pad for connecting to the first connecting line. That is, four lap pads need to be provided.

[0103] When both ends of the fourth and fifth gate lines are connected by lap joints, each gate line has two lap joints and includes two lap joints, with one lap joint for each lap joint. That is, six lap joints are required.

[0104] Therefore, it can be seen that the above-described method of this application embodiment can save two overlapping plates, thereby reducing the projected area of ​​the pixel circuit.

[0105] For example, the second transistor is Figure 2 The T2 transistor has its gate connected to the second connection line and is used to receive the Gate_N signal.

[0106] When the first connection line is located on a layer away from the fourth gate line, the distance between the first connection line and the fifth gate line is closer. The two ends of the fifth gate line are connected to the first connection line through vias, making the vias shallower and easier to process.

[0107] The fifth gate lines in two adjacent pixel circuits need to be connected by a connecting line so that the same signal can be passed through. The connecting line is at least partially located in the light-transmitting area. When the fifth gate line extends along the first direction, the connecting line connecting the fifth gate lines in two adjacent pixel circuits can also extend along the first direction, thereby reducing the area of ​​the connecting line located in the light-transmitting area and reducing the light obstruction by the connecting line.

[0108] The pixel circuit may further include a third channel line and a first electrode, a second electrode, and a third connecting wire stacked sequentially. The third channel line and the first electrode form a third transistor at their overlap. The second electrode has a notched structure; one end of the third connecting wire passes through the notched structure and connects to the first electrode, while the other end connects to the first and second channel lines. The first and second electrode plates form a capacitor.

[0109] For example, such as Figure 2 As shown, the third transistor is T3, the first transistor is T, the second transistor is T2, and the capacitor is Cst.

[0110] To reduce the projected area of ​​the pixel circuit, the areas of the first and second plates in the capacitor can be reduced. However, creating an opening at the center of the second plate to avoid the third connecting wire requires high precision and is difficult to achieve. Therefore, the opening to avoid the third connecting wire is placed at a corner of the second plate, forming a notched corner structure, which reduces the manufacturing difficulty.

[0111] The pixel circuit also includes a fifth channel line, a sixth channel line, and a sixth gate line. The sixth gate line and the fifth channel line overlap to form a fifth transistor. The sixth gate line and the sixth channel line overlap to form a sixth transistor, which is connected to the first electrode of the light-emitting device. The sixth gate line is connected to at least one first connection line through a via. The sixth gate line simultaneously forms the gate of both the fifth and sixth transistors, resulting in fewer traces within the pixel circuit and a reduced projected area.

[0112] For example, continue to refer to Figure 2 The fifth transistor is T5, and the sixth transistor is T6.

[0113] In the projection of the pixel circuit, the seventh transistor is located between the sixth transistor and the first transistor along the second direction.

[0114] For example, continue to refer to Figure 2 The sixth transistor can be a T6 transistor, and the seventh transistor can be a T7 transistor.

[0115] In related technologies, the T7 transistor is usually placed below the T6 transistor, resulting in a larger projected area for the pixel circuit.

[0116] In this embodiment, the seventh transistor is placed between the first transistor and the sixth transistor, making the distance between the seventh transistor and the first and fourth transistors closer, thereby making the trace connecting the seventh transistor and the first transistor shorter, and the trace connecting the seventh transistor and the fourth transistor also shorter, resulting in a smaller projected area of ​​the pixel circuit.

[0117] The pixel circuit may also include data signal lines and voltage signal lines. One end of the fifth channel line is connected to the second electrode plate via a fourth bonding wire. The voltage signal line is connected to the fourth bonding wire via a via. The data signal line is connected to one end of the fourth channel line, and the other end of the fourth channel line is connected to the other end of the fifth channel line.

[0118] For example, the fourth channel line and the fifth channel line are the same semiconductor trace extending along the second direction, meaning that the other ends of the fourth channel line and the other ends of the fifth channel line are a single structure. The fourth transistor is... Figure 2 In T4, the fifth transistor is Figure 2 T5, voltage signal line is connected Figure 2 The VDD signal shown is connected to the data signal line. Figure 2 Data signals are transmitted through the integrated structure of the fourth and fifth channel lines, which simplifies the routing of the semiconductor layers within the pixel circuit.

[0119] At least one second connection line connects to the data signal lines in two adjacent pixel circuits, and at least one second connection line connects to the voltage signal lines in two adjacent pixel circuits.

[0120] For example, the first connecting line and the second connecting line are arranged on different layers. In this way, the first connecting line extends along a first direction and the second connecting line extends along a second direction, and the first connecting line and the second connecting line are arranged on different layers, which makes the routing of the first connecting line and the second connecting line simpler.

[0121] Figure 4 for Figure 2 The diagram shows a layout design for a pixel circuit, with the marked transistors forming the area within the dashed box. Figures 5 to 34 It shows Figure 4 The diagram shows a schematic of each film layer in the pixel circuit and a partial diagram of the film layer stacking structure. For example, as shown... Figures 4 to 34 As shown, the fabrication process of the pixel circuit is as follows.

[0122] Depositing polycrystalline silicon layers, patterned to form Figure 5 The structure shown includes a third channel line 3, a fourth channel line 4, a fifth channel line 5, a sixth channel line 6, and a seventh channel line 7. The third channel line 3 is used to form T3, the fourth channel line 4 is used to form T4, the fifth channel line 5 is used to form T5, the sixth channel line 6 is used to form T6, and the seventh channel line 7 is used to form T7.

[0123] Depositing the first gate layer and patterning the first gate layer Figure 6 The structure shown includes a third gate line 11, a first electrode plate 12, and a sixth gate line 13. Figure 7This is a schematic diagram showing the overlap of the polysilicon layer and the first gate layer. The third gate line 11 overlaps with the fourth channel line 4 to form T4, and overlaps with the seventh channel line 7 to form T7. The third gate line 11 serves as the top gate of T4 and T7. The first electrode plate 12 is used to form... Figure 2 The capacitor has two plates, and the first plate 12 and the third channel line 3 overlap to form T3. The sixth gate line 13 overlaps with the fifth channel line 5 to form T5, and overlaps with the sixth channel line to form T6. The sixth gate line 13 is used to form the top gate of T5 and T6. The end of the third gate line 11 is provided with a first lap pad 14.

[0124] Deposit the second gate layer, and form it after patterning. Figure 8 The structure shown forms a first gate line 21, a fourth gate line 22, and a second electrode plate 23. A notched structure 24 is provided on the second electrode plate. The first gate line 21 is used to form the bottom gate of T1, the fourth gate line 22 is used to form the bottom gate of T2, and the second electrode plate 23 and the first electrode plate 12 form a capacitor Cst. Figure 9 This is a schematic diagram of the structure after the second gate layer is superimposed.

[0125] Deposited metal oxide layers, patterned to form Figure 10 The structure shown includes a first channel line 31 and a second channel line 32. The first channel line 31 is used to form T1, and the second channel line 32 is used to form T2. The first channel line 31 and the second channel line 32 are connected. Figure 11 This is a schematic diagram of the structure after the low-temperature polycrystalline oxide layer is superimposed.

[0126] The third gate layer is deposited and patterned to form Figure 12 The structure shown includes a second gate line 41 and a fifth gate line 42. The second gate line 41 is used to form the top gate of T1, and the fifth gate line 42 is used to form the top gate of T2. A second lap pad 43 is provided at the end of the fifth gate line. Figure 13 This is a schematic diagram of the structure after the third gate layer is stacked.

[0127] The first ILD layer is deposited. Figure 14 This is a mask diagram of the first ILD layer. Figure 15 This is a schematic diagram of the structure after the first ILD layer is superimposed. The diagram shows the vias formed by the first ILD layer.

[0128] The second ILD layer is deposited. Figure 16 This is a mask diagram of the second ILD layer. Figure 17 This is a schematic diagram of the structure after the second ILD layer is superimposed. The diagram shows the vias formed by the second ILD layer.

[0129] Deposit SD1 layer. Figure 18This is a schematic diagram of the SD1 layer. The SD1 layer includes a first bonding wire 51, which is connected to the first gate line 21 and the second gate line 41 through vias formed by the first ILD layer and the second ILD layer.

[0130] The SD1 layer also includes an initialization signal line 56, which is connected to the first channel line 31 and the seventh channel line 7 through vias formed by the first ILD layer and the second ILD layer.

[0131] The SD1 layer also includes a second bonding wire 52, which connects the fourth gate line 22 and the fifth gate line 42 through vias formed by the first ILD layer and the second ILD layer.

[0132] The SD1 layer also includes a third bonding wire 53. One end of the third bonding wire 53 passes through the notched structure 24 through a via formed by the first ILD layer and the second ILD layer and is connected to the first electrode plate 12. The other end of the third bonding wire 53 is connected to the first channel line 31 and the second channel line 32 through a via formed by the first ILD layer and the second ILD layer.

[0133] The SD1 layer also includes a fourth bonding wire 54, one end of which is connected to the fifth channel line 5, and the other end is connected to the second electrode plate 23.

[0134] The SD1 layer also includes a fifth connection wire 55, which connects the sixth channel line 6 and the seventh channel line 7.

[0135] Figure 19 This is a schematic diagram of the structure after the SD1 layer is superimposed.

[0136] PVX layer deposition. Figure 20 This is a mask diagram of the PVX layer. Figure 21 This is a schematic diagram of the structure after the PVX layer is superimposed. The diagram shows the vias formed by the PVX layer.

[0137] The first ITO layer is deposited. The first ITO layer includes a first connection line and the connection structure between the first connection line and the pixel circuit. Figure 22 This is the overlapping structure in the first ITO layer.

[0138] The first ITO layer includes a first lap structure 61 connected to the first lap wire 51, and the first lap structure 61 and at least one first connecting wire are integrally formed.

[0139] The first ITO layer also includes a second overlap structure 62 located at one end of the sixth gate line 13, a third overlap structure 63 located at the other end of the sixth gate line 13, and another first connection line is integral with the second overlap structure 62 and the third overlap structure 63. This first connection line is connected to the sixth gate line 13 through the second overlap structure 62 and the third overlap structure 63.

[0140] The first ITO layer also includes a fourth overlap structure 64 located at one end of the initialization signal line and a fifth overlap structure 65 located at the other end of the initialization signal line. A first connection line is connected to the initialization signal line through the fourth overlap structure 64 and the fifth overlap structure 65.

[0141] The first ITO layer also includes a sixth lap structure 66 located at one end of the third gate line 11 and a seventh lap structure 67 located at the other end of the third gate line 11. A first connection is connected to the third gate line 11 through the sixth lap structure 66 and the seventh lap structure 67.

[0142] The first ITO layer also includes an eighth overlap structure 68 located at one end of the fifth gate line 42 and a ninth overlap structure 69 located at the other end of the fifth gate line 42. A first connection is connected to the fifth gate line 42 through the eighth overlap structure 68 and the ninth overlap structure 69.

[0143] The first ITO layer also includes a tenth overlap structure 70 connected to the T4 channel line.

[0144] The first ITO layer also includes an eleventh lap structure 71 connected to the fourth lap joint 54.

[0145] The first ITO layer also includes a twelfth lap structure 72 connected to the fifth lap joint 55.

[0146] Figure 23 This is a schematic diagram of the structure after the first ITO layer is superimposed.

[0147] The first flat layer is deposited. Figure 24 This is the mask image for the first flat layer. Figure 25 This is a schematic diagram of the structure after the first planarization layer is superimposed. The diagram shows the vias formed by the first planarization layer.

[0148] The second ITO layer is deposited. The second ITO layer includes multiple second connection lines and connection structure 84. The multiple second connection lines include data signal connection lines 81 and voltage signal connection lines. The data signal connection line 81 is connected to the tenth overlap structure 70, the lower segment 82 of the voltage signal connection line is connected to the eleventh overlap structure 71, and the upper segment 83 is connected to the SD2 layer. Figure 26 For the second ITO layer, Figure 27 This is a schematic diagram of the structure after the second ITO layer is superimposed.

[0149] The second flat layer is deposited. Figure 28 This is the mask image for the second flat layer. Figure 29 This is a schematic diagram of the structure after the second planarization layer is superimposed. The diagram shows the vias formed by the second planarization layer.

[0150] Deposit SD2 layer. Figure 30 This is a schematic diagram of the SD2 layer. The SD2 layer includes an SD2 line 91 that connects the upper section 83 and the lower section 82 of the voltage signal connection line, and an anode adapter structure 92 that connects to the connection structure 85 and the anode 93 of the light-emitting device. Figure 31 This is a schematic diagram of the structure after the SD2 layer is superimposed.

[0151] The third flat layer is deposited. Figure 32 This is a mask image of the third flat layer. Figure 33 This is a schematic diagram of the structure after the third planarization layer is superimposed.

[0152] Depositing the anode layer of the light-emitting device. Figure 34 This is a schematic diagram of the anode layer, including anode 93.

[0153] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display backplane, characterized by, It includes multiple pixel circuits arranged at intervals, a light-transmitting area located between the pixel circuits, and multiple first connecting lines extending along a first direction, wherein the first connecting lines connect two adjacent pixel circuits; The pixel circuit includes a first gate line, a first channel line, and a second gate line stacked sequentially. The first channel line extends entirely along the first direction, and the first gate line and the second gate line extend entirely along the second direction. The first gate line, the first channel line, and the second gate line form a first transistor at their overlap. The second direction intersects the first direction. The first gate line and the second gate line are connected by a first bonding wire, and the first bonding wire is connected to the first connecting line through a via. The pixel circuit also includes a third gate line and a fifth gate line; In a projection perpendicular to the light-emitting surface, the fifth gate line is located between the first channel line and the third gate line, and the end of the fifth gate line is provided with a second overlapping plate; The third gate line is bent away from the position opposite to the second lap pad in the direction away from the fifth gate line.

2. The display backplane of claim 1, wherein, The pixel circuit further includes an initialization signal line and a seventh transistor, both of which are connected to the initialization signal line.

3. The display backplane of claim 2, wherein, The seventh transistor includes a seventh channel line, the first channel line includes a first end and a second end opposite to each other, and the first end of the seventh channel line is disposed adjacent to the second end of the first channel line; The initialization signal line connects the first end of the first channel line and the first end of the seventh channel line, and the initialization signal line extends along the routing path of the first channel line.

4. The display backplane of claim 3, wherein, The pixel circuit further includes a fourth channel line and a third gate line stacked together, wherein the third gate line and the fourth channel line form a fourth transistor at their overlap, and the third gate line forms the gate of the fourth transistor and the seventh transistor.

5. The display back panel according to claim 4, characterized in that, The third gate line is provided with a first lap plate at its end, and the third gate line is connected to at least one of the first connecting lines through the first lap plate.

6. The display back panel according to claim 4, characterized in that, The pixel circuit further includes a fourth gate line, a second channel line, and a fifth gate line stacked sequentially, wherein the fourth gate line, the second channel line, and the fifth gate line form a second transistor at their overlap. One end of the fourth gate line and one end of the fifth gate line are connected by a second connection wire, and the second connection wire is connected to a first connection line through a via; the other end of the fourth gate line or the other end of the fifth gate line is connected to the first connection line through a via.

7. The display back panel according to claim 6, characterized in that, The first connection line is located on a layer away from the fourth gate line of the fifth gate line, and the two ends of the fifth gate line are connected to the first connection line through vias.

8. The display back panel according to claim 6, characterized in that, The pixel circuit also includes a third channel line and a first electrode plate, a second electrode plate and a third connecting line arranged in sequence. The third channel line and the first electrode plate form a third transistor at their overlap. The second electrode plate has a notched structure. One end of the third connecting wire passes through the notched structure and connects to the first electrode plate. The other end of the third connecting wire connects to the first channel line and the second channel line.

9. The display back panel according to claim 8, characterized in that, The pixel circuit further includes a fifth channel line, a sixth channel line, and a sixth gate line. The sixth gate line and the fifth channel line form a fifth transistor at their overlap. The sixth gate line and the sixth channel line form a sixth transistor at their overlap. The sixth transistor is connected to the first electrode of the light-emitting device. The sixth gate line is connected to at least one of the first connection lines via a via.

10. The display back panel according to claim 9, characterized in that, In a projection perpendicular to the light-emitting surface, along the second direction, the seventh transistor is located between the sixth transistor and the first transistor.

11. The display back panel according to claim 9, characterized in that, The pixel circuit also includes data signal lines and voltage signal lines; One end of the fifth channel line and the second electrode plate are connected by a fourth bonding wire, and the voltage signal line is connected to the fourth bonding wire through a via. The data signal line is connected to one end of the fourth channel line, and the other end of the fourth channel line is connected to the other end of the fifth channel line.

12. The display back panel according to claim 11, characterized in that, It also includes multiple second connection lines extending along the second direction, at least one of the second connection lines connecting the data signal lines in two adjacent pixel circuits, and at least one of the second connection lines connecting the voltage signal lines in two adjacent pixel circuits.

13. The display back panel according to claim 12, characterized in that, The first connecting line and / or the second connecting line are transparent connecting lines.

14. A display device, characterized in that, include: The display backplate as described in any one of claims 1-13; as well as A light-emitting device is disposed on one side of the display back panel and connected to a pixel circuit, which is used to drive the light-emitting device to emit light.

Images