Composite diode and preparation method thereof, chip

Abstract

The application belongs to the technical field of semiconductors, and provides a composite diode, a preparation method thereof and a chip. A buffer layer, a GaN layer and an AlGaN layer are formed in a first preset region of an N-type silicon substrate, a plurality of P-type injection regions are formed in a second preset region of the N-type silicon substrate at a preset interval, a plurality of silicon-based diodes in parallel are obtained by the plurality of P-type injection regions and the N-type silicon substrate, heat released when current flows through the silicon-based diode can be offset by heat absorbed when current flows through the buffer layer, the GaN layer and the AlGaN layer, and thus the device (composite diode) formed can maintain a constant temperature in a working state, the problem that the voltage drop of the diode in a forward direction drifts with temperature is solved, the stability of the device is improved, and the application scenarios of the diode device are expanded.

Description

Technical Field

[0001] This application belongs to the field of semiconductor device technology, and in particular relates to a composite diode and its preparation method and chip. Background Technology

[0002] Diodes are very sensitive to temperature during use. Their forward voltage drop usually changes significantly with temperature. In circuits, when diodes are used for voltage regulation, their forward voltage drop will drift with temperature, reducing the stability of the device and greatly limiting the application scenarios of diode devices. Summary of the Invention

[0003] This application provides a composite diode and its fabrication method and chip, aiming to solve the problem of forward voltage drop drift with temperature in current diodes.

[0004] To address the aforementioned technical problems, the first aspect of this application provides that the composite diode includes:

[0005] N-type silicon substrate;

[0006] A buffer layer, a GaN layer, and an AlGaN layer are sequentially stacked in a first predetermined region of the N-type silicon substrate;

[0007] Multiple P-type implantation regions are formed at preset intervals on a second preset region of the N-type silicon substrate, and the multiple P-type implantation regions form a PN junction with the N-type silicon substrate; the first preset region and the second preset region do not contact each other;

[0008] An anode metal layer is formed on a portion of the surface of each of the P-type injection regions and on the surface of the spacer regions between the P-type injection regions, and forms a Schottky contact with each of the spacer regions;

[0009] A cathode metal layer is formed on a portion of the AlGaN layer and forms an ohmic contact with the AlGaN layer;

[0010] An ohmic contact layer is formed on the N-type silicon substrate, and the ohmic contact layer is in contact with the buffer layer, the GaN layer and the AlGaN layer, but is not in contact with the plurality of P-type implantation regions.

[0011] In one embodiment, the buffer layer, the GaN layer, and the AlGaN layer have the same shape, and the width of the buffer layer, the GaN layer, and the AlGaN layer is less than half the width of the N-type silicon substrate.

[0012] In one embodiment, the width of the P-type implantation region is less than one-fifth the width of the N-type silicon substrate.

[0013] In one embodiment, the area of ​​the anode metal layer covering a single P-type injection region is equal to half the area of ​​the single P-type injection region.

[0014] In one embodiment, the depth of the P-type implantation region is greater than half the depth of the N-type silicon substrate.

[0015] In one embodiment, the ohmic contact layer has an L-shaped structure, and the horizontal portion of the ohmic contact layer contacts the N-type silicon substrate, while the vertical portion of the ohmic contact layer contacts the buffer layer, the GaN layer, and the AlGaN layer.

[0016] In one embodiment, the vertical portion of the ohmic contact layer contacts the side portion of the AlGaN layer.

[0017] In one embodiment, the cathode metal layer is located on the AlGaN layer on the side away from the anode metal layer.

[0018] A second aspect of this application also provides a method for fabricating a composite diode, the method comprising:

[0019] A buffer layer, a GaN layer, and an AlGaN layer are sequentially stacked on a first predetermined region of an N-type silicon substrate.

[0020] Multiple P-type implantation regions are formed at predetermined intervals in a second predetermined region of the N-type silicon substrate, and the multiple P-type implantation regions form a PN junction with the N-type silicon substrate; the first predetermined region and the second predetermined region do not contact each other;

[0021] An anode metal layer is formed on a portion of the surface of each of the P-type injection regions and on the surface of the spacer regions between the P-type injection regions; the anode metal layer forms a Schottky contact with each of the spacer regions;

[0022] A cathode metal layer is formed on a portion of the AlGaN layer; the cathode metal layer forms an ohmic contact with the AlGaN layer;

[0023] An ohmic contact layer is formed on the N-type silicon substrate, and the ohmic contact layer is in contact with the buffer layer, the GaN layer and the AlGaN layer, but is not in contact with the plurality of P-type implantation regions.

[0024] A third aspect of this application also provides a chip, including a composite diode as described in any of the above embodiments; or including a composite diode prepared by the preparation method described in the above embodiments.

[0025] The beneficial effects of the embodiments in this application compared with the prior art are:

[0026] By forming a buffer layer, a GaN layer, and an AlGaN layer in a first predetermined region of an N-type silicon substrate, and forming multiple P-type injection regions at predetermined intervals in a second predetermined region of the N-type silicon substrate, multiple parallel silicon-based diodes are obtained, formed by the multiple P-type injection regions and the N-type silicon substrate. This allows the heat released when current flows through the silicon-based diode to cancel out the heat absorbed when current flows through the buffer layer, GaN layer, and AlGaN layer, thereby enabling the formed device (composite diode) to maintain a constant temperature during operation. This solves the problem of voltage drop drift during forward conduction of the diode with temperature, improves the stability of the device, and expands the application scenarios of the diode device.

[0027] In addition, this application also forms a junction barrier Schottky diode (JBS) by forming multiple P-type injection regions at predetermined intervals in the second predetermined region of the N-type silicon substrate, thereby increasing the device's surge resistance, improving the breakdown voltage (BV), and increasing the device's electron mobility due to the two-dimensional electron gas (2DEG) introduced by the GaN layer and AlGaN layer, resulting in increased current. Attached Figure Description

[0028] Figure 1 A schematic diagram of a vertical cross-section of a composite diode provided in an embodiment of this application is shown;

[0029] Figure 2 A schematic diagram of the horizontal cross-section of a composite diode provided in an embodiment of this application is shown;

[0030] Figure 3 A schematic diagram illustrating the implementation flow of the composite diode fabrication method provided in this application embodiment is shown;

[0031] Figure 4 A schematic diagram of the formation of buffer layer 200, GaN layer 300, and AlGaN layer 400 provided in an embodiment of this application is shown;

[0032] Figure 5 This diagram shows a schematic diagram after etching the buffer layer 200, GaN layer 300, and AlGaN layer 400 according to an embodiment of this application.

[0033] Figure 6 A schematic diagram of the formation of a P-type injection region provided in an embodiment of this application is shown. Detailed Implementation

[0034] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0035] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0036] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0038] A Zener diode is a diode that uses the phenomenon that the current can vary over a wide range while the voltage remains basically constant when the PN junction is in reverse breakdown state to stabilize the voltage.

[0039] However, current diodes are very sensitive to temperature during use. The forward voltage drop usually changes significantly with temperature. In circuits, when diodes are used for voltage regulation, their forward voltage drop will drift with temperature, reducing the stability of the device and greatly limiting the application scenarios of diode devices.

[0040] To address the aforementioned technical problems, this application provides a composite diode, see [link to relevant documentation]. Figure 1 and Figure 2 As shown, the composite diode in this embodiment includes: an N-type silicon substrate 100, a buffer layer 200, a GaN layer 300, an AlGaN layer 400, multiple P-type injection regions 500, an anode metal layer 600, a cathode metal layer 700, and an ohmic contact layer 800.

[0041] Among them, the buffer layer 200, the GaN layer 300, and the AlGaN layer 400 are sequentially stacked on the surface of the first predetermined region of the N-type silicon substrate 100, and combined with... Figure 2As shown, multiple P-type implantation regions 500 are formed at preset intervals on a second preset region of an N-type silicon substrate 100, and the multiple P-type implantation regions 500 form a PN junction with the N-type silicon substrate 100; the first preset region and the second preset region do not contact each other; an anode metal layer 600 is formed on a portion of the surface of each P-type implantation region 500 and the surface of the spacer region between each P-type implantation region 500, and forms a Schottky contact with each spacer region; a cathode metal layer 700 is formed on a portion of an AlGaN layer 400, and forms an ohmic contact with the AlGaN layer 400; an ohmic contact layer 800 is formed on the N-type silicon substrate 100, and the ohmic contact layer 800 contacts the buffer layer 200, the GaN layer 300 and the AlGaN layer 400, and does not contact the multiple P-type implantation regions 500.

[0042] In the above structure, by forming a buffer layer 200, a GaN layer 300, and an AlGaN layer 400 in the first preset region of the N-type silicon substrate 100, and forming multiple P-type injection regions 500 at preset intervals in the second preset region of the N-type silicon substrate 100, multiple parallel silicon-based diodes formed by the multiple P-type injection regions 500 and the N-type silicon substrate 100 are obtained. This allows the heat released when the current flows through the silicon-based diode to cancel out the heat absorbed when the current flows through the buffer layer 200, the GaN layer 300, and the AlGaN layer 400. As a result, the formed device (composite diode) can maintain a constant temperature during operation, solving the problem of voltage drop drift during forward conduction of the diode with temperature, improving the stability of the device, and expanding the application scenarios of the diode device.

[0043] Specifically, since silicon-based diodes have a negative temperature coefficient of forward voltage drop and GaN has a positive temperature coefficient, the two cancel each other out, resulting in a composite diode with a very low temperature coefficient. This solves the problem of voltage drop drift during forward conduction with temperature, improves device stability, and expands the application scenarios of diode devices.

[0044] In this embodiment, the temperature coefficient of the silicon-based diode is approximately -0.23 mV / ℃, and the temperature coefficient of the GaN material is approximately +0.27 mV / ℃. When the two are combined, the final temperature coefficient is only 0.04 mV / ℃. By adjusting the ratio of the active area between the silicon-based diode and the GaN layer 300, the device can maintain a constant temperature during operation.

[0045] In addition, this application forms a plurality of P-type injection regions 500 at predetermined intervals in the second predetermined region of the N-type silicon substrate 100 to form a junction barrier Schottky diode (JBS), thereby increasing the surge resistance of the device, improving the breakdown voltage (BV), and improving the electron mobility and conduction current of the device by cooperating with the two-dimensional electron gas (2DEG) introduced by the GaN layer 300 and the AlGaN layer 400.

[0046] In one embodiment, the buffer layer 200, GaN layer 300, and AlGaN layer 400 have the same shape, and the width of the buffer layer 200, GaN layer 300, and AlGaN layer 400 is less than half the width of the N-type silicon substrate 100.

[0047] In this embodiment, a buffer layer 200 is disposed between the GaN layer 300 and the N-type silicon substrate 100. The buffer layer 200 reduces the thermal mismatch and lattice mismatch between the N-type silicon substrate 100 and the GaN layer 300, so that the GaN layer 300 and the P-type implantation region 500 are formed on the same N-type silicon substrate 100.

[0048] In one embodiment, the buffer layer 200 may be silicon carbide, located in a first predetermined region on the N-type silicon substrate 100.

[0049] In a specific application embodiment, a buffer layer 200 can be formed by depositing silicon carbide material in a first predetermined region on an N-type silicon substrate 100 via MOCVD, thereby reducing thermal mismatch and lattice mismatch between the N-type silicon substrate 100 and the gallium nitride layer.

[0050] In one embodiment, the area of ​​the first preset region on the N-type silicon substrate 100 is less than half the area of ​​the surface region of the N-type silicon substrate 100.

[0051] In one embodiment, the width of the P-type implantation region 500 is less than one-fifth the width of the N-type silicon substrate 100.

[0052] In this embodiment, there are multiple P-type implantation regions 500 on the N-type silicon substrate 100. Each P-type implantation region 500 forms a PN junction with the N-type silicon substrate 100, and all P-type implantation regions 500 are in contact with the anode metal layer 600, thereby forming multiple parallel PN junction structures.

[0053] In one embodiment, the area of ​​the anode metal layer 600 covering a single P-type injection region 500 is equal to half the area of ​​the single P-type injection region 500.

[0054] In this embodiment, multiple P-type injection regions 500 are arranged side by side, and the anode metal layer 600 is arranged in the same direction as the multiple P-type injection regions 500. The area of ​​the anode metal layer 600 covering each P-type injection region 500 is equal to half the area of ​​the P-type injection region 500.

[0055] In one embodiment, the depth of the P-type implantation region 500 is greater than half the depth of the N-type silicon substrate 100.

[0056] In this embodiment, multiple P-type implantation regions 500 can be formed on the N-type silicon substrate 100 by implanting P-type dopant ions into a second preset region on the N-type silicon substrate 100, wherein the concentration of the implanted P-type dopant ions is greater than the concentration of N-type dopant ions in the N-type silicon substrate 100, and the implantation depth of the P-type dopant ions is greater than half the depth of the N-type silicon substrate 100.

[0057] In one embodiment, the ohmic contact layer 800 has an L-shaped structure, and the horizontal portion of the ohmic contact layer 800 contacts the N-type silicon substrate 100, while the vertical portion of the ohmic contact layer 800 contacts the buffer layer 200, the GaN layer 300, and the AlGaN layer 400.

[0058] In this embodiment, by setting the ohmic contact layer 800 into an L-shaped structure, the horizontal part of the ohmic contact layer 800 contacts the N-type silicon substrate 100, and the vertical part of the ohmic contact layer 800 contacts the buffer layer 200, the GaN layer 300 and the AlGaN layer 400, thereby establishing an electron transport channel between the two-dimensional electron gas channel in the GaN layer 300 and the PN junction.

[0059] In one embodiment, the vertical portion of the ohmic contact layer 800 contacts the side portion of the AlGaN layer 400.

[0060] In this embodiment, the vertical portion of the ohmic contact layer 800 can extend to a portion of the side surface of the AlGaN layer 400, so that the 2DEG channel between the AlGaN layer 400 and the GaN layer 300 can be electrically connected to the ohmic contact layer 800, thereby improving the electron mobility and conduction current of the composite diode device.

[0061] In one embodiment, the cathode metal layer 700 is located on the AlGaN layer 400 on the side away from the anode metal layer 600.

[0062] In this embodiment, the cathode metal layer 700 is formed on the surface of the AlGaN layer 400. The AlGaN layer 400 can serve as a capping layer for the GaN layer 300, and the cathode metal layer 700 is located on the side away from the anode metal layer 600. When a positive voltage is applied to the anode metal layer 600, the current can flow through the PN junction and then through the ohmic contact layer 800 and the 2DEG to the cathode metal layer 700. At this time, by setting the active region area between the silicon-based diode and the GaN layer 300 to be the same, and utilizing the fact that the forward voltage drop of the silicon-based diode has a negative temperature coefficient and GaN has a positive temperature coefficient, the temperature coefficients of the two are canceled out. The resulting composite diode has a very low temperature coefficient, which achieves the purpose of solving the problem of the forward voltage drop of the diode drifting with temperature, improving the stability of the device, and expanding the application scenarios of the diode device.

[0063] This application also provides a method for preparing a composite diode, which is used to prepare the above-mentioned composite diode.

[0064] See Figure 3 As shown, the preparation method in this embodiment includes steps S100 to S500.

[0065] In step S100, a buffer layer 200, a GaN layer 300, and an AlGaN layer 400 are sequentially stacked on a first predetermined region of an N-type silicon substrate 100.

[0066] Combination Figure 4 and Figure 5 As shown, in the specific implementation of step S100, a buffer layer 200, a GaN layer 300, and an AlGaN layer 400 can be directly generated on the N-type silicon substrate 100. Then, the buffer layer 200, the GaN layer 300, and the AlGaN layer 400 are partially etched, leaving only the buffer layer 200, the GaN layer 300, and the AlGaN layer 400 on the first preset region of the N-type silicon substrate 100. The etched region is the second preset region, which can be used to form a PN junction.

[0067] In one embodiment, the buffer layer 200, GaN layer 300, and AlGaN layer 400 have the same shape, and the width of the buffer layer 200, GaN layer 300, and AlGaN layer 400 is less than half the width of the N-type silicon substrate 100.

[0068] In a specific application embodiment, a buffer layer 200 can be formed by depositing silicon carbide material in a first predetermined region on an N-type silicon substrate 100 via MOCVD, thereby reducing thermal mismatch and lattice mismatch between the N-type silicon substrate 100 and the GaN layer 300.

[0069] In step S200, a plurality of P-type implantation regions 500 are formed at a preset interval in the second preset region of the N-type silicon substrate 100, and the plurality of P-type implantation regions 500 form a PN junction with the N-type silicon substrate 100; the first preset region and the second preset region do not contact each other.

[0070] Combination Figure 2 and Figure 6 As shown, in one embodiment, multiple P-type injection regions 500 can be arranged at equal intervals.

[0071] In one embodiment, the width of the P-type implantation region 500 is less than one-fifth the width of the N-type silicon substrate 100.

[0072] In one embodiment, the depth of the P-type implantation region 500 is greater than half the depth of the N-type silicon substrate 100.

[0073] In step S300, an anode metal layer 600 is formed on a portion of the surface of each P-type injection region 500 and on the surface of the spacer region between each P-type injection region 500; the anode metal layer 600 forms a Schottky contact with each spacer region.

[0074] Combination Figure 1 and Figure 2 As shown, the anode metal layer 600 is elongated and formed on a portion of the surface of the P-type injection region 500, as well as on the surface of the spacer regions between the individual P-type injection regions 500.

[0075] In one embodiment, the area of ​​the anode metal layer 600 covering a single P-type injection region 500 is equal to half the area of ​​the single P-type injection region 500.

[0076] In step S400, a cathode metal layer 700 is formed on a portion of the AlGaN layer 400; the cathode metal layer 700 forms an ohmic contact with the AlGaN layer 400.

[0077] Combination Figure 1 As shown, in one embodiment, the cathode metal layer 700 is located on the AlGaN layer 400 on the side away from the anode metal layer 600.

[0078] In step S500, an ohmic contact layer 800 is formed on the N-type silicon substrate 100, and the ohmic contact layer 800 is in contact with the buffer layer 200, the GaN layer 300 and the AlGaN layer 400, but is not in contact with the plurality of P-type implantation regions 500.

[0079] Combination Figure 1As shown, in one embodiment, the ohmic contact layer 800 may have an L-shaped structure, and the horizontal portion of the ohmic contact layer 800 contacts the N-type silicon substrate 100, while the vertical portion of the ohmic contact layer 800 contacts the buffer layer 200, the GaN layer 300, and the AlGaN layer 400.

[0080] Combination Figure 1 As shown, in one embodiment, the vertical portion of the ohmic contact layer 800 may contact the side portion of the AlGaN layer 400, that is, the ohmic contact layer 800 does not fully cover the side of the AlGaN layer 400.

[0081] Combination Figure 1 As shown, in one embodiment, the ohmic contact layer 800 is located between the anode metal layer 600 and the cathode metal layer 700.

[0082] This application also provides a chip, including a composite diode as described in any of the above embodiments.

[0083] In one embodiment, the chip in this embodiment includes a composite diode fabricated by the fabrication method of any of the above embodiments.

[0084] In one embodiment, the chip includes a chip substrate on which one or more composite diodes are disposed. The composite diodes can be fabricated by the fabrication method in any of the above embodiments, or the composite diodes in any of the above embodiments can be disposed on the chip substrate.

[0085] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the composite diode.

[0086] In one specific application embodiment, the chip can be a switch chip, a driver chip, or a radio frequency chip.

[0087] The beneficial effects of the embodiments in this application compared with the prior art are:

[0088] By forming a buffer layer, a GaN layer, and an AlGaN layer in a first predetermined region of an N-type silicon substrate, and forming multiple P-type injection regions at predetermined intervals in a second predetermined region of the N-type silicon substrate, multiple parallel silicon-based diodes are obtained, formed by the multiple P-type injection regions and the N-type silicon substrate. This allows the heat released when current flows through the silicon-based diode to cancel out the heat absorbed when current flows through the buffer layer, GaN layer, and AlGaN layer, thereby enabling the formed device (composite diode) to maintain a constant temperature during operation. This solves the problem of voltage drop drift during forward conduction of the diode with temperature, improves the stability of the device, and expands the application scenarios of the diode device.

[0089] In addition, this application forms a plurality of P-type injection regions at predetermined intervals in the second predetermined region of the N-type silicon substrate to form a junction barrier Schottky diode (JBS), thereby increasing the device's surge protection capability, improving the breakdown voltage (BV), and increasing the device's electron mobility due to the two-dimensional electron gas (2DEG) introduced by the GaN layer and AlGaN layer, resulting in increased current.

[0090] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A composite diode, characterized in that, The composite diode includes: N-type silicon substrate; A buffer layer, a GaN layer, and an AlGaN layer are sequentially stacked in a first predetermined region of the N-type silicon substrate; Multiple P-type implantation regions are formed at preset intervals on a second preset region of the N-type silicon substrate, and each P-type implantation region forms a PN junction with the N-type silicon substrate; the first preset region and the second preset region do not contact each other; An anode metal layer is formed on a portion of the surface of each of the P-type injection regions and on the surface of the spacer regions between the P-type injection regions, and forms a Schottky contact with each of the spacer regions; A cathode metal layer is formed on a portion of the AlGaN layer and forms an ohmic contact with the AlGaN layer; An ohmic contact layer is formed on the N-type silicon substrate, and the ohmic contact layer is in contact with the buffer layer, the GaN layer and the AlGaN layer, but is not in contact with each of the P-type implantation regions.

2. The composite diode according to claim 1, characterized in that, The buffer layer, the GaN layer, and the AlGaN layer have the same shape, and the width of the buffer layer, the GaN layer, and the AlGaN layer is less than half the width of the N-type silicon substrate.

3. The composite diode according to claim 2, characterized in that, The width of the P-type implantation region is less than one-fifth the width of the N-type silicon substrate.

4. The composite diode according to claim 1, characterized in that, The area covered by the anode metal layer of a single P-type injection region is equal to half the area of ​​a single P-type injection region.

5. The composite diode according to claim 1, characterized in that, The depth of the P-type implantation region is greater than half the depth of the N-type silicon substrate.

6. The composite diode according to any one of claims 1-5, characterized in that, The ohmic contact layer has an L-shaped structure, and the horizontal portion of the ohmic contact layer contacts the N-type silicon substrate, while the vertical portion of the ohmic contact layer contacts the buffer layer, the GaN layer, and the AlGaN layer.

7. The composite diode according to claim 6, characterized in that, The vertical portion of the ohmic contact layer contacts the side portion of the AlGaN layer.

8. The composite diode according to any one of claims 1-5, characterized in that, The cathode metal layer is located on the AlGaN layer on the side away from the anode metal layer.

9. A method for fabricating a composite diode, characterized in that, The preparation method includes: A buffer layer, a GaN layer, and an AlGaN layer are sequentially stacked on a first predetermined region of an N-type silicon substrate. Multiple P-type implantation regions are formed at predetermined intervals in a second predetermined region of the N-type silicon substrate, and each P-type implantation region forms a PN junction with the N-type silicon substrate; the first predetermined region and the second predetermined region do not contact each other; An anode metal layer is formed on a portion of the surface of each of the P-type injection regions and on the surface of the spacer regions between the P-type injection regions; the anode metal layer forms a Schottky contact with each of the spacer regions; A cathode metal layer is formed on a portion of the AlGaN layer; the cathode metal layer forms an ohmic contact with the AlGaN layer; An ohmic contact layer is formed on the N-type silicon substrate, and the ohmic contact layer is in contact with the buffer layer, the GaN layer and the AlGaN layer, but is not in contact with each of the P-type implantation regions.

10. A chip, characterized in that, It includes the composite diode as described in any one of claims 1-8; or it includes the composite diode prepared by the preparation method described in claim 9.

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