Solar cell and method for preparing the same

Abstract

The present disclosure provides a solar cell, comprising: a substrate, a first emitter, a second emitter, an insulating spacer structure, a first electrode, and a second electrode; the substrate has a front surface and a back surface which are oppositely arranged; the first emitter and the second emitter are arranged on the back surface of the substrate, the first electrode is arranged on a side of the first emitter away from the substrate and electrically connected to the first emitter, and the second electrode is arranged on a side of the second emitter away from the substrate and electrically connected to the second emitter; the insulating spacer structure is arranged between the first emitter and the second emitter, and the first emitter and the second emitter are spaced apart by the insulating spacer structure. The insulating spacer structure effectively spaces the first emitter and the second emitter, avoiding the recombination of carriers at the interface between the first emitter and the second emitter, and thus can effectively reduce the reverse leakage current of the solar cell and improve the efficiency of the solar cell.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular, to a solar cell and a method for manufacturing the solar cell. Background Art

[0002] A solar cell is a device that can directly convert solar energy into electrical energy. Since solar energy has the characteristics of being almost infinite and clean, solar cells also have great development potential and application prospects.

[0003] A solar cell has a front surface for receiving sunlight and a back surface opposite thereto. Generally, the front surface of the solar cell has a positive electrode, and the back surface has a back electrode. Electrons and holes in the photo-generated carriers are respectively led out from the front surface and the back surface to form an electric current. However, the positive electrode located on the front surface will block part of the sunlight entering the solar cell, reducing the light absorption efficiency of the solar cell.

[0004] An interdigitated back contact (IBC) solar cell is a highly efficient cell structure. It arranges the electrodes on the back surface to improve the efficiency of the solar cell. However, there is a problem of excessive reverse leakage in currently mass-produced interdigitated back contact solar cells, which affects the efficiency of the solar cell. Summary of the Invention

[0005] Based on this, it is necessary to provide a solar cell for the problems in the above background art to reduce the reverse leakage of the solar cell and improve the efficiency of the solar cell.

[0006] According to some embodiments of the present disclosure, a solar cell is provided, which includes: a substrate, a first emitter, a second emitter, an insulating spacer structure, a first electrode, and a second electrode;

[0007] The substrate has a front surface and a back surface which are oppositely arranged; the first emitter and the second emitter are arranged on the back surface of the substrate, the first emitter has a first doping type, the second emitter has a second doping type opposite to the first doping type, the first electrode is arranged on a side of the first emitter away from the substrate and is electrically connected to the first emitter, and the second electrode is arranged on a side of the second emitter away from the substrate and is electrically connected to the second emitter;

[0008] The insulating spacer structure is arranged between the first emitter and the second emitter, and the first emitter and the second emitter are spaced apart by the insulating spacer structure.

[0009] In some embodiments of the present disclosure, the insulating spacer structure is annular, the first emitter is disposed in the area outside the ring of the insulating spacer structure, and the second emitter is disposed in the area inside the ring of the insulating spacer structure.

[0010] In some embodiments of the present disclosure, it further includes a doped remainder. The material and doping type of the doped remainder are the same as those of the first emitter. The doped remainder is disposed in the area inside the ring of the insulating spacer structure and is located between the second emitter and the insulating spacer structure.

[0011] In some embodiments of the present disclosure, the insulating spacer structure includes an annular spacer groove; optionally, the back surface of the substrate is exposed from the spacer groove.

[0012] In some embodiments of the present disclosure, the groove width of the spacer groove is 1 μm - 100 μm.

[0013] In some embodiments of the present disclosure, the insulating spacer structure further includes an insulating portion disposed in the spacer groove.

[0014] In some embodiments of the present disclosure, it further includes a back passivation layer. The back passivation layer is disposed on the side of the first emitter away from the substrate and on the side of the second emitter away from the substrate; optionally, the back passivation layer is integrally formed with the insulating portion.

[0015] In some embodiments of the present disclosure, it further includes a passivated contact structure disposed on the surface of the first emitter away from the substrate. The passivated contact structure includes a tunneling oxide layer and a polysilicon layer. The tunneling oxide layer and the polysilicon layer are sequentially stacked on the first emitter, and the polysilicon layer has the first doping type.

[0016] In some embodiments of the present disclosure, the thickness of the tunneling oxide layer is 1 nm - 2 nm; and / or,

[0017] The thickness of the polysilicon layer is 10 nm - 300 nm.

[0018] In some embodiments of the present disclosure, the back surface of the substrate has a first region and a second region outside the first region. The passivated contact structure is disposed on and covers the first region, and the insulating spacer structure is disposed on the second region.

[0019] In some embodiments of the present disclosure, there are multiple insulating spacer structures and multiple second emitters. The second electrode includes a connecting portion and multiple electrode portions. The multiple electrode portions are respectively in contact with the multiple second emitters. The electrode portions are disposed on the inner region of the ring of the insulating spacer structure. The connecting portion is connected to the adjacent electrode portions. The multiple electrode portions and the connecting portion are all disposed in the second region.

[0020] According to still some other embodiments of the present disclosure, there is also provided a method for manufacturing a solar cell, which includes the following steps:

[0021] Provide a substrate having a front side and a back side disposed opposite to each other;

[0022] Prepare a first doped layer covering the substrate on the back side of the substrate. The first doped layer has a first doping type;

[0023] Prepare an insulating spacer structure on the first doped layer. The first doped layer on one side of the insulating spacer structure is the first emitter;

[0024] Prepare a second emitter on the other side of the insulating spacer structure. The first emitter and the second emitter are spaced apart by the insulating spacer structure. The second emitter has a second doping type; and,

[0025] Prepare a first electrode electrically connected to the first emitter and a second electrode electrically connected to the second emitter.

[0026] In some embodiments of the present disclosure, the step of preparing the insulating spacer structure includes: etching the first doped layer to form an annular spacer groove penetrating through the first doped layer in the first doped layer. The insulating spacer structure includes the spacer groove.

[0027] In some embodiments of the present disclosure, after forming the spacer groove, there is also a step of placing the substrate in a texturing agent for cleaning and texturing treatment, so that a textured surface structure is formed on the front side of the substrate.

[0028] In some embodiments of the present disclosure, before preparing the second emitter, there is also: preparing an insulating passivation material on the back side of the substrate. The passivation material in the spacer groove forms an insulating portion. The insulating spacer structure includes the insulating portion; the passivation material on the passivation portion and the first doped layer forms a back passivation layer.

[0029] In some embodiments of the present disclosure, the step of preparing the first doped layer includes:

[0030] Sequentially prepare a tunneling oxide layer and a silicon material layer on the back side of the substrate;

[0031] The silicon material layer is subjected to doping element diffusion treatment and annealing treatment to form a polysilicon layer with a first doping type. During the annealing treatment, the doping elements are diffused into the material of the substrate to form a first doped layer covering the substrate.

[0032] In some embodiments of the present disclosure, the back surface of the substrate has a first region and a second region located outside the first region. After preparing the polysilicon layer, it further includes: removing the polysilicon layer and the tunneling oxide layer on the second region.

[0033] The solar cell provided by the present disclosure includes a first emitter and a second emitter disposed on the back surface of the substrate, and further includes an insulating spacer structure. The first emitter and the second emitter are spaced apart by the insulating spacer structure. By introducing the insulating spacer structure, the first emitter and the second emitter are effectively spaced apart, avoiding the recombination of carriers at the interface between the first emitter and the second emitter. Therefore, the reverse leakage of the solar cell can be effectively reduced, and the efficiency of the solar cell can be improved.

[0034] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly and implement it in accordance with the content of the specification, the following describes in detail with reference to the preferred embodiments of the present invention and the accompanying drawings. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0036] Figure 1 It is a schematic diagram of the back surface structure of a solar cell according to the present disclosure;

[0037] Figure 2 It is Figure 1 an enlarged schematic diagram of region A in

[0038] Figure 3 It is Figure 2 a schematic diagram of the cross-section BB' in

[0039] Figure 4 It is Figure 3 an enlarged schematic diagram of the insulating spacer structure in

[0040] Figure 5 It is Figure 2 a schematic diagram of the cross-section CC' in

[0041] Figure 6 Schematic diagram of the back structure of another solar cell of the present disclosure;

[0042] Figure 7 Schematic diagram of the preparation steps of a solar cell in the present disclosure;

[0043] Figure 8 Schematic diagram of the structure of the substrate;

[0044] Figure 9 It is to prepare a schematic diagram of the first doped layer on the basis of the structure shown in Figure 8 ;

[0045] Figure 10 It is to prepare a schematic diagram of the structure after removing part of the polysilicon layer and the tunneling oxide layer on the basis of the structure shown in Figure 9 ;

[0046] Figure 11 It is to prepare a schematic diagram of the spacer groove on the basis of the structure shown in Figure 10 ;

[0047] Figure 12 It is to prepare a schematic diagram of the passivation stack on the basis of the structure shown in Figure 11 ;

[0048] Among them, the meanings of the respective reference numerals are as follows:

[0049] 110. Substrate; 111. First region; 112. Second region; 1201. First doped layer; 121. First emitter; 122. First electrode; 131. Second emitter; 132. Second electrode; 1321. Electrode part; 1322. Connection part; 140. Insulating spacer structure; 141. Spacer groove; 142. Insulating part; 150. Doping remainder; 161. Tunneling oxide layer; 162. Polysilicon layer; 171. First back passivation layer; 172. Second back passivation layer; 181. First front passivation layer; 182. Second front passivation layer; 210. Substrate; 211. First region; 212. Second region; 221. First emitter; 222. First electrode; 231. Second emitter; 232. Second electrode; 240. Insulating spacer structure. Detailed implementation manners

[0050] For the convenience of understanding the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing particular embodiments only and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0052] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of this application.

[0053] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0054] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0055] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes as illustrated due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present application should not be construed as limited to the particular shapes of regions illustrated herein, but rather include shape deviations due to, for example, manufacturing. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of regions of the device and are not intended to limit the scope of the present application.

[0056] The present disclosure provides a solar cell, which includes: a substrate, a first emitter, a second emitter, an insulating spacer structure, a first electrode, and a second electrode;

[0057] The substrate has a front surface and a back surface that are oppositely disposed; the first emitter and the second emitter are disposed on the back surface of the substrate, the first emitter has a first doping type, the second emitter has a second doping type opposite to the first doping type, the first electrode is disposed on a side of the first emitter away from the substrate and is electrically connected to the first emitter, and the second electrode is disposed on a side of the second emitter away from the substrate and is electrically connected to the second emitter;

[0058] The insulating spacer structure is disposed between the first emitter and the second emitter, and the first emitter and the second emitter are spaced apart by the insulating spacer structure.

[0059] The solar cell provided by the present disclosure includes a first emitter and a second emitter disposed on the back surface of the substrate, and further includes an insulating spacer structure. The first emitter and the second emitter are spaced apart by the insulating spacer structure. By introducing the insulating spacer structure, the first emitter and the second emitter are effectively spaced apart, avoiding the recombination of carriers at the interface between the first emitter and the second emitter, and thus effectively reducing the reverse leakage current of the solar cell and improving the efficiency of the solar cell.

[0060] For ease of understanding the structure of the above solar cell, the Figure 1 present disclosure provides a schematic diagram of the back structure of a solar cell, Figure 2 showing Figure 1Schematic diagram of the enlarged structure of region A in Figure 3 shows Figure 2 Schematic cross-sectional structure diagram of the solar cell in at BB’, Figure 5 shows Figure 2 Schematic cross-sectional structure diagram of the solar cell in at CC’. Among them, Figure 1 In is omitted Figure 3 Regarding the first back passivation layer 171, the second back passivation layer 172, the polysilicon layer 162 and the tunneling oxide layer 161 in , in order to expose the first emitter 121, the second emitter 131 and the insulating spacer structure 140.

[0061] Please refer to Figures 1 - 2 As shown, the solar cell includes a substrate 110, a first emitter 121, a second emitter 131, an insulating spacer structure 140, a first electrode 122 and a second electrode 132.

[0062] Among them, the substrate 110 has a front surface and a back surface which are oppositely arranged. In the Figure 3 shown structure, the upper surface of the substrate 110 is the front surface, and the lower surface is the back surface. The first emitter 121, the second emitter 131, the first electrode 122 and the second electrode 132 are all arranged on the back surface of the substrate 110.

[0063] Referring to Figure 2 shown, both the first emitter 121 and the second emitter 131 are arranged on the back surface of the substrate 110. The first emitter 121 has a first doping type, and the second emitter 131 has a second doping type opposite to the first doping type. The first emitter 121 is used to export the carriers corresponding to the first doping type to the first electrode 122, and the second emitter 131 is used to export the carriers corresponding to the second doping type to the second electrode 132. It can be understood that the first doping type can be one of P-type and N-type, and the second doping type is the other of P-type and N-type. The first doping type and the second doping type can be prepared by doping different elements. For example, the first doping type is N-type and the second doping type is P-type. The first emitter 121 can be an N-type doped semiconductor, and the second emitter 131 can be a P-type doped semiconductor. The doping element of N-type doping can be a Group V element, such as phosphorus element. The element of P-type doping can be a Group III element, such as one or more of boron element, aluminum element and gallium element.

[0064] Among them, the conductivity type of the substrate 110 can be the same as that of the second emitter 131, that is, the substrate 110 has the second doping type. Further, the doping concentration of the second emitter 131 can be higher than the doping concentration of the substrate 110.

[0065] Among them, the first electrode 122 is disposed on a side of the first emitter 121 away from the substrate 110 and electrically connected to the first emitter 121, and the second electrode 132 is disposed on a side of the second emitter 131 away from the substrate 110 and electrically connected to the second emitter 131. It can be understood that the first electrode 122 can be electrically connected to the first emitter 121 by directly contacting the first emitter 121, or there can be other intermediate layers through which carriers can pass between the first electrode 122 and the first emitter 121. The second electrode 132 can be electrically connected to the second emitter 131 by directly contacting the second emitter 131, or there can be other intermediate layers through which carriers can pass between the second electrode 132 and the second emitter 131.

[0066] Referring to Figure 2 As shown, in some examples of this embodiment, the insulating structure is annular. It can be understood that annular means that the cross-section of the insulating spacer structure 140 is annular, and its three-dimensional shape can be an annular column, and annular can also be understood as a closed-loop cylinder or tube, that is, the insulating spacer structure 140 has an inner-ring region and an outer-ring region. The outer-ring region refers to the region outside the outer ring, and the inner-ring region refers to the region inside the inner ring.

[0067] The first emitter 121 is disposed in the outer-ring region of the insulating spacer structure 140, and the second emitter 131 is disposed in the inner-ring region of the insulating spacer structure 140, so that the first emitter 121 and the second emitter 131 are spaced apart by the insulating spacer structure 140. And the insulating spacer structure 140 insulates and spaces the inner-ring region and the outer-ring region, the first emitter 121 is located in the outer-ring region, and the second emitter 131 is located in the inner-ring region. Further, the insulating spacer structure 140 can be an insulating groove that spaces the outside and the inside, or an insulating material that spaces the outside and the inside, or an insulating groove provided with an insulating material.

[0068] In some examples of this embodiment, referring to Figure 3 As shown, the insulating spacer structure 140 includes an annular spacer groove 141, and the spacer groove 141 is formed between the first emitter 121 and the second emitter 131 to insulate and space the first emitter 121 and the second emitter 131.

[0069] Among them, the spacer groove 141 can be formed by etching. For example, the spacer groove 141 is prepared by laser etching. During the etching process, the etching can be carried out until the substrate 110 is exposed to insulate and space the first emitter 121 from the second emitter 131. At this time, the bottom wall of the spacer groove 141 is the substrate 110. In the actual preparation process, the substrate 110 should be cleaned after the spacer groove 141 is etched, which will form a textured structure on the substrate 110 at the bottom wall of the spacer groove 141, thereby affecting the light absorption efficiency on the front side of the substrate 110. In some examples of this embodiment, the part of the substrate 110 serving as the bottom wall of the groove has a textured structure, and the groove width of the spacer groove 141 ≤ 100 μm. By setting the width of the spacer groove 141 below 100 μm, the negative impact of the textured surface at the bottom wall of the spacer groove 141 on the light absorption efficiency can be minimized as much as possible, and at the same time, the requirements of a certain processing speed in the actual production process can be met.

[0070] Further, in some examples of this embodiment, the groove width of the spacer groove 141 is 1 μm - 100 μm. To reduce the negative impact of the textured surface at the bottom wall of the spacer groove 141 on the light absorption efficiency while ensuring the effective insulation of the spacer groove 141. As some examples, the groove width of the spacer groove 141 is 10 μm - 50 μm. Further optionally, the groove width of the spacer groove 141 is 15 μm - 30 μm.

[0071] In some examples of this embodiment, the insulating spacer structure 140, the first emitter 121 and the second emitter 131 are arranged in the same layer. Further, the first emitter 121 participates in forming the outer ring groove wall of the spacer groove 141, and the second emitter 131 participates in forming the inner ring groove wall of the spacer groove 141.

[0072] In some examples of this embodiment, a doped remainder 150 is further included. The material and doping type of the doped remainder 150 are the same as those of the first emitter 121. The doped remainder 150 is arranged in the inner ring region of the insulating spacer structure 140 and is located between the second emitter 131 and the insulating spacer structure 140.

[0073] In some examples of this embodiment, a passivated contact structure is further included. The passivated contact structure includes a tunneling oxide layer 161 and a polysilicon layer 162. The tunneling oxide layer 161 and the polysilicon layer 162 are sequentially stacked on the surface of the first emitter 121 away from the substrate 110. The polysilicon layer 162 has a first doping type. Among them, the passivated contact structure is used to reduce the contact recombination between the first emitter 121 and the first electrode 122 and improve the efficiency.

[0074] Among them, the thickness of the tunneling oxide layer 161 should be relatively thin so that carriers can pass through the tunneling oxide layer 161 and be led out to the polysilicon layer 162. In some examples of this embodiment, the thickness of the tunneling oxide layer 161 is 1 nm to 2 nm.

[0075] In some examples of this embodiment, the thickness of the polysilicon layer 162 is 10 nm to 300 nm.

[0076] Referring to Figure 1 As shown, in some examples of this embodiment, the back surface of the substrate 110 has a first region 111 and a second region 112 located outside the first region 111. Figure 1 The region inside the dotted line in [[ ]] is the second region 112, and the region outside the dotted line is the first region 111. The passivation contact structure is disposed on the first region 111 and covers the first region 111, and the insulating spacer structure 140 is disposed on the second region 112. In the actual preparation process, the passivation contact structure on the second region 112 can be removed by etching so that the passivation contact structure only covers the passivation contact structure of the first region 111. Further, the inner region of the ring of the insulating spacer structure 140 can also be located on the second region 112, and at this time, the second emitter 131 is also located on the second region 112.

[0077] Referring to Figure 1 As shown, in some examples of this embodiment, the second region 112 is a continuous region located between the first regions 111.

[0078] Referring to Figure 1 As shown, there are multiple insulating spacer structures 140 and second emitters 131. The second electrode 132 includes a connecting portion 1322 and multiple electrode portions 1321. The multiple electrode portions 1321 are respectively in contact with the multiple second emitters 131. The electrode portions 1321 are disposed on the inner region of the ring of the insulating spacer structure 140. The connecting portion 1322 connects the adjacent electrode portions 1321. The multiple electrode portions 1321 and the connecting portion 1322 are both disposed in the second region 112.

[0079] Among them, it can be understood that Figure 3 the second electrode 132 shown in [[ ]] is the electrode portion 1321 of the second electrode 132, and the electrode portion 1321 is directly in contact with the second emitter 131. Figure 5 the second electrode 132 shown in [[ ]] is the connecting portion 1322 of the second electrode 132, and the connecting portion 1322 is used to connect the adjacent electrode portions 1321.

[0080] Referring to Figure 3 and Figure 5As shown, in some examples of this embodiment, the front surface of the substrate 110 also has a matte structure to obtain a higher light absorption efficiency, and the bottom wall of the spacer groove 141 also has a matte structure. The matte structures on the front and back surfaces of the substrate 110 can be formed simultaneously in the same process step, or can be formed successively in different process steps respectively.

[0081] Referring to Figure 3 and Figure 4 As shown, in some examples of this embodiment, the insulating spacer structure 140 further includes an insulating portion 142 disposed in the spacer groove 141. Further, the solar cell further includes an insulating first back passivation layer 171, and the first back passivation layer 171 is disposed on the side of the first emitter 121 away from the substrate 110 and on the side of the second emitter 131 away from the substrate 110. Further, the first back passivation layer 171 and the insulating portion 142 are integrally formed.

[0082] Among them, the first back passivation layer 171 is used to passivate the surface of the solar cell. Generally, the passivation layer is disposed on the surface of the emitter layer to reduce surface recombination. In this embodiment, the first back passivation layer 171 and the insulating portion 142 are integrally formed, which can not only simplify the preparation process, but also the insulating portion 142 made of the passivation material can improve the interface recombination between the first emitter 121 and the second emitter 131.

[0083] In some examples of this embodiment, the solar cell may further include a second back passivation layer 172. The second back passivation layer 172 is disposed on the side of the first back passivation layer 171 away from the substrate 110. The second back passivation layer 172 is in contact with the first back passivation layer 171. The second back passivation layer 172 and the first back passivation layer 171 form a stacked passivation film to further improve the passivation effect.

[0084] In some examples of this embodiment, the materials of the first back passivation layer 171 and the second back passivation layer 172 are independently selected from one or more of silicon nitride, aluminum oxide, titanium oxide, silicon oxide, and silicon oxynitride. Among them, the material of the first back passivation layer 171 may be different from the material of the second back passivation layer 172.

[0085] Referring to Figure 3 and Figure 5 As shown, in some examples of this embodiment, the solar cell may further include a first front passivation layer 181 and a second front passivation layer 182. The first front passivation layer 181 and the second front passivation layer 182 are sequentially stacked on the front surface of the substrate 110. Among them, the first front passivation layer 181 and the second front passivation layer 182 form a stacked passivation film to further improve the passivation effect.

[0086] In some examples of this embodiment, the materials of the first positive passivation layer 181 and the second positive passivation layer 182 are independently selected from one or more of silicon nitride, aluminum oxide, titanium oxide, silicon oxide, and silicon oxynitride.

[0087] Referring to Figure 1 and Figure 3 As shown, in some examples of this embodiment, a part of the outer edge of the insulating spacer structure 140 may be flush with the edge of the second region 112.

[0088] Referring to Figure 1 and Figure 3 As shown, in some examples of this embodiment, a doped remainder 150 may also be provided in the inner region of the ring of the insulating spacer structure 140. The doped remainder 150 is located between the second emitter 131 and the insulating spacer structure 140, and the material and doping type of the doped remainder 150 are the same as those of the first emitter 121.

[0089] Figure 6 The schematic diagram of the back structure of another solar cell of the present disclosure is shown. Referring to Figure 6 As shown, the solar cell includes a substrate 210, a first emitter 221, a second emitter 231, a first electrode 222, a second electrode 232, and an insulating spacer structure 240. The substrate 210 has a first region 211 and a second region 212. The relative positional relationship between the components is similar to that of the solar cell in Figure 1 , and will not be elaborated here. Different from the solar cell shown in Figure 1 , only the second emitter 231 is provided in the inner region of the ring of the insulating spacer structure 240, and there is no doped remainder. At this time, the inner ring edge of the insulating spacer structure 240 is close to the edge of the second emitter 231.

[0090] It can be understood that in other embodiments, the outer ring edge of the insulating spacer structure can also be adjusted between the edge of the second region and the edge of the second emitter.

[0091] Furthermore, the present disclosure also provides a method for manufacturing the above-mentioned solar cell. The manufacturing method includes the following steps:

[0092] Provide a substrate having a front side and a back side disposed opposite to each other;

[0093] Prepare a first doped layer on the back side of the substrate to cover the substrate. The first doped layer has a first doping type;

[0094] Prepare an annular insulating spacer structure on the first doped layer, and use the first doped layer located outside the ring of the insulating spacer structure as the first emitter;

[0095] Fabricate a second emitter in contact with the substrate within the ring of the insulating spacer structure, the second emitter having a second doping type; and,

[0096] Fabricate a first electrode electrically connected to the first emitter and a second electrode electrically connected to the second emitter.

[0097] The method for fabricating the solar cell forms an annular insulating spacer structure in the first doped layer, and then fabricates a second emitter within the ring of the annular insulating spacer structure, such that there is an insulating spacer between the first emitter and the second emitter, avoiding carrier recombination at the interface between the first emitter and the second emitter and reducing leakage current. Moreover, by providing the insulating spacer structure, the first doped layer in the region within the ring of the insulating spacer structure can be used as a protective layer to prevent the formation of a textured structure on the substrate in the region within the ring, reducing the impact on the light absorption efficiency of the solar cell caused by introducing the insulating spacer structure.

[0098] In some examples of this embodiment, the step of fabricating the insulating spacer structure includes: etching the first doped layer to form an annular spacer groove penetrating the first doped layer, and the insulating spacer structure includes the spacer groove.

[0099] In some examples of this embodiment, after forming the spacer groove, the steps further include placing the substrate in a texturing agent for cleaning and texturing processes to form a textured structure on the front surface of the substrate.

[0100] In some examples of this embodiment, before fabricating the second emitter, the steps further include: fabricating an insulating passivation material on the back surface of the substrate, the passivation material located in the spacer groove forms an insulating portion, and the insulating spacer structure includes the insulating portion; the passivation material located on the passivation portion and the first doped layer forms a back passivation layer.

[0101] In some examples of this embodiment, the step of fabricating the first doped layer includes: sequentially fabricating a tunneling oxide layer and a silicon material layer on the back surface of the substrate; performing a doping element diffusion process and an annealing process on the silicon material layer to form a polysilicon layer having a first doping type, and during the annealing process, allowing the doping element to diffuse into the material of the substrate to form the first doped layer covering the substrate.

[0102] In some examples of this embodiment, the back surface of the substrate has a first region and a second region outside the first region. After fabricating the polysilicon layer, the steps further include: removing the polysilicon layer and the tunneling oxide layer on the second region.

[0103] Furthermore, Figure 7 shows Figure 1 a schematic diagram of the steps of the method for fabricating the solar cell in Figure 7 As shown, the method for fabricating the solar cell includes steps S1 to S6.

[0104] Step S1, provide a substrate.

[0105] Referring Figure 8 As shown, the substrate 110 has a front side and a back side which are oppositely arranged, and the back side of the substrate 110 is located below the substrate 110. Among them, the material of the substrate 110 can be silicon, such as single-crystalline silicon. The substrate 110 can have a second doping type, for example, the substrate 110 is a P-type doped silicon material.

[0106] In some examples of this embodiment, it further includes the step of texturing the front side of the substrate 110. Texturing the front side of the substrate 110 can include: placing the substrate 110 in a texturing agent to form a textured surface structure on the front side of the substrate 110. Among them, the textured surface structure can be pyramid-shaped.

[0107] In some examples of this embodiment, it further includes the step of polishing the back side of the substrate 110. Among them, chemical polishing agents can be selected for polishing during the polishing process.

[0108] Among them, the back side of the substrate 110 has a first region 111 and a second region 112. The second region 112 corresponds to the part that needs to be removed in the subsequent passivated contact structure to be prepared, and the first region 111 is located outside the second region 112.

[0109] Step S2, prepare a first doped layer on the substrate.

[0110] Among them, the first doped layer 1201 can be formed based on the material of the substrate 110, or it can be a new material layer deposited on the surface of the existing substrate 110. In some examples of this embodiment, the first doped layer 1201 can be doped on the back side of the substrate 110 to form. For example, the doping type of the first doped layer 1201 is N-type, and when preparing, the first doped layer 1201 can be prepared on the back side of the substrate 110 by phosphorus diffusion.

[0111] In some examples of this embodiment, the step of preparing the first doped layer 1201 can include: sequentially preparing a tunneling oxide layer 161 and a silicon material layer on the back side of the substrate 110; performing doping element diffusion treatment and annealing treatment on the silicon material layer to form a polysilicon layer 162 with a first doping type. It can be understood that during the doping element diffusion treatment and annealing treatment, the doping elements will also diffuse into the material of the substrate 110 to form a first emitter 121 covering the substrate 110. In this way, not only a first emitter 121 with a first doping type is formed on the substrate 110, but also a passivated contact structure is formed to reduce interface recombination and further improve the efficiency of the solar cell.

[0112] Figure 9 Shows in Figure 8Schematic diagram of the structure of further preparing a first passivation layer, a tunneling oxide layer 161, and a polysilicon layer 162 on the shown structure. Refer to Figure 9 As shown, a first doping layer 1201 covers the back surface of the substrate 110. The first doping layer 1201 is used to form a first emitter 121 in subsequent manufacturing processes. It can be understood that only a part of the first doping layer 1201 is used as the first emitter 121, and a part of the first doping layer 1201 is removed in subsequent manufacturing processes. Optionally, a part of the first doping layer 1201 is not removed but remains as an ineffective part.

[0113] In some examples of this embodiment, after forming the first doping layer 1201, it further includes a step of removing the side and front surface plating of the substrate 110.

[0114] Refer to Figure 9 As shown, the passivated contact structure includes a tunneling oxide layer 161 and a polysilicon layer 162 arranged in a stacked manner. In some examples of this embodiment, the steps of preparing the passivated contact structure include: sequentially preparing a tunneling oxide layer 161 and a polysilicon layer 162 on the first doping layer 1201, wherein the polysilicon layer 162 has a first doping type.

[0115] Among them, the tunneling oxide layer 161 can be prepared by oxidizing a part of the first doping layer 1201, or can be prepared on the first doping layer 1201 by a deposition method. In some examples of this embodiment, the tunneling oxide layer 161 is prepared on the first doping layer 1201 by chemical vapor deposition.

[0116] Among them, the polysilicon layer 162 can be prepared by a deposition method. Further, the polysilicon layer 162 can be directly doped during the deposition process, or can be doped after forming the polysilicon layer 162. In some examples of this embodiment, first, an amorphous silicon layer is deposited on the surface of the tunneling oxide layer 161 by chemical vapor deposition, then the amorphous silicon layer is doped, and then the amorphous silicon layer is annealed to form a polysilicon layer 162 with a first doping type.

[0117] It can be understood that in this step S2, the tunneling oxide layer 161 and the polysilicon layer 162 cover the entire first doping layer 1201.

[0118] Step S3, removing the polysilicon layer and the tunneling oxide layer on the second region.

[0119] Figure 10 Shows Figure 9 Schematic diagram of the structure of removing a part of the polysilicon layer 162 and the tunneling oxide layer 161 on the basis of the shown structure. Refer to Figure 10As shown, the partial polysilicon layer 162 and the tunneling oxide layer 161 located on the second region 112 are removed. It can be understood that there is no polysilicon layer 162 and tunneling oxide layer 161 on the second region 112.

[0120] Among them, the method of removing the polysilicon layer 162 and the tunneling oxide layer 161 can be selected from etching. The specific method of etching can be selected from wet etching or laser etching.

[0121] In some examples of this embodiment, the polysilicon layer 162 and the tunneling oxide layer 161 are removed by laser etching.

[0122] It can be understood that after removing the polysilicon layer 162 and the tunneling oxide layer 161 on the second region 112, a part of the first doped layer 1201 on the second region 112 is exposed, and the first doped layer 1201 can be used as a protective layer for the substrate 110.

[0123] Step S4, prepare an annular spacer groove on the first doped layer.

[0124] In some examples of this embodiment, the step of preparing the spacer groove 141 includes: removing a part of the first doped layer 1201 to form an annular spacer groove 141.

[0125] Figure 11 Shows the structural schematic diagram of preparing the spacer groove 141 based on the Figure 10 shown structure. Referring to Figure 11 As shown, a part of the first doped layer 1201 on the second region 112 is removed to form an annular spacer groove 141. The first doped layer 1201 in the outer region of the ring of the spacer groove 141 serves as the first emitter 121, while the first doped layer 1201 in the inner region of the ring of the spacer groove 141 can be retained and used as the doped remainder 150. The first emitter 121 and the doped remainder 150 are insulated and spaced apart.

[0126] In some examples of this embodiment, the spacer groove 141 penetrates through the first doped layer 1201 so that the bottom of the spacer groove 141 is the substrate 110.

[0127] In some examples of this embodiment, the method of removing the first doped layer 1201 is laser etching.

[0128] In some examples of this embodiment, in the step of preparing the annular spacer groove 141, the groove width of the spacer groove 141 is controlled ≤ 100 μm. Further, the groove width of the spacer groove 141 can be controlled to be 1 μm to 100 μm. As some examples, the groove width of the spacer groove 141 is 10 μm to 50 μm. Further optionally, the groove width of the spacer groove 141 is 15 μm to 30 μm.

[0129] It can be understood that after forming the spacer groove 141 by laser etching, there is still residual material on the surface of the substrate 110. Therefore, the substrate 110 needs to be chemically cleaned.

[0130] In some examples of this embodiment, a texturing agent is used to chemically clean the substrate 110 to prepare a textured structure on the front surface of the substrate 110 while cleaning the substrate 110, simplifying the preparation process. It can be understood that the substrate 110 in the inner region of the ring of the spacer groove 141 is covered by the doped remainder 150. Therefore, only the part of the substrate 110 exposed from the spacer groove 141 will form a textured structure.

[0131] It can be understood that if instead of forming the ring-shaped spacer groove 141, all of the first doping layer 1201 in the inner region of the ring of the spacer groove 141 is removed, the substrate 110 on all regions (i.e., the second region 112) not covered by the doped remainder 150 will form a textured structure, which will significantly reduce the light absorption efficiency of the substrate 110, resulting in a low efficiency of the solar cell.

[0132] Step S5, preparing a first back passivation layer, a second back passivation layer, a first front passivation layer, and a second front passivation layer.

[0133] Figure 12 shows on Figure 11 a schematic structural diagram of preparing a passivation stack based on the shown structure. Referring to Figure 12 as shown, the first back passivation layer 171 covers the back surface of the substrate 110. Further, when preparing the first back passivation layer 171, the passivation material is also filled into the spacer groove 141 to form an insulating portion 142. It can be understood that the passivation material should be selected from insulating materials to prevent conduction between the first emitter 121 and the doped remainder 150.

[0134] In some examples of this embodiment, the materials of the first back passivation layer 171 and the first front passivation layer 181 are the same. During the preparation process, the first back passivation layer 171 and the first front passivation layer 181 can be prepared simultaneously on the front and back surfaces of the substrate 110.

[0135] In some examples of this embodiment, after preparing the first back passivation layer 171 and the first front passivation layer 181, it further includes the step of preparing a second back passivation layer 172 and a second front passivation layer 182.

[0136] In some examples of this embodiment, the materials of the second back passivation layer 172 and the second front passivation layer 182 are the same. During the preparation process, the second back passivation layer 172 and the second front passivation layer 182 can be prepared simultaneously on the front and back surfaces of the substrate 110.

[0137] Step S6, preparing a second emitter, a first electrode, and a second electrode.

[0138] It can be understood that after step S6, a cross-sectional structure of the solar cell as shown in Figure 3 can be formed. Among them, the first electrode 122 passes through the first back passivation layer 171 and the second back passivation layer 172 and then contacts the polysilicon layer 162, and is electrically connected to the first emitter 121 through the tunneling oxide layer 161 and the polysilicon layer 162.

[0139] In some examples of this embodiment, in the step of preparing the first electrode 122, the tunneling oxide layer 161 and the polysilicon layer 162 are first etched to form a first connection hole, and then a conductive material is filled in the first connection hole to form the first electrode 122.

[0140] In some examples of this embodiment, the material of the first electrode 122 can be one or more of silver and copper.

[0141] In some examples of this embodiment, the second emitter 131 can be prepared by co-sintering the material of the second electrode 132 with the material of the substrate 110.

[0142] The second electrode 132 passes through the first back passivation layer 171 and the second back passivation layer 172, and the second electrode 132 contacts the second emitter 131.

[0143] In some examples of this embodiment, in the step of preparing the second electrode 132, the tunneling oxide layer 161 and the polysilicon layer 162 can be first etched to form a second connection hole, and then the material of the second electrode 132 is filled in the second connection hole, and a sintering treatment is performed to form the second emitter 131 and the second electrode 132.

[0144] Among them, the material of the second electrode 132 can include aluminum.

[0145] It can be understood that through step S1 to step S6, a solar cell structure shown in the present disclosure can be prepared.

[0146] For the convenience of understanding the specific implementation manner and advantages of the solar cell of the present disclosure, the present disclosure further provides the following examples and comparative examples. Through the differences between the examples and the comparative examples, the advantages of the solar cell of the present disclosure will also be obvious.

[0147] Example 1

[0148] Using a P-type monocrystalline silicon wafer as the substrate, the substrate is subjected to alkaline polishing to remove the mechanical damage layer and contaminants on the surface of the substrate;

[0149] Deposit a tunneling oxide layer with a thickness of 2 nm and an amorphous silicon layer with a thickness of 100 nm on the back of the substrate. Perform phosphorus doping treatment and annealing treatment on the amorphous silicon layer to convert the amorphous silicon layer into an N-type polycrystalline silicon layer, and form a first doped layer under the tunneling oxide layer;

[0150] Remove the polycrystalline silicon layer and the tunneling oxide layer on the second region by laser etching to expose the first doped layer;

[0151] Etch a plurality of annular spacer grooves on the first doped layer in the second region by laser etching, with the groove width of the spacer grooves being 25 μm; the first doped layer in the outer region of the ring serves as the first emitter, and the first doped layer in the inner region of the ring serves as the doped remainder. Then, clean and texture the substrate in a texturing agent to form a textured structure on the front surface of the substrate and the back surface exposed by the spacer grooves;

[0152] Deposit an alumina layer on both the front and back surfaces of the substrate as the first front passivation layer and the first back passivation layer, and then deposit a silicon nitride film layer as the second front passivation layer and the second back passivation layer;

[0153] Perform film opening treatment by laser etching to expose part of the polycrystalline silicon layer and part of the substrate in the second region;

[0154] Screen-print silver paste on the polycrystalline silicon layer and screen-print aluminum paste on the second region of the substrate. Sinter to form a second emitter at the part where the aluminum paste contacts the substrate, and form a first electrode with the silver paste and a second electrode with the aluminum paste.

[0155] Example 2

[0156] Use a P-type single-crystalline silicon wafer as the substrate. Perform alkaline polishing on the substrate to remove the mechanical damage layer and contaminants on the surface of the substrate, and then prepare a textured structure on the front surface of the substrate;

[0157] Deposit a tunneling oxide layer with a thickness of 2 nm and an amorphous silicon layer with a thickness of 100 nm on the back of the substrate. Perform phosphorus doping treatment and annealing treatment on the amorphous silicon layer to convert the amorphous silicon layer into an N-type polycrystalline silicon layer, and form a first doped layer under the tunneling oxide layer;

[0158] Remove the polycrystalline silicon layer and the tunneling oxide layer on the second region by laser etching to expose the first doped layer;

[0159] Etch a plurality of annular spacer grooves on the first doped layer in the second region by laser etching, with the groove width of the spacer grooves being 20 μm; the first doped layer in the outer region of the ring serves as the first emitter, and the first doped layer in the inner region of the ring serves as the doped remainder. Then, clean the substrate in a texturing agent;

[0160] An alumina layer is deposited on both the front and back sides of the substrate as the first front passivation layer and the first back passivation layer, and then a silicon nitride film layer is deposited as the second front passivation layer and the second back passivation layer;

[0161] Laser etching is used for film opening treatment to expose part of the polysilicon layer and part of the substrate in the second region;

[0162] Silver paste is screen-printed on the polysilicon layer, and aluminum paste is screen-printed on the second region of the substrate. Sintering makes the part where the aluminum paste contacts the substrate form the second emitter, and makes the silver paste form the first electrode and the aluminum paste form the second electrode.

[0163] Comparative Example 1

[0164] Using a P-type monocrystalline silicon wafer as the substrate, the substrate is subjected to alkaline polishing to remove the mechanical damage layer and contaminants on the surface of the substrate;

[0165] Phosphorus doping is carried out on the back side of the substrate to form an N-type first doping layer;

[0166] A tunneling oxide layer with a thickness of 2 nm and an amorphous silicon layer with a thickness of 100 nm are deposited on the back side of the substrate. The amorphous silicon layer is subjected to phosphorus doping treatment and annealing treatment to convert the amorphous silicon layer into an N-type polysilicon layer;

[0167] The polysilicon layer on the second region of the back side is sequentially removed by wet etching;

[0168] The substrate is placed in a texturing agent for cleaning and texturing treatment to form a textured surface structure on the front side of the substrate;

[0169] An alumina layer is deposited on both the front and back sides of the substrate as the first front passivation layer and the first back passivation layer, and then a silicon nitride film layer is deposited as the second front passivation layer and the second back passivation layer;

[0170] Laser etching is used for film opening treatment to expose the polysilicon layer in the N region and the substrate in the P region;

[0171] Silver paste is screen-printed in the N region, and aluminum paste is screen-printed in the P region. Sintering makes the part where the aluminum paste contacts the substrate form the second emitter, and makes the silver paste form the first electrode and the aluminum paste form the second electrode.

[0172] Comparative Example 2

[0173] Using a P-type monocrystalline silicon wafer as the substrate, the substrate is subjected to alkaline polishing to remove the mechanical damage layer and contaminants on the surface of the substrate;

[0174] Deposit a tunneling oxide layer with a thickness of 2 nm and an amorphous silicon layer with a thickness of 100 nm on the back side of the substrate. Perform phosphorus doping treatment and annealing treatment on the amorphous silicon layer to convert the amorphous silicon layer into an N-type polysilicon layer, and form a first doping layer under the tunneling oxide layer;

[0175] Remove the polysilicon layer and the tunneling oxide layer on the second region by laser etching to expose the first doping layer;

[0176] Remove the first doping layer on the entire second region by laser etching, and then place the substrate in a texturing agent for cleaning and texturing treatment to form a textured surface structure on the second region on the back side of the substrate and on the front side;

[0177] Deposit an alumina layer on both the front and back sides of the substrate as the first front passivation layer and the first back passivation layer, and then deposit a silicon nitride film layer as the second front passivation layer and the second back passivation layer;

[0178] Perform film opening treatment by laser etching to expose a part of the polysilicon layer and a part of the substrate in the second region;

[0179] Screen-print silver paste on the polysilicon layer and screen-print aluminum paste on the second region of the substrate. Sinter to form a second emitter at the part where the aluminum paste contacts the substrate, and form a first electrode with the silver paste and a second electrode with the aluminum paste.

[0180] Experiment: Test the efficiency of the solar cells of Examples 1 to 2 and Comparative Examples 1 to 2 and the reverse leakage current at a reverse voltage of 11 V. The results can be seen in Table 1. Among them, in the column evaluating the reverse leakage current, the reverse leakage current is divided into two intervals. "<1" means that the reverse leakage current of the solar cells is all below 1 A, indicating that its reverse leakage current is suppressed. ">5" means that the reverse leakage current of the solar cells is all above 5 A, indicating that its reverse leakage current is relatively serious.

[0181] Table 1

[0182]

[0183] Referring to Table 1, compared with Examples 1 and 2, the reverse leakage current of Comparative Example 1 is significantly higher. This is mainly because no spacer grooves are prepared in the first emitter in Comparative Example 1, and there is no insulating spacer structure in the present disclosure, resulting in a problem of high leakage current. Although the reverse leakage current of Comparative Example 2 is reduced, its efficiency is also significantly reduced. This is mainly because in the preparation process of Comparative Example 2, the first doping layer on the entire second region is removed and then texturing treatment is performed, which results in a textured surface structure in the entire second region, thereby reducing the efficiency.

[0184] It should be understood that, unless otherwise clearly specified herein, there is no strict order restriction for the execution of the described steps, and these steps can be executed in other orders. Moreover, at least a part of the described steps may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily need to be completed at the same moment, but can be executed at different moments, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0185] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0186] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

Claims

1. A solar cell, characterized in that, comprising: a substrate, a first emitter, a second emitter, an insulating spacer structure, a first electrode and a second electrode; the substrate has a front surface and a back surface which are oppositely arranged; the first emitter and the second emitter are arranged on the back surface of the substrate, the first emitter has a first doping type, the second emitter has a second doping type opposite to the first doping type, the first electrode is arranged on a side of the first emitter away from the substrate and is electrically connected to the first emitter, and the second electrode is arranged on a side of the second emitter away from the substrate and is electrically connected to the second emitter; the insulating spacer structure is arranged between the first emitter and the second emitter, and the first emitter and the second emitter are spaced apart by the insulating spacer structure; the insulating spacer structure includes an annular spacer groove and an insulating portion arranged in the spacer groove.

2. The solar cell according to claim 1, characterized in that, the insulating spacer structure is annular, the first emitter is arranged in an outer region of the ring of the insulating spacer structure, and the second emitter is arranged in an inner region of the ring of the insulating spacer structure.

3. The solar cell according to claim 2, characterized in that, further comprising a doping remainder portion, the material and doping type of the doping remainder portion are the same as those of the first emitter, the doping remainder portion is arranged in the inner region of the ring of the insulating spacer structure and is located between the second emitter and the insulating spacer structure.

4. The solar cell according to any one of claims 1 to 3, characterized in that, the back surface of the substrate is exposed from the spacer groove.

5. The solar cell according to claim 4, characterized in that, the groove width of the spacer groove is 1 μm - 100 μm.

6. The solar cell according to claim 1, characterized in that, further comprising a back passivation layer, the back passivation layer is arranged on a side of the first emitter away from the substrate and on a side of the second emitter away from the substrate.

7. The solar cell according to claim 6, characterized in that, the back passivation layer and the insulating portion are integrally formed.

8. The solar cell according to any one of claims 1 to 7, characterized in that, further comprising a passivated contact structure arranged on a surface of the first emitter away from the substrate, the passivated contact structure includes a tunneling oxide layer and a polysilicon layer, the tunneling oxide layer and the polysilicon layer are sequentially stacked on the first emitter, and the polysilicon layer has the first doping type.

9. The solar cell according to claim 8, characterized in that, the thickness of the tunneling oxide layer is 1 nm - 2 nm; and / or, the thickness of the polysilicon layer is 10 nm - 300 nm.

10. The solar cell according to claim 8, characterized in that, the back surface of the substrate has a first region and a second region located outside the first region, the passivated contact structure is arranged on the first region and covers the first region, and the insulating spacer structure is arranged on the second region.

11. The solar cell according to claim 10, wherein, there are a plurality of the insulation spacing structures and the second emitters, the second electrode includes a connection part and a plurality of electrode parts, the plurality of electrode parts are respectively in contact with the plurality of second emitters, the electrode parts are arranged on the inner area of the ring of the insulation spacing structure, the connection part is connected to the adjacent electrode parts, and the plurality of electrode parts and the connection part are all arranged in the second area.

12. A method for manufacturing a solar cell, wherein, it includes the following steps: providing a substrate having a front side and a back side which are oppositely arranged; preparing a first doped layer covering the substrate on the back side of the substrate, the first doped layer having a first doping type; preparing an insulation spacing structure on the first doped layer, and the first doped layer on one side of the insulation spacing structure is a first emitter; preparing a second emitter on the other side of the insulation spacing structure, the first emitter and the second emitter being spaced apart by the insulation spacing structure, the second emitter having a second doping type; and, preparing a first electrode electrically connected to the first emitter and preparing a second electrode electrically connected to the second emitter; the step of preparing the insulation spacing structure includes: removing a part of the first doped layer to form an annular spacing groove, and the insulation spacing structure includes the spacing groove; before preparing the second emitter, it further includes: preparing an insulating passivation material on the back side of the substrate, and the passivation material in the spacing groove forms an insulating part, and the insulation spacing structure includes the insulating part.

13. The method for manufacturing a solar cell according to claim 12, wherein, the spacing groove penetrates through the first doped layer.

14. The method for manufacturing a solar cell according to claim 12, wherein, after forming the spacing groove, it further includes the steps of placing the substrate in a texturing agent for cleaning treatment and texturing treatment, so that a textured surface structure is formed on the front side of the substrate.

15. The method for manufacturing a solar cell according to claim 12, wherein, in the step of preparing the insulating passivation material on the back side of the substrate, the passivation material on the insulating part and the first doped layer forms a back passivation layer.

16. The method for manufacturing a solar cell according to any one of claims 12 to 15, wherein, the step of preparing the first doped layer includes: sequentially preparing a tunneling oxide layer and a silicon material layer on the back side of the substrate; performing doping element diffusion treatment and annealing treatment on the silicon material layer to form a polysilicon layer having a first doping type, and during the annealing treatment, enabling the doping element to diffuse into the material of the substrate to form a first doped layer covering the substrate.

17. The method for manufacturing a solar cell according to claim 16, wherein, the back side of the substrate has a first area and a second area outside the first area, and after preparing the polysilicon layer, it further includes: removing the polysilicon layer and the tunneling oxide layer on the second area.

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