Decoding method and decoding device

Abstract

The present disclosure provides a decoding method and a decoding device. The decoding method includes: dividing a to-be-decoded bit sequence into m to-be-decoded sub-segments; independently decoding the m to-be-decoded sub-segments to obtain 2s candidate paths with the highest probability of occurrence of the a-bit sequence of the m a-sub-segments; using a combination of the 2s candidate paths of the a-bit sequence to obtain r candidate paths with the highest probability of occurrence of the v-bit sequence of the corresponding v-sub-segment; using a combination of multiple candidate paths with the highest probability of occurrence of the v-bit sequence to obtain q candidate paths with the highest probability of occurrence of the v-bit sequence; splitting the s candidate paths with the highest probability of occurrence among the q candidate paths of the v-bit sequence into m v-sub-segments, performing path splitting on the s candidate paths of the corresponding a-sub-segment included in the m v-sub-segments to obtain 2s candidate paths for the next a-bit; and obtaining a corresponding decoding result based on the Lmax candidate paths with the highest probability of occurrence of the v-bit sequence.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a decoding method and a decoding device. Background Art

[0002] In the Successive Cancellation List (SCL) decoding scheme for polar codes, the bit sequence to be decoded is split into multiple mutually coupled subsegments of equal length. Each subsegment undergoes independent SCL decoding. The decoding results of each subsegment (defined as a bit space) are then jointly processed to obtain the decoding result of the polar code (defined as v bit space). Summary of the Invention

[0003] The inventors have noticed that in the process of jointly processing the sub-segment decoding results, it is necessary to enumerate and combine multiple alternative paths of two bit values ​​of multiple a bits. As the number of sub-segments increases, the computational complexity becomes very high.

[0004] Accordingly, the present disclosure provides a decoding solution that can effectively reduce computational complexity.

[0005] According to a first aspect of an embodiment of the present disclosure, a decoding method is provided, comprising: dividing a received bit sequence to be decoded of length N into m sub-segments to be decoded of length n; independently decoding the m sub-segments to be decoded to obtain 2s candidate paths with the highest probability of occurrence of the a-bit sequences of the m a-sub-segments; using a combination of the 2s candidate paths of the a-bit sequences corresponding to the m a-sub-segments to obtain r candidate paths with the highest probability of occurrence of the v-bit sequences of the corresponding v-sub-segments; and using the probability of occurrence of the v-bit sequences of the m v-sub-segments to obtain r candidate paths with the highest probability of occurrence of the v-bit sequences of the corresponding v-sub-segments. The combination of the largest multiple alternative paths obtains q alternative paths with the highest probability of occurrence of a v-bit sequence with a length of m times the v-subsegment; the s alternative paths with the highest probability of occurrence among the q alternative paths of the v-bit sequence with a length of m times the v-subsegment are split into m v-subsegments, and the s alternative paths of the corresponding a-subsegments included in the m v-subsegments are split to obtain 2s candidate paths for the next a-bit in the decoding process; the corresponding decoding result is obtained according to the Lmax alternative paths with the highest probability of occurrence of the v-bit sequence with a length of N.

[0006] In some embodiments, N, m, and n are all integer powers of 2; s≤L; s≤r≤Lmax; r≤q≤Lmax; L≤Lmax≤2L; and the decoding process is polar code SCL decoding.

[0007] In some embodiments, independently decoding the m sub-segments to be decoded to obtain 2s candidate paths with the highest probability of occurrence of the a-bit sequences of the m a-subsegments, respectively, includes: decoding the bits in the m sub-segments to be decoded bit by bit in sequence to obtain 2s candidate paths with the highest probability of occurrence of the a-bits in the corresponding positions of the m a-subsegments, respectively, until the decoding processing of each bit in the sub-segment to be decoded is completed; the 2s candidate paths with the highest probability of occurrence of the a-bits are the 2s candidate paths with the highest probability of occurrence of the a-bit sequences composed of the a-bits that have been decoded and the a-bits currently being processed in the a-subsegment.

[0008] In some embodiments, the combination of 2s candidate paths of the a-bit sequences corresponding to the m a-subsegments is used to obtain r alternative paths with the highest probability of occurrence of the v-bit sequence of the corresponding v-subsegment, including: for each a-bit at the same position of the m a-subsegments, the probability of occurrence of the 2s candidate paths is arranged in descending order; the maximum probability of occurrence paths of the a-bits at the same position of the m a-subsegments are combined into the alternative paths with the highest probability of occurrence of the v-bits at the same position of the corresponding v-subsegment; the maximum probability of occurrence path is replaced by other paths except the maximum probability of occurrence path of the a-bits at the same position of the m a-subsegments, and the path occurrence probability of the v-bits at the corresponding position of the corresponding v-subsegment is updated, and the r paths with the highest probability of occurrence are retained as alternative paths.

[0009] In some embodiments, the combination of multiple alternative paths with the highest probability of occurrence of the v-bit sequence of the m v-subsegments is used to obtain q alternative paths with the highest probability of occurrence of the v-bit sequence with a length m times that of the v-subsegment, including: arranging the r alternative paths of the m v-subsegments in descending order of the probability of occurrence of the r alternative paths; combining the maximum probability paths of the m v-subsegments into an alternative path with the highest probability of occurrence of the v-bit sequence with a length m times that of the v-subsegment; replacing the maximum probability path with other paths of the m v-subsegments except the maximum probability path, and updating the probability of occurrence of the v-bit sequence with a length m times that of the v-subsegment, and retaining the q paths with the highest probability of occurrence as alternative paths.

[0010] In some embodiments, obtaining the corresponding decoding result based on the Lmax alternative paths with the highest probability of occurrence of the v-bit sequence of length N includes: verifying the Lmax alternative paths of the v-bit sequence of length N, and using the alternative path with the highest probability of occurrence among the verified alternative paths as the decoding output; if no alternative path passes the verification, using the alternative path with the highest probability of occurrence among the Lmax alternative paths as the decoding output, or initiating retransmission.

[0011] In some embodiments, when the v bit is a frozen bit, if the alternative path of the a bit causes the corresponding v bit to be not a predetermined value of the frozen bit, the alternative path combination of the a bit is deleted.

[0012] According to a second aspect of an embodiment of the present disclosure, a decoding device is provided, comprising: a first processing module configured to divide a received to-be-decoded bit sequence of length N into m to-be-decoded sub-segments of length n; a second processing module configured to independently perform decoding processing on the m to-be-decoded sub-segments to obtain 2s candidate paths with the highest probability of occurrence of the a-bit sequences of the m a-sub-segments; a third processing module configured to use a combination of the 2s candidate paths of the a-bit sequences corresponding to the m a-sub-segments to obtain r candidate paths with the highest probability of occurrence of the v-bit sequences of the corresponding v-sub-segments, and to use the combinations of the 2s candidate paths of the a-bit sequences corresponding to the m a-sub-segments to obtain r candidate paths with the highest probability of occurrence of the v-bit sequences of the corresponding v-sub-segments. A combination of multiple alternative paths with the highest probability of occurrence of the v-bit sequence of the m v-subsegments is performed to obtain q alternative paths with the highest probability of occurrence of the v-bit sequence with a length m times the v-subsegment, and the s alternative paths with the highest probability of occurrence among the q alternative paths of the v-bit sequence with a length m times the v-subsegment are split into m v-subsegments, and the s alternative paths of the corresponding a-subsegments included in the m v-subsegments are path-splitting to obtain 2s candidate paths for the next a-bit in the decoding process, and the corresponding decoding result is obtained according to the Lmax alternative paths with the highest probability of occurrence of the v-bit sequence with a length N.

[0013] In some embodiments, N, m, and n are all integer powers of 2; s≤L; s≤r≤Lmax; r≤q≤Lmax; L≤Lmax≤2L; and the decoding process is polar code SCL decoding.

[0014] In some embodiments, the second processing module is configured to decode the bits in the m sub-segments to be decoded bit by bit in sequence to obtain 2s candidate paths with the highest probability of occurrence of the a bit in the corresponding positions of the m a sub-segments, until the decoding processing of each bit in the sub-segment to be decoded is completed; the 2s candidate paths with the highest probability of occurrence of the a bit are the 2s candidate paths with the highest probability of occurrence of the a bit sequence composed of the a bits that have completed decoding processing and the a bits currently being processed in the a sub-segment.

[0015] In some embodiments, the third processing module is configured to arrange the occurrence probabilities of the 2s candidate paths in descending order for each a bit at the same position of the m a sub-segments, combine the paths with the maximum occurrence probability of the a bits at the same position of the m a sub-segments into the alternative paths with the maximum occurrence probability of the v bits at the same position of the corresponding v sub-segments, replace the paths with the maximum occurrence probability with other paths except the path with the maximum occurrence probability of the a bits at the same position of the m a sub-segments, update the path occurrence probability of the v bits at the corresponding positions of the corresponding v sub-segments, and retain the r paths with the maximum occurrence probability as alternative paths.

[0016] In some embodiments, the third processing module is configured to arrange the r alternative paths of the m v sub-segments in descending order of the occurrence probabilities of the r alternative paths, combine the maximum occurrence probability paths of the m v sub-segments into an alternative path with the maximum occurrence probability of a v-bit sequence whose length is m times that of the v sub-segment, replace the maximum occurrence probability path with other paths of the m v sub-segments except the maximum occurrence probability path, update the occurrence probability of the v-bit sequence whose length is m times that of the v sub-segment, and retain the q paths with the maximum occurrence probability as alternative paths.

[0017] In some embodiments, the third processing module is configured to verify the Lmax alternative paths of the v-bit sequence of length N, and use the alternative path with the highest probability of appearing among the verified alternative paths as the decoding output; if no alternative path passes the verification, use the alternative path with the highest probability of appearing among the Lmax alternative paths as the decoding output, or initiate retransmission.

[0018] In some embodiments, the third processing module is configured to, when the v bit is a frozen bit, delete the a-bit alternative path combination if the a-bit alternative path causes the corresponding v bit to be not a predetermined value of the frozen bit.

[0019] According to a third aspect of an embodiment of the present disclosure, a decoding device is provided, comprising: a memory configured to store instructions; a processor coupled to the memory, the processor being configured to execute a method as described in any of the above embodiments based on the instructions stored in the memory.

[0020] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the method described in any of the above embodiments is implemented.

[0021] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0023] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0024] Figure 1 A flowchart of a decoding method according to an embodiment of the present disclosure is shown;

[0025] Figure 2 This is a schematic structural diagram of a decoding device according to an embodiment of the present disclosure;

[0026] Figure 3 FIG. 4 is a schematic structural diagram of a decoding device according to another embodiment of the present disclosure.

[0027] It should be understood that the size of each part shown in the drawings is not drawn according to the actual proportional relationship.In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0028] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure, its application, or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0029] The words “include” or “comprising” and the like used in the present disclosure mean that the elements preceding the word include the elements listed after the word, and do not exclude the possibility of also including other elements.

[0030] All terms (including technical or scientific terms) used in this disclosure have the same meaning as those understood by one of ordinary skill in the art to which this disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in, for example, general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined herein.

[0031] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0032] Figure 1The flowchart of a decoding method according to an embodiment of the present disclosure is shown in FIG. In some embodiments, the following decoding method is performed by a decoding device.

[0033] In step 101, a received bit sequence to be decoded with a length of N is divided into m sub-segments to be decoded with a length of n.

[0034] In some embodiments, N, m, and n are all integer powers of 2.

[0035] In step 102, the m sub-segments to be decoded are decoded independently to obtain 2s candidate paths with the highest probability of occurrence of the a-bit sequences of the m a-sub-segments.

[0036] In some embodiments, s≤L, and the decoding process is polar code SCL decoding.

[0037] In some embodiments, the bits in the m to-be-decoded sub-segments are decoded bit by bit in sequence to obtain 2s candidate paths with the highest probability of occurrence of the a-bit at the corresponding position of the m a-sub-segments, until decoding of every bit in the to-be-decoded sub-segment is completed. The 2s candidate paths with the highest probability of occurrence of the a-bit are the 2s candidate paths with the highest probability of occurrence of the a-bit sequence consisting of the a-bits that have been decoded and the a-bit currently being processed in the a-sub-segment.

[0038] For example, m sub-segment SCL decoders decode the jth a bit of the i-th a sub-segment respectively. Split the path to obtain l candidate paths, i = 1, 2, 3, ..., m, j = 1, 2, 3, ..., n. When l < = 2 * L, 1 = 2 j , when l>2*L, l=2*L. After path splitting, each a bit has two bit values ​​0 and 1, and there are 2L paths to be selected, so There are 2 sub-segments m L paths to be selected, and There are 2 sub-segments m / 2 L paths to be selected, There are 2 sub-segments m / 4 L paths to be selected; and The number of candidate paths is and Generally speaking, The number of candidate paths for the sub-segment is R = 2 Ai L,A i for The number of times A appears in the subsegment transformation formula from subsegment a to subsegment v, i The values ​​of are shown in Table 1 below.

[0039] <![CDATA[A m ]]> <![CDATA[A m-1 ]]> <![CDATA[A m-2 ]]> <![CDATA[A m-3 ]]> <![CDATA[A m-4 ]]> <![CDATA[A m-5 ]]> <![CDATA[A m-6 ]]> <![CDATA[A m-7 ]]> … <![CDATA[A4]]> <![CDATA[A3]]> <![CDATA[A2]]> <![CDATA[A1]]> m m / 2 m / 2 m / 4 m / 2 m / 4 m / 4 m / 8 … 4 2 2 1

[0040] Table 1

[0041] It should be noted that if If it is a frozen bit, no splitting is performed.

[0042] For example, the subsegment transformation formula from subsegment a to subsegment v is as follows:

[0043]

[0044] Wherein, j = 1, 2, 3,…, n.

[0045] In step 103, r candidate paths with the highest probability of occurrence of the v bit sequence of the corresponding v sub-segment are obtained by using the combination of 2s candidate paths of the a bit sequences corresponding to the m a sub-segments.

[0046] In some embodiments, s≤r≤Lmax, L≤Lmax≤2L.

[0047] In some embodiments, for each a bit at the same position in the m a sub-segments, the occurrence probabilities of the 2s candidate paths are sorted in descending order. The paths with the highest occurrence probabilities for the a bits at the same position in the m a sub-segments are combined to form the candidate paths with the highest occurrence probabilities for the v bits at the same position in the corresponding v sub-segments. The paths with the highest occurrence probabilities are replaced with paths other than the path with the highest occurrence probabilities for the a bits at the same position in the m a sub-segments, and the occurrence probabilities of the paths for the v bits at the corresponding positions in the corresponding v sub-segments are updated, retaining the r paths with the highest occurrence probabilities as the candidate paths.

[0048] In step 104, a combination of multiple candidate paths with the highest probability of occurrence of the v-bit sequence of m v-subsegments is used to obtain q candidate paths with the highest probability of occurrence of the v-bit sequence with a length m times that of the v-subsegments.

[0049] In some embodiments, r≤q≤Lmax, L≤Lmax≤2L.

[0050] In some embodiments, for the r candidate paths of m v subsegments, the occurrence probabilities of the r candidate paths are sorted in descending order. The paths with the highest occurrence probabilities of the m v subsegments are combined into a candidate path with the highest occurrence probability of a v-bit sequence whose length is m times that of the v subsegments. The path with the highest occurrence probability is replaced by paths other than the path with the highest occurrence probability of the m v subsegments, and the occurrence probabilities of the v-bit sequence whose length is m times that of the v subsegments are updated, retaining the q paths with the highest occurrence probabilities as candidate paths.

[0051] In step 105, the s alternative paths with the highest probability of appearing among the q alternative paths of the v-bit sequence whose length is m times that of the v-subsegment are split into m v-subsegments, and the s alternative paths of the corresponding a-subsegments included in the m v-subsegments are path-split to obtain 2s candidate paths for the next a-bit in the decoding process.

[0052] In step 106, corresponding decoding results are obtained based on the Lmax candidate paths with the highest probability of occurrence of the v-bit sequence with a length of N.

[0053] In some embodiments, Lmax alternative paths of a v-bit sequence of length N are checked, and the alternative path with the highest probability of appearing among the checked alternative paths is used as the decoding output; if no alternative path passes the check, the alternative path with the highest probability of appearing among the Lmax alternative paths is used as the decoding output, or retransmission is initiated.

[0054] The present disclosure is described below through specific examples.

[0055] Example 1:

[0056] The following describes the process of determining a maximum of Lmax alternative paths for a certain v bit in a corresponding v sub-segment using a maximum of 2L candidate paths for multiple a bits, and the process of selecting L alternative paths for the next a-bit path splitting using a maximum of Lmax alternative paths for a certain v bit in a corresponding v sub-segment that has been determined.

[0057] 1) For each a bit at the same position in the m a subsegments, sort the 2s candidate paths in descending order of probability. Calculate the substitution ratio T = Pk / P1, where k = 2, 3, 4, ..., 2L, between the probability of the kth candidate path and the probability of the first candidate path. Select the Lmax-1 largest substitution ratio, where Lmax is the maximum number of candidate paths specified for the v subsegment. Stop the calculation when the calculated probability of the kth candidate path is smaller than the Lmax-1 largest substitution ratio.

[0058] 2) Calculate, from largest to smallest, the Lmax-2 combined substitution ratios of each pairwise combination of different a bits among the Lmax-1 largest substitution ratios obtained in step 1), compare them with the Lmax-1 largest substitution ratio obtained in step 1), and select the Lmax-1 largest substitution ratio. If all the substitution ratios obtained in step 2) are smaller than the substitution ratios obtained in step 1), stop the calculation; otherwise, proceed to the next step.

[0059] 3) Calculate the Lmax-3 combined substitution ratios of the three combinations of different a bits in the Lmax-1 largest substitution ratios obtained in step 2) from large to small, compare them with the Lmax largest substitution ratios obtained in step 2), and select the Lmax-1 largest substitution ratio. If the substitution ratios obtained in step 3 are all smaller than the substitution ratios obtained in step 2), stop calculating; otherwise, continue in this way until all combined substitution ratios are processed.

[0060] If the above steps 1), 2) and 3) are performed simultaneously, the calculation results of the above steps 1), 2) and 3) are arranged in descending order together, and the Lmax-1 calculation results with the largest replacement ratio are retained. Every time a new calculation result is obtained, the Lmax-1 calculation result with the largest replacement ratio is rearranged and updated until the latest calculation results of the above steps 1), 2) and 3) are all less than the Lmax-1 calculation result with the largest replacement ratio.

[0061] In the above selection process, if the v bit is a frozen bit, and the selected a-bit candidate path makes the calculation result of the subsegment transformation equation from the a subsegment to the v subsegment not equal to the specific value of the frozen bit, then the corresponding a-bit candidate path combination is deleted.

[0062] For example, when m=8, L=4, Sub-segment The occurrence probabilities of the 2L candidate paths are P1-P8, i = 1, 2, 3, …, 8. Obviously, when only the first two largest occurrence probabilities P1 and P2 are considered to participate in the combination, the candidate paths composed of the four combinations of 8 a-bits with the largest probability of v bits are [P1, P1, P1, P1, P1, P1, P1, P1] and the combination of the a-bit with the largest substitution ratio T1 (P2 / P1) and other a-bit P1 paths, namely: [P1, P1, P1, P1, P1, P1, P1, P1], [P2, P1, P1, P1, P1, P1, P1, P1], [P1, P2, P1, P1, P1, P1, P1, P1, P1], [P1, P2, P1, P1, P1, P1, P1, P1], [P1, P1, P1, P1, P1, P2, P1, P1, P1, P1].

[0063] When considering the third maximum probability P3 to participate in the combination, The substitution ratio T2 = 0.94, greater than The substitution ratio T1 = 0.9333, that is, the probability of occurrence of the combination path of [P1, P3, P1, P1, P1, P1, P1, P1] is greater than that of [P1, P1, P1, P1, P2, P1, P1, P1], therefore, the four candidate paths with the largest probability of occurrence of the v bit are [P1, P1, P1, P1, P1, P1, P1, P1], [P2, P1, P1, P1, P1, P1, P1, P1], [P1, P2, P1, P1, P1, P1, P1, P1, P1], [P1, P3, P1, P1, P1, P1, P1, P1, P1], and T4 = Tx*Ty is the probability of pairwise combination of the four maximum substitution ratios. The maximum substitution ratios of the same a bit are not combined, as shown in Table 2 below (the data in the table are example data, and P5-P8 are not involved in the calculation).

[0064]

[0065]

[0066] Table 2

[0067] Obviously, there is no need to consider the 4th to 8th combinations with the highest probability of occurrence.

[0068] like is the frozen bit, and The combination of [P1,P3,P1,P1,P1,P1,P1,P1] makes If the calculation result is not equal to the specific value of the frozen bit, the corresponding a-bit candidate path combination [P1, P3, P1, P1, P1, P1, P1, P1] is deleted.

[0069] and Sub-segment The occurrence probabilities of the 2L candidate paths are P1-P8, i = 1, 2, 3, ..., 8. The four candidate paths consisting of four combinations of four a bits with the highest probability of the v bit occurring are [P1, P1, P1, P1] and the P1 path combination with the largest a bit in the substitution ratio T1 and T2 and other a bits, namely: [P1, P1, P1, P1], [P2, P1, P1, P1], [P3, P1, P1, P1], and [P1, P1, P1, P2], as shown in Table 3 below (the data in the table are example data, and P5-P8 are not involved in the calculation).

[0070] P1 T1=P2 / P1 T2=P3 / P1 T3=P4 / P1 T4=Tx*Ty T5=Tx*Ty*Tz P2 P3 P4 <![CDATA[a 2j ]]> 0.002 0.9500 0.9400 0.8500 0.8821 0.0019 0.0019 0.0017 <![CDATA[a 4j ]]> 0.080 0.8125 0.5000 0.4375 0.8729 0.0650 0.0400 0.0350 <![CDATA[a 6j ]]> 0.040 0.8750 0.6250 0.3750 0.0350 0.0250 0.0150 <![CDATA[a 8j ]]> 0.070 0.9286 0.7857 0.5000 0.0650 0.0550 0.0350

[0071] Table 3

[0072] Sub-segment The probabilities of occurrence of the 2L candidate paths are P1-P8, i = 1, 2, 3, ..., 8. The four possible combinations of four a-bits with the highest probability of occurrence of the v-bit are [P1, P1] and the combinations of the a-bits with the highest substitution ratios T1 and T2 and other a-bit P1 paths, namely: [P1, P1], [P2, P1], [P1, P2], and [P1, P3], as shown in Table 4 below. (The data in the table is for example only; P5-P8 are not included in the calculation.) T4 = Tx * Ty is the pairwise combination of the three maximum substitution ratios.

[0073] P1 T1=P2 / P1 T2=P3 / P1 T3=P4 / P1 T4=Tx*Ty P2 P3 P4 <![CDATA[a 4j ]]> 0.080 0.8125 0.5000 0.4375 0.7545 0.0650 0.0400 0.0350 <![CDATA[a 8j ]]> 0.070 0.9286 0.7857 0.5000 0.6384 0.0650 0.0550 0.0350

[0074] Table 4

[0075] Example 2:

[0076] The process of obtaining Lmax candidate paths of v bit sequences by concatenating Lmax candidate paths of multiple v sub-segments through a concatenation operation is described by way of example.

[0077] Method 1: Concatenate m v sub-segments into a v bit sequence. Concatenate two v sub-segments of length k and number of alternative paths Lmax into a v sub-segment of length 2k and number of alternative paths Lmax. The details are as follows:

[0078] Arrange the Lmax candidate paths of the two v subsegments in descending order of probability, and calculate each pairwise combination from highest to lowest until the Lmax combinations with the highest probability are obtained. Among the Lmax combinations with the highest probability of a v-bit sequence of length 2k, all a bits contained in the v subsegments in the L combinations with the highest probability are used for the next a-bit path splitting in the subsegment SCL decoder.

[0079] For example, if Lmax=4, the occurrence probabilities of the four candidate paths are shown in Table 5 below.

[0080] P1 P2 P3 P4 v1 0.0200 0.0193 0.0180 0.0170 v2 0.0400 0.0350 0.0250 0.0150

[0081] Table 5

[0082] and The occurrence probabilities of the Lmax alternative paths of the sub-segment are P1-P4 respectively. The candidate paths formed by the four combinations of the highest probability of occurrence of the v sub-segment are [P1, P1] and the combination of the candidate paths with the largest substitution ratios T1 and T2 and the v sub-segment P1 path. Obviously, the combinations with the highest probability of occurrence are [P1, P1], [P2, P1], [P1, P2], and [P3, P1], as shown in Table 6 below.

[0083] P1 T1=P2 / P1 T2=P3 / P1 T3=P4 / P1 T4=Tx*Ty P2 P3 P4 v1 0.02 0.9650 0.9000 0.8500 0.8444 0.0193 0.0180 0.0170 v2 0.04 0.8750 0.6250 0.7875 0.0350 0.0250 0.0150

[0084] Table 6

[0085] Repeat the selection of the Lmax alternative paths in the above v sub - segments and the splicing process of two v sub - segments until the splicing of all v sub - segments is completed.

[0086] Method 2: Adopt the same steps and methods as those in the processing process of Embodiment 1, except that the occurrence probabilities of the Lmax alternative paths in the v sub - segments are used to replace the occurrence probabilities of the 2L candidate paths of the a bits. After processing, the occurrence probabilities of the Lmax alternative paths of the v - bit sequence are obtained.

[0087] When j < N / m, if r ≤ Lmax, then split the r splicing paths of the v - bit sequence with a length of j*m after splicing into m combined path groups. Each combined path group contains at most r alternative paths with a length of j. The m combined path groups are respectively used as the starting points of the path splitting of the (k + 1)-th bit of m SCL decoders; if r > Lmax, then select the Lmax splicing paths with the largest occurrence probabilities from the r splicing paths with a length of j*m. Split the selected Lmax splicing paths into m combined path groups. Each combined path group contains at most Lmax alternative paths with a length of j. The m combined path groups are respectively used as the starting points of the path splitting of the (k + 1)-th bit of m SCL decoders.

[0088] When j = N / m, use the Lmax splicing paths with a length of N as the alternative paths of the v - bit sequence.

[0089] Since the selection of the Lmax alternative paths of the v - bit sequence and the splicing process of two v sub - segments only involve a few candidate paths with the largest occurrence probabilities of the a bits and a few alternative paths with the largest occurrence probabilities of the v sub - segments, and do not need to traverse all candidate paths or alternative paths, the computational complexity is significantly reduced.

[0090] Figure 2 It is a schematic structural diagram of a decoding device according to an embodiment of the present disclosure. As Figure 2 shown, the decoding device includes a first processing module 21, a second processing module 22, and a third processing module 23.

[0091] The first processing module 21 is configured to divide the received bit sequence to be decoded with a length of N into m sub - segments to be decoded with a length of n.

[0092] In some embodiments, N, m, and n are all integer powers of 2.

[0093] The second processing module 22 is configured to independently perform decoding processing on the m sub - segments to be decoded to respectively obtain the 2s candidate paths with the largest occurrence probabilities of the a - bit sequences of the m a sub - segments.

[0094] In some embodiments, the second processing module 22 is configured to decode the bits in the m sub-segments to be decoded bit by bit in sequence to obtain 2s candidate paths with the highest probability of occurrence of the a bit in the corresponding positions of the m a sub-segments, until the decoding processing of each bit in the sub-segment to be decoded is completed; the 2s candidate paths with the highest probability of occurrence of the a bit are the 2s candidate paths with the highest probability of occurrence of the a bit sequence composed of the a bits that have completed decoding processing in the a sub-segment and the a bit currently being processed.

[0095] The third processing module 23 is configured to use a combination of 2s candidate paths of a-bit sequences corresponding to m a-subsegments to obtain r candidate paths with the highest probability of occurrence of the v-bit sequence of the corresponding v-subsegment, use a combination of multiple candidate paths with the highest probability of occurrence of the v-bit sequence of m v-subsegments to obtain q candidate paths with the highest probability of occurrence of the v-bit sequence with a length m times that of the v-subsegment, split the s candidate paths with the highest probability of occurrence among the q candidate paths of the v-bit sequence with a length m times that of the v-subsegment into m v-subsegments, perform path splitting on the s candidate paths of the corresponding a-subsegments included in the m v-subsegments to obtain 2s candidate paths for the next a bit in the decoding process, and obtain the corresponding decoding result based on the Lmax candidate paths with the highest probability of occurrence of the v-bit sequence with a length of N.

[0096] In some embodiments, s≤L, s≤r≤Lmax, r≤q≤Lmax, L≤Lmax≤2L, and the decoding process is polar code SCL decoding.

[0097] In some embodiments, the third processing module 23 is configured to arrange the occurrence probabilities of the 2s candidate paths in descending order for each a bit at the same position of the m a sub-segments, combine the maximum occurrence probability paths of the a bits at the same position of the m a sub-segments into the alternative paths with the maximum occurrence probability of the v bits at the same position of the corresponding v sub-segments, replace the maximum occurrence probability paths with other paths except the maximum occurrence probability paths of the a bits at the same position of the m a sub-segments, update the path occurrence probabilities of the v bits at the corresponding positions of the corresponding v sub-segments, and retain the r paths with the maximum occurrence probability as alternative paths.

[0098] In some embodiments, the third processing module 23 is configured to arrange the occurrence probabilities of the r alternative paths of the m v sub-segments in descending order, combine the maximum occurrence probability paths of the m v sub-segments into the alternative path with the maximum occurrence probability of the v-bit sequence whose length is m times that of the v sub-segment, replace the maximum occurrence probability path with other paths of the m v sub-segments except the maximum occurrence probability path, update the occurrence probability of the v-bit sequence whose length is m times that of the v sub-segment, and retain the q paths with the maximum occurrence probability as alternative paths.

[0099] In some embodiments, the third processing module 23 is configured to verify the Lmax alternative paths of the v-bit sequence of length N, and use the alternative path with the highest probability of appearing among the verified alternative paths as the decoding output; if no alternative path passes the verification, use the alternative path with the highest probability of appearing among the Lmax alternative paths as the decoding output, or initiate retransmission.

[0100] In some embodiments, the third processing module 23 is configured to delete the alternative path combination of the a bit if the alternative path of the a bit causes the corresponding v bit to be not the predetermined value of the frozen bit when the v bit is a frozen bit.

[0101] Figure 3 FIG. 1 is a schematic diagram of the structure of a decoding device according to another embodiment of the present disclosure. Figure 3 As shown, the decoding device includes a memory 31 and a processor 32.

[0102] The memory 31 is used to store instructions. The processor 32 is coupled to the memory 31. The processor 32 is configured to execute the instructions stored in the memory. Figure 1 The method according to any one of the embodiments.

[0103] like Figure 3 As shown, the decoding device further includes a communication interface 33 for exchanging information with other devices. At the same time, the decoding device further includes a bus 34 through which the processor 32, the communication interface 33, and the memory 31 communicate with each other.

[0104] Memory 31 may include high-speed RAM memory or non-volatile memory, such as at least one disk storage device. Memory 31 may also be a memory array. Memory 31 may also be divided into blocks, and the blocks may be combined into virtual volumes according to certain rules.

[0105] Furthermore, the processor 32 may be a central processing unit (CPU), or may be an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the present disclosure.

[0106] The present disclosure also relates to a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which, when executed by a processor, implement the following Figure 1 The method according to any one of the embodiments.

[0107] In some embodiments, the above-mentioned functional modules can be implemented as a general-purpose processor, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components or any appropriate combination thereof for performing the functions described in the present disclosure.

[0108] Thus far, the embodiments of the present disclosure have been described in detail. To avoid obscuring the concept of the present disclosure, some details known in the art have not been described. Based on the above description, those skilled in the art can fully understand how to implement the technical solutions disclosed herein.

[0109] Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art will understand that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. Those skilled in the art will understand that the above embodiments may be modified or some technical features may be replaced with equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A decoding method, comprising: Divide the received to-be-decoded bit sequence of length N into m to-be-decoded sub-segments of length n; Independently decoding the m to-be-decoded sub-segments to obtain 2s candidate paths with the highest probability of occurrence of the a-bit sequences of the m a-sub-segments; Using the combination of 2s candidate paths of the a-bit sequences corresponding to the m a-subsegments, we obtain the r candidate paths with the highest probability of occurrence of the v-bit sequences corresponding to the v-subsegments; Using the combination of multiple candidate paths with the highest probability of occurrence of the v-bit sequence of m v-subsegments, we obtain q candidate paths with the highest probability of occurrence of the v-bit sequence whose length is m times that of the v-subsegments; Splitting the s candidate paths with the highest probability among the q candidate paths of the v-bit sequence whose length is m times that of the v-subsegment into m v-subsegments, and performing path splitting on the s candidate paths of the corresponding a-subsegments included in the m v-subsegments to obtain 2s candidate paths for the next a-bit in decoding processing; The corresponding decoding results are obtained according to the Lmax candidate paths with the highest probability of occurrence of the v-bit sequence with a length of N.

2. The method according to claim 1, wherein: N, m and n are all powers of 2; s≤ L, where L is the number of alternative paths; s≤ r≤ Lmax; r≤ q≤ Lmax; L≤ Lmax≤ 2L; The decoding process is polar code SCL decoding.

3. The method according to claim 1, wherein Decoding the m sub-segments to be decoded independently to obtain 2s candidate paths with the highest probability of occurrence of the a-bit sequences of the m a-sub-segments, respectively, including: Decoding the bits in the m to-be-decoded sub-segments bit by bit in sequence to obtain 2s candidate paths with the highest probability of occurrence of the a bit at the corresponding position of the m a sub-segments, until decoding of every bit in the to-be-decoded sub-segment is completed; The 2s candidate paths with the highest probability of occurrence of the a bit are the 2s candidate paths with the highest probability of occurrence of the a-bit sequence composed of the a bits that have completed decoding processing and the a bits currently being processed in the a sub-segment.

4. The method according to claim 1, wherein By using the combination of 2s candidate paths of the a-bit sequences corresponding to the m a-subsegments, the r candidate paths with the highest probability of occurrence of the v-bit sequences corresponding to the v-subsegments are obtained, including: For each a bit at the same position in the m a sub-segments, sort the occurrence probabilities of the 2s candidate paths in descending order; Combine the paths with the highest probability of occurrence of the a bit at the same position of the m a sub-segments into an alternative path with the highest probability of occurrence of the v bit at the same position of the corresponding v sub-segment; The path with the highest probability of occurrence is replaced by the paths other than the path with the highest probability of occurrence of the a bit at the same position of the m a sub-segments, and the path occurrence probabilities of the v bits at the corresponding positions of the corresponding v sub-segments are updated, and the r paths with the highest probability of occurrence are retained as alternative paths.

5. The method according to claim 1, wherein By using the combination of the multiple candidate paths with the highest probability of occurrence of the v-bit sequence of the m v-subsegments, q candidate paths with the highest probability of occurrence of the v-bit sequence having a length m times that of the v-subsegments are obtained, including: For the r candidate paths of the m v sub-segments, arrange the occurrence probabilities of the r candidate paths in descending order; Combine the maximum probability paths of m v sub-segments into a maximum probability alternative path of v bit sequences whose length is m times that of the v sub-segments; The path with the highest occurrence probability is replaced by other paths except the path with the highest occurrence probability of m v sub-segments, and the occurrence probability of v bit sequences with a length of m times that of v sub-segments is updated, and the q paths with the highest occurrence probability are retained as alternative paths.

6. The method according to claim 1, wherein The corresponding decoding results obtained based on the Lmax candidate paths with the highest probability of occurrence of the v-bit sequence of length N include: Verify the Lmax alternative paths of the v-bit sequence of length N, and use the alternative path with the highest probability among the verified alternative paths as the decoding output; if no alternative path passes the verification, use the alternative path with the highest probability among the Lmax alternative paths as the decoding output, or start retransmission.

7. The method according to any one of claims 1 to 6, wherein In the case where the v bit is a frozen bit, if the alternative path of the a bit causes the corresponding v bit to be not the predetermined value of the frozen bit, the alternative path combination of the a bit is deleted.

8. A decoding device comprising: A first processing module is configured to divide a received to-be-decoded bit sequence of length N into m to-be-decoded sub-segments of length n; A second processing module is configured to independently decode the m to-be-decoded sub-segments to obtain 2s candidate paths with the highest probability of occurrence of the a-bit sequences of the m a-sub-segments; The third processing module is configured to use a combination of 2s candidate paths of a-bit sequences corresponding to m a-subsegments to obtain r candidate paths with the highest probability of occurrence of the v-bit sequence of the corresponding v-subsegment, use a combination of multiple candidate paths with the highest probability of occurrence of the v-bit sequence of m v-subsegments to obtain q candidate paths with the highest probability of occurrence of the v-bit sequence with a length m times that of the v-subsegment, split the s alternative paths with the highest probability of occurrence among the q alternative paths of the v-bit sequence with a length m times that of the v-subsegment into m v-subsegments, perform path splitting on the s alternative paths of the corresponding a-subsegments included in the m v-subsegments to obtain 2s candidate paths for the next a bit in the decoding process, and obtain the corresponding decoding result according to the Lmax alternative paths with the highest probability of occurrence of the v-bit sequence with a length of N.

9. The apparatus according to claim 8, wherein: N, m and n are all powers of 2; s≤ L, where L is the number of alternative paths; s≤ r≤ Lmax; r≤ q≤ Lmax; L≤ Lmax≤ 2L; The decoding process is polar code SCL decoding.

10. The device according to claim 8, wherein The second processing module is configured to decode the bits in the m sub-segments to be decoded bit by bit in sequence to obtain 2s candidate paths with the highest probability of occurrence of the a bits at the corresponding positions of the m a sub-segments, until the decoding processing of each bit in the sub-segment to be decoded is completed; the 2s candidate paths with the highest probability of occurrence of the a bits are the 2s candidate paths with the highest probability of occurrence of the a-bit sequences composed of the a bits that have completed decoding processing and the a bits currently being processed in the a sub-segment.

11. The device according to claim 8, wherein The third processing module is configured to arrange the occurrence probabilities of the 2s candidate paths in descending order for each a bit at the same position of the m a sub-segments, combine the paths with the maximum occurrence probability of the a bits at the same position of the m a sub-segments into the alternative paths with the maximum occurrence probability of the v bits at the same position of the corresponding v sub-segments, replace the paths with the maximum occurrence probability with other paths except the path with the maximum occurrence probability of the a bits at the same position of the m a sub-segments, update the path occurrence probability of the v bits at the corresponding positions of the corresponding v sub-segments, and retain the r paths with the maximum occurrence probability as alternative paths.

12. The device according to claim 8, wherein The third processing module is configured to arrange the r alternative paths of the m v sub-segments in descending order of occurrence probability, combine the maximum occurrence probability paths of the m v sub-segments into an alternative path with the maximum occurrence probability of a v-bit sequence whose length is m times that of the v sub-segment, replace the maximum occurrence probability path with other paths of the m v sub-segments except the maximum occurrence probability path, update the occurrence probability of the v-bit sequence whose length is m times that of the v sub-segment, and retain the q paths with the maximum occurrence probability as alternative paths.

13. The device according to claim 8, wherein The third processing module is configured to verify Lmax candidate paths of the v-bit sequence of length N, and use the candidate path with the highest probability among the candidate paths that pass the verification as the decoding output; If no alternative path passes the check, the alternative path with the highest probability among the Lmax alternative paths is used as the decoding output, or retransmission is started.

14. The device according to any one of claims 8 to 13, wherein: The third processing module is configured to, when the v bit is a frozen bit, delete the a-bit alternative path combination if the a-bit alternative path causes the corresponding v bit to be not a predetermined value of the frozen bit.

15. A decoding device comprising: a memory configured to store instructions; A processor is coupled to the memory, and the processor is configured to execute the method according to any one of claims 1 to 7 based on instructions stored in the memory.

16. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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