Encoding and decoding methods for LDPC and related apparatuses, device, and storage medium

Abstract

The present application discloses an encoding method for low-density parity-check (LDPC) codes. The method comprises: acquiring an information bit sequence; and on the basis of a check matrix, performing LDPC encoding on the information bit sequence to obtain an encoded bit sequence, wherein the check matrix is determined by a base matrix, the base matrix comprises a fundamental sub-matrix, and the fundamental sub-matrix is formed by concatenating at least two basic unit blocks with cyclic or translational properties. Compared with existing 5G new radio (NR) matrices of which shifting values are all obtained by random search without guidance from a fixed algebraic structure, the base matrix having cyclic block structures or translational block structures designed in the present application can be guided by a fixed algebraic structure, thereby solving the technical problems of the lack of practical code design for LDPC and the difficulty in finding a cycle-free exponent matrix by means of random search.

Description

LDPC encoding and decoding method and related devices, equipment and storage medium

[0001] This application claims priority to the Chinese patent application with application number 202410247233.5 filed with the State Intellectual Property Office of China on March 4, 2024, and priority to the Chinese patent application with the invention name “LDPC encoding and decoding method and related devices, equipment and storage medium”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to an LDPC encoding and decoding method and related devices, equipment, and computer-readable storage media. Background Art

[0003] Low-density parity-check (LDPC) code is a channel coding scheme very close to the Shannon line, with good performance and low complexity. It has been identified by 3GPP as the 5G data channel coding scheme.

[0004] LDPC codes are encoded using a generator matrix. The most widely used LDPC codes have a QC structure, which uses a set shift for each block to avoid bad structures such as short loops and improve the code distance. Due to its powerful error correction performance, LDPC codes have been widely used in wired and wireless communication systems, personal area networks, and solid-state drives. In these applications, information transmission or reading is subject to interference from channel noise, which can cause errors. The high error correction performance and low decoding complexity of LDPC codecs ensure reliable information transmission or storage.

[0005] How to further improve the performance of QC LDPC codes is a problem that people are concerned about. Summary of the Invention

[0006] The present application provides an LDPC encoding and decoding method and related devices, equipment and computer-readable storage medium, which can further improve the performance of QC LDPC codes.

[0007] In a first aspect, the present application provides an LDPC code encoding method, the method comprising:

[0008] obtaining an information bit sequence;

[0009] Performing low-density parity check (LDPC) coding on the information bit sequence according to a check matrix to obtain a coded bit sequence;

[0010] The check matrix is ​​determined by a base matrix, and the base matrix includes a basic sub-matrix; the basic sub-matrix is ​​formed by splicing at least two basic unit blocks with circulation or translation.

[0011] Through the above embodiments, compared with the existing 5G new radio (NR) matrix, whose shifting values ​​are all the results of random search and lack fixed algebraic structure guidance, the base matrix with a cyclic block or translation block structure designed in this application can have a fixed algebraic structure guidance, which solves the technical problem of lack of practical code design for LDPC and difficulty in finding a cyclic-free exponential matrix through random search.

[0012] In a second aspect, an embodiment of the present application provides a method for decoding an LDPC code, the method comprising:

[0013] Obtaining a first log likelihood ratio (LLR) sequence corresponding to the received first channel reception sequence;

[0014] Decoding the first LLR sequence according to a check matrix;

[0015] The check matrix is ​​determined by a base matrix, and the base matrix includes a basic sub-matrix; the basic sub-matrix is ​​formed by splicing at least two basic unit blocks.

[0016] In a possible implementation manner of the first aspect and the second aspect, the base matrix further includes a portion of the truncated and spliced ​​basic sub-matrices.

[0017] Through the above embodiments, the spliced ​​basic submatrix can include not only the entire basic submatrix but also a truncated portion of the basic submatrix. The base matrix with a cyclic block or shifted block structure designed in this application can have a fixed algebraic structure guidance, solving the technical problem of the lack of practical code design for LDPC and the difficulty in finding a cyclic-free exponential matrix through random search.

[0018] In a possible implementation manner of the first aspect and the second aspect, the basic unit block is formed by stacking at least two single-cycle blocks.

[0019] Through the above embodiment, the basic unit block is formed by superimposing single-cycle blocks, which is more conducive to achieving a fixed algebraic structure guidance and regular algebraic characteristics, solving the technical problems of lack of practical code design for LDPC and difficulty in finding a cycle-free exponential matrix through random search.

[0020] In a possible implementation of the first and second aspects, the loop structure of the single-loop block itself is as follows: starting from the second row, the non-zero position of the current row is the position of the non-zero position of the previous row shifted by 1 unit; the non-zero position of the first row is the position of the non-zero position of the last row shifted by 1 unit; different single-loop blocks have different non-zero positions and / or non-zero numbers in the first row.

[0021] Through the above embodiments, the cyclic structure of the single-cycle block of the present application can be reasonably and efficiently implemented, thereby helping to achieve a fixed algebraic structure guidance and regular algebraic characteristics, solving the technical problems of the lack of practical code design for LDPC and the difficulty in finding a cycle-free exponential matrix through random search.

[0022] In a possible implementation of the first and second aspects, the number and position of non-zero values ​​in the first row of the single loop block are confirmed by a column identification vector; the number of elements in the column identification vector corresponds to the number of non-zero values ​​in the first row, and the size of the elements in the column identification vector represents the column identifier of the non-zero position in the first row;

[0023] The column identification vector is determined by the degree of non-zero coefficients in the polynomial; different single-loop blocks correspond to different polynomials.

[0024] Through the above embodiment, the column identification vector is determined by the degree of non-zero coefficients in the polynomial, which can reasonably and efficiently achieve a fixed algebraic structure guidance with regular algebraic characteristics, and solve the technical problems of lack of practical code design for LDPC and difficulty in finding a cycle-free exponential matrix through random search.

[0025] In a possible implementation manner of the first aspect and the second aspect, the at least two basic unit blocks include at least two different basic unit blocks.

[0026] Through the above embodiments, the basic sub-matrix of the present application may include two different basic unit blocks, which can solve the problem that the LDPC check matrix containing short cycles will cause a relatively high error floor in decoding.

[0027] In a possible implementation manner of the first aspect and the second aspect, the basic sub-matrix is ​​formed by superimposing at least two sub-matrices.

[0028] Through the above embodiments, the basic sub-matrix of the present application can be split into at least two sub-matrices in the form of superposition or combination, which can reasonably and efficiently implement the cyclic structure of the single cyclic block of the present application, thereby helping to achieve a fixed algebraic structure guidance and regular algebraic characteristics, solving the technical problem of lack of practical code design for LDPC and difficulty in finding a cycle-free exponential matrix through random search.

[0029] In a possible implementation of the first and second aspects, the values ​​of the basic submatrix include 0, 1 and 2; the position representation with the value of 0 represents no shift value element, the position representation with the value of 1 represents 1 shift value element, and the position representation with the value of 2 represents 2 shift value elements.

[0030] Through the above embodiments, the present application adopts the idea of ​​jointly designing the base matrix and the Shifting Value. The values ​​of the basic sub-matrix may include values ​​used to characterize elements with two shift values, such as a value of 2, which can realize the fine-grained Shifting Value design of non-fully connected BG. Compared with the existing short-cycle-free design method, it can correspond to a smaller order of magnitude lifting factor to meet the conditions. In addition, the base matrix in the form of a multi-edge cycle has a consistent threshold for the base matrix of the core array of 5G NR. Compared with the single-edge LDPC, Multi edge LDPC can achieve cycle free or a small number of cycles at a smaller lifting size.

[0031] In a possible implementation manner of the first and second aspects, the at least two sub-matrices include a first sub-matrix and a second sub-matrix; wherein,

[0032] The first sub-matrix is ​​formed by mixing and splicing at least two single-block cyclic unilateral quasi-cyclic LDPC unit blocks;

[0033] The second sub-matrix is ​​formed by non-mixing or mixing splicing of at least two single-sided quasi-cyclic LDPC unit blocks.

[0034] Through the above embodiments, the design of the base matrix of the present application has regular algebraic characteristics, which solves the problem that the existing 5G NR matrix is ​​the result of random search and lacks a fixed algebraic structure guidance. It also solves the problem that the LDPC check matrix containing short cycles will cause a relatively high error floor in decoding.

[0035] In a possible implementation manner of the first and second aspects, a shift value matrix corresponding to the basic sub-matrix is ​​formed by combining a first shift value matrix corresponding to the first sub-matrix and a second shift value matrix corresponding to the second sub-matrix;

[0036] The shift value matrix corresponding to each basic unit block in the first shift value matrix satisfies a p-row shift cycle, where p is an integer greater than or equal to 1;

[0037] The second shift value matrix satisfies a cycle of W units of translation; W is related to the total number of columns of the basic sub-matrix.

[0038] The above embodiments implement a combination of Shifting Values, addressing the issue of high decoding error floors caused by LDPC parity check matrices containing short cycles from a short-cycle-free perspective. The algebraic feature construction of this application supports fine-grained Shifting Values. Compared to existing short-cycle-free designs, this fine-grained Shifting Value design can meet requirements for smaller lifting sizes.

[0039] In a possible implementation manner of the first aspect and the second aspect, the base matrix includes a plurality of the basic sub-matrices, and the shift values ​​corresponding to the same positions among the plurality of the basic sub-matrices are the same or satisfy an arithmetic progression characteristic.

[0040] Through the above embodiments, the non-fully connected BG designed by this application and the fine-grained Shifting Value design scheme can achieve C4-free at a smaller scale compared to the fully connected i*j design method. For the construction method of the fully connected BG based on the finite field, the shifting value of the i-row and j-column is the construction method of S_i*R_j, and the minimum lifting size is n (number of columns), and it is required to be a prime number. The Shifting Value of the construction method designed by this application can be jointly optimized with the non-fully connected BG, and the code length n is not required to be a prime number. The minimum lifting size of C4-free is smaller in magnitude. The Shifting Value design has no error floor, which is consistent with the best Shifting Value performance of random search.

[0041] In a possible implementation of the first and second aspects, the basic sub-matrix is ​​a 4×n matrix; the basic sub-matrix corresponds to the shift value A of the shift value matrix. i (j) A corresponding to the position where the basic submatrix takes a value of 2 i (j) is related to the total number of columns of the basic sub-matrix and the column index where the position of 2 is located.

[0042] Through the above embodiments, the construction of the algebraic features of the present application supports fine granularity. Compared with the existing short-circuit-free design method, the fine-grained Shifting Value design of the present application can correspond to a smaller order of magnitude of lifting size to meet the conditions. Specifically, the required Lifting Size of the C4-free Shifting Value design can reach the optimal limit; for the same row and column degree distribution, the circle-free Lifting Size limit achieved by Multi-edge is smaller than the circle-free Lifting Size limit achieved by Single-edge. Therefore, under reasonable design, with the same code length and code rate, Multi-edge can achieve better performance; for C4 and C6-free Shifting Value designs, the required Lifting Size can reach the optimal limit or the same order of magnitude.

[0043] In a possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) Satisfy the following formula:

[0044] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix;

[0045] The B i (j) is generated by the translation of a vector h, where the value of the vector h satisfies the formula The sequence is based on the number of columns of the basic sub-matrix as a unit, and each cycle is to the left units to form the next row.

[0046] Through the above embodiment, for any N, when the lifting factor lifting size is When within the range, the matrix C4free.

[0047] In a possible implementation manner of the first aspect and the second aspect, the at least two basic unit blocks include the same basic unit blocks.

[0048] Through the above embodiments, the basic sub-matrix of the present application can be formed by splicing or shifting the same basic unit blocks, which can solve the problem that the LDPC check matrix containing short cycles will cause a relatively high error floor in decoding.

[0049] In a possible implementation manner of the first aspect and the second aspect, the same basic unit block is formed by superimposing two single-sided quasi-cyclic LDPC unit blocks.

[0050] Through the above embodiments, the design of the base matrix of the present application has regular algebraic characteristics, which solves the problem that the existing 5G NR matrix is ​​the result of random search and lacks fixed algebraic structure guidance. It also solves the situation where the LDPC check matrix containing short cycles will cause a relatively high error floor in decoding. In addition, a combination form of Shifting Value is realized. From the perspective of short cycle free, the situation where the LDPC check matrix containing short cycles will cause a relatively high error floor in decoding is solved. The construction of the algebraic characteristics of the present application supports fine granularity. Compared with the existing short cycle free design method, the fine-grained Shifting Value design scheme of the present application can correspond to a smaller order of magnitude lifting size to meet the conditions.

[0051] In a possible implementation manner of the first aspect and the second aspect, the shift value matrix corresponding to the basic sub-matrix has a cyclic characteristic.

[0052] In a possible implementation of the first and second aspects, the basic submatrix is ​​a 4×n matrix; the shift values ​​corresponding to the first two rows in the basic submatrix are shifted by two positions as the shift values ​​corresponding to the third and fourth rows in the basic submatrix.

[0053] Through the above embodiments, the non-fully connected BG designed by this application and the fine-grained Shifting Value design scheme can achieve C4-free at a smaller scale compared to the fully connected i*j design method. For the construction method of the fully connected BG based on the finite field, the shifting value of the i-row and j-column is the construction method of S_i*R_j, and the minimum lifting size is n (number of columns), and it is required to be a prime number. The Shifting Value of the construction method designed by this application can be jointly optimized with the non-fully connected BG, and the code length n is not required to be a prime number. The minimum lifting size of C4-free is smaller in magnitude. The Shifting Value design has no error floor, which is consistent with the best Shifting Value performance of random search.

[0054] In a possible implementation of the first and second aspects, the shift value A of the shift value matrix corresponding to the basic sub-matrix is i (j) A corresponding to the position where the basic submatrix takes a value of 2 i (j) is related to the total number of columns of the basic sub-matrix and the column index where the position of 2 is located.

[0055] Through the above embodiments, the construction of the algebraic features of the present application supports fine granularity. Compared with the existing short-circuit-free design method, the fine-grained Shifting Value design of the present application can correspond to a smaller order of magnitude of lifting size to meet the conditions. Specifically, the required Lifting Size of the C4-free Shifting Value design can reach the optimal limit; for the same row and column degree distribution, the circle-free Lifting Size limit achieved by Multi-edge is smaller than the circle-free Lifting Size limit achieved by Single-edge. Therefore, under reasonable design, with the same code length and code rate, Multi-edge can achieve better performance; for C4 and C6-free Shifting Value designs, the required Lifting Size can reach the optimal limit or the same order of magnitude.

[0056] In a possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) Satisfy the following formula:

[0057] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0058] Through the above embodiments, when When within the range, the matrix C4free can adapt to the requirements of fine-grained code length and ensure performance.

[0059] In a possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) Satisfy the following formula:

[0060] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0061] According to the above embodiment, for any n, when When within the range, the matrix C4free.

[0062] In a possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) Satisfy the following formula:

[0063] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0064] According to the above embodiment, for any n, when lifting size is all odd numbers in the range of n-1, the matrix C4free.

[0065] In a possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) Satisfy the following formula:

[0066] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0067] According to the above embodiment, when the lifting size is When , the matrix C4C6free. Only when the lifting size is z is any positive integer that does not satisfy C4 or C6 free conditions. This allows the rounding requirements of different code lengths to be met, ensuring stable performance.

[0068] In a possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) Satisfy the following formula:

[0069] When t is an odd number, When t is an even number,

[0070] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0071] According to the above embodiment, for any n, when When , the matrix C4, C6 is free. It can meet the requirements of different code lengths for circles and ensure stable performance.

[0072] In a possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) Satisfy the following formula:

[0073] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0074] Through the above embodiments, when For all odd numbers, the matrix is ​​C4free.

[0075] In a possible implementation of the first and second aspects, the shift value A of the shift value matrix i (j) Satisfy the following formula:

[0076] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0077] Through the above embodiments, when The matrix C4free.

[0078] In a third aspect, an embodiment of the present application provides a communication device having the function of implementing the behavior in the method embodiment of the first aspect above. The communication device can be a communication device, or a component of a communication device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the communication device. The functions of the communication device can be implemented by hardware, or can be implemented by hardware executing corresponding software, and the hardware or software includes one or more modules or units corresponding to the above functions. In one possible implementation, the communication device includes an interface module and a processing module, wherein: the interface module is used to obtain an information bit sequence, and the processing module is used to perform low-density parity check LDPC encoding on the information bit sequence according to a check matrix to obtain a coded bit sequence, wherein the check matrix is ​​determined by a base matrix, and the base matrix includes a basic submatrix; the basic submatrix is ​​spliced ​​by at least two basic unit blocks with cycles or shifts.

[0079] For possible implementations of the communication device of the third aspect, reference may be made to various possible implementations of the first aspect.

[0080] For the technical effects brought about by various possible implementations of the third aspect, reference may be made to the introduction to the technical effects of the first aspect or various possible implementations of the first aspect.

[0081] In a fourth aspect, an embodiment of the present application provides a communication device having the function of implementing the behavior in the method embodiment of the second aspect above. The communication device can be a communication device, or a component of a communication device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the communication device. The functions of the communication device can be implemented by hardware, or by hardware executing corresponding software implementations, and the hardware or software includes one or more modules or units corresponding to the above functions. In one possible implementation, the communication device includes an interface module and a processing module, wherein: the interface module is used to receive a first channel received sequence; the processing module is used to obtain a first log-likelihood ratio LLR sequence corresponding to the received first channel received sequence, and decode the first LLR sequence according to a check matrix; wherein the check matrix is ​​determined by a base matrix, and the base matrix includes a basic submatrix; the basic submatrix is ​​spliced ​​by at least two basic unit blocks with cycles or shifts.

[0082] Regarding the technical effects brought about by various possible implementations of the fourth aspect, reference may be made to the introduction to the technical effects of the first aspect or various possible implementations of the first aspect.

[0083] In a fifth aspect, an embodiment of the present application provides another communication device, which includes a processor, the processor is coupled to a memory, and the memory is used to store programs or instructions. When the program or instruction is executed by the processor, the communication device executes the method shown in the above-mentioned first aspect or any possible implementation of the first aspect, or when the program or instruction is executed by the processor, the communication device executes the method shown in the above-mentioned second aspect or any possible implementation of the second aspect.

[0084] In the embodiment of the present application, during the execution of the above method, the process of sending information (or signals) in the above method can be understood as the process of outputting information based on the instructions of the processor. When outputting information, the processor outputs the information to the transceiver so that it can be transmitted by the transceiver. After being output by the processor, the information may also need to undergo other processing before reaching the transceiver. Similarly, when the processor receives input information, the transceiver receives the information and inputs it into the processor. Furthermore, after the transceiver receives the information, the information may need to undergo other processing before being input into the processor.

[0085] For operations such as sending and / or receiving involved in the processor, unless otherwise specified, or unless they conflict with their actual functions or internal logic in the relevant descriptions, they can be generally understood as instructions output based on the processor.

[0086] During implementation, the processor may be a processor specifically configured to execute these methods, or may be a processor that executes computer instructions in a memory to execute these methods, such as a general-purpose processor. For example, the processor may also be configured to execute a program stored in the memory. When the program is executed, the communication device performs the methods described in the first aspect, the second aspect, or any possible implementation of the first and second aspects.

[0087] In a possible implementation, the memory is located outside the communication device. In a possible implementation, the memory is located inside the communication device.

[0088] In a possible implementation, the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together.

[0089] In a possible implementation, the communication device further includes a transceiver, and the transceiver is used to receive signals or send signals, etc.

[0090] In a sixth aspect, the present application provides a computer-readable storage medium, which stores a computer program, and the computer program includes program instructions, which, when executed, enable the computer to execute the method as shown in the first aspect or any possible implementation of the first aspect, or, when executed, enable the computer to execute the method as shown in the second aspect or any possible implementation of the second aspect.

[0091] In the seventh aspect, the present application provides a computer program product, which includes a computer program, and the computer program includes program instructions, which, when executed, enable the computer to execute the method as shown in the first aspect or any possible implementation of the first aspect, or, when executed, enable the computer to execute the method as shown in the second aspect or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] FIG1 is an example of a check matrix H of an LDPC code provided by the present application;

[0093] FIG2 is a Tanner graph of a check matrix H of an LDPC code provided in an embodiment of the present application;

[0094] FIG3 is an example of four types of CPM (4×4) provided by this application;

[0095] FIG4 is a schematic structural diagram of a BG1 provided in an embodiment of the present application;

[0096] FIG5 is a schematic diagram showing the relationship between a coding rate and the number of bits of a code block (CB) provided in an embodiment of the present application;

[0097] FIG6 is a schematic diagram of a scenario architecture of a communication system provided in an embodiment of the present application;

[0098] FIG7 is a schematic diagram of the generation principle of a basic unit block according to an embodiment of the present application;

[0099] FIG8 is a schematic diagram of the splicing of basic unit blocks provided in an embodiment of the present application;

[0100] FIG9 is a schematic diagram of the principle of hybrid splicing provided by an embodiment of the present application;

[0101] FIG10 is a schematic diagram of a 4×n high-rate BG with four rows of 3 / 4 edge density in a hybrid splicing embodiment of the present application;

[0102] FIG11 is a schematic diagram of a non-hybrid splicing 4×n high-rate BG with four rows and 3 / 4 edge density;

[0103] FIG12a is a schematic diagram showing the principle of SV value design provided in an embodiment of the present application;

[0104] FIG12 b is a schematic diagram of a Shifting Value design corresponding to a 4×n BG provided in an embodiment of the present application;

[0105] FIG13 is a schematic diagram showing the principle of SV value design provided in an embodiment of the present application;

[0106] FIG14 is a schematic diagram of a Shifting Value design corresponding to a 4×n BG provided in an embodiment of the present application;

[0107] FIG15 is a schematic diagram of another Shifting Value design corresponding to a 4×n BG provided in an embodiment of the present application;

[0108] FIG16 is a schematic diagram of another Shifting Value design corresponding to a 4×n BG provided in an embodiment of the present application;

[0109] FIG17 is a schematic diagram of another Shifting Value design corresponding to a 4×n BG provided in an embodiment of the present application;

[0110] FIG18 is a schematic diagram of another Shifting Value design corresponding to a 4×n BG provided in an embodiment of the present application;

[0111] FIG19 is a schematic diagram of another Shifting Value design corresponding to a 4×n BG provided in an embodiment of the present application;

[0112] FIG20 a is a schematic diagram of another Shifting Value design corresponding to a 4×n BG provided in an embodiment of the present application;

[0113] FIG20 b is a schematic diagram of coding performance provided by an embodiment of the present application;

[0114] FIG21 is a schematic structural diagram of a communication device 2100 provided in an embodiment of the present application;

[0115] FIG22 is a schematic structural diagram of another communication device 220 provided in an embodiment of the present application;

[0116] FIG23 is a schematic structural diagram of another communication device 230 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0117] The terms "first" and "second" in the specification, claims, and drawings of this application are used only to distinguish different objects and are not used to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to the process, method, product, or device.

[0118] In this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary," "for example," or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete way.

[0119] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It will be understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0120] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and appended claims of the present application, the singular expressions "one", "a kind of", "said", "above", "the" and "this" are intended to also include plural expressions, unless there is a clear contrary indication in the context. It should also be understood that the term "and / or" used in the present application refers to and includes any or all possible combinations of one or more listed items. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The term "multiple" used in the present application refers to two or more.

[0121] It is understood that in each embodiment of the present application, "A corresponds to B" means that there is a corresponding relationship between A and B, and B can be determined according to A. However, it should also be understood that determining (or generating) B according to (or based on) A does not mean that B is determined (or generated) only according to (or based on) A, and B can also be determined (or generated) according to (or based on) A and / or other information.

[0122] In order to facilitate understanding of the solution of this application, the relevant concepts of LDPC codes in this application are first introduced.

[0123] LDPC codes, short for low-density parity-check codes, are parity-check codes with a low-density property. The low density here refers to the low density of the parity check matrix of the LDPC code. Therefore, to understand LDPC codes, it's important to first understand the concepts of parity check codes, parity check matrices, and low density.

[0124] 1. Parity check code

[0125] Parity-check codes are a coding method that uses redundant bits to ensure that the number of "1s" in a codeword is always odd or even. They are also error-correcting codes. Parity-check codes are commonly used for digital encoding in the binary field 0-1. One or more check bits (check bits) are added to the end of the codeword. The odd or even number of 1s in the codeword is used to determine whether the codeword has errors before or after transmission. For example, if parity check is used for the codeword 100, the check bit can be 1, ensuring that the sum (exclusive OR) of all codewords, s, is 0, or 1001. If, after transmission, it becomes 1101, an information bit (also called a bit) is incorrect, then s is 1, indicating a transmission error. It should be understood that if an even number of information bits are incorrect, the algorithm fails. Therefore, multiple check bits can be added. For example, the four-bit codeword 1101 can be grouped, with the first check bit used to verify the first and second information bits (i.e., the first two information bits, 11). For example, to make the sum of the first two information bits equal to 0, the first parity bit should be 0. Similarly, the second parity bit can verify the last two information bits of the codeword 1101, so the second parity bit should be 1. Therefore, the encoded codeword is 110101. This is the principle of LDPC codes, which is the meaning of "PC." Therefore, LDPC codes are block codes that use parity checking. Adding the property of low density yields LDPC codes.

[0126] 2. Low-density properties of LDPC codes

[0127] The low-density property of LDPC codes refers to the small number of 1s in the parity check matrix. LDPC codes are linear block codes whose parity check matrices are sparse. The number of zero elements in the parity check matrix far outnumbers the number of non-zero elements. In other words, the row weight (the number of 1s in each row) and column weight (the number of 1s in each column) of the parity check matrix are very small compared to the code length of the LDPC code.

[0128] 3. Check Matrix and Generator Matrix of LDPC Code

[0129] Taking the codeword 1101 above as an example, the check relationship between the information bit and the check bit of the codeword can be written in the form of a matrix. Let the information bits be c1, c2, c3, c4, and the check bits be p1, p2. c = [c1, c2, c3, c4], x = [c1, c2, c3, c4, p1, p2]. Here c and x are the codewords before and after encoding, respectively, that is, c is the information bit, x is the codeword bit or encoding bit, and x can be understood as information bit + check bit. In the example of codeword 1101, the check relationship between the information bit and the check bit of codeword 1101 can be expressed as the following linear relationship: c1+c2+p1=0, c3+c4+p2=0. This linear relationship can be written as the following formula: x·H T =s=0 (1);

[0130] Where H is: s=(0,0). Here H is the check matrix, s is the check code, H T The idea of ​​formula (1) is that after the information bit c is encoded by the generator matrix G (G is determined by H), the resulting codeword bit x must satisfy x·H T = 0. To easily determine whether the result is 0, we introduce the concept of syndrome s. As long as s is all 0, the transmission is fine. In this application, "·" represents a matrix multiplication operation, and "A·B" represents the matrix multiplication product of matrix A and matrix B.

[0131] The codeword bit x obtained by encoding c through the generator matrix G can satisfy the following formula: x=c·G; (2);

[0132] Where c represents the uncoded codeword (or bit sequence), and G represents the generator matrix. G and H T Orthogonal to each other, that is, G·H T = 0. The generator matrix can be obtained by transforming the check matrix. In other words, knowing the check matrix, we can obtain the generator matrix corresponding to the check matrix. Formula (2) shows that the codeword bits are obtained by multiplying the information bits by the generator matrix.

[0133] 4. Tanner Graph

[0134] In 1981, Tanner represented the codewords of LDPC codes using a graph. This type of graph is now called a Tanner graph, and there is a one-to-one correspondence between a Tanner graph and a parity check matrix. A Tanner graph consists of two types of vertices: variable nodes, representing codeword bits, and check nodes, representing check constraints. Each check node represents a check constraint, as explained below using Figures 1 and 2.

[0135] See Figure 1, which shows an example of a check matrix H for an LDPC code provided in this application. In Figure 1, {Vi} represents a set of variable nodes, and {Ci} represents a set of check nodes. Each row of the check matrix H corresponds to a check equation, and each column corresponds to a codeword bit. In Figure 1, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the variable node and the check node involved to obtain a Tanner graph.

[0136] Refer to Figure 2, which is a Tanner graph of a check matrix H of an LDPC code provided in an embodiment of the present application. As shown in Figure 2, the Tanner graph represents the check matrix of the LDPC code. For example, for a check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, namely n variable nodes (also called information nodes or bit nodes) and m check nodes, and m and n are both integers greater than 0. Among them, the above-mentioned n variable nodes correspond to the n columns of the check matrix H respectively, and the above-mentioned m check nodes correspond to the m rows of the check matrix H respectively. The loop in the Tanner graph is composed of vertices connected to each other, and the loop uses one of the vertices in this group of vertices as both the starting point and the end point, and only passes through each node once. The length of the loop is defined as the number of edges it contains, and the girth of the graph can also be called the size of the graph, which is defined as the minimum loop length in the graph. In Figure 2, the girth is 6, as shown by the black line in Figure 2.

[0137] 5. LDPC code encoding

[0138] Based on the above description, we can see that the codeword bits are obtained by multiplying the information bits by the generator matrix, and the generator matrix can be obtained by transforming the check matrix. Therefore, the entire LDPC code encoding process is actually a check matrix construction process. The check matrix H can be transformed into H = [IP]; from G·H T = 0, and the generated matrix G = [-P T I]; information bit c is encoded by the generator matrix G to obtain codeword bit x, that is, x = c·G. Where I represents the information bit part, P represents the check bit part, and x is the codeword bit.

[0139] 6. Decoding of LDPC Codes

[0140] The LDPC code decoding process is to iterate messages between the variable nodes and the check nodes through the check rule between the check bits (or check symbols) and the information bits (or information symbols) until a message that satisfies x·H is found. T = = codeword, the output x is the decoded codeword. LDPC code decoding algorithms fall into three categories: hard decision decoding, soft decision decoding, and hybrid decoding.

[0141] 7. Expand the base matrix to obtain the check matrix

[0142] The base matrix of an LDPC code can be expanded into a check matrix for LDPC codes of various code lengths as needed. Typically, the base matrix of an LDPC code contains only two elements, 0 and 1. In this application, the 0 in the base matrix can be replaced by a blank, "-", "-1", or other numbers or symbols, and this application is not limited thereto. In this application, when the check matrix is ​​obtained by expanding the base matrix, the 1 in the base matrix can be expanded into a non-all-zero square matrix (also referred to as a non-all-zero square matrix), and the 0 element in the base matrix can be expanded into an all-zero square matrix (also referred to as an all-zero square matrix). In this application, an all-zero square matrix refers to a square matrix in which each element is 0, such as a square matrix of size (27×27). In this application, a non-all-zero square matrix refers to a square matrix that includes at least one non-zero element, such as a circulant permutation matrix (CPM). CPM is a cyclic shift of a unit matrix. In other words, a cyclic shift of a unit matrix is ​​called CPM. The meaning of CPM in the following description is the same and will not be repeated here. In this application, any CPM can be represented by a numerical value and an expansion factor. In other words, any CPM corresponds to a numerical value and an expansion factor. The different sizes of two CPMs means that the expansion factors corresponding to the two CPMs are different. In this application, the expansion factor corresponding to a CPM can be referred to as a specific expansion factor value, an expansion factor value, or a cyclic shift factor, etc. The numerical value corresponding to a CPM can be referred to as a cyclic shift coefficient. The expansion factor corresponding to a CPM represents the size of the CPM, that is, the expansion factors of CPMs of different sizes are different. For example, the expansion factor of a CPM of size (27×27) is 27. Or, the expansion factor of a CPM of size 27 indicates that the size of the CPM is (27×27). For another example, the expansion factor of a CPM of size (54×54) is 54. The meaning of the expansion factors of subsequent CPMs is the same and will not be repeated here. It should be noted that the expansion factors of each CPM in the check matrix are the same. For example, a base matrix of size (12×24) is expanded using an expansion factor Z=27 to obtain a check matrix. The expansion factor of each CPM in the check matrix is ​​Z. In the present application, the numerical value (integer) corresponding to CPM represents the number of bits of the unit matrix cyclically shifted to the right. Figure 3 is an example of 4 types of CPM provided by this application (4×4). As shown in Figure 3, P0 represents a (4×4) unit matrix, P0 can be regarded as a CPM with an expansion factor of 4 and a corresponding numerical value of 0, P1 is a CPM with an expansion factor of 4 and a corresponding numerical value of 1, P2 is a CPM with an expansion factor of 4 and a corresponding numerical value of 2, and P3 is a CPM with an expansion factor of 4 and a corresponding numerical value of 3. Figure 3 is an example of 4 types of CPM provided in an embodiment of the present application. It should be understood that any CPM can be obtained by cyclically shifting the corresponding unit matrix to the right, and will not be described in detail here. It should be understood that the 1 in the base matrix can be expanded to a CPM of any size, and the 0 in the base matrix can be expanded to an all-zero square matrix of any size.The meaning or function of 1 or 0 in the basis matrix below is consistent with the above description and will not be repeated here.

[0143] The method of expanding the base matrix to obtain the check matrix can be as follows: replace the 1 in the base matrix with CPM, and replace the 0 with a square matrix of all zeros of the corresponding size. For example, each element in the base matrix is ​​0 or 1. When the check matrix is ​​expanded from the base matrix, each 0 in the base matrix is ​​expanded into a (Z×Z) all-zero matrix, and each 1 in the base matrix is ​​expanded into a (Z×Z) CPM, where Z is the expansion factor corresponding to the CPM, and the values ​​corresponding to different CPMs are the same or different. Therefore, a series of check matrices for LDPC codes can be obtained from the base matrix. The sizes of these check matrices and the expansion factors of each CPM can be different, but they correspond to or conform to the same base matrix.

[0144] In this application, the base matrix of the LDPC code can contain three elements: 0, 1, and 2. The 2 in the base matrix can also be expanded to a non-all-zero square matrix. The 2 in the base matrix can represent an element with two shift values. The non-all-zero square matrix expanded from the 2 in the base matrix is ​​shifted by CPM according to the values ​​corresponding to the two shift value elements and then superimposed.

[0145] It is understandable that the value representing an element with 2 shift values ​​can be 2 or other values. The embodiments of the present application do not limit this, as long as the protocol specifies a value for representing an element with 2 shift values.

[0146] Before introducing the method provided by the embodiments of the present application, the following briefly introduces the base graph (BG), BG1, and BG2. It is understood that the following description of BG1 and BG2 is only an example. For other descriptions of BG1 and BG2, reference can be made to relevant standards or protocols, etc., and the embodiments of the present application do not limit this.

[0147] Take a BG1 as an example: Figure 4 is a structural diagram of a BG1 provided in an embodiment of the present application. Figure 5 is a schematic diagram of the relationship between a coding rate and the number of bits (bits) of a CB provided in an embodiment of the present application. Exemplarily, the applicable code length of BG1 is information bits K = 308 to 8448 bits, and the code rate R is 0.25 <= R <= 0.95. The applicable code length of BG2 is information bits K = 40 to 3840 bits, and the code rate R is 0.20 <= R <= 0.95. It can be seen that BG1 is mainly aimed at scenarios with medium and high code rates and longer data packets, while BG2 is mainly aimed at scenarios with medium and low code rates and shorter data packets.

[0148] However, the current 5G air interface NR-LDPC codes BG1 and BG2 have the following shortcomings: the base matrix and shifting value (SV) are obtained by random search, relying on a large number of searches; the short-cycle-free property cannot be theoretically guaranteed; and the current 5G NR-LDPC codes BG1 and BG2 are both single-edge LDPC codes. The theoretical lower bound of the lifting factor (lifting size) that guarantees short-cycle freedom for single-edge LDPC is inferior to that of multi-edge LDPC.

[0149] Given the lack of theoretical guarantees for short-cycle-free 5G NR-LDPC codes, we designed the LDPC base graph from a short-cycle-free perspective. For a fixed base matrix, we implemented shifting value design. This ensures short-cycle-free LDPC decoding performance. We combined the base matrix and shifting value design to ensure short-cycle-free LDPC codes, as shown in Table 1 below:

[0150] Shifting Value feature: For an n*n fully connected matrix, the row and column labels are set to {0,…,n-1}, and the shifting value of the i-th row and j-th column is designed to be i*j; (if n is a prime number p, the shifting value of the i-th row and j-th column can be designed to be i*j(mod p)).

[0151] However, this design is n*n fully connected, which is highly complex and cannot guarantee performance. In addition, the only condition that is met is C4free, which is far from sufficient for medium and long codes.

[0152] The technical solutions provided in the embodiments of the present application can be applied to various communication systems, for example, the Internet of Things (IoT) system, the narrowband Internet of Things (NB-IoT) system, the long term evolution (LTE) system, the fifth generation (5G) communication system, and new communication systems that will emerge in the future development of communications.

[0153] Wireless communication systems typically consist of cells, each containing a base station (BS). The BS provides communication services to multiple mobile stations (MSs). A base station consists of a BBU (Baseband Unit) and an RRU (Remote Radio Unit). The BBU and RRU can be placed in different locations, for example: a remote RRU in a high-traffic area and a central equipment room. Alternatively, the BBU and RRU can be placed in the same equipment room. Alternatively, the BBU and RRU can be separate components within the same rack.

[0154] As shown in Figure 6, a schematic diagram of the scenario architecture of the communication system provided by an embodiment of the present application, the communication system may include at least one network device and at least one terminal device, such as terminal devices 1 to terminal devices 4 in Figure 6. Exemplarily, terminal device 3 and terminal device 4 as shown in Figure 6 can communicate directly. For example, direct communication between terminal devices can be achieved through D2D technology. Terminal devices 1 to terminal devices 4 can communicate with network devices respectively. It is understandable that terminal device 3 and terminal device 4 can communicate directly with the network device or indirectly with the network device, such as communicating with the network device via other terminal devices (not shown in Figure 6). It should be understood that Figure 6 exemplarily shows a network device and multiple terminal devices, as well as communication links between each communication device. Optionally, the communication system may include multiple network devices, and each network device may include other numbers of terminal devices within its coverage range, such as more or fewer terminal devices, which is not limited in this embodiment of the present application. The following describes terminal devices and network devices in detail.

[0155] A terminal device is a device with wireless transceiver capabilities. The terminal device can communicate with an access network device (or also referred to as an access device) in a radio access network (RAN). The terminal device may also be referred to as user equipment (UE), access terminal, terminal, subscriber unit, user station, mobile station, remote station, remote terminal, mobile device, user terminal, user agent, or user device. In one possible implementation, the terminal device may be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; it may also be deployed on water (such as a ship, etc.). In one possible implementation, the terminal device may be a handheld device with wireless communication capabilities, a vehicle-mounted device, a wearable device, a sensor, a terminal in the Internet of Things, a terminal in the Internet of Vehicles, a drone, a terminal device in any form in a 5G network or future network, etc., and the embodiments of the present application are not limited to this. It is understood that the terminal device shown in the embodiments of the present application may include not only vehicles (such as cars) in the Internet of Vehicles, but also vehicle-mounted devices or vehicle-mounted terminals in the Internet of Vehicles, etc. The embodiments of the present application do not limit the specific form of the terminal device when applied to the Internet of Vehicles. It can be understood that the terminal devices shown in the embodiments of the present application can also communicate with each other through technologies such as D2D, V2X or M2M. The embodiments of the present application do not limit the communication method between terminal devices.

[0156] A network device may be a device deployed in a wireless access network to provide wireless communication services to terminal devices. The network device may also be referred to as an access network device, access device, or RAN device. Exemplarily, the network device may be a next-generation node B (gNB), a next-generation evolved node B (ng-eNB), or a network device used in 6G communications. The network device may be any device with wireless transceiver capabilities, including but not limited to the base stations described above (including base stations deployed on satellites). The network device may also be a device with base station functionality in 6G. Optionally, the network device may be an access node, wireless relay node, or wireless backhaul node in a wireless local area network (Wi-Fi) system. Optionally, the network device may be a wireless controller in a cloud radio access network (CRAN) scenario. Optionally, the network device may be a wearable device or an in-vehicle device. Optionally, the network device may also be a small cell, a transmission reception point (TRP) (or also referred to as a transmission point), or the like. It is understandable that the network device may also be a base station, satellite, or the like in a future evolved public land mobile network (PLMN). The network device may also be a communication device that carries base station functions in a non-terrestrial communication system, D2D, V2X, or M2M, and the specific type of network device is not limited in the embodiments of the present application. In systems with different wireless access technologies, the names of communication devices with network device functions may be different, and the embodiments of the present application will not list them one by one. Optionally, in some deployments of network devices, the network device may include a centralized unit (CU) and a distributed unit (DU), etc. In other deployments of network devices, the CU may also be divided into a CU-control plane (CP) and a CU-user plane (UP), etc. In still other deployments of network devices, the network device may also be an open radio access network (ORAN) architecture, etc., and the embodiments of the present application do not limit the specific deployment method of the network device.

[0157] An embodiment of the present application provides an LDPC code encoding method, which is executed by a network device at a transmitting end, and includes obtaining an information bit sequence; performing low-density parity check (LDPC) encoding on the information bit sequence according to a check matrix to obtain a coded bit sequence; wherein the check matrix is ​​determined by a base matrix, and the base matrix includes a basic submatrix; the basic submatrix is ​​spliced ​​by at least two basic unit blocks with cycles or translations; and then the coded bit sequence is sent to a receiving end device.

[0158] Correspondingly, an LDPC code decoding method provided in an embodiment of the present application is executed by a network device at the receiving end, including obtaining a first log-likelihood ratio LLR sequence corresponding to a received first channel reception sequence; and decoding the first LLR sequence according to a check matrix.

[0159] The embodiment of the present application proposes a design scheme for Multi-edge LDPC codes based on a cyclic structure, which covers all isomorphic matrices and their sub-matrices at the same time. It adopts the idea of ​​jointly designing the base matrix and the shifting value, proposes a combination form of the shifting value, and characterizes the numerical characteristics of the shifting value based on the formula expression from the perspective of short cycle free, and describes the relationship between the shifting value design scheme and the lifting size. The base matrix of the Multi-edge cyclic form has a consistent threshold value compared with the base matrix of the core array of 5G NR. Multi-edge LDPC lacks practical code design, and it is difficult to find a cycle-free exponential matrix through random search. Compared with Single-edge LDPC, Multi-edge LDPC can achieve cycle free or a small number of cycles at a smaller lifting size. In this scheme, when the base matrix is ​​determined, the shifting value design has no error floor, ensuring fine granularity while ensuring performance.

[0160] First, the form of the base matrix BG in this application is explained: it is generated by concatenating / truncation of single cyclic blocks. A single cyclic block can be composed of a superposition of multiple polynomials with coefficients of 0 and 1, and is determined by the block dimension m.

[0161] Specifically, the number and position of non-zero values ​​in the first row of a single loop block are determined by a column identification vector; the number of elements in the column identification vector corresponds to the number of non-zero values ​​in the first row, and the size of the elements in the column identification vector represents the column identifier of the non-zero position in the first row; the column identification vector is determined by the degree of non-zero coefficients in the polynomial; different single loop blocks correspond to different polynomials. Specifically, the formation method can be as follows:

[0162] First, assume that the dimension of the basis matrix is ​​m*m, and take the elements of vector p (vector p is the number of non-zero coefficients in the polynomial) as column indices, and take the position value of the remaining elements as 0 to generate the first row of the matrix; then the non-zero position of each row is formed by shifting the previous row to the right by 1 unit, generating an m*m dimensional cyclic block; then, the cyclic blocks generated by the vector p of multiple polynomials are superimposed to generate a basic unit block.

[0163] For example: polynomial g(x) = 2 + x 3 It can be expressed by the polynomial g(x)=1+x 3 and the polynomial g(x)=1, then the cyclic blocks generated by the vector p of these two polynomials are superimposed to generate a basic unit block, as shown in FIG7 , a schematic diagram of the generation principle of the basic unit block of the embodiment of the present application, where the polynomial g(x)=1+x 3 The degree of the nonzero coefficients of the polynomial g(x) = 1 is 0; then the vector p = (0), which yields the nonzero elements in the first row of the left matrix. The left matrix is ​​formed by shifting the nonzero positions in each row by 1 unit to the right. The degree of the nonzero coefficients of the polynomial g(x) = 1 is 0; then the vector p = (0), which yields the nonzero elements in the first row of the right matrix. The right matrix is ​​formed by shifting the nonzero positions in each row by 1 unit to the right. This yields two different single-loop blocks, which are then superimposed to form a basic unit block.

[0164] The base matrix of the present application is formed by splicing basic sub-matrices, and the basic sub-matrix is ​​spliced ​​by at least two basic unit blocks with cycles or translations. The basic unit block can be generated by superimposing at least two single-cycle blocks (such as the superposition of two different single-cycle blocks in Figure 7). That is, the base matrix of the present application includes the base graph spliced / truncated by the basic unit blocks, and all matrices isomorphic to it.

[0165] Taking the m×N Base Graph, the basic unit block splicing, taking the 4-row N-column non-fully connected Base Graph as an example, the matrix characteristics are as shown in Figure 8. The basic unit block splicing diagram has m rows and n columns, and the last basic unit block g j (x) can only be cut off part of it as BG. j (x) Select columns with row weights as even as possible.

[0166] In the embodiment of the present application, there are two ways to splice the basic unit blocks: mixed splicing (i.e., splicing different basic unit blocks) and non-mixed splicing (i.e., splicing the same basic unit blocks). Take the 4×n basis matrix BG design as an example, and take the case where the row and column weights are both three as an example:

[0167] As shown in Figure 9, hybrid splicing can be formed by combining four different basic unit blocks in any proportion to form a 4×n column weight three BG. Figure 10 shows a schematic diagram of a hybrid spliced ​​4×n high-rate BG with four rows of 3 / 4 edge density. The three different basic unit blocks can be regarded as a hybrid unit (that is, the basic sub-matrix corresponding to the hybrid splicing method). The base matrix in the embodiment of the present application can be spliced ​​by multiple hybrid units.

[0168] Non-hybrid splicing can be as shown in Figure 11, where each basic unit block of each splicing is the same. In this case, each basic unit block can be regarded as a basic sub-matrix. The base matrix in the embodiment of the present application can be formed by splicing multiple identical basic unit blocks. Figure 11 shows a schematic diagram of a non-hybrid splicing 4×n high-rate BG with four rows of 3 / 4 edge density.

[0169] This construction method is very universal. The embodiment of the present application is aimed at this type of base graph and designs its corresponding Shifting Value.

[0170] The following describes the design of the Shifting Value with a loop structure in this application:

[0171] For basic submatrices spliced ​​together from different basic unit blocks: Different basic unit blocks can be formed by stacking at least two submatrices. The at least two submatrices can include a first submatrix and a second submatrix; wherein the first submatrix can be formed by splicing together at least two single-sided quasi-cyclic LDPC unit blocks in a mixed manner; and the second submatrix can be formed by splicing together at least two single-sided quasi-cyclic LDPC unit blocks in a non-mixed or mixed manner.

[0172] The values ​​in the basic submatrix include 0, 1, and 2; a position with a value of 0 represents no shift value element, a position with a value of 1 represents one shift value element, and a position with a value of 2 represents two shift value elements. In this embodiment of the application, a value of 2 is used as an example to represent two shift value elements, but the value is not limited to 2.

[0173] The shift value matrix corresponding to the basic sub-matrix is ​​composed of a first shift value matrix corresponding to the first unilateral quasi-cyclic LDPC unit block and a second shift value matrix corresponding to the second unilateral quasi-cyclic LDPC unit block; the shift value matrix corresponding to each basic unit block in the first shift value matrix satisfies a single-block cycle; the second shift value matrix satisfies a cycle with W units shifted; W is related to the total number of columns of the basic sub-matrix.

[0174] In one implementation, the translation mode of at least one matrix is ​​non-mixed; the splitting rule is that the values ​​at the same position are split into at least two matrices, so that any matrix is ​​a single-sided QC-LDPC; the at least two matrices have SV value design modes that respectively satisfy the cyclic characteristics, wherein the mixed form of the single-sided QC-LDPC is a single block cycle of the basic unit block, and the split non-mixed matrix is ​​a cycle of a certain unit of the translation of the entire hybrid unit (for example: the example in the figure is a translation units of left loop).

[0175] Taking the four-row 3 / 4 edge density multi-sided QC-LDPC base graph of Figure 10 as an example, as shown in Figure 12a, the principle schematic diagram of the SV value design provided by the embodiment of the present application, its SV value can be decomposed into a combination of different forms of single-sided QC-LDPC. The mixed form of single-sided QC-LDPC is the first sub-matrix of the present application, and the corresponding shift value matrix is ​​the first shift value matrix of the present application; the non-mixed form of single-sided QC-LDPC is the second sub-matrix of the present application, and the corresponding shift value matrix is ​​the second shift value matrix of the present application. That is, the second sub-matrix in Figure 12a is explained using the non-mixed splicing of single-sided QC-LDPC as an example.

[0176] As shown in Figure 12a, the SV value satisfies the cyclic characteristic, and the SV value of the same texture is the same. It is understandable that the embodiment of the present application is to illustrate the texture filling adopted in order to illustrate the circulation or translation law of the SV value. In actual applications, there is no texture in the matrix. For the basic sub-matrix formed by the splicing of the mixing units, the shift values ​​corresponding to the same position (which can be understood as the same position of the mixing unit) between the basic sub-matrices are the same or satisfy the arithmetic progression characteristics. Taking n=12 in Figure 10 as an example, the non-mixed form of unilateral QC-LDPC conforms to the cycle of the entire mixing unit with a left translation of W=3 units.

[0177] For example, the basic sub-matrix is ​​a 4×n matrix; the shift value A of the shift value matrix corresponding to the basic sub-matrix is i (j) satisfies the following formula (3):

[0178] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix;

[0179] The B i (j) is generated by the translation of a vector h, where the value of the vector h satisfies the formula The sequence is based on the number of columns of the basic sub-matrix as a unit, and each cycle is to the left units to form the next row.

[0180] Taking 12 columns as an example, as shown in FIG12b , a schematic diagram of a Shifting Value design corresponding to a 4×n BG provided in an embodiment of the present application is shown. The mixing unit is shown in the upper part of FIG12b , and the SV value example in the lower part of FIG12b can be obtained by the above formula (3).

[0181] The above example can obtain the following theoretical guarantee: for any N, when the lifting factor is When within the range, the matrix C4free.

[0182] For the basic submatrix composed of identical basic unit blocks, the same basic unit block is constructed by stacking two single-sided quasi-cyclic LDPC unit blocks. The shift value matrix corresponding to the basic submatrix has a cyclic property. The values ​​in the basic submatrix include 0, 1, and 2. The position with a value of 0 represents no shift value element, the position with a value of 1 represents one shift value element, and the position with a value of 2 represents two shift value elements.

[0183] Exemplarily, the basic sub-matrix may be a 4×n matrix; the shift values ​​corresponding to the first two rows in the basic sub-matrix are shifted by two positions as the shift values ​​corresponding to the third and fourth rows in the basic sub-matrix.

[0184] Taking the four-row 3 / 4 edge density multilateral QC-LDPC base graph of Figure 11 as an example, as shown in Figure 13, a schematic diagram of the principle of SV value design provided by an embodiment of the present application, a single basic cyclic block, the same texture CPM, and the same shifting value; the lower part of Figure 13 corresponds to that for BGs with the same (isomorphic) row and column transformations, the shifting value digital sequence in the same color box is the same.

[0185] For example, the basic sub-matrix is ​​a 4×n matrix; the shift value A of the shift value matrix corresponding to the basic sub-matrix is i (j) satisfies the following formula (4):

[0186] Here, x and y are functions of i and are related to the size of the lifting factor and the total number of columns in the base graph. The following examples are divided into five options to give specific x and y design methods.

[0187] Option 1:

[0188] For formula (4),

[0189] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0190] Taking 12 columns and 16 columns as examples, FIG14 shows a schematic diagram of a Shifting Value design corresponding to a 4×n BG provided in an embodiment of the present application. An example of the SV value can be obtained by the above formula (4).

[0191] Option 1 above can be theoretically guaranteed as follows: When within the range, the matrix C4free can adapt to the requirements of fine-grained code length and ensure performance.

[0192] Option 2:

[0193] For formula (4),

[0194] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0195] Taking 20 columns and 24 columns as examples, FIG15 shows another schematic diagram of Shifting Value design corresponding to 4×n BG provided in an embodiment of the present application. An example of SV value can be obtained by the above formula (4).

[0196] Option 2 above can be theoretically guaranteed as follows: for any n, when When within the range, the matrix C4free.

[0197] Option 3:

[0198] For formula (4),

[0199] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0200] Taking 12 columns as an example, as shown in FIG16 , another schematic diagram of Shifting Value design corresponding to 4×n BG provided in an embodiment of the present application, an example of SV value can be obtained by the above formula (4).

[0201] Option 3 above can be theoretically guaranteed as follows: for any n, when lifting size ≥ all odd numbers in the range n-1, the matrix is ​​C4-free.

[0202] Option 4:

[0203] For formula (4),

[0204] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0205] Taking 12, 16, 20 and 24 columns as examples, as shown in FIG17 , another Shifting Value design diagram corresponding to a 4×n BG provided in an embodiment of the present application can be obtained by using the above formula (4). The value on the left side of the matrix is ​​the minimum lifting size that satisfies the circle property.

[0206] Option 4 above can be theoretically guaranteed as follows: when the lifting size is When the lifting Only when the lifting size is z is any positive integer that does not satisfy C4 or C6 free conditions. This allows the rounding requirements of different code lengths to be met, ensuring stable performance.

[0207] Option 5:

[0208] For formula (4),

[0209] When t is an odd number, When t is an even number,

[0210] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0211] Option 5 above can be theoretically guaranteed as follows: for any n, when When , the matrix C4, C6 is free. It can meet the requirements of different code lengths for circles and ensure stable performance.

[0212] Take 12, 16, 20 and 24 columns respectively, and when t is an odd number, take When t is an even number,

[0213] For example, as shown in FIG18 , another Shifting Value design diagram corresponding to a 4×n BG according to an embodiment of the present application, an example of the SV value can be obtained by the above formula (4). The value on the left side of the matrix is ​​the minimum Lifting Size that satisfies the circle property.

[0214] That is, the following theoretical guarantee can be obtained at this time: when t is an odd number, when When t is an even number, C4, C6-free, or with only a small amount of C6, evenly distributed, with no error floor. This meets the requirements of different code lengths for loops and ensures stable performance.

[0215] For example, the basic sub-matrix is ​​a 4×n matrix; the shift value A of the shift value matrix corresponding to the basic sub-matrix is i (j) satisfies the following formula (5):

[0216] Here, x and y are functions of i and are related to the size of the lifting factor and the total number of columns in the base graph. The following two examples provide specific x and y design methods.

[0217] Option a:

[0218] For formula (5),

[0219] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0220] Taking 12 columns as an example, as shown in FIG19 , a schematic diagram of a Shifting Value design corresponding to another 4×n BG provided in an embodiment of the present application, an example of the SV value can be obtained by the above formula (5).

[0221] Option a above can be theoretically guaranteed as follows: For all odd numbers, the matrix is ​​C4free.

[0222] It is understandable that there may be other ways to determine the values ​​of y1(i) and y2(i): for all i and j, and i≠j, y1 and y2 that satisfy the conditions y1(i)≠y1(j), y2(i)≠y2(j), y1(i)≠y2(j), y1(i)≠y2(i) can replace the corresponding positions in the above formula.

[0223] Option b:

[0224] For formula (5),

[0225] The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

[0226] Taking 12 columns as an example, FIG20 a shows another schematic diagram of Shifting Value design corresponding to 4×n BG provided in an embodiment of the present application. An example of SV value can be obtained by the above formula (5).

[0227] Option b above can be theoretically guaranteed as follows: The matrix C4free.

[0228] Through the above embodiments, the non-fully connected BG designed by this application and the fine-grained Shifting Value design scheme can achieve C4-free at a smaller scale compared to the fully connected i*j design method. For the construction method of the fully connected BG based on the finite field, the shifting value of the i row and j column is the construction method of S_i*R_j, and the minimum lifting size is n (number of columns), and it is required to be a prime number. The Shifting Value of the construction method designed by this application can be jointly optimized with the non-fully connected BG, and the code length n is not required to be a prime number. The minimum lifting size of C4-free is smaller in magnitude. The Shifting Value design has no error floor, which is consistent with the best Shifting Value performance of random search, as shown in the performance diagram of Figure 20b.

[0229] The structure of a communication device that can implement the LDPC code encoding method or LDPC code decoding method provided in the embodiments of the present application is described below with reference to the accompanying drawings.

[0230] Figure 21 is a schematic diagram of the structure of a communication device 2100 provided in an embodiment of the present application. The communication device 2100 can implement the functions or steps implemented by the transmitting network device or the receiving network device in each of the above-mentioned method embodiments. The communication device may include a processing module 2110 and an interface module 2120. Optionally, it may also include a storage unit, which can be used to store instructions (code or program) and / or data. The processing module 2110 and the interface module 2120 can be coupled to the storage unit. For example, the processing module 2110 can read the instructions (code or program) and / or data in the storage unit to implement the corresponding method. The above-mentioned units can be set independently or partially or fully integrated. For example, the interface module 2120 may include a sending module and a receiving module. The sending module can be a transmitter, and the receiving module can be a receiver. The entity corresponding to the interface module 2120 can be a transceiver or a communication interface.

[0231] In some possible implementations, the communication device 2100 can implement the corresponding behaviors and functions of the transmitting or receiving network devices in the above-described method embodiments. For example, the communication device 2100 can be a transmitting or receiving device, or a component (e.g., a chip or circuit) used in the transmitting or receiving device. The interface module 2120 is used to perform all information receiving or sending operations. The processing module 2110 is used to perform all operations except the sending and receiving operations.

[0232] Figure 22 is a schematic diagram of the structure of another communication device 220 provided in an embodiment of the present application. The communication device in Figure 22 can correspondingly implement the functions or steps implemented by the transmitting end network device or the receiving end network device in each of the above method embodiments.

[0233] As shown in FIG. 22 , the communication device 220 includes at least one processor 2210 and a transceiver 2220 .

[0234] In some embodiments of the present application, the transceiver 2220, for example, performs all receiving or sending operations of the transmitting end network device or the receiving end network device in the above-mentioned various method embodiments. The processor 2210, for example, performs all operations of the transmitting end network device or the receiving end network device in the above-mentioned various method embodiments except for the sending and receiving operations.

[0235] The transceiver 2220 is used to communicate with other devices / apparatuses via a transmission medium. The processor 2210 utilizes the transceiver 2220 to transmit and receive data and / or signaling, and is used to implement the methods described in the above method embodiments. The processor 2210 can implement the functions of the processing module 2110, and the transceiver 2220 can implement the functions of the interface module 2120.

[0236] Optionally, the communication device 220 may further include at least one memory 2230 for storing program instructions and / or data. The memory 2230 is coupled to the processor 2210. Coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units, or modules, which may be electrical, mechanical, or other forms, and is used for information exchange between devices, units, or modules. The processor 2210 may operate in conjunction with the memory 2230. The processor 2210 may execute program instructions stored in the memory 2230. At least one of the at least one memory may be included in the processor.

[0237] The specific connection medium between the transceiver 2220, processor 2210, and memory 2230 is not limited in the embodiments of the present application. In Figure 22, the memory 2230, processor 2210, and transceiver 2220 are connected via a bus 2240. The bus is represented by a bold line in Figure 22. The connection methods between other components are merely schematic and are not limiting. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 22 only uses a single bold line, but this does not mean that there is only one bus or only one type of bus.

[0238] In the embodiments of the present application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present application may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0239] Figure 23 is a schematic diagram of the structure of another communication device 230 provided in an embodiment of the present application. As shown in Figure 23, the communication device shown in Figure 23 includes a logic circuit 2301 and an interface 2302. The processing module 2110 in Figure 21 can be implemented with a logic circuit 2301, and the interface module 2120 in Figure 21 can be implemented with an interface 2302. Among them, the logic circuit 2301 can be a chip, a processing circuit, an integrated circuit or a system on chip (SoC) chip, etc., and the interface 2302 can be a communication interface, an input and output interface, etc. In the embodiment of the present application, the logic circuit and the interface can also be coupled to each other. The embodiment of the present application does not limit the specific connection method of the logic circuit and the interface.

[0240] In some embodiments of the present application, the logic circuit and interface may be used to execute the functions or operations performed by the transmitting-end network device or the receiving-end network device in the above-mentioned various method embodiments.

[0241] The present application also provides a computer-readable storage medium, in which a computer program or instruction is stored. When the computer program or instruction is executed on a computer, the computer executes the method of the above embodiment.

[0242] The present application also provides a computer program product, which includes instructions or a computer program. When the instructions or the computer program are run on a computer, the method in the above embodiment is executed.

[0243] The present application also provides a communication system, comprising the above-mentioned transmitting end and the above-mentioned receiving end.

[0244] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the above claims.

Claims

1. A coding method for LDPC codes, characterized in that: include: obtaining an information bit sequence; Performing low-density parity check (LDPC) coding on the information bit sequence according to a check matrix to obtain a coded bit sequence; The check matrix is ​​determined by a base matrix, and the base matrix includes a basic sub-matrix; the basic sub-matrix is ​​formed by splicing at least two basic unit blocks with circulation or translation.

2. A decoding method for an LDPC code, characterized in that: include: Obtaining a first log-likelihood ratio (LLR) sequence corresponding to the received first channel reception sequence; Decoding the first LLR sequence according to a check matrix; The check matrix is ​​determined by a base matrix, and the base matrix includes a basic sub-matrix; the basic sub-matrix is ​​formed by splicing at least two basic unit blocks with circulation or translation.

3. The method according to claim 1 or 2, characterized in that The base matrix also includes a portion of the truncated and concatenated basic sub-matrix.

4. The method according to any one of claims 1 to 3, characterized in that The basic unit block is formed by stacking at least two single-cycle blocks.

5. The method according to any one of claims 1 to 4, characterized in that The loop structure of the single loop block itself is as follows: starting from the second row, the non-zero position of the current row is the position of the non-zero position of the previous row shifted by 1 unit; the non-zero position of the first row is the position of the non-zero position of the last row shifted by 1 unit; different single loop blocks have different non-zero positions and / or numbers of non-zeros in the first row.

6. The method according to any one of claims 1 to 5, characterized in that The at least two basic unit blocks include at least two different basic unit blocks.

7. The method according to claim 6, characterized in that The basic sub-matrix is ​​formed by superimposing at least two sub-matrices.

8. The method according to claim 7, characterized in that The values ​​of the basic submatrix include 0, 1 and 2; the position with the value 0 represents no shift value element, the position with the value 1 represents 1 shift value element, and the position with the value 2 represents 2 shift value elements.

9. The method according to claim 8, characterized in that The at least two sub-matrices include a first sub-matrix and a second sub-matrix; wherein, The first sub-matrix is ​​formed by mixing and splicing at least two single-block cyclic unilateral quasi-cyclic LDPC unit blocks; The second sub-matrix is ​​formed by non-mixing or mixing splicing of at least two single-sided quasi-cyclic LDPC unit blocks.

10. The method according to claim 9, characterized in that The shift value matrix corresponding to the basic sub-matrix is ​​formed by combining a first shift value matrix corresponding to the first sub-matrix and a second shift value matrix corresponding to the second sub-matrix; The shift value matrix corresponding to each basic unit block in the first shift value matrix satisfies a p-row shift cycle, where p is an integer greater than or equal to 1; The second shift value matrix satisfies the requirement of shifting W units in a cycle; The W is related to the total number of columns of the basic sub-matrix.

11. The method according to any one of claims 8 to 10, characterized in that: The base matrix includes a plurality of basic sub-matrices, and the shift values ​​corresponding to the same positions among the plurality of basic sub-matrices are the same or satisfy an arithmetic progression characteristic.

12. The method according to any one of claims 8 to 11, characterized in that The basic sub-matrix is ​​a 4×n matrix; the basic sub-matrix corresponds to the shift value A of the shift value matrix i (j) A corresponding to the position where the basic submatrix takes a value of 2 i (j) is related to the total number of columns of the basic sub-matrix and the column index where the position of 2 is located.

13. The method according to claim 12, characterized in that The shift value A of the shift value matrix i (j) Satisfy the following formula: The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix; The B i (j) is generated by the translation of a vector h, where the value of the vector h satisfies the formula The sequence is based on the number of columns of the basic sub-matrix as a unit, and each cycle is to the left units to form the next row.

14. The method according to any one of claims 1 to 5, characterized in that The at least two basic unit blocks include the same basic unit block components.

15. The method according to claim 14, characterized in that The same basic unit block is formed by superimposing two single-sided quasi-cyclic LDPC unit blocks.

16. The method according to claim 15, characterized in that The values ​​of the basic submatrix include 0, 1 and 2; the position with the value 0 represents no shift value element, the position with the value 1 represents 1 shift value element, and the position with the value 2 represents 2 shift value elements.

17. The method according to claim 16, characterized in that The shift value matrix corresponding to the basic sub-matrix has a cyclic characteristic.

18. The method according to claim 16, characterized in that The basic sub-matrix is ​​a 4×n matrix; the shift values ​​corresponding to the first two rows in the basic sub-matrix are shifted by two positions to serve as the shift values ​​corresponding to the third and fourth rows in the basic sub-matrix.

19. The method according to claim 18, characterized in that The shift value A of the shift value matrix corresponding to the basic sub-matrix i (j) A corresponding to the position where the basic submatrix takes a value of 2 i (j) is related to the total number of columns of the basic sub-matrix and the column index where the position of 2 is located.

20. The method according to claim 19, characterized in that The shift value A of the shift value matrix i (j) Satisfy the following formula: The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

21. The method according to claim 19, wherein The shift value A of the shift value matrix i (j) Satisfy the following formula: The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

22. The method according to claim 19, wherein The shift value A of the shift value matrix i (j) Satisfy the following formula: The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

23. The method according to claim 19, wherein The shift value A of the shift value matrix i (j) Satisfy the following formula: The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

24. The method according to claim 19, wherein The shift value A of the shift value matrix i (j) Satisfy the following formula: When t is an odd number, When t is an even number, The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic submatrix; and the s is an arbitrary integer.

25. The method according to claim 19, wherein The shift value A of the shift value matrix i (j) Satisfy the following formula: The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

26. The method according to claim 19, wherein The shift value A of the shift value matrix i (j) Satisfy the following formula: The i is a column number identifier, ranging from 1 to the n; the j is a value of the basic sub-matrix.

27. A communication device, characterized in that: The method comprises modules or units for implementing the method according to any one of claims 1 to 26.

28. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed, the method according to any one of claims 1 to 26 is executed.

29. A communication device, characterized in that: The communication device comprises a processor, the processor is coupled to a memory, the memory stores instructions, and the processor is configured to execute the instructions so that the communication device performs the method according to any one of claims 1 to 26.

30. The communication device according to claim 29, wherein: Also included is the memory.

31. The communication device according to claim 29 or 30, characterized in that A transceiver is also included for receiving signals and / or sending signals.

32. A computer program product, characterized in that A computer program is included, comprising program instructions which, when executed, cause the method of any one of claims 1 to 26 to be performed.

33. A communication device, characterized in that: The method comprises a logic circuit and an interface, wherein the logic circuit is used to execute the method according to any one of claims 1 to 26, and the interface is used to receive signals and / or send signals.

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