Data stream error detection and correction verification method, device and equipment and storage medium

Abstract

The application discloses a data stream error detection and correction verification method and device, equipment and a storage medium, and the method comprises the following steps: reading the first data stream output after the sending end Hamming code encoding, decoding the first data stream, and obtaining the first information code; obtaining the first check code according to the first information code, performing XOR operation on the first check code and the first original check code in the first data stream, and obtaining the first verification result; Hamming code encoding the second information code to obtain the second data stream, and sending the second data stream to the receiving end; obtaining the second check code after the receiving end decodes the second data stream, performing XOR operation on the second check code and the second original check code in the second data stream, and obtaining the second verification result; and obtaining the verification result of the data stream transmission process error detection and correction based on the first verification result, the first data stream, the second verification result and the second data stream. The verification of the Hamming code SECDED check data stream can be realized, and the data processing speed is high.

Description

Technical Field

[0001] This invention belongs to the field of FPGA (Field Programmable Gate Array) technology, and in particular relates to verification methods, devices, equipment and storage media for data flow error detection and correction. Background Technology

[0002] Hamming code is a linear debugging code used in the telecommunications field, named after its inventor, Richard Wesley Hamming. Hamming codes insert verification bits into the transmitted message stream to detect and correct bit errors that occur when a computer stores or moves data streams. Due to their simplicity, Hamming codes are widely used in RAM. The SECDED (single error correction, double error detection) version of Hamming code adds an additional detection bit, enabling the detection of two or fewer simultaneous bit errors and the correction of single-bit errors. Current implementations of Hamming code SECDED for data stream verification use a C language implementation via a DPI (Direct Programming Interface), resulting in slow data processing and simulation speeds, low verification efficiency, long development cycles, and a lack of verification of the location where data bit errors occur. Summary of the Invention

[0003] Based on this, the present invention provides a verification method, apparatus, device and storage medium for data stream error detection and correction, which solves the problems of slow data processing speed and lack of verification of the location of data bit errors in existing Hamming code data stream verification.

[0004] This invention provides a verification method for data stream error detection and correction, the method comprising:

[0005] S1: Read the first data stream output after Hamming code encoding at the sending end, decode the first data stream, and obtain the first information code;

[0006] S2: Obtain the first verification code according to the first information code, and XOR the first verification code with the first original verification code in the first data stream to obtain the first verification result. The first verification result is used to verify whether the encoding of the first data stream is correct.

[0007] S3: Encode the second information code using Hamming code to obtain the second data stream, and send the second data stream to the receiving end;

[0008] S4: Obtain the second check code after the receiver decodes the second data stream, XOR the second check code with the second original check code in the second data stream to obtain the second verification result, which is used to verify whether the receiver's decoding is correct;

[0009] S5: Based on the first verification result, the first data stream, the second verification result, and the second data stream, obtain the verification result of error detection and correction during the data stream transmission process.

[0010] Furthermore, the process after S4 and before S5 includes:

[0011] Decode the second data stream and output the first signal based on the decoding result;

[0012] Obtain the second signal output by the receiver after decoding the second data stream;

[0013] Using the first signal as a reference, compare the first signal and the second signal. If the second signal is consistent with the first signal, then the decoding function of the receiving end is normal.

[0014] Further, in step S2, the first detection bit is obtained based on the first information code stream as follows:

[0015] The length of the first check code is calculated from the length of the first information code. The position of the first check code is determined based on the length of the first check code. Zeros are padded at the position of the first check code. The first information code with the same check position as the first check code is XORed to obtain the value of the first check code.

[0016] Furthermore, S5 specifically includes:

[0017] If no errors occur in the first verification result and the second verification result, then no errors occur during the data stream transmission process;

[0018] If the first verification result contains a bit error, obtain the first overall check code after decoding the first data stream, and XOR the first overall check code with the first original overall check code in the first data stream. If the result is zero, the encoding of the first data stream has a single-bit error; otherwise, it is a double-bit error. The first original overall check code is obtained by XORing the data stream composed of the information code and the check code in the first data stream.

[0019] If the second verification result has a bit error, obtain the second overall check code after decoding the second data stream, and XOR the second overall check code with the second original overall check code in the second data stream. If the result is zero, the receiving end has a single bit error in decoding; otherwise, it is a double bit error. The second original overall check code is obtained by XORing the data stream composed of the information code and the check code in the second data stream.

[0020] Furthermore, the verification method for data flow error detection and correction is implemented using System Verilog or VHDL.

[0021] Furthermore, the length of the first check code, calculated from the length of the first information code, is 2. m ≥m+k+1, where m is the length of the first check code and k is the length of the first information code.

[0022] Further, determining the position of the first check code based on its length is as follows:

[0023] The first checksum is in the second position of the first data stream. t Bits, where t = 0, 1, 2, ..., m-1, and m is the length of the first check code.

[0024] The present invention also provides a verification device for data stream error detection and correction, the device comprising:

[0025] The reading module is used to read the first data stream output after Hamming code encoding at the sending end, decode the first data stream, and obtain the first information code.

[0026] The first verification result acquisition module is used to acquire a first verification code based on the first information code, and to perform an XOR operation between the first verification code and the first original verification code in the first data stream to obtain a first verification result. The first verification result is used to verify whether the encoding of the first data stream is correct.

[0027] The encoding module is used to encode the second information code using Hamming code to obtain the second data stream, and then send the second data stream to the receiving end.

[0028] The second verification result acquisition module is used to acquire the second check code after the receiving end decodes the second data stream, and to XOR the second check code with the second original check code in the second data stream to obtain the second verification result. The second verification result is used to verify whether the decoding by the receiving end is correct.

[0029] The verification result acquisition module is used to acquire the verification results of error detection and correction during the data stream transmission process based on the first verification result, the first data stream, the second verification result, and the second data stream.

[0030] The present invention also provides a computer device, the computer device comprising:

[0031] Memory containing executable program code;

[0032] The processor connected to the memory;

[0033] The processor calls the executable program code stored in the memory to execute the data stream error detection and correction verification method described in any of the above-mentioned embodiments.

[0034] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the data stream error detection and correction verification method described in any of the preceding claims.

[0035] The data stream error detection and correction verification method provided by this invention can verify the Hamming code SECDED check data stream, and features fast data processing and simulation speeds, high verification efficiency, and shortened development cycle. It also verifies the location of data bit errors. The data stream error detection and correction verification device, equipment, and storage medium provided by this invention can also achieve the above effects. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A flowchart illustrating the verification method for data stream error detection and correction provided in this embodiment of the invention;

[0038] Figure 2 This is an application scenario for a data stream error detection and correction verification method provided in an embodiment of the present invention;

[0039] Figure 3 A flowchart illustrating another data stream error detection and correction verification method provided in an embodiment of the present invention;

[0040] Figure 4 This is a structural block diagram of a data stream error detection and correction verification device provided in an embodiment of the present invention.

[0041] Figure 5 This is a schematic diagram of the structure of a computer device disclosed in an embodiment of the present invention;

[0042] Figure 6An embodiment of the present invention discloses a computer storage medium. Detailed Implementation

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0044] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0046] In the following description, suffixes such as “module,” “part,” or “unit” used to denote elements are used only for the purposes of this application and have no specific meaning in themselves.

[0047] like Figure 1 The diagram shown is a flowchart illustrating the verification method for data stream error detection and correction provided in an embodiment of the present invention. The method includes:

[0048] S1: Read the first data stream output after Hamming code encoding at the sending end, decode the first data stream, and obtain the first information code;

[0049] S2: Obtain the first verification code according to the first information code, and XOR the first verification code with the first original verification code in the first data stream to obtain the first verification result. The first verification result is used to verify whether the encoding of the first data stream is correct.

[0050] S3: Encode the second information code using Hamming code to obtain the second data stream, and send the second data stream to the receiving end;

[0051] S4: Obtain the second check code after the receiver decodes the second data stream, XOR the second check code with the second original check code in the second data stream to obtain the second verification result, which is used to verify whether the receiver's decoding is correct;

[0052] S5: Based on the first verification result, the first data stream, the second verification result, and the second data stream, obtain the verification result of error detection and correction during the data stream transmission process.

[0053] Specifically, in this embodiment, such as Figure 2The illustration shows an application scenario of a data stream error detection and correction verification method provided in this embodiment of the invention. The method is applied to an SV (System Verilog) model. At the sending end, the information code is encoded using Hamming code to obtain a first data stream. In the prior art, the first data stream is directly sent to the receiving end. In this application, the receiving end is an FPGA (Field Programmable Gate Array). The FPGA's interface calls C language to perform Hamming code SECDED verification of the data stream. However, this method suffers from slow data processing and simulation speeds, resulting in low verification efficiency. Furthermore, it does not verify whether the data bit error occurs during data stream transmission due to encoding at the output end or decoding at the receiving end. Therefore, this application provides an SV model between the output end and the receiving end. This SV model is a bridge model, including a decoding side and an encoding side. The decoding side reads the first data stream output by the receiving end, decodes the first data stream according to the preset encapsulation format during encoding, obtains the first information code corresponding to the decoded information code, and then performs Hamming code encoding on the first information code to obtain the first check code. Next, the first check code and the first original check code in the first data stream are XORed to obtain the first verification result, which is used to verify whether the encoding of the first data stream is correct. That is, if the result of XORing the first check code and the first original check code is zero, then the transmitting end has not encountered any errors in Hamming code encoding of the information code; if the result of XORing the first check code and the first original check code is one, then the transmitting end has encountered errors in Hamming code encoding of the information code. The encoding side performs Hamming code encoding on the second information code to obtain the second data stream, which is then sent to the FPGA. The FPGA decodes the second data stream. The SV model encoding side obtains the second checksum after the FPGA decodes the second data stream. Then, it XORs the second checksum with the second original checksum in the second data stream to obtain a second verification result used to verify whether the FPGA decoding is correct. That is, if the XOR result of the second checksum and the second original checksum is zero, then no bit error occurred when the FPGA decoded the second data stream; if the XOR result of the second checksum and the second original checksum is one, then a bit error occurred when the FPGA decoded the second data stream. When a bit error occurs when the sending end performs Hamming code encoding on the information code, it determines whether a single-bit error or a double-bit error occurred during the Hamming code encoding based on the first verification result and the first data stream. When a bit error occurs when the FPGA decodes the second data stream, it determines whether a single-bit error or a double-bit error occurred during the Hamming code encoding on the information code by the sending end, based on the second verification result and the second data stream. The above method can be used to verify the Hamming code SECDED check data stream, with fast data processing and simulation speed, high verification efficiency, shortened R&D cycle, and also verify the location of data bit errors.

[0054] In some embodiments, such as Figure 3 The diagram shown is a flowchart illustrating another data stream error detection and correction verification method provided by an embodiment of the present invention. After S4 and before S5, the method further includes:

[0055] S401: Decode the second data stream and output the first signal based on the decoding result;

[0056] S402: Obtain the second signal output by the receiver after decoding the second data stream;

[0057] S403: Using the first signal as a reference, compare the first signal and the second signal. If the second signal is consistent with the first signal, then the decoding function of the receiving end is normal.

[0058] Specifically, in this embodiment, the encoding side of the SV model sends the second data stream to the decoding side. The decoding side decodes the second data stream and generates a first signal as a reference based on the decoding result. Then, the second signal output by the FPGA after decoding the second data stream is acquired, and the second signal is compared with the first signal. If the second signal and the first signal are consistent, it indicates that the FPGA decoding function is normal. Otherwise, the FPGA decoding function is abnormal.

[0059] In some embodiments, obtaining the first detection bit based on the first information code bit stream in S2 is as follows:

[0060] The length of the first check code is calculated from the length of the first information code. The position of the first check code is determined based on the length of the first check code. Zeros are padded at the position of the first check code. The first information code with the same check position as the first check code is XORed to obtain the value of the first check code.

[0061] Preferably, the length of the first check code, calculated from the length of the first information code, is 2. m ≥m+k+1, where m is the length of the first check code and k is the length of the first information code.

[0062] Preferably, determining the position of the first check code based on its length is as follows:

[0063] The first checksum is in the second position of the first data stream. t Bits, where t = 0, 1, 2, ..., m-1, and m is the length of the first check code.

[0064] Specifically, the decoding side of the SV model decodes the first data stream to obtain the first information code after decoding. It calculates the length of the first check code based on the length of the first information code, determines the position of the first check code based on the length of the first check code, pads the position of the first check code with zeros, and then performs an XOR operation on the first information code that is at the same check position as the first check code to obtain the value of the first check code, thereby obtaining the first check code.

[0065] In some embodiments, S5 specifically means: if no errors occur in the first verification result and the second verification result, then no errors occur during the data stream transmission process;

[0066] If the first verification result has a bit error, obtain the first overall check code after decoding the first data stream, and XOR the first overall check code with the first original overall check code in the first data stream. If the result is zero, the first data stream encoding has a single bit error; otherwise, it is a double bit error.

[0067] If the second verification result contains a bit error, the second overall check code after decoding the second data stream is obtained. The second overall check code and the second original overall check code in the second data stream are XORed. If the result is zero, the receiving end has a single-bit error in decoding; otherwise, it is a double-bit error.

[0068] Specifically, in this embodiment, if no errors occur in the first verification result and the second verification result, that is, no errors occur during the encoding process at the sending end and the decoding process at the FPGA, then no errors occur during the data stream transmission. When the first data stream is obtained by Hamming code encoding at the sending end, the data stream composed of the information code and the check code is XORed to obtain the first original overall check code. The data stream composed of the information code and the check code and the first original overall check code are encapsulated with the first original overall check code according to a preset data format to obtain the first data stream. The preset data format can be set according to the user's actual needs. The SV model decoding side reads and decodes the first data stream to obtain the first overall check code corresponding to the first original overall check code. The first overall check code and the first original overall check code in the first data stream are XORed. If the result is zero, then the encoding of the first data stream has a single-bit error; otherwise, it is a double-bit error. When the SV model encoding side performs Hamming code encoding on the second information code, it obtains the check code of the second information code based on the second information code. It then XORs the data stream composed of the second information code and the check code to obtain the second original overall check code. This second original overall check code is then XORed with the second overall check code corresponding to the second original overall check code obtained from the FPGA decoding of the second data stream. If the result is zero, a single-bit error has occurred at the receiving end; otherwise, a double-bit error has occurred. This method implements the specific procedure for verifying the Hamming code's validation of the data stream.

[0069] In some embodiments, the data stream error detection and correction verification method is implemented using System Verilog or VHDL.

[0070] Specifically, SystemVerilog, abbreviated as SV, is a relatively new language. It is built on the Verilog language and is an extension and enhancement of the IEEE 1364 Verilog-2001 standard. It is compatible with Verilog 2001 and combines hardware description language (HDL) with modern high-level verification language (HVL), and has recently become the language for next-generation hardware design and verification.

[0071] VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) is primarily used in digital circuit design. A complete VHDL program consists of five parts: Entity, Architecture, Configuration, Package, and Library. Entities and Architectures are essential basic structures in a VHDL program; they form the simplest VHDL program. Entities describe the external characteristics of circuit devices; Architectures describe the internal logic functions or circuit structure; Packages store data types, constants, and subroutines that can be shared across design modules; Configurations are used to select necessary units from the Library to assemble different versions of the system design; and the Library stores compiled entities, architectures, package sets, and configurations.

[0072] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0073] In some embodiments, such as Figure 4The diagram shows a structural block diagram of a data stream error detection and correction verification device provided in an embodiment of the present invention. The device includes: a reading module 401, used to read a first data stream output after Hamming code encoding at the sending end, decode the first data stream, and obtain a first information code; a first verification result acquisition module 402, used to obtain a first check code based on the first information code, and XOR the first check code with a first original check code in the first data stream to obtain a first verification result, wherein the first verification result is used to verify whether the encoding of the first data stream is correct; an encoding module 403, used to Hamming code encode a second information code to obtain a second data stream, and send the second data stream to the receiving end; a second verification result acquisition module 404, used to obtain a second check code after the receiving end decodes the second data stream, and XOR the second check code with a second original check code in the second data stream to obtain a second verification result, wherein the second verification result is used to verify whether the decoding at the receiving end is correct; and a verification result acquisition module 405, used to acquire the verification result of error detection and correction during data stream transmission based on the first verification result, the first data stream, the second verification result, and the second data stream.

[0074] Specific limitations regarding the verification device for data stream error detection and correction can be found in the limitations of the verification method for data stream error detection and correction described above, and will not be repeated here. Each module in the aforementioned verification device for data stream error detection and correction can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0075] like Figure 5 The diagram shown is a structural schematic of a computer device disclosed in an embodiment of the present invention. The computer device may include:

[0076] Memory 501 storing executable program code;

[0077] Processor 502 connected to memory 501;

[0078] The processor 502 calls the executable program code stored in the memory 501 to execute the steps in the data flow error detection and correction verification method disclosed in this invention.

[0079] like Figure 6 As shown, an embodiment of the present invention discloses a computer storage medium 601, which stores computer instructions. When the computer instructions are invoked, they are used to execute the steps in the data stream error detection and correction verification method disclosed in the present invention.

[0080] The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0081] Through the detailed description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0082] Finally, it should be noted that the automatic error correction method, apparatus, computer device, and storage medium for Chinese text disclosed in the embodiments of the present invention are merely preferred embodiments of the present invention and are only used to illustrate the technical solutions of the present invention, not to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A verification method for data stream error detection and correction, characterized in that, The method includes: S1: Read the first data stream output after Hamming code encoding at the sending end, decode the first data stream, and obtain the first information code; S2: Obtain the first verification code according to the first information code, and XOR the first verification code with the first original verification code in the first data stream to obtain the first verification result. The first verification result is used to verify whether the encoding of the first data stream is correct. S3: Encode the second information code using Hamming code to obtain the second data stream, and send the second data stream to the receiving end; S4: Obtain the second check code after the receiver decodes the second data stream, XOR the second check code with the second original check code in the second data stream to obtain the second verification result, which is used to verify whether the receiver's decoding is correct; S5: Based on the first verification result, the first data stream, the second verification result, and the second data stream, obtain the verification result of error detection and correction during the data stream transmission process.

2. The verification method for data stream error detection and correction according to claim 1, characterized in that, After S4 and before S5, the following are also included: Decode the second data stream and output the first signal based on the decoding result; Obtain the second signal output by the receiver after decoding the second data stream; Using the first signal as a reference, compare the first signal and the second signal. If the second signal is consistent with the first signal, then the decoding function of the receiving end is normal.

3. The verification method for data stream error detection and correction according to claim 1, characterized in that, In step S2, the first detection bit is obtained based on the first information code stream as follows: The length of the first check code is calculated from the length of the first information code. The position of the first check code is determined based on the length of the first check code. Zeros are padded at the position of the first check code. The first information code with the same check position as the first check code is XORed to obtain the value of the first check code.

4. The verification method for data stream error detection and correction according to claim 2, characterized in that, Specifically, S5 is: If no errors occur in the first verification result and the second verification result, then no errors occur during the data stream transmission process; If the first verification result contains a bit error, obtain the first overall check code after decoding the first data stream, and XOR the first overall check code with the first original overall check code in the first data stream. If the result is zero, the encoding of the first data stream has a single-bit error; otherwise, it is a double-bit error. The first original overall check code is obtained by XORing the data stream composed of the information code and the check code in the first data stream. If the second verification result has a bit error, obtain the second overall check code after decoding the second data stream, and XOR the second overall check code with the second original overall check code in the second data stream. If the result is zero, the receiving end has a single bit error in decoding; otherwise, it is a double bit error. The second original overall check code is obtained by XORing the data stream composed of the information code and the check code in the second data stream.

5. The verification method for data stream error detection and correction according to claim 1, characterized in that, The data stream error detection and correction verification method is implemented using SystemVerilog or VHDL.

6. The verification method for data stream error detection and correction according to claim 3, characterized in that, The length of the first check code is calculated from the length of the first information code as: 2m ≥ m + k + 1, where m is the length of the first check code and k is the length of the first information code.

7. The verification method for data stream error detection and correction according to claim 6, characterized in that, The step of determining the position of the first check code based on its length is as follows: The first check code is located at the 2t-th bit of the first data stream, where t = 0, 1, 2, ..., m-1, and m is the length of the first check code.

8. A verification device for data stream error detection and correction, characterized in that, The device includes: The reading module is used to read the first data stream output after Hamming code encoding at the sending end, decode the first data stream, and obtain the first information code. The first verification result acquisition module is used to acquire a first verification code based on the first information code, and to perform an XOR operation between the first verification code and the first original verification code in the first data stream to obtain a first verification result. The first verification result is used to verify whether the encoding of the first data stream is correct. The encoding module is used to encode the second information code using Hamming code to obtain the second data stream, and then send the second data stream to the receiving end. The second verification result acquisition module is used to acquire the second check code after the receiving end decodes the second data stream, and to XOR the second check code with the second original check code in the second data stream to obtain the second verification result. The second verification result is used to verify whether the decoding by the receiving end is correct. The verification result acquisition module is used to acquire the verification results of error detection and correction during the data stream transmission process based on the first verification result, the first data stream, the second verification result, and the second data stream.

9. A computer device, characterized in that, The computer device includes: Memory containing executable program code; The processor connected to the memory; The processor calls the executable program code stored in the memory to execute the data stream error detection and correction verification method as described in any one of claims 1-7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the data stream error detection and correction verification method as described in any one of claims 1-7.

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