Display panel and display device

Abstract

The present disclosure relates to a display panel and a display device, and pertains to the field of display technologies. The display panel includes a display area and a peripheral area including a lead-out area, and the lead-out area includes a bonding portion; the display panel includes a driving backplane, a light-emitting device, a packaging adhesive, and a packaging cover plate. The driving backplane includes a substrate and a circuit layer, and the circuit layer includes a packaging substrate and a power bus distributed in a direction away from the substrate. The packaging substrate is disposed in the peripheral area and surrounds the display area; at least a part of the power bus is located in the lead-out area, and the part of the power bus located in the lead-out area is between the display area and the bonding portion and is connected to the bonding portion; the packaging substrate overlaps with at most the part of the power bus located in the lead-out area; the packaging substrate is a reflective structure. The light-emitting device is disposed on a side of the circuit layer away from the substrate and is located in the display area. The packaging adhesive is at least partially disposed on a surface of the packaging substrate away from the substrate and surrounds outside the display area along the extending trajectory of the packaging substrate. The packaging cover plate is disposed on a surface of the packaging adhesive away from the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Display panels are an indispensable part of electronic devices such as mobile phones. Among them, organic electroluminescent display panels (OLEDs) that use organic light-emitting diodes as light-emitting devices are widely used. In the prior art, in order to prevent the light-emitting devices from being corroded by external water and oxygen, the light-emitting devices need to be packaged. However, the packaging effect of the existing packaging method needs to be improved.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a display device, which can improve the packaging effect.

[0005] According to one aspect of the present disclosure, a display panel is provided, comprising a display area and a peripheral area outside the display area, wherein the peripheral area comprises a lead-out area, and the lead-out area comprises a binding portion; the display panel comprises:

[0006] A driving backplane, comprising a substrate and a circuit layer arranged on one side of the substrate, wherein the circuit layer comprises a packaging substrate and a power bus distributed in a direction away from the substrate, wherein the packaging substrate is arranged in the peripheral area and around the display area; the power bus is at least partially located in the lead-out area, and the part of the power bus located in the lead-out area is located between the display area and the binding portion and is connected to the binding portion; the packaging substrate at most overlaps with the part of the power bus located in the lead-out area; and the packaging substrate is a reflective structure;

[0007] A light emitting device is provided on a side of the circuit layer away from the substrate and located in the display area;

[0008] The packaging glue is at least partially disposed on a surface of the packaging base away from the substrate and surrounds the display area along an extension track of the packaging base;

[0009] The packaging cover is arranged on the surface of the packaging glue away from the substrate.

[0010] In an exemplary embodiment of the present disclosure, the package substrate includes a transfer portion at a portion of the lead-out region;

[0011] The power bus includes a first bus portion and a second bus portion, wherein the first bus portion is at least partially located on a side of the adapter portion close to the display area; the second bus portion is at least partially located on a side of the adapter portion away from the display area and is connected to the binding portion; the first bus portion and the second bus portion are both connected to the adapter portion.

[0012] In an exemplary embodiment of the present disclosure, the transition portion includes a first transition portion and a second transition portion spaced apart along a first direction;

[0013] The power bus includes a first power bus and a second power bus, wherein the first bus portion and the second bus portion of the first power bus are connected via the first adapter portion; and the first bus portion and the second bus portion of the second power bus are connected via the second adapter portion.

[0014] In an exemplary embodiment of the present disclosure, the circuit layer also includes a plurality of first signal lines, the first signal lines are at least partially located in the lead-out area and between the display area and the binding portion; the portion of the first signal line located in the lead-out area includes a first segment extending along the first direction and a second segment extending along the second direction, the second segment connecting the first segment and the binding portion.

[0015] In an exemplary embodiment of the present disclosure, the peripheral area further includes side areas distributed along the first direction on both sides of the display area and a top area distributed on a side of the display area away from the lead-out area;

[0016] The packaging substrate comprises a substrate body located in the side area and the top area, at least a portion of the first section, and at least a portion of the second section;

[0017] Each of the first signal lines includes two signal line groups that are symmetrically distributed about the central axis of the binding portion along the second direction; and the first adapter portion is located between the two signal line groups.

[0018] In an exemplary embodiment of the present disclosure, the peripheral area further includes side areas distributed along the first direction on both sides of the display area and a top area distributed along the second direction on a side of the display area away from the lead-out area;

[0019] The first section is located between the transition portion and the display area, and the second section and the transition portion are distributed along the first direction;

[0020] The packaging substrate comprises a substrate body located in the side area and the top area and at least a portion of each of the second segments;

[0021] Each of the first signal lines is divided into two signal line groups that are symmetrically distributed about the central axis of the binding portion along the second direction; and the adapter portion is located outside the two signal line groups.

[0022] In an exemplary embodiment of the present disclosure, the packaging substrate further includes a first dummy portion, which is spaced apart between the first transition portion and the second transition portion along the first direction; and the packaging glue covers the first dummy portion.

[0023] In an exemplary embodiment of the present disclosure, a second dummy portion is provided between the second sections belonging to the packaging substrate, and the packaging glue covers the second dummy portion.

[0024] In an exemplary embodiment of the present disclosure, both the first dummy portion and the second dummy portion extend along the second direction.

[0025] In an exemplary embodiment of the present disclosure, at least a portion of the second section belonging to the packaging substrate extends along a bending track.

[0026] In an exemplary embodiment of the present disclosure, at least a portion of the second section belonging to the packaging substrate includes a first bending portion and a second bending portion bent in opposite directions in the first direction, and the first bending portion and the second bending portion are alternately distributed along the second direction.

[0027] In an exemplary embodiment of the present disclosure, the circuit layer further includes a plurality of first signal lines, wherein at least a portion of the first signal lines is located in the lead-out area and between the display area and the binding portion; a portion of the first signal lines located in the lead-out area includes a first segment extending along a first direction and a second segment extending along a second direction, wherein the second segment connects the first segment and the binding portion;

[0028] The portion of the power bus located in the lead-out area includes a first bus portion extending along the first direction and a second bus portion extending along the second direction, the second bus portion connecting the first bus portion and the binding portion; the first bus portion is located between the first signal line and the display area; the second bus portion overlaps with the first section, and the packaging glue covers the second bus portion.

[0029] In an exemplary embodiment of the present disclosure, the second bus portion is provided with a plurality of first through holes, and the packaging glue fills the first through holes.

[0030] In an exemplary embodiment of the present disclosure, a width of the second bus portion in the first direction is not greater than 300 μm.

[0031] In an exemplary embodiment of the present disclosure, a second through hole is provided in a partial area of the encapsulation substrate.

[0032] In an exemplary embodiment of the present disclosure, a filling layer is filled in the second through hole, and a plurality of third through holes are provided in the filling layer; the encapsulation adhesive fills each of the third through holes.

[0033] In an exemplary embodiment of the present disclosure, the circuit layer includes a first gate layer, a first gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a first planarization layer, a second source-drain layer, and a second planarization layer that are sequentially distributed in a direction away from the substrate; the light-emitting device is disposed on a surface of the second planarization layer away from the substrate;

[0034] The encapsulation substrate is located on the first gate layer or the second gate layer, and the power bus is located on the first source-drain layer or the second source-drain layer.

[0035] According to one aspect of the present disclosure, there is provided a display device including the display panel described in any one of the above.

[0036] For the display panel and the display device of the present disclosure, the light-emitting device can be covered by an encapsulation cover plate and sealed by an encapsulation adhesive to protect the light-emitting device. At the same time, since a light-emitting encapsulation substrate is provided in the peripheral area and the encapsulation adhesive is provided on the encapsulation substrate, the light intensity of the encapsulation adhesive can be enhanced, the curing degree of the encapsulation adhesive can be improved, and the connection between the encapsulation cover plate and the driving backplane can be made more tight and firm, thereby improving the encapsulation effect. In addition, by using the encapsulation substrate to carry the encapsulation adhesive, it is beneficial to improve the flatness of the surface where the encapsulation adhesive is located, and reduce the risk of cracks occurring in the ball drop test when there are large steps with significant height differences in the area covered by the encapsulation adhesive, thereby improving the product yield.

[0037] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0039] Figure 1 It is a top view of an embodiment of the display panel of the present disclosure.

[0040] Figure 2 It is a schematic diagram of the wiring of an embodiment of the display panel of the present disclosure.

[0041] Figure 3 This is a cross-sectional schematic view of an embodiment of the display panel of the present disclosure.

[0042] Figure 4 This is a partial cross-sectional schematic view of the display area in an embodiment of the display panel of the present disclosure.

[0043] Figure 5 This is a cross-sectional schematic view of the first embodiment of the display panel of the present disclosure.

[0044] Figure 6 is Figure 5 a partial schematic view of

[0045] Figure 7 This is a cross-sectional schematic view of the second embodiment of the display panel of the present disclosure.

[0046] Figure 8 This is a cross-sectional schematic view of the third embodiment of the display panel of the present disclosure.

[0047] Figure 9 is Figure 8 a partial schematic view of

[0048] Figure 10 This is a partial top view of the encapsulation substrate in an embodiment of the display panel of the present disclosure.

[0049] Figure 11 This is a partial top view of the substrate main body in an embodiment of the display panel of the present disclosure.

[0050] Figure 12 This is a partial top view of the encapsulation substrate in another embodiment of the display panel of the present disclosure.

[0051] Figure 13 This is a partial top view of the lead-out area in an embodiment of the display panel of the present disclosure. Detailed Embodiments

[0052] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0053] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and refer to the possibility of the existence of additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0054] The first direction X and the second direction Y in this document are only two directions that are perpendicular to each other or intersect at other angles. In the drawings of the present disclosure, the first direction X may be horizontal and the second direction Y may be vertical, but it is not limited thereto. If the display panel rotates, the actual orientations of the first direction X and the second direction Y may change.

[0055] The "overlap" of feature A and feature B in this document means that the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate at least partially coincide.

[0056] An embodiment of the present disclosure provides a display panel, as Figures 1 - 3 shown, the display panel includes a display area AA and a peripheral area WA outside the display area AA. The peripheral area WA includes a lead-out area FA, and the lead-out area FA includes a bonding portion BA; the display panel includes:

[0057] The driving backplane BP includes a substrate SU and a circuit layer TL provided on one side of the substrate SU. The circuit layer TL includes a packaging substrate TB and a power bus distributed in a direction away from the substrate SU. The packaging substrate TB is provided in the peripheral area WA and at least partially surrounds the display area AA; the power bus is at least partially located in the lead-out area FA, and the part of the power bus located in the lead-out area FA is located between the display area AA and the bonding portion BA and is connected to the bonding portion BA; the packaging substrate TB at most overlaps with the part of the power bus located in the lead-out area FA; the packaging substrate TB is a reflective structure;

[0058] The light-emitting device LD is provided on the side of the circuit layer TL away from the substrate SU and is located in the display area AA;

[0059] The encapsulation glue FR is at least partially provided on the surface of the packaging substrate TB away from the substrate SU and at least partially surrounds outside the display area AA along the extension track of the packaging substrate TB;

[0060] The encapsulation cover plate CG is provided on the surface of the encapsulation glue FR away from the substrate SU.

[0061] The display panel according to the embodiments of the present disclosure can cover the light-emitting device LD through the encapsulation cover plate CG and seal it with the encapsulation adhesive FR to protect the light-emitting device LD. At the same time, since the light-emitting encapsulation substrate TB is provided in the peripheral area WA and the encapsulation adhesive FR is provided on the encapsulation substrate TB, the illumination intensity of the encapsulation adhesive FR can be enhanced, the curing degree of the encapsulation adhesive FR can be improved, and the connection between the encapsulation cover plate CG and the driving backplane BP can be made closer and firmer, thereby improving the encapsulation effect. In addition, by carrying the encapsulation adhesive FR with the encapsulation substrate TB, it is beneficial to improve the flatness of the surface where the encapsulation adhesive FR is located, and reduce the risk of cracks occurring in the ball drop test when there are large steps with significant height differences in the area covered by the encapsulation adhesive FR, thereby improving the product yield.

[0062] The display panel of the present disclosure will be described in detail below:

[0063] As Figure 1 shown, the display area AA of the display panel is an area that can emit light and is used to display images. The peripheral area WA is located outside the display area AA. The peripheral area WA can be a continuous or discontinuous annular area surrounding the display area AA, or it can also be a semi-closed area such as a "U" shape. The shape of the peripheral area WA is not specifically limited here. The peripheral area WA may include an extraction area FA, and the extraction area FA has a bonding portion BA. The bonding portion BA can be connected to a flexible circuit board, and the flexible

[0064] circuit board can be connected to a control circuit board, and the control circuit board can transmit signals to the bonding portion BA5 through the flexible circuit board.

[0065] As Figure 1 and Figure 2 shown, in some embodiments of the present disclosure, the peripheral area WA can be divided into multiple areas, including the extraction area FA surrounding the display area AA, two side areas SA and a top area TA. The two side areas SA can be distributed along the first direction X on both sides of the display area AA

[0066] and can be symmetrically arranged about the central axis of the display area AA along the second direction Y. The top area TA0 and the extraction area FA can be distributed along the second direction Y on both sides of the display area AA, that is, the top area TA is located on the side of the display area AA away from the extraction area. The extraction area FA, the two side areas SA and the top area TA can be connected to form an annular peripheral area WA surrounding the display area AA.

[0067] The above display area AA and peripheral area WA are divided according to their functions, rather than defining the boundaries of entities for implementing partitioning in the display panel.

[0068] 5 As Figures 2 - 4As shown, the driving backplane BP has a driving circuit for driving the light-emitting device LD to emit light. The driving circuit may include a pixel circuit located in the display area AA and a peripheral circuit located in the peripheral area WA, where:

[0069] The number of pixel circuits is multiple, and they are arranged in an array along the first direction X and the second direction Y into

[0070] multiple rows and columns. One pixel circuit can be connected to one light-emitting device LD. Of course, there may also be a case where one pixel circuit is connected to multiple light-emitting devices LD. In this article, only the case where the pixel circuit and the light-emitting device LD are connected in a one-to-one correspondence is taken as an example for illustration.

[0071] The pixel circuit may include multiple transistors and capacitors, and it can be a pixel circuit such as 3T1C, 7T1C, 8T1C, etc. nTmC means that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C").

[0072] The peripheral circuit can be connected to the pixel circuit and the light-emitting device LD, and can control the current passing through the light-emitting device LD through the pixel circuit, thereby controlling the brightness of the light-emitting device LD. The peripheral circuit may include multiple transistors and capacitors, and it may include a gate driving circuit and a light-emitting control circuit, etc. Of course, it may also include other circuits, and no special limitation is made on the specific structure of the peripheral circuit here.

[0073] The above-mentioned pixel circuit can adopt LTPS (low-temperature polycrystalline silicon) technology, that is, each transistor of the pixel circuit is a low-temperature polycrystalline silicon transistor. Of course, LTPO (LTPS + Oxide) can also be adopted, and no special limitation is made here.

[0074] Next, an exemplary description of each film layer of the driving backplane BP will be given:

[0075] As Figure 3 and Figure 4 shown, the driving backplane BP may include a substrate SU and a circuit layer TL, where:

[0076] The substrate SU can be the base of the driving backplane BP, which can carry the pixel circuit and the peripheral circuit. The substrate SU can be a rigid or flexible structure, and it can be a single-layer or multi-layer structure, and no special limitation is made here.

[0077] The circuit layer TL is disposed on one side of the substrate SU, and it can include each transistor and capacitor of the driving circuit.

[0078] As Figure 4As shown, in some embodiments of the present disclosure, the circuit layer TL may include a semiconductor layer POL, a first gate insulating layer GI1, a first gate layer GA1, a second gate insulating layer GI2, a second gate layer GA2, an interlayer dielectric layer ILD, a first source-drain layer SD1, a first planarization layer PLN1, a second source-drain layer SD2, and a second planarization layer PLN2, which are stacked in sequence along a direction away from the substrate SU, where:

[0079] The semiconductor layer POL may be disposed on one side of the substrate SU and includes the channels of the respective transistors, and its material may be polysilicon.

[0080] The first gate insulating layer GI1 may cover the semiconductor layer POL, and the material of the first gate insulating layer GI1 may be an insulating material such as silicon nitride or silicon oxide.

[0081] The first gate layer GA1 may be disposed on the surface of the first gate insulating layer GI1 away from the substrate SU and includes the gates of the respective transistors and the first electrode plate of the capacitor.

[0082] The second gate insulating layer GI2 may cover the first gate layer GA1, and its material may be an insulating material such as silicon nitride or silicon oxide.

[0083] The second gate layer GA2 may be disposed on the surface of the second gate insulating layer GI2 away from the substrate SU and includes the second electrode plate of the capacitor, and the second electrode plate overlaps with the first electrode plate to form a capacitor.

[0084] The interlayer dielectric layer ILD may cover the second gate layer GA2, and the material of the interlayer dielectric layer ILD may include inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride, etc., and no special limitation is made here.

[0085] The first source-drain layer SD1 may be disposed on the surface of the interlayer dielectric layer ILD away from the substrate SU, and it may be a single-layer or multi-layer structure, and its material may include one or more of metals such as Ti, Al, Mg, and Ag. For example, the first source-drain layer SD1 may include a first sub-layer, a second sub-layer, and a third sub-layer stacked in sequence along a direction away from the substrate SU. Among them, the first sub-layer and the third sub-layer may use the same metal material, for example, Ti, and the second sub-layer may use a metal material different from that of the first sub-layer and the third sub-layer, for example, Al.

[0086] The first planarization layer PLN1 may be disposed on the side of the first source-drain layer SD1 away from the substrate SU, and its material may be an insulating material such as resin. In addition, the circuit layer TL may further include a passivation layer, which may cover the first source-drain layer SD1, and the first planarization layer PLN1 may cover the passivation layer. Of course, the first planarization layer PLN1 may also directly cover the first source-drain layer SD1.

[0087] The second source-drain layer SD2 can be disposed on the surface of the first flat layer PLN1 away from the substrate SU. It can be a single-layer or multi-layer structure, and its material can include one or more of metals such as Ti, Al, Mg, Ag, etc. For example, the second source-drain layer SD2 can be the same three-layer structure as the first source-drain layer SD1.

[0088] A second flat layer PLN2 can cover the second source-drain layer SD2, and its material can be an insulating material such as resin.

[0089] As shown, the circuit layer TL can include a plurality of traces for transmitting signals, including a plurality of power lines VDL and data lines DAL. The power lines VDL can extend along the second direction Y, and at least a part of any one power line VDL is located within the display area AA. Each power line VDL can be spaced apart along the first direction X, and a column of pixel circuits can be connected to one power line VDL. The first power signal can be transmitted to the pixel circuits through the power line VDL. At least a part of any one data line DAL is located within the display area AA. A column of pixel circuits can be connected to one data line DAL, and the data signal can be transmitted to the pixel circuits through the data line DAL to control the brightness of the light-emitting device LD. For example, the power lines VDL and the data lines DAL can be located on the second source-drain layer SD2.

[0090] As Figure 2 shown, the circuit layer TL can also include a power bus located in the peripheral area WA. The power bus is at least partially located in the lead-out area FA, and the part of the power bus located in the lead-out area FA is located between the display area AA and the bonding part BA and is connected to the bonding part BA. The power bus can include a first power bus VDM and a second power bus VSM, where: The first power bus VDM is at least partially located in the lead-out area FA and is located between the display area AA and the bonding part BA. Each power line VDL is connected to the first power bus VDM, so that the first power signal can be transmitted to each power line VDL through the first power bus VDM. At the same time, in order to facilitate inputting the first power signal to the first power bus VDM, the first power bus VDM can be connected to the bonding part BA, and the first power signal can be transmitted to the first power bus VDM through the bonding part BA.

[0091] As Figure 2 shown, the second power bus VSM is at least partially located in the lead-out area FA and is located between the display area AA and the bonding part BA and is connected to the bonding part BA. The second power signal can be transmitted to the second power bus VSM through the bonding part BA.

[0092] The first power bus VDM and the second power bus VSM can be arranged on the same layer, and both can be located on the first source-drain layer SD1 or the second source-drain layer SD2.

[0093] The second power bus VSM is at least partially located in the lead-out area FA and is located between the display area AA and the bonding part BA and is connected to the bonding part BA. The second power signal can be transmitted to the second power bus VSM through the bonding part BA.

[0094] The first power bus VDM and the second power bus VSM can be arranged on the same layer, and both can be located on the first source-drain layer SD1 or the second source-drain layer SD2.

[0095] The bonding portion BA may include a plurality of pads spaced apart along the first direction X. One pad may be connected to a trace, and the trace may be the first power bus VDM, the second power bus VSM, the first signal line DL, the second signal line GL, etc. The pad may be used to bond with a flexible circuit board, 1, or the pad may also be a pin of a driving chip provided on the driving backplane BP. The structure of the bonding portion BA is not specifically limited herein.

[0096] As Figure 2 shown, in some embodiments of the present disclosure, the first power bus VDM may be entirely located in the lead-out area FA, or may extend from the lead-out area FA to the side area SA. The second power bus VSM may extend at least from the side area SA to the lead-out area FA. For example, the second power bus VSM may extend from the top area TA through the side area SA to the lead-out area FA and be connected to the bonding portion BA. The second power bus VSM may be symmetric about the central axis of the display area AA along the second direction Y. The second power bus VSM is located outside the first power bus VDM, that is, the first power bus VDM is located within the range surrounded by the second power bus VSM. The second power bus VSM may extend from two side areas SA to the lead-out area FA and be connected to the bonding portion BA. The position where the first power bus VDS is connected to the bonding portion BA is between the two positions where the second power bus VSM is connected to the bonding portion BA.

[0097] In addition, as Figure 2 shown, the circuit layer TL may further include a plurality of first signal lines DL and second signal lines GL, where:

[0098] The first signal line DL is at least partially located in the lead-out area FA. One first signal line DL may be connected to a data line DAL, and the first signal line DL may be connected to the bonding portion BA to transmit a data signal to the data line DAL through the bonding portion BA. The first signal line DL is located between the display area AA and the bonding portion BA. The portion of any first signal line DL located in the lead-out area FA may include a first segment DL1 extending along the first direction X and a second segment DL2 extending along the second direction Y. One end of the first segment DL1 may be connected to the data line DAL, and the other end may be connected to the second segment DL2. The second segment DL2 may be connected to the bonding portion BA. The first signal line DL may be located in the first gate layer GA1 or the second gate layer GA2. Therefore, the first power bus VDM and the second power bus VSM may be located on the side of the first signal line DL away from the substrate SU and may overlap with the first signal line DL.

[0099] It should be noted that the extending directions of the first section DL1 and the second section DL2 of the first signal line DL refer to the trends of their extensions, rather than being limited to being strictly parallel to the straight lines and arrow directions shown in the first direction X and the second direction Y in the figure. For example, in Figure 8 , there is a certain included angle between the first section DL1 and the straight line showing the first direction X, but the first section DL1 still extends along the first direction X from one side of the display panel to the other side. Therefore, in the embodiments of the present disclosure, Figures 5 - 8 , the extending direction of the first section DL1 can still be defined as the first direction X, and one end of the first section DL1 connected to the second section LD2 can be skewed towards the bonding portion BA. Of course, the first section DL1 can also extend parallel to the straight line showing the first direction X in the figure.

[0100] As Figure 2 shown, the second signal line GL can be connected to the peripheral circuit. For example, the second signal line GL can be connected to the gate driving circuit and the light emitting control circuit, and one gate driving circuit and the light emitting control circuit can be simultaneously connected to multiple second signal lines GL, and different second signal lines GL can transmit different signals. Each second signal line GL can at least extend from the side region SA to the lead-out region FA and be connected to the bonding portion BA. The second signal line GL can be located in the first source-drain layer SD1 or the second source-drain layer SD2, so that each second signal line GL is located on the side of each first signal line DL close to the display region AA. For example, the second signal line GL and the power supply line can both be located in the first source-drain layer SD1.

[0101] As Figure 4 shown, each light emitting device LD can be disposed on one side of the driving backplane BP. For example, the light emitting device LD can be disposed on the surface of the second flat layer PLN2 far from the substrate SU. Each light emitting device LD is located in the display region AA. At the same time, the light emitting device LD can be an OLED (organic light emitting diode). Of course, it can also be a Micro LED (micro light emitting diode) and a Mini LED (sub-millimeter light emitting diode), and can also be a light emitting device such as a QLED (quantum dot diode).

[0102] For example, the light emitting device LD can include a first electrode ANO, a light emitting layer EL, and a second electrode CAT stacked in a direction away from the driving backplane BP, where: the first electrode ANO can be disposed on one side of the driving backplane BP and be distributed in an array. For example, the first electrode ANO can be disposed on the surface of the second flat layer PLN2 far from the substrate SU. The first electrode ANO is connected to the pixel circuit. The light emitting layer EL can include a hole injection layer, a hole transport layer, a light emitting material layer, an electron transport layer, and an electron injection layer stacked in a direction away from the driving backplane BP. Each light emitting device LD can share the second electrode CAT, that is to say, the second electrode CAT can be a continuous integral layer structure.

[0103] The second electrode CAT can be connected to the second power bus VSD in the peripheral area WA, so that a second power signal can be applied to the second electrode CAT through the second power bus VSD.

[0104] In addition, as Figure 3 and Figure 4 shown, in order to define the light-emitting range of the light-emitting device LD and prevent crosstalk, a pixel definition layer PDL can be provided on the surface where the first electrode ANO is provided, and the pixel definition layer PDL is located in the display area AA. It can be provided with openings exposing each first electrode ANO, and the light-emitting layer EL is stacked with the first electrode ANO in the openings. For example, both the pixel definition layer PDL and the first electrode ANO are provided on the surface of the second flat layer PLN2 away from the substrate SU. The opening of the pixel definition layer PDL can be smaller than the first electrode ANO it exposes. Since the light-emitting layer EL is a whole-layer structure, therefore, in addition to being stacked with the first electrode ANO in the opening, the light-emitting layer EL also covers the pixel definition layer PDL.

[0105] The light-emitting material layers of different light-emitting devices LD are spaced apart from each other, so that the light-emitting device LD can directly emit monochromatic light, and the light-emitting colors of different light-emitting devices LD can be different, thus realizing color display. Of course, the light-emitting material layers of each light-emitting device LD can also be a continuous whole-layer structure, so that the light-emitting colors of each light-emitting device LD are the same, and color display can be realized in cooperation with the color filter layer CFL located on the side of the light-emitting device LD away from the driving backplane BP.

[0106] As Figure 3 and Figure 4 shown, the display panel can also include a packaging adhesive FR and a packaging cover plate CG, where:

[0107] The packaging adhesive FR can be used to bond the packaging cover plate CG and the driving backplane to encapsulate the light-emitting device LD in the display area AA, blocking the erosion of water and oxygen from the outside world to the light-emitting device LD.

[0108] The packaging adhesive FR can be in a ring structure, and it can surround outside the display area AA. That is to say, the packaging adhesive FR can extend to the top area TA, the side area SA and the lead-out area FA at the same time. At the same time, the packaging adhesive FR is located on the side of the bonding part BA close to the display area AA in the lead-out area FA.

[0109] The packaging cover plate CG can be made of a transparent hard material such as glass or acrylic, and it can be bonded to the surface of the packaging adhesive FR away from the substrate SU. The material of the packaging adhesive FR can use frit glue, which can be mixed by glass powder and solvent, etc., and is melted after laser sintering to achieve a sealed bond. In addition, an inert gas can be filled into the space surrounded by the packaging cover plate CG, the driving backplane BP and the packaging adhesive FR.

[0110] In addition, in order to support the encapsulation cover plate CG, the number of support posts PS can be multiple, and they are arrayed on the side of the light-emitting device LD away from the driving backplane BP, and at least some of the support posts PS are located in the display area AA. The support posts PS can be directly disposed on the surface of the pixel definition layer PDL away from the substrate SU. The second electrode CAT covers the support posts PS and protrudes at positions corresponding to the support posts PS. Of course, the support posts PS can also be disposed on the surface of the second electrode CAT away from the substrate SU.

[0111] The encapsulation cover plate CG can be disposed on the side of the support posts PS away from the driving backplane BP. For example, the encapsulation cover plate CG can be on the second electrode CAT lifted by the support posts PS, and can be in direct contact with the support posts PS disposed on the surface of the second electrode CAT away from the substrate SU.

[0112] As Figure 2 shown, in order to improve the encapsulation effect, the circuit layer TL can include an encapsulation substrate TB. The encapsulation substrate TB is disposed in the peripheral area WA and surrounds the display area AA. The encapsulation substrate TB overlaps at most with the part of the power bus in the lead-out area. The encapsulation glue FR can be disposed on the surface of the encapsulation substrate TB away from the substrate SU and can extend along the extension track of the encapsulation substrate TB, so that the encapsulation substrate TB can be used to support the encapsulation glue FR. At the same time, the encapsulation substrate TB is a reflective structure, so that the curing degree of the encapsulation glue FR can be improved through the reflection of the encapsulation substrate TB, making the encapsulation glue FR more firm, thereby improving the sealing effect.

[0113] As Figure 2 shown, the encapsulation substrate TB is located in the top area TA, the side area SA, and the lead-out area FA, and the encapsulation substrate TB is outside the second signal line GL. The encapsulation substrate TB can be located in the first gate layer GA1 or the second gate layer GA2. For example, the encapsulation substrate TB and the first signal line DL are located in the first gate layer GA1, and the power line is located in the first source-drain layer SD1. Therefore, the power line is on the side of the encapsulation substrate TB away from the substrate SU. At the same time, the encapsulation substrate TB can include multiple spaced parts distributed around the display area AA, rather than necessarily a continuous annular structure. At the same time, at least a part of the encapsulation substrate TB can utilize the local area of the routing such as the first signal line DL.

[0114] The encapsulation substrate TB can include a substrate main body TB1. The substrate main body TB1 is located in the side area SA and the top area TA, and is on the side of the second signal line GL away from the display area AA, that is, outside the second signal line GL. The part of the first signal line DL in the lead-out area FA can be a part of the encapsulation substrate TB. That is to say, the encapsulation substrate TB can include the substrate main body TB1 and a part of the first signal line DL.

[0115] The inventors found that if the power supply line overlaps with the encapsulation substrate TB in the lead-out area FA, and the encapsulation adhesive FR covers not only the part of the encapsulation substrate TB that does not overlap with the power supply line but also the part where the power supply line overlaps with the encapsulation substrate TB, compared with the encapsulation substrate TB that does not overlap with the power supply line, there is a height difference, that is, a step difference, between the power bus overlapping with the encapsulation substrate TB and the encapsulation substrate TB that does not overlap with the power bus, which causes the encapsulation adhesive FR to have a slope and a drop. During the ball drop test, it is easy to be unevenly stressed due to the existence of the aforementioned drop, resulting in cracks and test failure, and the yield rate needs to be improved. Therefore, the inventors proposed to reduce or eliminate the overlapping area between the power supply line and the encapsulation substrate TB, so that the encapsulation adhesive FR is located on the surface of the encapsulation substrate TB far from the substrate SU as much as possible.

[0116] The following is an exemplary description in combination with the structure and distribution mode of the encapsulation substrate TB:

[0117] As Figure 5 and Figure 6 shown, in the first embodiment of the present disclosure, the part of the power bus in the lead-out area FA may include a first bus part and a second bus part. The first bus part extends along the first direction X and is located between the first signal line DL and the second signal line GL. The second bus part may extend along the second direction Y, and the second bus part may connect the first bus part and the bonding part BA. The second bus overlaps with the first section DL1 of the first signal line DL, and the encapsulation adhesive FR may cover the second bus part.

[0118] As Figure 5 and Figure 6 shown, in one embodiment, the first bus part VDM1 of the first power bus VDM and the first bus part VSM1 of the second bus part VDM2 may be distributed along the first direction X and are located between the display area AA and the first section DL1 of each first signal line DL. The second bus part VDM2 of the first power bus VDM and the second bus part VSM2 of the second power bus VSM may extend along the second direction Y and be connected to the bonding part BA.

[0119] The second bus section VDM2 and the second bus section VSM2 overlap with the first section DL1, and these first sections DL1 are part of the package substrate TB, that is, the first power bus VDM and the second power bus VSM overlap with the package substrate TB only in the second bus section VSM2 and the second bus section VSM2, while the first bus section VDM1 and the first bus section VSM1 do not overlap with the package substrate TB. The packaging glue FR covers the package substrate TB and the second bus section VSM2 and the second bus section VSM2. By designing the structure of the power line, it is avoided that both the first power bus VDM and the second power bus VSM overlap with the package substrate TB, so that the overlapping area is reduced, the first power bus VDM and the second power bus VSM directly covered by the packaging glue FR are reduced, and the range of the step difference is reduced, which is conducive to reducing the range of crack generation and improving product yield.

[0120] Furthermore, the widths of the second bus portion VSM2 and the second bus portion VSM2 in the first direction X can be made no greater than 300 μm to avoid excessive overlap.

[0121] Further, such as Figure 5 and Figure 6 As shown, the second bus portion VSM2 and the second bus portion VSM2 may be provided with a plurality of first through holes Ho1, and the packaging glue FR may fill the first through holes Ho1, thereby increasing the contact surface between the packaging glue FR and the second bus portion VSM2 and the second bus portion VSM2, and increasing the complexity of the cross-section, which is beneficial to blocking water and oxygen, thereby improving the sealing effect.

[0122] like Figure 7 and Figure 8 As shown, in other embodiments of the present disclosure, in the lead-out area FA, the power bus and the packaging substrate TB can also be made not to overlap, so that the packaging glue FR ranges from the surface of the packaging substrate TB away from the substrate SU, and the power bus is located outside the range covered by the packaging glue FR, thereby eliminating the step difference caused by the overlap of the power bus and the packaging glue FR, and reducing the risk of cracks. Among them, the packaging substrate TB can include a transition portion CP in the lead-out area FA, and the power bus is divided into a first bus portion and a second bus portion located on both sides of the transition portion CP. The first bus portion and the second bus portion can be connected through the transition portion CP, so that the packaging substrate TB does not overlap with the power bus, thereby eliminating the step difference in the packaging glue FR.

[0123] The following is an exemplary description:

[0124] like Figure 7As shown, in the second embodiment of the present disclosure, the first segment DL1 of each first signal line DL is located between the power bus and the binding portion BA, and the first bus portion is at least partially located on the side of the adapter CP close to the display area AA; the second bus portion is at least partially located on the side of the adapter CP away from the display area AA, and is connected to the binding portion BA. The first bus portion and the second bus portion are located on the surface of the adapter CP away from the substrate SU, and the first bus portion and the second bus portion are both connected to the adapter. The packaging glue FR covers the adapter CP, and the adapter CP is part of the packaging base TB, so that the packaging glue FR does not need to cover the power line.

[0125] like Figure 7 As shown, in one embodiment, the transfer portion CP is located on a side of the first signal line DL away from the display area AA. The transfer portion CP and at least a portion of the first signal line DL are distributed along the first direction X, and the portion of the first signal line DL serves as a part of the package substrate TB. At the same time, the first bus portion of the power bus includes a side of the transfer portion CP close to the display area AA, the second bus portion is located between the transfer portion CP and the binding portion BA, and is connected to the binding portion BA, and the first bus portion and the second bus portion are connected through the transfer portion CP.

[0126] Further, the transfer portion CP may include a first transfer portion CP1 and a second transfer portion CP2 spaced apart along the first direction X. The power bus may include a first power bus VDM and a second power bus VSM. The first bus portion VDM1 and the second bus portion VDM2 of the first power bus VDM are connected through the first transfer portion CP1. The first signal line DL in the lead-out area FA includes two signal line groups DLC symmetrically distributed about the central axis of the binding portion BA along the second direction Y, the first transfer portion CP1 is located between the two signal line groups DLC, and the first bus portion VDM1 and the second bus portion VDM2 of the first power bus VDM are connected through the first transfer portion CP1.

[0127] like Figure 7 As shown, the second transfer portion CP2 and the base body TB1 located in the side area SA can be an integrated structure, that is, the second transfer portion CP2 can be the portion of the base body TB1 in the side area SA extending to the lead-out area FA, and the first bus portion VSM1 and the second bus portion VSM2 of the second power bus VSM are connected through the second transfer portion CP2.

[0128] like Figure 2 and Figure 7 As shown, in this embodiment, the package substrate TB may include a substrate body TB1 located in the side area SA and the top area TA, at least a portion of the first segment DL1 of at least a portion of the first signal line DL, and at least a portion of the second segment DL2.

[0129] like Figure 8 andFigure 9 As shown, in the third embodiment of the present disclosure, the first segment DL1 of each first signal line DL is located between the transfer portion CP and the display area AA, the transfer portion CP is located between the first segment DL1 and the binding portion BA, and the second segment DL2 of the first signal line DL and the transfer portion CP are distributed along the first direction X. Each first signal line DL is divided into two signal line groups DLC that are symmetrically distributed about the central axis of the binding portion BA along the second direction Y; the transfer portion CP is located outside the two signal line groups DLC.

[0130] The package substrate TB may include a substrate body TB1 located in the side area SA and the top area TA and at least a partial region of each second segment DL2 .

[0131] like Figure 8 and Figure 9 As shown, in one embodiment, the transfer portion CP may include a first transfer portion CP1 and a second transfer portion CP2 spaced apart along the first direction X, the second transfer portion CP2 is located between the side area SA and the first transfer portion CP1, and the first transfer portion CP1, the second transfer portion CP2 and the second segment DL2 of the first signal line DL are distributed along the first direction X. The first segment DL1 of the first signal line DL is located between the transfer portion CP and the display area AA.

[0132] The power bus may include a first power bus VDM and a second power bus VSM, wherein a first bus portion VDM1 of the first power bus VDM is connected to a second bus portion VDM2 via a first adapter portion CP1; a first bus portion VSM1 of the second power bus VSM is connected to a second bus portion VSM2 via a second adapter portion CP2. Both the second bus portion VDM2 and the second bus portion VSM2 are connected to a binding portion BA.

[0133] like Figure 8 and Figure 9 As shown, in order to improve the uniformity of the packaging substrate TB, the packaging substrate TB may also include a first dummy portion DU1, and the first dummy portion DU1 may be arranged between the first adapter portion CP1 and the second adapter portion CP2 along the first direction X, and the packaging glue FR may cover the first dummy portion DU1. The first dummy portion DU1 is floating, that is, no electrical signal is connected. The space between the first adapter portion CP1 and the second adapter portion CP2 can be filled by the first dummy portion DU1, so that the packaging glue FR is smoother, and the uniformity of the packaging glue FR is further improved, and the area of ​​the bonding surface between the packaging glue FR and the packaging substrate TB is increased, and the barrier effect against water and oxygen is improved. The number of the first dummy portion DU1 can be multiple, and they can be distributed at intervals along the first direction X, and the first dummy portion DU1 can extend along the second direction Y.

[0134] like Figure 8 and Figure 9As shown, the circuit layer TL may further include a test line CT, which is at least partially disposed in the lead-out area FA and connected to the binding portion BA. The test line CT may overlap with the second bus portion VDM2 and the second bus portion VSM2, and the test line CT may be located in the first gate layer GA1 or the second gate layer GA2.

[0135] Further, such as Figure 7 and Figure 8 As shown, at least a portion of the second segments DL2 of at least a portion of the first signal lines DL belongs to the packaging substrate TB, and a second dummy portion DU2 may be provided between two adjacent second segments DL2, and the packaging glue FR may cover each second dummy portion DU2. The second dummy portion DU2 may fill the space between two adjacent second ends DL2, making the packaging glue FR smoother, further improving the uniformity of the packaging glue FR, and increasing the area of ​​the bonding surface between the packaging glue FR and the packaging substrate TB, thereby improving the barrier effect against water and oxygen.

[0136] The number of the second dummy parts DU2 may be plural, and a second dummy part DU2 is disposed between two adjacent second segments DL2 . The second dummy parts DU2 may be distributed along the first direction X at intervals and extend along the second direction Y.

[0137] Furthermore, in some embodiments of the present disclosure, the first dummy portion DU1 is a linear structure with the same width as the second segment DL2 of the first signal line DL, one or more second dummy portions DU2 are arranged between two adjacent second segments DL2, and the spacing between two adjacent second dummy portions DU2 and one adjacent second dummy portion DU2 and the second segment DL2 is the same. At the same time, multiple first dummy portions DU1 can be arranged between the first transfer portion CP1 and the second transfer portion CP2, and the spacing between the first dummy portions DU1 here is equal to the spacing between the second dummy portions DU2 between the second segments DL2, so that the overall density of the first dummy portion DU1, the second dummy portion DU2 and the second segment DL2 in the packaging substrate TB is consistent, which is conducive to improving the uniformity within the coverage range of the packaging glue FR.

[0138] like Figure 13 As shown, in some embodiments of the present disclosure, at least a portion of the second segment DL2 belonging to the packaging substrate TB can extend along a bending track, thereby increasing the bonding surface area between the packaging glue FR and the packaging substrate TB and improving the barrier effect against water and oxygen.

[0139] Further, such as Figure 13As shown, at least a part of the second section DL2 of the encapsulation substrate TB may include a first bending part WP1 and a second bending part WP2 that are bent reversely in the first direction X, and the first bending part WP1 and the second bending part WP2 may be alternately distributed along the second direction Y. The shapes of the first bending part WP1 and the second bending part WP2 may be non-closed polygons, such as rectangles. Of course, they may also be curved shapes such as arcs.

[0140] In some embodiments of the present disclosure, as Figure 10 and Figure 11 shown, a second through hole Ho2 is provided in a partial area of the encapsulation substrate TB. At the same time, the second through hole Ho2 may be filled with a filling layer FL, and the filling layer FL is provided with a plurality of third through holes Ho3. The encapsulation adhesive FR fills each third through hole Ho3, increasing the area of the bonding surface between the encapsulation adhesive FR and the encapsulation substrate TB and improving the barrier effect against water and oxygen.

[0141] For example, the encapsulation substrate TB is located in the first gate layer GA1 or the second gate layer GA2, that is, it is arranged on the same layer as the first gate layer GA1 or the second gate layer GA2. The filling layer FL may be formed simultaneously with the interlayer dielectric layer ILD, that is, arranged on the same layer.

[0142] Furthermore, there is a certain distance between the second through hole Ho2 and the boundary of the encapsulation substrate TB, and this distance may be greater than 30 μm.

[0143] As Figure 12 shown, in some embodiments of the present disclosure, a second through hole Ho2 is provided in a partial area of the encapsulation substrate TB. The second through hole Ho2 may be filled with a plurality of filling parts FL1, and the filling parts FL1 are arranged in an array in the second through hole Ho2. The encapsulation adhesive FR fills the second through hole Ho2 and covers each filling part FL1, so that the contact surface with the encapsulation adhesive FR can be increased through the second through hole Ho2 and the filling parts FL1, and the barrier effect against water and oxygen can be improved.

[0144] The embodiments of the present disclosure also provide a display device, and the display device may include the display panel of any of the above embodiments. The display panel is the display panel of any of the above embodiments, and its specific structure and beneficial effects may refer to the embodiments of the display panel in the above text, which will not be elaborated here.

[0145] The display device of the present disclosure may be an electronic device with a display function such as a mobile phone, a smart watch, a smart bracelet, a tablet computer, a television, etc., which will not be listed one by one here.

[0146] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A display panel, characterized in that, It includes a display area and a peripheral area outside the display area. The peripheral area includes a lead-out area, and the lead-out area includes a bonding part; The display panel includes: A driving backplane, including a substrate and a circuit layer provided on one side of the substrate. The circuit layer includes a packaging substrate and a power bus distributed in a direction away from the substrate. The packaging substrate is provided in the peripheral area and at least partially surrounds the display area; At least part of the power bus is located in the lead-out area. The part of the power bus located in the lead-out area is located between the display area and the bonding part and is connected to the bonding part; The packaging substrate overlaps at most with the part of the power bus located in the lead-out area; The packaging substrate is a reflective structure; Light-emitting devices, provided on the side of the circuit layer away from the substrate and located in the display area; Packaging glue, at least partially provided on the surface of the packaging substrate away from the substrate and at least partially surrounding the outside of the display area along the extension track of the packaging substrate; A packaging cover plate, provided on the surface of the packaging glue away from the substrate.

2. The display panel according to claim 1, wherein The part of the packaging substrate in the lead-out area includes a transfer part; The power bus includes a first bus part and a second bus part. The first bus part is at least partially located on the side of the transfer part close to the display area; The second bus part is at least partially located on the side of the transfer part away from the display area and is connected to the bonding part; Both the first bus part and the second bus part are connected to the transfer part.

3. The display panel according to claim 2, wherein The transfer part includes a first transfer part and a second transfer part spaced apart in a first direction; The power bus includes a first power bus and a second power bus. The first bus part and the second bus part of the first power bus are connected through the first transfer part; The first bus part and the second bus part of the second power bus are connected through the second transfer part.

4. The display panel according to claim 3, characterized in that, The circuit layer further includes a plurality of first signal lines. The first signal lines are at least partially located in the lead-out area and are located between the display area and the bonding part; The part of the first signal line located in the lead-out area includes a first segment extending in the first direction and a second segment extending in a second direction intersecting the first direction. The second segment connects the first segment and the bonding part.

5. The display panel according to claim 4, wherein The peripheral area further includes side areas distributed on both sides of the display area in the first direction and a top area distributed on the side of the display area away from the lead-out area; The packaging substrate includes a substrate main body located in the side areas and the top area, at least part of the area of the first segment, and at least part of the area of the second segment; The second segment of each first signal line includes two signal line groups symmetrically distributed about the central axis of the bonding part in the second direction; The first transfer part is located between the two signal line groups.

6. The display panel according to claim 4, wherein The peripheral area further includes side areas distributed on both sides of the display area in the first direction and a top area distributed on the side of the display area away from the lead-out area in the second direction; The first segment is located between the transfer part and the display area, and the second segment is distributed along the first direction with the transfer part; The packaging substrate comprises a substrate body located in the side area and the top area and at least a portion of each of the second segments; The second section of each of the first signal lines is divided into two signal line groups that are symmetrically distributed about the central axis of the binding portion along the second direction; and the adapter portion is located outside the two signal line groups.

7. The display panel according to claim 6, wherein The packaging substrate further includes a first dummy portion, which is spaced apart between the first transfer portion and the second transfer portion along the first direction; and the packaging glue covers the first dummy portion.

8. The display panel according to claim 7, characterized in that, A second dummy portion is provided between the second sections belonging to the packaging substrate, and the packaging glue covers the second dummy portion.

9. The display panel according to claim 8, wherein The first dummy portion and the second dummy portion both extend along the second direction.

10. The display panel according to claim 4, wherein At least a portion of the second section belonging to the package substrate extends along a bending track.

11. The display panel according to claim 4, characterized in that, At least part of the second section belonging to the packaging substrate includes a first bending portion and a second bending portion that are bent in opposite directions in the first direction, and the first bending portion and the second bending portion are alternately distributed along the second direction.

12. The display panel according to claim 1, wherein The circuit layer further includes a plurality of first signal lines, wherein at least a portion of the first signal lines is located in the lead-out area and between the display area and the binding portion; a portion of the first signal lines located in the lead-out area includes a first segment extending along a first direction and a second segment extending along a second direction, wherein the second segment connects the first segment and the binding portion; The portion of the power bus located in the lead-out area includes a first bus portion extending along the first direction and a second bus portion extending along the second direction, the second bus portion connecting the first bus portion and the binding portion; the first bus portion is located between the first signal line and the display area; the second bus portion overlaps with the first section, and the packaging glue covers the second bus portion.

13. The display panel according to claim 12, wherein The second bus portion is provided with a plurality of first through holes, and the packaging glue fills the first through holes.

14. The display panel according to claim 12, wherein, A width of the second bus portion in the first direction is not greater than 300 μm.

15. The display panel according to any one of claims 1-14, characterized in that, A partial area of ​​the packaging substrate is provided with a second through hole.

16. The display panel according to claim 15, wherein, The second through hole is filled with a filling layer, and the filling layer is provided with a plurality of third through holes; the packaging glue fills each of the third through holes.

17. The display panel according to any one of claims 1-14, characterized in that, The circuit layer comprises a first gate layer, a first gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a first flat layer, a second source-drain layer, and a second flat layer, which are sequentially distributed in a direction away from the substrate; the light emitting device is arranged on a surface of the second flat layer away from the substrate; The packaging substrate is located at the first gate layer or the second gate layer, and the power bus is located at the first source-drain layer or the second source-drain layer.

18. A display device, characterized in that, A display panel comprising any one of claims 1-17.

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