A data reading circuit and a control method of the data reading circuit

Abstract

A data reading circuit and its control method are disclosed, relating to the field of circuit technology. This invention addresses the problems of large board space occupied by the adjustment circuit in existing memory technologies, resulting in waste, and slow reading speed. Specifically, the data reading circuit includes a sensitive amplifier, a first switch, a second switch, a current adjustment circuit, a data unit, and a reference unit. The first input terminal of the sensitive amplifier is coupled to the first terminal of the first switch and the data unit. The second input terminal of the sensitive amplifier is coupled to the first terminal of the second switch and the reference unit. The second terminal of the first switch is coupled to the second terminal of the second switch via the current adjustment circuit. The current adjustment circuit is used to adjust the current at either the first or second input terminal of the sensitive amplifier.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a data reading circuit and a control method for the data reading circuit. Background Technology

[0002] Variable resistive memory is a new type of memory where a data cell typically consists of a storage medium cell and a transistor (ITIR). For example... Figure 1 As shown, the storage medium cell can be a resistor R with variable resistance states. Different resistance states of resistor R can represent data "0" and data "1". The gate of the transistor is controlled by the word line (WL) and is responsible for selecting or not selecting this data cell. The 1T1R structure is connected to the bit line (BL) and the source line (SL).

[0003] like Figure 2 As shown, during the reading process of the new type of memory, a suitable voltage is applied to the data cell through the reading circuit, so that data cells with different resistance states will respectively flow with high current I. H and low current I L Then, the current I in the data branch is amplified by a sense amplifier (S / A). D Current I of the reference branch REF In comparison, this is amplified into a recognizable high / low level output signal. That is, the sensitivity amplifier is based on I... REF Identify D isI H or I L However, in practical applications, the resistance value of the data unit fluctuates to some extent, such as... Figure 3 As shown, I H and I L It exhibits a Gaussian distribution, resulting in a very small REF window, containing only I... REF The value is in the REF window, I REF Talent between I H with I L between.

[0004] However, the transistors in the read circuit have manufacturing defects, which cannot guarantee I... REF Located within the ideal REF window. When I REF When I is too large, a low-impedance data cell may be read as a high-impedance data cell, leading to incorrect data cell reading. REF When the impedance is too small, a high-resistivity data cell may be read as a low-resistivity data cell, leading to incorrect data cell reading. Therefore, regardless of I... REF Both excessively large and excessively small values ​​will result in a lower yield rate for the circuit.

[0005] To improve the I in new memory REF accuracy, Figure 4 This is a data readout circuit including an adjustment circuit (“Logic Process Compatible 40-nm 16-Mb, embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution”), which can adjust I... REF Adjust the size (trimming). For example Figure 4 As shown, by setting symmetrical adjustment circuits on the data branch and reference branch of each S / A, the adjustment can be based on the I in each S / A. REF The actual deviation is determined by activating different numbers of branches in the adjustment circuit, thereby altering the I value on the reference branch to varying degrees. REF Or I on the data branch D .

[0006] However, due to I REF It will only be too large or too small, therefore Figure 4 The adjustment circuit in the circuit is only used on one side, while the adjustment circuit on the other side remains idle. Therefore, the idle adjustment circuit occupies a large area of ​​the board, resulting in waste. Combined with... Figure 4 ,like Figure 5 As shown, the adjustment circuit is composed of multiple columns of transistors connected in parallel. These multiple columns of transistors are connected in parallel to node C, which will cause the parasitic capacitance of each column of transistors to be directly added to node C, thereby increasing the load on node C, resulting in a slower charging and discharging speed on BL, and affecting the reading speed of S / A. Summary of the Invention

[0007] This application provides a data reading circuit and a control method for the data reading circuit, which can reduce the board area occupied by the adjustment circuit and improve the reading speed.

[0008] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0009] A first aspect of this application provides a data readout circuit, which includes a sensitive amplifier, a first switch, a second switch, a current adjustment circuit, a data unit, and a reference unit. The first input terminal of the sensitive amplifier is coupled to the first terminal of the first switch and the data unit. The second input terminal of the sensitive amplifier is coupled to the first terminal of the second switch and the reference unit. The second terminal of the first switch is coupled to the second terminal of the second switch via the current adjustment circuit. The current adjustment circuit is used to adjust the current at either the first or second input terminal of the sensitive amplifier. Based on this solution, the data readout circuit can selectively adjust the current of the data branch or the current of the reference branch using the first and second switches. Therefore, only one current adjustment circuit is needed to adjust the current of the data branch or the reference branch. Compared to the prior art where a trimming circuit is set on each of the data branch and the reference branch, with one trimming circuit adjusting the current of the data branch and another trimming circuit adjusting the current of the reference branch, the board area occupied by the adjustment circuit is reduced. Furthermore, the solution of this application, by setting the first switch and the second switch, ensures that the parasitic capacitance of the multi-row transistors in the current regulation circuit is not added to the first node C1 (the coupling point between the first input terminal of the sensitive amplifier, the first terminal of the first switch, and the data unit) and the second node C2 (the coupling point between the second input terminal of the sensitive amplifier, the first terminal of the second switch, and the reference unit), thereby reducing the parasitic capacitance at the first node C1 and the second node C2 and improving the S / A reading speed.

[0010] In conjunction with the first aspect, in one possible implementation, the aforementioned current regulation circuit includes M first regulation branches, where M is an integer greater than or equal to 1. Each first regulation branch includes a third switch and a first transistor connected in series with the third switch. The first terminal of the first transistor is coupled to the second terminals of the first and second switches, the second terminal of the first transistor is coupled to the first terminal of the third switch, and the second terminal of the third switch is coupled to a power supply. The third terminals of the first transistors in the M first regulation branches are coupled to each other. Based on this scheme, when the first or second switch is closed, the first regulation branch is activated, reducing the current in the regulated branch. It is understood that when the first switch is closed, the regulated branch is a data branch; when the second switch is closed, the regulated branch is a reference branch. When the current in the reference branch is too high, the regulated branch remains a reference branch; when the current in the reference branch is too low, the regulated branch remains a data branch. Multiple first regulation branches in the aforementioned current regulation circuit can provide different levels of regulation.

[0011] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, each of the first regulating branches further includes a second transistor, the first terminal of which is coupled to the second terminal of the first transistor, and the second terminal of which is coupled to the first terminal of the third switch. The third terminals of the second transistors in the M first regulating branches are coupled to each other. Based on this scheme, a first regulating branch may include two transistors (a first transistor and a second transistor) connected in series to increase the equivalent resistance in each first regulating branch. Optionally, each first regulating branch may also include three or more transistors, which are connected in series with the third switch. The third terminals of the transistors located at corresponding positions in the M first regulating branches may be coupled to each other, thereby making the equivalent resistance of different first regulating branches the same.

[0012] Combining the first aspect and the aforementioned possible implementations, in another possible implementation, the current regulating circuit includes N second regulating branches, where N is an integer greater than or equal to 1. Each second regulating branch includes a fourth switch and a third transistor connected in series with the fourth switch. The first terminal of the third transistor is coupled to the second terminals of both the first and second switches, and the second terminal of the third transistor is coupled to the first terminal of the fourth switch. The second terminal of the fourth switch is grounded. The third terminals of the third transistors in the N second regulating branches are coupled to each other. Based on this scheme, when the first or second switch is closed, the second regulating branch is activated, increasing the current in the regulated branch. It is understood that when the first switch is closed, the regulated branch is a data branch; when the second switch is closed, the regulated branch is a reference branch. When the current in the reference branch is high, the regulated branch is a data branch; when the current in the reference branch is low, the regulated branch is a reference branch. Multiple second regulating branches in the aforementioned current regulating branch can provide different levels of regulation.

[0013] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, each of the aforementioned second regulating branches further includes a fourth transistor. The first terminal of the fourth transistor is coupled to the second terminal of the third transistor, and the second terminal of the fourth transistor is coupled to the first terminal of the fourth switch. The third terminals of the fourth transistors in the N second regulating branches are coupled to each other. Based on this scheme, the second regulating branch may include two transistors (the third transistor and the fourth transistor) connected in series to increase the equivalent resistance in each second regulating branch. Optionally, each second regulating branch may also include three or more transistors connected in series with the fourth switch. The third terminals of the transistors located at corresponding positions in the N second regulating branches may be coupled to each other, thereby making the equivalent resistance of different second regulating branches the same.

[0014] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the data reading circuit further includes a register file and a one-time programmable memory coupled to the register file. The register file is coupled to the first switch, the second switch, and the current regulation circuit. The register file is used to obtain control information from the one-time programmable memory and, based on this control information, control the first switch and the current regulation circuit, or control the second switch and the current regulation circuit. The control information includes the control method of the first switch and the current regulation circuit, or the control method of the second switch and the current regulation circuit. Based on this solution, when the current in the reference branch is too high or too low, the data reading circuit can control the first switch or the second switch through the register file and adjust the current magnitude of the reference branch or the data branch through the current regulation circuit, so that the current in the reference branch is within the ideal REF window, thereby improving the accuracy of data unit reading. Optionally, the control information may include closing the first switch and the switch in the current regulation circuit, or closing the second switch and the switch in the current regulation circuit.

[0015] In conjunction with the first aspect and the aforementioned possible implementations, in another possible implementation, the data reading circuit further includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is coupled to the first terminal of the first switch, the second terminal of the fifth transistor is coupled to the data unit, and the third terminal of the fifth transistor is coupled to a preset voltage. The first terminal of the sixth transistor is coupled to the first terminal of the second switch, the second terminal of the sixth transistor is coupled to the reference unit, and the third terminal of the sixth transistor is coupled to the preset voltage. Based on this solution, by coupling the fifth and sixth transistors to the preset voltage, the current magnitude of the data unit and the reference unit can be controlled, preventing malfunctions in either the reference unit or the data unit due to excessive current.

[0016] A second aspect of this application provides a control method for a data reading circuit. The data reading circuit includes a sensitive amplifier, a first switch, a second switch, a current adjustment circuit, a data unit, and a reference unit. The first input terminal of the sensitive amplifier is coupled to the first terminal of the first switch and the data unit. The second input terminal of the sensitive amplifier is coupled to the first terminal of the second switch and the reference unit. The second terminal of the first switch is coupled to the second terminal of the second switch via the current adjustment circuit. The current adjustment circuit is used to adjust the current at the first input terminal of the sensitive amplifier, or to adjust the current at the second input terminal of the sensitive amplifier. The method includes: acquiring control information; the control information includes either the control mode of the first switch and the current adjustment circuit, or the control mode of the second switch and the current adjustment circuit; and, based on the control information, controlling the first switch and the current adjustment circuit, or controlling the second switch and the current adjustment circuit. Based on this solution, by acquiring control information, the current of the data branch or the current of the reference branch can be adjusted so that the current of the reference branch is within an ideal REF window, enabling accurate reading of the data from the data unit. This solution addresses situations where the reference data current is too high or too low by controlling a first or second switch and adjusting the current in the reference or data branch via a current regulation circuit. This ensures the reference branch current remains within the ideal REF window. In other words, this solution requires only one current regulation circuit to adjust the current in either the data or reference branch, reducing the board area occupied by the adjustment circuit and improving the S / A reading speed. Furthermore, by using the first and second switches, the parasitic capacitance at the first node C1 and the second node C2 is reduced, further enhancing the S / A reading speed.

[0017] In conjunction with the second aspect, in one possible implementation, the data reading circuit further includes a register file and a one-time programmable memory coupled to the register file. The register file is coupled to the first switch, the second switch, and the current regulation circuit. The acquisition of control information includes the register file acquiring the control information from the one-time programmable memory. Based on this solution, by acquiring control information from the one-time programmable memory through the register file, the register file can adjust the current of the data branch or the current of the reference branch, ensuring that the current of the reference branch is within the ideal REF window, thus enabling accurate reading of the data from the data unit.

[0018] In conjunction with the second aspect and the aforementioned possible implementations, in another possible implementation, before the register file obtains the control information from the one-time programmable memory, the method may further include: the register file receiving first information, which indicates the start of a read cycle. Based on this scheme, when performing a read operation on a data unit, the register file can obtain control information from the one-time programmable memory to adjust the current of the data branch or the current of the reference branch, so that the current of the reference branch is within an ideal REF window, thereby ensuring accurate reading of the data unit's data.

[0019] Combining the second aspect and the above possible implementations, in another possible implementation, the current regulation circuit includes M first regulation branches, where M is an integer greater than or equal to 1. Each first regulation branch includes a third switch and a first transistor connected in series with the third switch. The first terminal of the first transistor is coupled to the second terminals of the first and second switches, the second terminal of the first transistor is coupled to the first terminal of the third switch, and the second terminal of the third switch is coupled to a power supply. The third terminals of the first transistors in the M first regulation branches are coupled to each other. Based on this scheme, when the first or second switch is closed, the first regulation branch is turned on, which can reduce the current of the regulated branch. It is understood that when the first switch is closed, the regulated branch is a data branch; when the second switch is closed, the regulated branch is a reference branch. When the current in the reference branch is too high, the regulated branch is a reference branch; when the current in the reference branch is too low, the regulated branch is a data branch. Multiple first regulation branches in the above current regulation branch can provide different levels of regulation.

[0020] In conjunction with the second aspect and the above possible implementations, in another possible implementation, each of the first regulating branches further includes a second transistor, the first terminal of which is coupled to the second terminal of the first transistor, and the second terminal of which is coupled to the first terminal of the third switch. The third terminals of the second transistors in the M first regulating branches are coupled to each other. Based on this scheme, the first regulating branch may include two transistors (the first transistor and the second transistor) connected in series to increase the equivalent resistance in each first regulating branch. Optionally, each first regulating branch may also include three or more transistors, which are connected in series with the third switch. The third terminals of the transistors located at corresponding positions in the M first regulating branches may be coupled to each other, thereby making the equivalent resistance of different first regulating branches the same.

[0021] Combining the second aspect and the aforementioned possible implementations, in another possible implementation, when the current in the aforementioned reference branch is too high, the control information includes closing the aforementioned second switch and the third switch in J1 of the aforementioned first regulating branches, where J1 is an integer greater than or equal to 1 and less than or equal to M. Based on this scheme, when the current in the reference branch is too high, closing the second switch activates multiple first regulating branches, allowing these multiple first regulating branches to be connected in parallel with the reference branch to shunt the current, thereby reducing the current in the reference branch. This ensures that the current in the reference branch is within the ideal REF window, guaranteeing the correct reading of data from the data unit.

[0022] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the method further includes: the register file receiving second information indicating the end of the read cycle; and the register file, based on the second information, turning off the second switch and the third switch in J1 of the first regulating branches. Based on this scheme, at the end of the read cycle, the second switch and multiple first regulating branches can be disconnected, so that during the next read of a data unit, the second switch and the current regulating circuit can be controlled again according to the control information to accurately read the data unit.

[0023] Combining the second aspect and the aforementioned possible implementations, in another possible implementation, when the current in the aforementioned reference branch is too low, the control information includes closing the aforementioned first switch and the third switch in P1 of the aforementioned first regulating branches, where P1 is an integer greater than or equal to 1 and less than or equal to M. Based on this scheme, when the current in the reference branch is too low, closing the first switch activates multiple first regulating branches, allowing these multiple first regulating branches to be connected in parallel with the data branch to shunt current, thereby reducing the current in the data branch. This is equivalent to increasing the current in the reference branch, ensuring that the current in the reference branch is within the range of the adjusted current I in the data branch. H 'and I L This ensures that the data in the data unit is read correctly.

[0024] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the method further includes: the register file receiving second information indicating the end of the read cycle; and the register file, based on the second information, turning off the first switch and the third switch in P1 of the first regulating branches. Based on this scheme, at the end of the read cycle, the first switch and multiple first regulating branches can be disconnected, so that during the next read of a data unit, the first switch and the current regulating circuit can be controlled again according to the control information to accurately read the data unit.

[0025] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the current regulating circuit includes N second regulating branches, where N is an integer greater than or equal to 1. Each second regulating branch includes a fourth switch and a third transistor connected in series with the fourth switch. The first terminal of the third transistor is coupled to the second terminals of both the first and second switches, and the second terminal of the third transistor is coupled to the first terminal of the fourth switch. The second terminal of the fourth switch is grounded. The third terminals of the third transistors in the N second regulating branches are coupled to each other. Based on this scheme, when the first or second switch is closed, the second regulating branch is activated, increasing the current in the regulated branch. It is understood that when the first switch is closed, the regulated branch is a data branch; when the second switch is closed, the regulated branch is a reference branch. When the current in the reference branch is too high, the regulated branch is a data branch; when the current in the reference branch is too low, the regulated branch is a reference branch. Multiple second regulating branches in the above current regulating circuit can provide different levels of regulation.

[0026] In conjunction with the second aspect and the above possible implementations, in another possible implementation, each of the above-mentioned second regulating branches further includes a fourth transistor, the first terminal of which is coupled to the second terminal of the third transistor, and the second terminal of which is coupled to the first terminal of the fourth switch. The third terminals of the fourth transistors in the N second regulating branches are coupled to each other. Based on this scheme, the second regulating branch may include two transistors (the third transistor and the fourth transistor) connected in series to increase the equivalent resistance in each second regulating branch. Optionally, each second regulating branch may also include three or more transistors, which are connected in series with the fourth switch. The third terminals of the transistors located at corresponding positions in the N second regulating branches may be coupled to each other, so that the equivalent resistance of different second regulating branches is the same.

[0027] Combining the second aspect and the aforementioned possible implementations, in another possible implementation, when the current in the aforementioned reference branch is too high, the aforementioned control information includes closing the aforementioned first switch and the fourth switch in P2 of the aforementioned second regulating branches, where P2 is an integer greater than or equal to 1 and less than or equal to N. Based on this scheme, when the current in the reference branch is too high, by closing the first switch, multiple second regulating branches are activated, making the current in the data branch the sum of the current on the data unit and the currents in the multiple second regulating branches. This increases the current in the data branch, which is equivalent to decreasing the current in the reference branch, thus increasing the current I in the reference branch. REF No longer too large.

[0028] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the method further includes: the register file receiving second information indicating the end of the read cycle; and the register file, based on the second information, turning off the first switch and the fourth switch in the P2 second regulating branches. Based on this scheme, at the end of the read cycle, the first switch and multiple second regulating branches can be disconnected, so that during the next read of a data unit, the first switch and the current regulating circuit can be controlled again according to the control information to accurately read the data unit.

[0029] Combining the second aspect and the aforementioned possible implementations, in another possible implementation, when the current in the aforementioned reference branch is too low, the control information includes closing the aforementioned second switch and the fourth switch in J2 of the aforementioned second regulating branches, where J2 is an integer greater than or equal to 1 and less than or equal to N. Based on this scheme, when the current in the reference branch is too low, by closing the second switch, multiple second regulating branches are turned on, making the current in the reference branch the sum of the current on the reference unit and the currents in the multiple second regulating branches, thus increasing the current I in the reference branch. REF This makes the current I in the reference branch... REF No longer too small.

[0030] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the method further includes: the register file receiving second information indicating the end of the read cycle; and the register file, based on the second information, turning off the second switch and the fourth switch in the J2 second adjustment branches. Based on this scheme, at the end of the read cycle, the second switch and multiple second adjustment branches can be disconnected, so that during the next read of a data unit, the second switch and the current adjustment circuit can be controlled again according to the control information to accurately read the data unit.

[0031] In conjunction with the second aspect and the above possible implementations, in another possible implementation, the data reading circuit further includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is coupled to the first terminal of the first switch, the second terminal of the fifth transistor is coupled to the data unit, and the third terminal of the fifth transistor is coupled to a preset voltage. The first terminal of the sixth transistor is coupled to the first terminal of the second switch, the second terminal of the sixth transistor is coupled to the reference unit, and the third terminal of the sixth transistor is coupled to the preset voltage. Based on this solution, by coupling the fifth and sixth transistors to the preset voltage, the current magnitude of the data unit and the reference unit can be controlled, preventing the reference unit or the data unit from malfunctioning due to excessive current.

[0032] A third aspect of this application provides a storage device, which includes a controller and a data reading circuit as described in the first aspect above.

[0033] A fourth aspect of this application provides a terminal device, the terminal device including a processor and a memory, the memory including the data reading circuit as described in the first aspect above. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of a data unit provided in an embodiment of this application;

[0035] Figure 2 This is a schematic diagram of a data reading circuit provided in an embodiment of this application;

[0036] Figure 3 A schematic diagram illustrating the relationship between the REF window and the current of the data branch, provided for an embodiment of this application;

[0037] Figure 4 This is a schematic diagram of another data reading circuit provided in an embodiment of this application;

[0038] Figure 5 This is a schematic diagram of the structure of the adjustment circuit generating parasitic capacitance in a data reading circuit provided in an embodiment of this application;

[0039] Figure 6 This is a schematic diagram of another data reading circuit provided in an embodiment of this application;

[0040] Figure 7 This is a schematic diagram of a current regulation circuit provided in an embodiment of this application;

[0041] Figure 8 This is a schematic diagram of another current regulation circuit provided in an embodiment of this application;

[0042] Figure 9 This is a schematic diagram of another data reading circuit provided in an embodiment of this application;

[0043] Figure 10 This is a schematic diagram of another data reading circuit provided in an embodiment of this application;

[0044] Figure 11 This is a schematic diagram of another data reading circuit provided in an embodiment of this application;

[0045] Figure 12 This is a schematic diagram of another data reading circuit provided in an embodiment of this application;

[0046] Figure 13This is a schematic diagram of another data reading circuit provided in an embodiment of this application;

[0047] Figure 14 A timing diagram of signals in a data reading circuit provided in an embodiment of this application;

[0048] Figure 15 A flowchart illustrating a control method for a data reading circuit provided in an embodiment of this application;

[0049] Figure 16 A schematic diagram illustrating the control effect of a data reading circuit provided in an embodiment of this application;

[0050] Figure 17 A schematic diagram illustrating the control effect of another data reading circuit provided in an embodiment of this application;

[0051] Figure 18 A flowchart illustrating another control method for a data reading circuit provided in an embodiment of this application. Detailed Implementation

[0052] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple. Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order. For example, the "first" in the first switch and the "second" in the second switch in the embodiments of this application are only used to distinguish different switches. The descriptions of "first" and "second" appearing in the embodiments of this application are only for illustration and to distinguish the described objects, and have no order, nor do they indicate a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0053] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0054] To address the issues of large board space occupied by the trimming circuit in existing memory technologies, resulting in waste and slow read speeds, this application provides a data read circuit that reduces the board space occupied by the trimming circuit and improves the read speed of the memory. It should be noted that the current regulation circuit in the following embodiments of this application is a trimming circuit.

[0055] Figure 6 A data reading circuit provided in an embodiment of this application, such as Figure 6 As shown, the data reading circuit includes a sensitive amplifier S / A, a first switch K1, a second switch K2, a current adjustment circuit, a data unit, and a reference unit. Specifically, the first input terminal a1 of the sensitive amplifier S / A is coupled to the first terminal a2 of the first switch K1 and the data unit; the second input terminal b1 of the sensitive amplifier S / A is coupled to the first terminal a3 of the second switch K2 and the reference unit; and the second terminal b2 of the first switch K1 is coupled to the second terminal b3 of the second switch K2 through the current adjustment circuit.

[0056] For example, such as Figure 6 As shown, the second terminal b2 of the first switch K1 is coupled to the first terminal ① of the current regulating circuit, and the second terminal b3 of the second switch K2 is coupled to the second terminal ② of the current regulating circuit.

[0057] The aforementioned data unit is used to store data. During the reading of the data unit, S / A is based on the current I of the reference branch. REF Determine the current I of the data branch. D It is a high current I H or low current I L The data is then amplified into a recognizable high or low level output signal. In other words, the aforementioned reference unit is used to determine the read result of the data unit.

[0058] The aforementioned current adjustment circuit is used to adjust the current at the first input terminal a1 of the sensitive amplifier S / A, or to adjust the current at the second input terminal b1 of the sensitive amplifier S / A. Combined with... Figure 6 As shown, the current at the first input terminal a1 of the sensitive amplifier S / A is the current I of the data branch. D The current at the second input terminal b1 of the sensitive amplifier S / A is the current I of the reference branch. REF.

[0059] For example, such as Figure 6 As shown, the first input terminal a1 of the sensitive amplifier S / A, the first terminal a2 of the first switch K1, and the data unit are coupled to the first node C1. The current I in the data branch... D Let I be the current in the branch from the first input terminal a1 of the sensitive amplifier S / A to the first node C1. The second input terminal b1 of the sensitive amplifier S / A is coupled to the first terminal a3 of the second switch K2 and the reference unit to the second node C2. The current I in the reference branch is... REF This refers to the current in the branch from the second input terminal b1 of the sensitive amplifier S / A to the second node C2. In other words, the current regulation circuit can adjust I by injecting or drawing current into or from the first node C1. D I can also be adjusted by injecting or extracting current into the second node C2. REF .

[0060] With the first switch K1 closed, the current I in the data branch can be adjusted via the current regulating circuit. D With the second switch K2 closed, the current I in the reference branch can be adjusted via the current regulating circuit. REF That is, the current of the data branch or the reference branch can be adjusted by using the first switch K1 and the second switch K2. Optionally, the current I in the reference branch... REF If the current is too high or too low, the current in the reference branch can be adjusted to make the current in the reference branch fall within the ideal REF window. Alternatively, the current in the reference branch can be adjusted to make the current in the reference branch fall within the ideal REF window. Whether the data branch or the reference branch is used as the adjustment branch depends on the circuit structure of the current regulation circuit.

[0061] The data reading circuit provided in this application allows for the selection and adjustment of the current in the data branch or the reference branch via a first switch and a second switch. Compared to the prior art, which uses a separate trimming circuit for the data branch and a separate trimming circuit for the reference branch, this application only requires a single current adjustment circuit to adjust either the data branch or the reference branch current, thus reducing the board area occupied by the adjustment circuit.

[0062] Understandably, the data reading circuit provided in this application, compared to... Figure 5The circuit shown isolates the current regulation circuit from the first node C1 via the first switch K1 and from the second node C2 via the second switch K2. This prevents the parasitic capacitance of the multi-row transistors in the current regulation circuit from being added to the first node C1 and the second node C2, thereby reducing the parasitic capacitance at the first node C1 and the second node C2 and improving the S / A reading speed.

[0063] In one implementation, combined with Figure 6 ,like Figure 7 As shown in (a), the current regulation circuit includes M first regulation branches, where M is an integer greater than or equal to 1. Each first regulation branch includes a third switch K3 and a first transistor Q1 connected in series with the third switch K3. The first terminal a4 of the first transistor Q1 is coupled to the second terminal b2 of the first switch K1 and the second terminal b3 of the second switch K2. The second terminal b4 of the first transistor Q1 is coupled to the first terminal a5 of the third switch K3. The second terminal b5 of the third switch K3 is connected to the power supply V. DD The coupling connection is between the third terminal c4 of the first transistor Q1 in the M first regulation branches.

[0064] Understandable. Figure 7 In (a), by coupling the third terminal c4 of the first transistor Q1 in all the first regulation branches together, the equivalent resistance of different first regulation branches can be made the same.

[0065] Optional, such as Figure 7 As shown in (b), each first regulating branch may further include a second transistor Q2, the first terminal a6 of which is coupled to the second terminal b4 of the first transistor Q1, the second terminal b6 of which is coupled to the first terminal a5 of the third switch K3, and the third terminals c6 of the second transistors Q2 in the M first regulating branches are coupled to each other.

[0066] Understandable. Figure 7 In (b), by coupling the third terminal c4 of the first transistor Q1 in all the first regulation branches to each other and coupling the third terminal c6 of the second transistor Q2 to each other, the equivalent resistance of different first regulation branches can be made the same.

[0067] Optional, Figure 7 The first regulating branch shown in (a) and Figure 7The difference between the first regulating branches shown in (b) is that the number of transistors included in the two regulating branches is different, and therefore the equivalent resistances of the two regulating branches are different. Optionally, each first regulating branch may also include three or more transistors, which are connected in series with the third switch K3. The third terminals of the transistors located at corresponding positions in the M first regulating branches can be coupled together, so that the equivalent resistances of the different first regulating branches are the same. The embodiments of this application do not limit the specific number of transistors included in the first regulating branch. Figure 7 (a) in the diagram is illustrated using only one example where the first regulation branch includes a transistor (Q1). Figure 7 (b) in the example only illustrates the first regulation branch, which includes two transistors (Q1 and Q2). In practical applications, the number of transistors in the first regulation branch can be set according to the chip requirements.

[0068] Figure 7 The current regulation circuit shown in (a) and Figure 7 The current regulation circuit shown in (b) provides a regulation method where, when the first switch K1 or the second switch K2 is closed, the current in the regulated branch is reduced by shunting the first regulating branch. The regulated branch can be a data branch or a reference branch. For example, when the first switch K1 is closed, the regulated branch is a data branch; when the second switch K2 is closed, the regulated branch is a reference branch. This can be understood in conjunction with... Figure 7 The current regulation circuit shown in the diagram is such that when the current in the reference branch is too large, the branch being regulated is the reference branch; when the current in the reference branch is too small, the branch being regulated is the data branch.

[0069] For example, combining Figure 6 and Figure 7 As shown, the current I in the reference branch REF If the current is too high, the current I in the reference branch can be adjusted by closing the second switch K2 and the third switch K3 in the first regulating branch. REF The current can be diverted to the first regulating branch, thereby reducing the current I in the reference branch. REF This makes the current I in the reference branch... REF No longer too large.

[0070] For example, combining Figure 6 and Figure 7 As shown, the current I in the reference branch REF If the current is too low, the current I in the data branch can be increased by closing the first switch K1 and the third switch K3 in the first regulating branch. D The current can be diverted to the first regulating branch, thereby reducing the current I in the data branch. D This is equivalent to increasing the current I in the reference branch. REFThis makes the current I in the reference branch... REF No longer too small.

[0071] Understandably, multiple first-level regulation branches in a current regulation circuit can provide different levels of regulation. For example, the current I in the reference branch... REF When the current is significantly higher than the reference current, more of the third switch K3 in the first regulating branch can be closed, thus increasing the current I in the reference branch. REF The current can be diverted to more of the first regulating branches, thereby increasing the current I in the reference branch after diversion. REF It can be located within the REF window. The current I in the reference branch... REF When the current is slightly too large or too small, the third switch K3 in the first regulating branch can be closed less frequently, thus reducing the current I in the reference branch. REF The current can be diverted to a smaller portion of the first regulating branch, thereby reducing the current I in the reference branch. REF It can be located within the REF window. Optionally, the range information of the current regulation branch and the information of the regulation data branch or reference branch can be written into the one-time programmable memory after the chip has been tested at the factory.

[0072] In another implementation method, combined with Figure 6 ,like Figure 8 As shown in (a), the current regulation circuit includes N second regulation branches, where N is an integer greater than or equal to 1. Each second regulation branch includes a fourth switch K4 and a third transistor Q3 connected in series with the fourth switch K4. The first terminal a7 of the third transistor Q3 is coupled to the second terminal b2 of the first switch K1 and the second terminal b3 of the second switch K2. The second terminal b7 of the third transistor Q3 is coupled to the first terminal a8 of the fourth switch K4, which is grounded. The third terminals c7 of the third transistors Q3 in the N second regulation branches are coupled to each other. Optionally, the values ​​of M and N can be the same or different.

[0073] Understandable. Figure 8 In (a), by coupling the third terminal c7 of the third transistor Q3 in all the second regulation branches together, the equivalent resistance of the different second regulation branches can be made the same.

[0074] Optional, such as Figure 8 As shown in (b), each second regulating branch may further include a fourth transistor Q4, the first terminal a9 of which is coupled to the second terminal b7 of the third transistor, the second terminal b9 of which is coupled to the first terminal a8 of the fourth switch K4, and the third terminals c9 of the fourth transistors Q4 in the N second regulating branches are coupled to each other.

[0075] Understandable. Figure 8In (b), by coupling the third terminal c7 of the third transistor Q3 in all the second regulation branches to each other and the third terminal c9 of the fourth transistor Q4 to each other, the equivalent resistance of the different second regulation branches can be made the same.

[0076] Optional, Figure 8 The second regulating branch shown in (a) and Figure 8 The difference between the two second regulating branches shown in (b) is that they contain different numbers of transistors, resulting in different equivalent resistances. Optionally, each second regulating branch may also include three or more transistors connected in series. The third terminals of the transistors located at corresponding positions in the N second regulating branches can be coupled together, thereby making the equivalent resistances of the different second regulating branches the same. The embodiments of this application do not limit the specific number of transistors included in the second regulating branch. Figure 8 (a) in the diagram only illustrates the case where the second regulation branch includes a transistor (Q3). Figure 8 (b) in the diagram only illustrates the second regulation branch, which includes two transistors (Q3 and Q4). In practical applications, the number of transistors in the second regulation branch can be set according to the chip requirements.

[0077] Figure 8 The current regulation circuit shown in (a) and Figure 8 The current regulating circuit shown in (b) provides an adjustment method that increases the current of the regulated branch when either the first switch K1 or the second switch K2 is closed. The regulated branch can be a data branch or a reference branch. For example, when the first switch K1 is closed, the regulated branch is a data branch; when the second switch K2 is closed, the regulated branch is a reference branch. It is understandable that, in conjunction with... Figure 8 The current regulation circuit shown in the diagram is such that when the current in the reference branch is too large, the branch being regulated becomes the data branch, and when the current in the reference branch is too small, the branch being regulated becomes the reference branch.

[0078] For example, combining Figure 6 and Figure 8 As shown, the current I in the reference branch REF If the current is too high, the first switch K1 and the fourth switch K4 in the second regulating branch can be closed to reduce the current I in the data branch. D The current I in the data branch is the sum of the current in the data unit and the current in the second regulating branch, thus increasing the current I in the data branch. D This is equivalent to reducing the current I in the reference branch. REF This makes the current I in the reference branch... REF No longer too large.

[0079] For example, combining Figure 6and Figure 8 As shown, the current I in the reference branch REF If the current is too low, the current I in the reference branch can be adjusted by closing the second switch K2 and the fourth switch K4 in the second regulating branch. REF The current I in the reference branch is increased because it is the sum of the current in the reference unit and the current in the second regulating branch. REF This makes the current I in the reference branch... REF No longer too small.

[0080] Understandably, multiple secondary regulation branches in a current regulation circuit can provide different levels of adjustment. For example, the current I in the reference branch... REF When the current is significantly lower than the reference current, the second switch K2 and the fourth switch K4 in the second regulating branch can be closed to reduce the current I in the reference branch. REF The sum of the current on the reference unit and the currents on a plurality of second regulating branches makes the current I of the reference branch... REF Increase it to a greater extent, thereby referencing the current I of the branch. REF It can be located within the REF window. The current I in the reference branch... REF When the current is slightly lower than the reference current, the second switch K2 and the fourth switch K4 in the second regulating branch can be closed to reduce the current I in the reference branch. REF The sum of the current on the reference unit and the current in the lesser second regulating branch is such that the current I in the reference branch is... REF Increase it to a smaller extent, thereby referencing the current I of the branch. REF It can be located within the REF window. Optionally, the range information of the current regulation branch and the information of the regulation data branch or reference branch can be written into the one-time programmable memory after the chip has been tested at the factory.

[0081] Understandably, when the current in the reference branch is too high or too low, the data reading circuit provided in this application can close the first or second switch and adjust the current in the reference branch or data branch through the current adjustment circuit, so that the current in the reference branch is within the ideal REF window. Compared with the prior art, which sets trimming circuits on the data branch and the reference branch respectively, with one trimming circuit adjusting the current in the data branch and another trimming circuit adjusting the current in the reference branch, this application only needs to set a current adjustment circuit to adjust the current in the data branch or the reference branch, thus reducing the board area occupied by the adjustment circuit.

[0082] Optionally, the data reading circuit provided in this application may include one or more data units, and the data reading circuit may also include one or more reference units. The embodiments of this application are not limited in this regard. Figure 6The example only uses a data read circuit that includes one data unit and one reference unit.

[0083] Optionally, when the data read circuitry includes multiple data units and a reference unit, each of the multiple data units is coupled to a word line WL, which is used to select a data unit.

[0084] For example, such as Figure 9 As shown, the data read circuit includes 512 data units, each coupled to a word line. The 512 data units are coupled to word lines WL0 to WL respectively. 511 Each word line is used to select a data unit for reading.

[0085] Optionally, the data read circuit may also include two data cell groups and two reference cells, with each data cell group comprising multiple data cells. The multiple data cells in each data cell group are coupled to a bit line selector (BLMUX) and a source line selector (SLMUX), and each data cell is coupled to a word line (WL). BLMUX and SLMUX are used to select a bit line and a source line, respectively, while WL is used to select a data cell.

[0086] For example, such as Figure 10 As shown, the data readout circuit includes two data unit groups, namely the first data unit group and the second data unit group, and two reference units, namely reference unit 1 and reference unit 2. The first data unit group and the second data unit group each include 512 data units, and the 512 data units are respectively coupled to bit lines WL0 to WL 511 When reading a data unit from the first data unit group, that data unit and reference unit 1 are selected, while the data unit and reference unit 2 from the second data unit group are not selected. Comparison I D with I REF Output high and low level signals. When reading a data unit in the second data unit group, that data unit and reference unit 2 are selected, while the data units in the first data unit group and reference unit 1 are not selected. Compare I D with I REF It outputs high and low level signals. Understandably, data cells or reference cells can be selected or deselected using BLMUX, SLMUX, and WL.

[0087] Optional, such as Figure 11As shown, the data reading circuit also includes a register file and a one-time programmable memory coupled to the register file. The register file is coupled to the first switch K1, the second switch K2, and the current regulation circuit. The register file is used to obtain control information from the one-time programmable memory and control the first switch K1 and the current regulation circuit, or the second switch K2 and the current regulation circuit, based on the control information. The control information includes the control mode of the first switch K1 and the current regulation circuit, or the control mode of the second switch K2 and the current regulation circuit. Optionally, after the chip has been tested at the factory, the control information can be written into the one-time programmable memory, which can be a One-Time Programmable (OTP) or an eFuse.

[0088] For example, when the current regulation circuit in the data reading circuit is Figure 7 In the circuit shown, when the current in the reference branch is too high, the control information includes closing the second switch K2 and the third switch K3 in J1 of the first regulating branches, where J1 is an integer greater than or equal to 1 and less than or equal to M. When the current in the reference branch is too low, the control information includes closing the first switch K1 and the third switch K3 in P1 of the first regulating branches, where P1 is an integer greater than or equal to 1 and less than or equal to M. J1 and P1 are the gear position information; the values ​​of J1 and P1 differ depending on the degree to which the current in the reference branch is too high or too low.

[0089] For example, when the current regulation circuit in the data reading circuit is Figure 8 In the circuit shown, when the current in the reference branch is too high, the control information includes closing the first switch K1 and the fourth switch K4 in the P2 second regulating branches, where P2 is an integer greater than or equal to 1 and less than or equal to N. When the current in the reference branch is too low, the control information includes closing the second switch K2 and the fourth switch K4 in the J2 second regulating branches, where J2 is an integer greater than or equal to 1 and less than or equal to N. J2 and P2 are the gear position information; the values ​​of J2 and P2 differ depending on the degree to which the current in the reference branch is too high or too low.

[0090] Optionally, the register file can obtain control information from the one-time programmable memory at the start of the read cycle and control the data read circuit based on the control information, so that the current of the reference branch can be within the ideal REF window.

[0091] Optionally, at the end of the read cycle, the register file can disconnect the first switch and the switch in the current regulation circuit, or disconnect the second switch and the switch in the current regulation circuit.

[0092] The data reading circuit provided in this application can control the first or second switch through the register file when the current in the reference branch is too large or too small, and adjust the current of the reference branch or data branch through the current adjustment circuit so that the current of the reference branch can be within the ideal REF window.

[0093] Optional, such as Figure 12 As shown, the data reading circuit may further include a fifth transistor Q5 and a sixth transistor Q6. The first terminal a10 of the fifth transistor Q5 is coupled to the first terminal a2 of the first switch K1, the second terminal b10 of the fifth transistor Q5 is coupled to the data unit, and the third terminal c10 of the fifth transistor Q5 is coupled to a preset voltage V. C The first terminal a11 of the sixth transistor Q6 is coupled to the first terminal a3 of the second switch K2, the second terminal b11 of the sixth transistor Q6 is coupled to the reference cell, and the third terminal c11 of the sixth transistor Q6 is coupled to the preset voltage V. C .

[0094] Optionally, the third terminal C10 of the fifth transistor Q5 can be coupled to the third terminal C11 of the sixth transistor Q6 to a preset voltage V. C .

[0095] Understandably, after the fifth and sixth transistors are coupled to the preset voltage, they can control the current of the data unit and the reference unit, thus preventing the reference unit or the data unit from malfunctioning due to excessive current.

[0096] Optionally, the first transistor Q1 to the sixth transistor Q6 can be field effect transistors (FETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs). Optionally, the first switch K1 to the fourth switch K4 can also be MOSFETs.

[0097] The data reading circuit provided in this application can close the first or second switch when the current in the reference branch is too high or too low, and adjust the current in the data branch or reference branch through the current adjustment circuit to ensure that the current in the reference branch is within the ideal REF window. That is, this application only requires one current adjustment circuit to adjust the current in the data branch or reference branch, thus reducing the board area occupied by the adjustment circuit. Furthermore, by setting the first and second switches, the parasitic capacitance at the first node C1 and the second node C2 is reduced, improving the S / A reading speed.

[0098] For example, such as Figure 13As shown, taking the S / A in the data readout circuit as an example with a cross-coupled inverter structure, combined with... Figure 14 The waveforms of the various signals shown illustrate the operation of the data reading circuit provided in this application.

[0099] Combination Figure 13 and Figure 14 As shown, when the PRE signal in the cross-coupled inverter is low, Q and QB are forced to precharge to the same potential. BLMUX, SLMUX, and WL rise from their initial low potentials to high potentials, connecting the data and reference cells to the read circuit. Due to the different resistance values ​​on the data and reference branches, after a period of time, the current I in the data branch... D and the current I of the reference branch REF This will generate a stable current signal with a certain magnitude difference; this stage can be called the precharge stage. After the PRE signal goes high, the S / A amplification stage begins, due to the current I in the data branch... D and the current I of the reference branch REF This causes the discharge speeds on the two branches to be different, which in turn generates a small voltage difference between Q and QB of the cross-coupled inverter. The S / A then amplifies this voltage difference through positive feedback, ultimately outputting a rail-to-rail high / low level signal.

[0100] like Figure 14 As shown, during the data reading process, the current regulation circuit operates in the precharge phase of the S / A circuit. The T_EN signal and either the first switch K1 or the second switch K2 are activated simultaneously with BLMUX, SLMUX, and WL, connecting the current regulation circuit to the data reading circuit, thereby enabling adjustment of the current in the data branch or the reference branch.

[0101] This application embodiment also provides a control method for a data reading circuit, which can be used to control a data reading circuit. Figures 11 to 13 In any of the data reading circuits shown, the current regulation circuit in the data reading circuit can be Figure 7 or Figure 8 The current regulation circuit shown is as follows: Figure 15 As shown, the control method includes steps S1501-S1503.

[0102] (Optional) S1501, Receive the first information from the register file.

[0103] This first piece of information is used to indicate the start of the read cycle.

[0104] For example, when the S / A starts reading a data unit, the register file receives the first information indicating the start of the read cycle.

[0105] S1502, Obtain control information from the register file.

[0106] The control information includes the control mode of the first switch K1 and the current regulation circuit, or the control mode of the second switch K2 and the current regulation circuit.

[0107] Optionally, step S1502 above may include: the register file obtaining control information from a one-time programmable memory based on the first information.

[0108] For example, the current regulation circuit in the data reading circuit is as follows: Figure 7 In the current regulation circuit shown, if the current in the reference branch is too high, the control information includes closing the second switch K2 and the third switch K3 in J1 of the first regulation branches, where J1 is an integer greater than or equal to 1 and less than or equal to M. If the current in the reference branch is too low, the control information includes closing the first switch K1 and the third switch K3 in P1 of the first regulation branches, where P1 is an integer greater than or equal to 1 and less than or equal to M.

[0109] For example, the current regulation circuit in the data reading circuit is as follows: Figure 8 In the current regulation circuit shown, if the current in the reference branch is too high, the control information includes closing the first switch K1 and the fourth switch K4 in P2 of the second regulation branches, where P2 is an integer greater than or equal to 1 and less than or equal to N. If the current in the reference branch is too low, the control information includes closing the second switch K2 and the fourth switch K4 in J2 of the second regulation branches, where J2 is an integer greater than or equal to 1 and less than or equal to N.

[0110] Optionally, the control information stored in the one-time programmable memory can be written after testing at the chip factory. In other words, whether the branch to be adjusted is a data branch or a reference branch, and the specific gear information (J1, P1, P2, and J2) in the current regulation circuit, are all obtained through chip testing.

[0111] S1503, the register file controls the first switch and current regulation circuit, or controls the second switch and current regulation circuit, based on the control information.

[0112] Optionally, at the start of the read cycle, the register file may, based on control information, close the first switch and the switch in the current regulation circuit, or close the second switch and the switch in the current regulation circuit.

[0113] For example, the current regulation circuit in the data reading circuit is as follows: Figure 7In the case of the current regulation circuit shown, if the current in the reference branch is too large, step S1503 includes: closing the second switch K2 and the third switch K3 in the J1 first regulation branches. If the current in the reference branch is too small, step S1503 includes: closing the first switch K1 and the third switch K3 in the P1 first regulation branches.

[0114] For example, the current regulation circuit in the data reading circuit is as follows: Figure 8 In the case of the current regulation circuit shown, if the current in the reference branch is too large, step S1503 includes: closing the first switch K1 and the fourth switch K4 in the P2 second regulation branches. If the current in the reference branch is too small, step S1503 includes: closing the second switch K2 and the fourth switch K4 in the J2 second regulation branches.

[0115] Reference branch current I REF Ideally, it should be located within the REF window so that the current I in the data branch is... D It can be divided into high current I H and low current I L Accurately read data cells. However, due to process variations in transistors, the current I in the reference branch cannot be guaranteed. REF Located within the ideal REF window.

[0116] For example, such as Figure 16 As shown in (a), the current I in the reference branch REF If the value is not within the REF window and is smaller than the ideal value, then some I... L Greater than I REF This can lead to incorrect reading of data units. (Taking the data reading circuit as an example...) Figure 13 Taking the circuit shown as an example, as Figure 13 As shown, the current regulation circuit in this data reading circuit is... Figure 7 The current regulating circuit is shown in (a) above. If the current I in the reference branch... REF If the value is too small, after the register obtains the control information, it closes the first switch K1 and the third switch K3 in the P1 first regulating branches. At this time, the current I in the data branch... D Because the current is reduced due to parallel shunting, it is equivalent to increasing the current I in the reference branch. REF .like Figure 16 As shown in (b), the adjusted current I of the data branch. H 'and I L '( Figure 16 (as shown by the dashed line in (b)) The current I of the data branch before adjustment H and I L ( Figure 16(as shown by the solid line in (b)) decreased, thus I REF It can be between I H 'and I L Between ', the current I of the reference branch REF Located in the new REF window'( Figure 16 Within the REF window in (b), the data unit can be read correctly.

[0117] For example, such as Figure 17 As shown in (a), the current I in the reference branch REF If the value is not within the REF window and is larger than the ideal value, then some I... H Less than I REF This can lead to incorrect reading of data units. (Taking the data reading circuit as an example...) Figure 13 Taking the circuit shown as an example, as Figure 13 As shown, the current regulation circuit in this data reading circuit is... Figure 7 The current regulating circuit is shown in (a) above. If the current I in the reference branch... REF If the value is too high, after the register obtains the control information, it closes the second switch K2 and the third switch K3 in the J1 first regulating branches. At this time, the current I in the reference branch... REF The current will decrease because it is split in parallel. For example... Figure 17 As shown in (b), the adjusted reference branch current I REF 'Current I of the reference branch before adjustment' REF The current I in the adjusted reference branch has been reduced. REF Located within the REF window, I REF 'Between I H and I L Therefore, it is able to correctly read data units.

[0118] The control method for the data reading circuit provided in this application, when performing a data unit reading operation, obtains control information from a one-time programmable memory through a register file, thereby adjusting the current of the data branch or the reference branch so that the current of the reference branch is within the ideal REF window, enabling accurate reading of the data unit's data. If the current of the reference data is too high or too low, this solution can control a first switch or a second switch through the register file, and adjust the current of the reference branch or the data branch through a current adjustment circuit, ensuring that the current of the reference branch is within the ideal REF window. In other words, this solution only requires a single current adjustment circuit to adjust the current of the data branch or the reference branch, reducing the board area occupied by the adjustment circuit and improving the S / A reading speed.

[0119] This application embodiment also provides a control method for a data reading circuit, which can be used to control a data reading circuit. Figures 11 to 13 In any of the data reading circuits shown, the current regulation circuit in the data reading circuit can be Figure 7 or Figure 8 The current regulation circuit shown is as follows: Figure 18 As shown, in addition to the steps S1501-S1503 described above, the control method may also include steps S1504-S1505.

[0120] S1504, The register file receives the second information.

[0121] The second piece of information is used to indicate the end of the reading cycle.

[0122] S1505, the register file controls the first switch and current regulation circuit, or controls the second switch and current regulation circuit, based on the second information.

[0123] Optionally, at the end of the read cycle, the register file can disconnect the first switch and the switch in the current regulation circuit, or disconnect the second switch and the switch in the current regulation circuit.

[0124] For example, the current regulation circuit in the data reading circuit is as follows: Figure 7 In the case of the current regulation circuit shown, if the current in the reference branch is too large, step S1505 includes: based on the second information, turning off the second switch K2 and the third switch K3 in the J1 first regulation branches. If the current in the reference branch is too small, step S1505 includes: based on the second information, turning off the first switch K1 and the third switch K3 in the P1 first regulation branches.

[0125] For example, the current regulation circuit in the data reading circuit is as follows: Figure 8 In the case of the current regulation circuit shown, if the current in the reference branch is too large, step S1505 includes: based on the second information, turning off the first switch K1 and the fourth switch K4 in the P2 second regulation branches. If the current in the reference branch is too small, step S1505 includes: based on the second information, turning off the second switch K2 and the fourth switch K4 in the J2 second regulation branches.

[0126] Understandably, this solution uses the current regulation circuit to shut off at the end of the reading cycle, as well as the first switch, so that when reading the data unit again, the switch in the data reading circuit can be controlled again according to the control information to accurately read the data unit.

[0127] The control method for the data reading circuit provided in this application, when performing a data unit reading operation, obtains control information from a one-time programmable memory through a register file, thereby adjusting the current of the data branch or the reference branch so that the current of the reference branch is within the ideal REF window, enabling accurate reading of the data unit's data. If the current of the reference data is too high or too low, this solution can control a first switch or a second switch through the register file, and adjust the current of the reference branch or data branch through a current adjustment circuit, ensuring the current of the reference branch is within the ideal REF window. That is, this solution only requires one current adjustment circuit to adjust the current of the data branch or the reference branch, reducing the board area occupied by the adjustment circuit and improving the S / A reading speed. Furthermore, after reading is completed, the register file turns off the current adjustment circuit and the first switch or second switch. During the next data unit reading, the switches in the data reading circuit can be controlled again according to the control information to accurately read the data unit.

[0128] This application embodiment also provides a storage device, which includes a controller and any of the aforementioned data read circuits. Optionally, the storage device may include multiple data read circuits, and the circuit structure of each data read circuit can be... Figure 6 , Figure 9 , Figure 10 , Figure 11 , Figure 12 or Figure 13 In any of the circuits shown, the current regulation circuit in the data reading circuit can be structured as follows: Figure 7 or Figure 8 The circuit shown. The circuit structure of the current regulation circuit in different data reading circuits can be the same or different.

[0129] This application embodiment also provides a terminal device, which includes a processor and a memory, the memory including any of the data reading circuits described above. Optionally, the memory may include one or more data reading circuits, and the circuit structure of each data reading circuit may be as follows: Figure 6 , Figure 9 , Figure 10 , Figure 11 , Figure 12 or Figure 13 In any of the circuits shown, the current regulation circuit in the data reading circuit can be structured as follows: Figure 7 or Figure 8 The circuit shown. The circuit structure of the current regulation circuit in different data reading circuits can be the same or different.

[0130] The steps of the methods or algorithms described in this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a core network interface device. Of course, the processor and storage medium can also exist as discrete components in the core network interface device.

[0131] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0132] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A data reading circuit, characterized in that, The data reading circuit includes a sensitive amplifier, a first switch, a second switch, a current adjustment circuit, a data unit, and a reference unit; wherein, the first input terminal of the sensitive amplifier is coupled to the first terminal of the first switch and the data unit, the second input terminal of the sensitive amplifier is coupled to the first terminal of the second switch and the reference unit, and the second terminal of the first switch is coupled to the second terminal of the second switch through the current adjustment circuit; The current adjustment circuit is used to adjust the current at the first input terminal of the sensitive amplifier, or to adjust the current at the second input terminal of the sensitive amplifier.

2. The circuit according to claim 1, characterized in that, The current regulation circuit includes M first regulation branches, where M is an integer greater than or equal to 1. Each first regulation branch includes a third switch and a first transistor connected in series with the third switch. The first terminal of the first transistor is coupled to the second terminal of the first switch and the second terminal of the second switch. The second terminal of the first transistor is coupled to the first terminal of the third switch. The second terminal of the third switch is coupled to the power supply. The third terminals of the first transistors in the M first regulating branches are coupled to each other.

3. The circuit according to claim 2, characterized in that, Each of the first regulating branches further includes a second transistor, the first terminal of which is coupled to the second terminal of the first transistor, the second terminal of which is coupled to the first terminal of the third switch, and the third terminals of the second transistors in the M first regulating branches are coupled to each other.

4. The circuit according to claim 1, characterized in that, The current regulation circuit includes N second regulation branches, where N is an integer greater than or equal to 1. Each second regulation branch includes a fourth switch and a third transistor connected in series with the fourth switch. The first terminal of the third transistor is coupled to the second terminal of the first switch and the second terminal of the second switch. The second terminal of the third transistor is coupled to the first terminal of the fourth switch. The second terminal of the fourth switch is grounded. The third terminals of the third transistors in the N second regulating branches are coupled to each other.

5. The circuit according to claim 4, characterized in that, Each of the second regulating branches further includes a fourth transistor, the first terminal of which is coupled to the second terminal of the third transistor, the second terminal of which is coupled to the first terminal of the fourth switch, and the third terminals of the fourth transistors in the N second regulating branches are coupled to each other.

6. The circuit according to any one of claims 2-5, characterized in that, The data reading circuit further includes a register file and a one-time programmable memory coupled to the register file. The register file is coupled to the first switch, the second switch, and the current regulation circuit. The register file is used to obtain control information from the one-time programmable memory and control the first switch and the current regulation circuit based on the control information, or to control the second switch and the current regulation circuit. The control information includes the control mode of the first switch and the current regulation circuit, or it includes the control mode of the second switch and the current regulation circuit.

7. The circuit according to claim 1, characterized in that, The data reading circuit further includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is coupled to the first terminal of the first switch, the second terminal of the fifth transistor is coupled to the data unit, and the third terminal of the fifth transistor is coupled to a preset voltage. The first terminal of the sixth transistor is coupled to the first terminal of the second switch, the second terminal of the sixth transistor is coupled to the reference unit, and the third terminal of the sixth transistor is coupled to the preset voltage.

8. A control method for a data reading circuit, characterized in that, The data reading circuit includes a sensitive amplifier, a first switch, a second switch, a current adjustment circuit, a data unit, and a reference unit; wherein, the first input terminal of the sensitive amplifier is coupled to the first terminal of the first switch and the data unit, the second input terminal of the sensitive amplifier is coupled to the first terminal of the second switch and the reference unit, and the second terminal of the first switch is coupled to the second terminal of the second switch through the current adjustment circuit; the current adjustment circuit is used to adjust the current at the first input terminal of the sensitive amplifier, or to adjust the current at the second input terminal of the sensitive amplifier; the method includes: Acquire control information; the control information includes the control mode of the first switch and the current regulating circuit, or, includes the control mode of the second switch and the current regulating circuit; Based on the control information, control the first switch and the current regulation circuit, or control the second switch and the current regulation circuit.

9. The method according to claim 8, characterized in that, The data reading circuit further includes a register file and a one-time programmable memory coupled to the register file. The register file is coupled to the first switch, the second switch, and the current regulation circuit. The acquisition of control information includes: The register file obtains the control information from the one-time programmable memory.

10. The method according to claim 9, characterized in that, Before the register file retrieves the control information from the one-time programmable memory, the method further includes: The register file receives first information, which is used to indicate the start of a read cycle.

11. The method according to claim 9 or 10, characterized in that, The current regulation circuit includes M first regulation branches, where M is an integer greater than or equal to 1. Each first regulation branch includes a third switch and a first transistor connected in series with the third switch. The first terminal of the first transistor is coupled to the second terminal of the first switch and the second terminal of the second switch. The second terminal of the first transistor is coupled to the first terminal of the third switch. The second terminal of the third switch is coupled to the power supply. The third terminals of the first transistors in the M first regulating branches are coupled to each other.

12. The method according to claim 11, characterized in that, Each of the first regulating branches further includes a second transistor, the first terminal of which is coupled to the second terminal of the first transistor, the second terminal of which is coupled to the first terminal of the third switch, and the third terminals of the second transistors in the M first regulating branches are coupled to each other.

13. The method according to claim 11, characterized in that, If the current in the reference branch is too high, the control information includes closing the second switch and the third switch in J1 of the first regulating branches, where J1 is an integer greater than or equal to 1 and less than or equal to M.

14. The method according to claim 13, characterized in that, The method further includes: The register file receives second information, which is used to indicate the end of the read cycle; Based on the second information, the register file shuts down the second switch and the third switch in the J1 first regulating branches.

15. The method according to claim 11, characterized in that, When the current in the reference branch is too low, the control information includes closing the first switch and the third switch in P1 of the first regulating branches, where P1 is an integer greater than or equal to 1 and less than or equal to M.

16. The method according to claim 15, characterized in that, The method further includes: The register file receives second information, which is used to indicate the end of the read cycle; Based on the second information, the register file shuts down the first switch and the third switch in the P1 first regulating branches.

17. The method according to claim 9 or 10, characterized in that, The current regulation circuit includes N second regulation branches, where N is an integer greater than or equal to 1. Each second regulation branch includes a fourth switch and a third transistor connected in series with the fourth switch. The first terminal of the third transistor is coupled to the second terminal of the first switch and the second terminal of the second switch. The second terminal of the third transistor is coupled to the first terminal of the fourth switch. The second terminal of the fourth switch is grounded. The third terminals of the third transistors in the N second regulating branches are coupled to each other.

18. The method according to claim 17, characterized in that, Each of the second regulating branches further includes a fourth transistor, the first terminal of which is coupled to the second terminal of the third transistor, the second terminal of which is coupled to the first terminal of the fourth switch, and the third terminals of the fourth transistors in the N second regulating branches are coupled to each other.

19. The method according to claim 17, characterized in that, If the current in the reference branch is too high, the control information includes closing the first switch and the fourth switch in P2 of the second regulating branches, where P2 is an integer greater than or equal to 1 and less than or equal to N.

20. The method according to claim 19, characterized in that, The method further includes: The register file receives second information, which is used to indicate the end of the read cycle; Based on the second information, the register file shuts down the first switch and the fourth switch in the P2 second regulating branches.

21. The method according to claim 17, characterized in that, When the current in the reference branch is too low, the control information includes closing the second switch and the fourth switch in J2 of the second regulating branches, where J2 is an integer greater than or equal to 1 and less than or equal to N.

22. The method according to claim 21, characterized in that, The method further includes: The register file receives second information, which is used to indicate the end of the read cycle; Based on the second information, the register file shuts down the second switch and the fourth switch in the J2 second regulating branches.

23. The method according to claim 8, characterized in that, The data reading circuit further includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is coupled to the first terminal of the first switch, the second terminal of the fifth transistor is coupled to the data unit, and the third terminal of the fifth transistor is coupled to a preset voltage. The first terminal of the sixth transistor is coupled to the first terminal of the second switch, the second terminal of the sixth transistor is coupled to the reference unit, and the third terminal of the sixth transistor is coupled to the preset voltage.

24. A storage device, characterized in that, The storage device includes a controller and a data reading circuit as described in any one of claims 1 to 7.

25. A terminal device, characterized in that, The terminal device includes a processor and a memory, the memory including a data reading circuit as described in any one of claims 1-7.

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