semiconductor devices

Abstract

The semiconductor device of the present invention comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer, which is provided on the upper surface of the first semiconductor layer and is of the first conductivity type and has an impurity concentration lower than that of the first semiconductor layer; a well region, which is provided on the upper surface side of the second semiconductor layer in the active region and is of the second conductivity type; a source region, which is provided on the upper surface side of the well region and is of the first conductivity type; a gate electrode, which is provided directly above the high-concentration region and the well region, the high-concentration region being provided on the upper surface side of the second semiconductor layer in the terminal region and is of the second conductivity type and has an impurity concentration higher than that of the well region; and a source electrode, which is electrically connected to the source region and the high-concentration region, wherein the impurity concentration of the first semiconductor layer is greater than or equal to 4×10 18 cm ‑3 , thickness is greater than or equal to 4μm.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Patent Document 1 discloses a semiconductor device having a hexagonal semiconductor substrate containing silicon carbide, i.e., an n-type substrate. A semiconductor layer including an n-type drift layer is formed on the substrate. A p-type first semiconductor region is formed on the upper surface of the semiconductor layer in a termination region surrounding the element region. A silicide layer is formed on the upper surface of the first semiconductor region. A contact plug is connected to the first semiconductor region via the silicide layer. When viewed from above, the first semiconductor region has a ring-shaped structure connecting a first extension portion extending in a first direction, a second extension portion extending in a second direction, a third extension portion extending in a third direction, and a fourth extension portion extending in a fourth direction.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-112171 Summary of the Invention

[0004] Patent Document 1 improves the distribution of the pn current flowing through the terminal region to suppress the expansion of stacking faults. However, the hole density in the active region is not considered, and there is a possibility that the degradation of electrical characteristics cannot be fully suppressed.

[0005] An object of the present invention is to obtain a semiconductor device capable of suppressing degradation of electrical characteristics.

[0006] The semiconductor device of the present invention comprises: a semiconductor layer having an active region in which a MOSFET is formed and an end region surrounding the active region when viewed from above; a gate electrode provided on the upper surface of the semiconductor layer; a source electrode provided on the upper surface of the semiconductor layer; and a drain electrode provided on the surface of the semiconductor layer opposite to the upper surface, wherein the semiconductor layer comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer provided on the upper surface of the first semiconductor layer, having the first conductivity type and an impurity concentration lower than that of the first semiconductor layer. The first semiconductor layer is low; the well region is arranged on the upper surface side of the second semiconductor layer in the active region and is of the second conductivity type; the source region is arranged on the upper surface side of the well region and is of the first conductivity type; and the high concentration region is arranged on the upper surface side of the second semiconductor layer in the terminal region and is of the second conductivity type, with an impurity concentration higher than that of the well region. The gate electrode is arranged directly above the well region. The source electrode is electrically connected to the source region and the high concentration region. The impurity concentration of the first semiconductor layer is greater than or equal to 4×10 18 cm -3 , thickness is greater than or equal to 4μm.

[0007] Effects of the Invention

[0008] In the semiconductor device according to the present invention, the provision of the first semiconductor layer can suppress the hole density in the active region and thus suppress a decrease in the electrical characteristics of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0010] Figure 2 yes Figure 1 AA cross-sectional view.

[0011] Figure 3 yes Figure 1 BB cross-sectional view.

[0012] Figure 4 This is a diagram explaining the relationship between the first semiconductor layer and the hole density.

[0013] Figure 5 It is a top view of the semiconductor device according to the second embodiment.

[0014] Figure 6 yes Figure 5 CC cross-sectional view. DETAILED DESCRIPTION

[0015] The semiconductor device according to each embodiment will be described with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and redundant description may be omitted.

[0016] Implementation Method 1

[0017] Figure 1 This is a top view of the semiconductor device 100 according to the first embodiment. In the following, n-type is the first conductivity type and p-type is the second conductivity type. However, it is not limited thereto, and n-type may be the second conductivity type and p-type may be the first conductivity type. In addition, the active region refers to the region where the main current of the semiconductor device flows. In addition, the terminal region refers to the region provided around the active region. In addition, Figure 1 In order to illustrate the structure of the semiconductor device 100, parts of electrodes and insulating films are omitted.

[0018] Semiconductor device 100 has a rectangular shape when viewed from above. It constitutes a semiconductor chip. An active region 101 is provided in the center of semiconductor device 100, and a SiC-MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is formed in active region 101. Termination regions 102 are provided on the periphery of semiconductor device 100. Gate wiring 25 is provided in termination regions 102 to surround active region 101. P-type high-concentration regions 20 are provided outside gate wiring 25 to surround active region 101.

[0019] For convenience, a unit cell UC is shown in region 80. In an actual device structure, a plurality of unit cells UC are provided in active region 101. The source regions of the plurality of unit cells UC are electrically connected in parallel.

[0020] Figure 2 yes Figure 1 AA cross-sectional view. Figure 3 yes Figure 1 BB cross-sectional view. Semiconductor device 100 includes a semiconductor layer 11; multiple gate electrodes 24 provided on the upper surface of semiconductor layer 11; a source electrode 28 provided on the upper surface of semiconductor layer 11; and a drain electrode 30 provided on the surface of semiconductor layer 11 opposite the upper surface. Semiconductor layer 11 includes an active region 101 in which a MOSFET is formed and an end region 102 surrounding active region 101 when viewed from above. Semiconductor layer 11 is formed of silicon carbide.

[0021] The semiconductor layer 11 includes a substrate 10 formed of SiC containing n-type impurities. A first semiconductor layer 12 is provided on the upper surface of the substrate 10. The first semiconductor layer 12 is an epitaxial growth layer containing n+-type impurities. The concentration of the first semiconductor layer 12 is higher than that of the substrate 10. The impurity concentration of the first semiconductor layer 12 is, for example, greater than or equal to 4×10 18 cm -3 , with a thickness of 4 μm or greater. The first semiconductor layer 12 functions as a buffer layer. A second semiconductor layer 14 having a lower impurity concentration than the first semiconductor layer 12 is provided on the upper surface of the first semiconductor layer 12. The second semiconductor layer 14 is an epitaxial growth layer containing n-type impurities.

[0022] In the active region 101, a p-type well region 16 is provided on the upper surface side of the second semiconductor layer 14. The impurity concentration of the well region 16 is, for example, 1×10 18 cm -3A plurality of well regions 16 are selectively provided on the outermost surface of the second semiconductor layer 14. An n-type source region 18 is provided on the upper surface side of the well region 16. In addition, a p-type high concentration region 20 is provided between adjacent source regions 18 on the upper surface side of the well region 16. The high concentration region 20 is also called a well contact region. The impurity concentration of the high concentration region 20 is, for example, 1×10 20 cm -3 .

[0023] In the termination region 102, a well region 16 is also provided on the upper surface side of the second semiconductor layer 14. In the termination region 102, a high-concentration region 20 is provided on the upper surface side of the well region 16. The high-concentration region 20 in the active region 101 and the high-concentration region 20 in the termination region 102 are formed in the same layer. The high-concentration region 20 is formed simultaneously in the active region 101 and the termination region 102.

[0024] In the terminal region 102, a withstand voltage maintaining region 32 is provided on the upper surface side of the second semiconductor layer 14. The impurity concentration of the withstand voltage maintaining region 32 is, for example, 1×10 18 cm -3 The impurity concentration of high concentration region 20 is higher than that of withstand voltage maintaining region 32. Withstand voltage maintaining region 32 is provided on the periphery of well region 16 in terminal region 102. The arrangement and impurity concentration of withstand voltage maintaining region 32 are changed according to the required withstand voltage level.

[0025] In the active region 101, a gate insulating film 22 is provided on the upper surface of the second semiconductor layer 14. In the active region 101, the gate insulating film 22 is provided from the upper surface of the portion of the second semiconductor layer 14 sandwiched by the well region 16, through the upper surface of the well region 16, and to the upper surface of the end edge of the source region 18. A gate electrode 24 is provided on the gate insulating film 22. The gate electrode 24 is provided directly above the portion of the second semiconductor layer 14 sandwiched by the well region 16, the well region 16, and the source region 18. The gate insulating film 22 and the gate electrode 24 are covered by an interlayer insulating film 26. The interlayer insulating film 26 is covered by a source electrode 28. In the active region 101, the source electrode 28 is in contact with and electrically connected to the portion of the source region 18 not covered by the interlayer insulating film 26 and the high-concentration region 20.

[0026] In the termination region 102, the gate electrode 24 is provided directly above the high-concentration region 20 via an insulating film. Figure 3In the example shown in FIG. 1 , one gate electrode 24 among the plurality of gate electrodes 24 is provided in a portion of the second semiconductor layer 14 sandwiched between the well region 16 and the withstand voltage maintaining region 32, directly above the well region 16 and the high-concentration region 20. Furthermore, the source electrode 28 extends to the terminal region 102. In the terminal region 102, the source electrode 28 contacts and is electrically connected to a portion of the high-concentration region 20 that is not covered by the interlayer insulating film 26. The source electrode 28 passes between adjacent gate electrodes 24 provided above the terminal region 102 and is electrically connected to the high-concentration region 20.

[0027] When the main current flows through the semiconductor device 100, the current flows from the drain electrode 30 toward the source electrode 28. In this case, the semiconductor device 100 operates as a MOSFET. When the reverse current flows, the current flows from the source electrode 28 toward the drain electrode 30. In this case, the semiconductor device 100 operates as a PN diode. The parasitic PN diode within the semiconductor device 100 is also called a body diode.

[0028] During PN diode operation, the electrical characteristics of a semiconductor device may degrade as the current is applied for an extended period. This can occur due to the formation of BPDs (Basal Plane Dislocations) in the epitaxial layer of the SiC substrate. Generally, when hole current flows through a region where BPDs are formed, the BPDs grow and cause stacking faults. This can lead to an increase in the on-state resistance and a decrease in the device's withstand voltage.

[0029] In order to prevent this phenomenon, it is conceivable to reduce the BPD itself or to prevent the flow of current with a hole density exceeding a certain level that causes the growth of BPD.

[0030] In contrast, in this embodiment, a p-type high-concentration region 20 is provided in the terminal region 102. This allows a region with a high hole density, which can cause the expansion of crystal defects, to be formed in the terminal region 102, making it possible to facilitate the flow of hole current through the terminal region 102. Consequently, the expansion of crystal defects into the active region 101 can be suppressed, thereby preventing a decrease in the electrical characteristics of the semiconductor device 100.

[0031] Furthermore, in the termination region 102, the high-concentration region 20 is in contact with the source electrode 28. This allows a PN diode to be formed in the termination region 102, unlike in the active region 101, and allows the current path from the source electrode 28 to be concentrated in the termination region 102. Consequently, the region in which the hole current flows can be further limited.

[0032] Figure 4 This is a diagram illustrating the relationship between the first semiconductor layer 12 and the hole density. Figure 4Figure 2 shows simulation results of the hole density near the boundary between the active region 101 and the termination region 102 when a reverse current flows through the semiconductor device 100. The position where X = 0 corresponds to the interface between the active region 101 and the termination region 102. The region where X is positive corresponds to the termination region 102, and the region where X is negative corresponds to the active region 101. The hole density represents the hole density near the interface between the substrate 10 and the first semiconductor layer 12.

[0033] Figure 4 The solid line in the figure shows that the impurity concentration of the first semiconductor layer 12 is 4×10 18 cm -3 , the results when the thickness is 4μm. Figure 4 The dotted line in the figure shows that the impurity concentration of the first semiconductor layer 12 is 1×10 18 cm -3 , the results when the thickness is 1μm.

[0034] like Figure 4 As shown, the impurity concentration of the first semiconductor layer 12 is 4×10 18 cm -3 When the thickness is 4 μm, the impurity concentration is 1×10 18 cm -3 Furthermore, compared to a 1 μm thickness, the hole density within the active region 101 can be reduced. The higher the impurity concentration of the first semiconductor layer 12 or the thicker the first semiconductor layer 12, the greater the effect of reducing the hole density. The first semiconductor layer 12 has the function of blocking the hole current that flows in the active region 101 during PN diode operation. Therefore, the first semiconductor layer 12 can reduce the hole density in the active region 101.

[0035] The impurity concentration of the first semiconductor layer 12 is 4×10 18 cm -3 When the thickness is 4 μm, the hole density in the terminal region 102 is approximately 1.5 times greater than that in the active region 101. This can significantly suppress the propagation of crystal defects into the active region 101 and reduce the degradation of the electrical characteristics of the semiconductor device 100.

[0036] Furthermore, in this embodiment, a gate electrode 24 is also provided in the termination region 102. Providing the gate electrode 24 directly above the high-concentration region 20 and the well region 16 in the termination region 102 stabilizes the potential in the termination region 102. In particular, the potential around the well region 16 can be stabilized. This stabilizes the characteristics of the PN diode in the termination region 102 and allows for stable control of the hole density. Consequently, degradation of the electrical characteristics of the semiconductor device 100 can be suppressed.

[0037] The structure of semiconductor device 100 is not limited to the above. Any semiconductor device 100 may be a MOSFET having a parasitic diode. The concentrations of each layer are merely examples. Furthermore, as long as the PN diode characteristics of the termination region 102 are not affected, the gate electrode 24 may not be provided in the termination region 102.

[0038] These modifications can be appropriately applied to the semiconductor devices according to the following embodiments. Note that since the semiconductor devices according to the following embodiments have many similarities with the first embodiment, the description will focus on the differences from the first embodiment.

[0039] Implementation Method 2

[0040] Figure 5 This is a top view of a semiconductor device 200 according to Embodiment 2. Semiconductor device 200 differs from semiconductor device 100 in the formation location of high-concentration region 20. The remaining structure is the same as semiconductor device 100. High-concentration region 20 in terminal region 102 of semiconductor device 200 is formed only on the sides along the <1-100> direction, of the four sides of terminal region 102 surrounding active region 101 when viewed from above.

[0041] Figure 6 yes Figure 5 No p+ type impurity implantation region, ie, high concentration region 20 is formed on the side of the terminal region 102 along the <11-20> direction.

[0042] Such a high-concentration region 20 can be formed using photolithography technology. The high-concentration region 20 can be formed by ion implanting p-type impurities into the semiconductor layer 11 using a resist mask that is closed above the side along the <11-20> direction and open above the side along the <1-100> direction.

[0043] The growth direction of the defect is Figure 5 The <1-100> direction shown in FIG. Therefore, if high-concentration regions 20 are formed on two sides of the terminal region 102 parallel to the <11-20> direction, defects may propagate toward the active region 101 starting from the BPD generated in the terminal region 102. In this embodiment, high-concentration regions 20 are not formed on the two sides parallel to the <11-20> direction. Therefore, the region that serves as the starting point for the propagation of crystal defects can be limited. Consequently, the propagation of crystal defects toward the center of the active region 101 can be suppressed, further reducing the degradation of the electrical characteristics of the semiconductor device 200.

[0044] The technical features described in each embodiment may be used in combination as appropriate.

[0045] Description of the label

[0046] 10 substrate, 11 semiconductor layer, 12 first semiconductor layer, 14 second semiconductor layer, 16 well region, 18 source region, 20 high-concentration region, 22 gate insulating film, 24 gate electrode, 25 gate wiring, 26 interlayer insulating film, 28 source electrode, 30 drain electrode, 32 withstand voltage holding region, 100 semiconductor device, 101 active region, 102 terminal region, 200 semiconductor device, UC unit cell.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor layer having an active region in which a MOSFET is formed and an end region surrounding the active region when viewed from above; a gate electrode disposed on the upper surface of the semiconductor layer; a source electrode, disposed on the upper surface of the semiconductor layer; as well as a drain electrode provided on a surface of the semiconductor layer opposite to the upper surface; The semiconductor layer has: a substrate of a first conductivity type; a first semiconductor layer disposed on the upper surface of the substrate, exhibiting the first conductivity type and having an impurity concentration higher than that of the substrate; a second semiconductor layer disposed on an upper surface of the first semiconductor layer, exhibiting the first conductivity type and having an impurity concentration lower than that of the first semiconductor layer; a well region provided on the upper surface side of the second semiconductor layer in the active region and having a second conductivity type; a source region disposed on the upper surface side of the well region and having the first conductivity type; and a high-concentration region provided on the upper surface side of the second semiconductor layer in the terminal region, exhibiting the second conductivity type and having an impurity concentration higher than that of the well region; The gate electrode is arranged directly above the well region, The source electrode is electrically connected to the source region and the high-concentration region, The impurity concentration of the first semiconductor layer is greater than or equal to 4×10 18 cm -3 , thickness is greater than or equal to 4μm.

2. The semiconductor device according to claim 1, wherein having a plurality of gate electrodes, The source electrode is electrically connected to the high-concentration region by passing between gate electrodes that are adjacent to each other and are provided on the termination region among the plurality of gate electrodes.

3. The semiconductor device according to claim 1, wherein A withstand voltage maintaining region is provided in the terminal region on the upper surface side of the second semiconductor layer, The high-concentration region has a higher impurity concentration than the withstand voltage maintaining region.

4. The semiconductor device according to claim 2, wherein A withstand voltage maintaining region is provided in the terminal region on the upper surface side of the second semiconductor layer, The high-concentration region has a higher impurity concentration than the withstand voltage maintaining region.

5. The semiconductor device according to any one of claims 1 to 4, wherein The semiconductor layer is formed of silicon carbide.

6. The semiconductor device according to any one of claims 1 to 4, wherein: The high-concentration region is formed only on the side along the <1-100> direction among the four sides of the terminal region surrounding the active region in a plan view.

7. The semiconductor device according to claim 5, wherein The high-concentration region is formed only on the side along the <1-100> direction among the four sides of the terminal region surrounding the active region in a plan view.

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