Chip failure site localization method and apparatus

Abstract

Embodiments of the present disclosure provide a chip failure point positioning method and device, comprising: obtaining image information of a failed chip, wherein the failed chip comprises a transistor and a resistor, the transistor and the resistor are connected in series, a first end of the resistor is electrically connected with a first test point, a second end of the resistor is electrically connected with a first end of the transistor, a second end of the transistor is electrically connected with a second test point, and the first test point and the second test point are determined based on the image information; processing the failed chip based on the image information to form a metal contact point, wherein the metal contact point is located between the transistor and the resistor; forming a conductive structure between the first test point and the metal contact point to short the resistor; and powering on between the first test point and the second test point to perform failure point positioning, thereby ensuring the accuracy of transistor failure point positioning.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of semiconductor technology, and more specifically, to a method and apparatus for locating chip failure points. Background Technology

[0002] Integrated circuit chips are playing an increasingly important role in people's production and daily lives. However, chip failures are inevitable during research, development, production, and use. As people's requirements for product quality and reliability continue to increase, failure analysis is becoming increasingly important. Through chip failure analysis, integrated circuit designers can find design defects, process parameter mismatches, or improper design and operation. This provides necessary feedback information for design engineers to continuously improve or repair chip designs, making them more in line with design specifications. Furthermore, failure analysis can evaluate the effectiveness of different test vectors, providing necessary supplements to production testing and providing the necessary information foundation for optimizing verification testing processes.

[0003] For chip failure analysis, accurate failure point location is a crucial step and the key to the success of the analysis. Currently, the most widely used location method is the obirch method, which uses laser heating to cause a change in the chip's resistance, thereby pinpointing the failure location.

[0004] However, in the existing technology, for chip structures with series resistors, when a chip fails, the series resistors affect the accuracy of locating the chip failure point during the location process based on the Obirch location method. Summary of the Invention

[0005] The embodiments described herein provide a method and apparatus for locating chip failure points.

[0006] Firstly, based on the content of this disclosure, a method for locating chip failure points is provided, including:

[0007] Image information of a failed chip is acquired, wherein the failed chip includes a transistor and a resistor, the transistor and the resistor are connected in series, a first end of the resistor is electrically connected to a first test point, a second end of the resistor is electrically connected to a first end of the transistor, and a second end of the transistor is electrically connected to a second test point, the first test point and the second test point are determined based on the image information;

[0008] Based on the image information, the failed chip is processed to form metal contact points, wherein the metal contact points are located between the transistor and the resistor;

[0009] A conductive structure is formed between the first test point and the metal contact point to short-circuit the resistor;

[0010] Power is applied between the first test point and the second test point to locate the failure point.

[0011] In some embodiments of this disclosure, the failed chip includes at least a substrate layer, a first metal layer, and a first insulating layer, and the resistor is electrically connected to the transistor through the first metal layer;

[0012] The process of forming metal contact points by processing the failed chip based on the image information includes:

[0013] Based on the image information, the probe contact position is determined;

[0014] The first insulating layer is processed to remove the first insulating layer of the first metal layer at the probe contact position, forming a metal contact point.

[0015] In some embodiments of this disclosure, the process of treating the first insulating layer to remove the first insulating layer of the first metal layer at the probe contact location to form a metal contact point includes:

[0016] The first insulating layer is bombarded with an ion beam, and the first insulating layer of the first metal layer at the probe contact position is removed by the ion beam to form a metal contact point.

[0017] In some embodiments of this disclosure, forming a conductive structure between the first test point and the metal contact point to short-circuit the resistor includes:

[0018] A second metal layer is formed on the side of the first insulating layer away from the substrate layer, so that the first test point and the metal contact point are electrically connected through the second metal layer.

[0019] In some embodiments of this disclosure, after forming a second metal layer on the side of the first insulating layer opposite to the substrate layer to electrically connect the first test point and the metal contact point through the second metal layer, the method further includes:

[0020] A second insulating layer is formed on the side of the second metal layer opposite to the substrate layer.

[0021] In some embodiments of this disclosure, the material of the conductive structure includes foil.

[0022] In some embodiments of this disclosure, the step of powering on between the first test point and the second test point to locate the failure point includes:

[0023] Power is applied between the first test point and the second test point, and the transistor is scanned with an electron beam based on the power-on voltage to locate the failure point of the transistor.

[0024] In some embodiments of this disclosure, performing electron beam scanning on the transistor based on the power-on voltage to locate the failure point of the transistor includes:

[0025] The transistor is scanned using the electronic signal of the FIB to obtain an electronic image of the transistor;

[0026] The location of the transistor's failure point is determined by the brightness of the electronic image of the transistor. In some embodiments of this disclosure, the voltage of the electronic signal of the FIB is 0.5–2 kV.

[0027] Secondly, according to the present disclosure, a chip failure point location device is provided, comprising: locating chip failure points based on the method described in any one of the first aspects.

[0028] The chip failure point location method and apparatus provided in this application, when the acquired failed chip is a transistor-resistor series chip, processes the acquired image information of the failed chip to form metal contact points. Then, a conductive material is used to connect the first test point and the metal contact points, short-circuiting the resistor connected in series with the transistor, thereby locating the failure point of the transistor. Since the metal contact points formed by processing the failed chip are located between the transistor and the resistor, when the conductive material is used to connect the metal contact points and the first test point, the resistor connected in series with the transistor is short-circuited. Therefore, during the power-on process between the first and second test points, the voltage applied only includes the transistor, ensuring the accuracy of the transistor failure point location. Furthermore, since the metal contact points are located between the transistor and the resistor, damage to the transistor caused by directly forming metal contact points on the transistor and directly contacting the transistor with a probe is avoided.

[0029] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0031] Figure 1This is a schematic flowchart of a chip failure point location method provided in an embodiment of this disclosure;

[0032] Figure 2 This is a schematic diagram of the circuit structure of a chip provided in an embodiment of this disclosure;

[0033] Figure 3 This is a schematic diagram of the circuit structure of another chip provided in an embodiment of this disclosure;

[0034] Figure 4 This is a partial structural schematic diagram of a faulty chip locating device provided in an embodiment of this disclosure.

[0035] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0037] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0038] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0039] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0040] Furthermore, in all embodiments of this disclosure, the source and drain (emitter and collector) of the transistor are symmetrical, the conduction current directions between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor are opposite, and the gate of the transistor is the control terminal; therefore, the remaining two ends of the transistor are referred to as the first terminal and the second terminal, respectively. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0041] In the description of this application, unless otherwise stated, "multiple" means two or more (including two), and similarly, "multiple groups" means two or more (including two groups).

[0042] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0043] In the prior art, the Obirch method for locating chip failure points is only relatively accurate for circuits that only contain transistors. When transistors and resistors are connected in series in a circuit, such as a P-type transistor and a resistor in series, the accuracy of the location results will be affected if the Obirch method is used to locate the failure point between the resistor and the transistor. Based on the problems existing in the prior art, this disclosure provides a chip failure point location method.

[0044] Figure 1 This is a flowchart illustrating a chip failure point location method provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the specific process of the chip failure point location method includes:

[0045] S110, Obtain image information of the failed chip.

[0046] The failed chip includes a transistor G and a resistor R. The transistor G is connected in series with the resistor R. The first end of the resistor R is electrically connected to the first test point A. The second end of the resistor R is electrically connected to the first end of the transistor G. The second end of the transistor G is electrically connected to the second test point B. The first test point A and the second test point B are determined based on image information.

[0047] The first test point A and the second test point B are the test points selected during the chip testing process after the chip is fabricated. Specifically, the failed chip can be scanned based on the electronic signal of FIB (Focused Ion Beam) to obtain the electronic image of the failed chip. The first test point and the second test point corresponding to the failed chip can be determined by obtaining the electronic image of the failed chip.

[0048] like Figure 2 As shown, the failed chip includes a resistor R and a transistor G connected in series. The first test point A is located at the first end of the resistor, and the second test point B is located at the second end of the transistor G. When locating the chip failure point based on the Obirch method, the existing method uses a FIB (Focused Ion Beam) to generate an ion source (most FIBs use Ga, but some devices have He and Ne ion sources). The ion beam generated by the ion source is accelerated by an ion gun, focused, and applied to the failed chip. A secondary electron signal is generated based on the FIB to obtain an electron image. The location of the failure point is determined based on the brightness of the electron image. However, when the transistor and resistor are connected in series, the existing positioning method, after applying voltage between the first and second test points, will affect the accuracy of the failure point location result due to the series resistor. That is, the failure point may be located on the resistor, and the transistor cannot be accurately located.

[0049] The obtained failed chips can be obtained by removing the packaging of a single chip, or by cutting the wafer to separate it from the wafer; there is no limitation here.

[0050] S120. Based on image information, the failed chip is processed to form metal contact points.

[0051] The metal contact point C is located between the transistor G and the resistor R.

[0052] Since the chip has already been fabricated, during the testing process via the first and second contact points, if a transistor has a failure point, the resistor connected in series with the transistor will affect the accuracy of locating the failure point. Furthermore, the failure point will be located on the resistor, not accurately on the transistor. Based on the problems of the existing technology, those skilled in the art have discovered through testing that by short-circuiting the resistor and applying pressure to the first and second contact points, the failure point can be accurately located. Therefore, after obtaining the image information of the failed chip, the probe contact position between the transistor and the resistor in the failed chip can be determined based on the image information. By processing the probe contact position of the failed chip to form a metal contact point, located between the transistor and the resistor, a conductive material is used to connect the first test point and the metal contact point, thus short-circuiting the resistor.

[0053] To accurately locate the failed chip, a metal contact point C is formed between the transistor G and the resistor R after processing the failed chip, such as... Figure 2 As shown, the metal contact point C formed serves as the contact point for shorting the resistor R.

[0054] In a specific implementation, the process of processing a failed chip to form metal contact points includes, for example, the following:

[0055] Based on the image information, the probe contact position is determined; the first insulating layer is processed to remove the first insulating layer of the first metal layer at the probe contact position, forming a metal contact point.

[0056] An exemplary fabrication process for a failed chip includes: firstly, forming a transistor and a resistor on a substrate, wherein the transistor includes a gate layer, a source layer, a drain layer, and an active layer. After forming the drain layer of the transistor and the resistor, an insulating layer is formed on the drain layer and the resistor. To achieve short-circuiting of the resistor, the first insulating layer is processed to remove the first insulating layer of the first metal layer at the probe contact position, forming a metal contact point. Then, vias and grooves are made in the insulating layer and the resistor. Finally, a first metal layer is formed on the side of the insulating layer away from the substrate through a process. The first metal layer is electrically connected to the transistor and the resistor through the vias. The material of the first metal layer can be copper, for example.

[0057] In a specific implementation, the image information of the failed chip can be obtained by scanning the failed chip based on the electronic signal of FIB (Focused Ion Beam) to obtain an electronic image of the failed chip. Based on the electronic image, the probe contact position between the transistor and the resistor can be accurately located.

[0058] The method of removing the first insulating layer of the first metal layer at the probe contact position to form a metal contact point is preferably to use FIB (Focused Ion Beam) for cutting.

[0059] The first insulating layer is bombarded by an ion beam generated by the FIB, and the first insulating layer at the probe contact position is removed by the ion beam to form a metal contact point.

[0060] The formed metal contact point is located between the transistor and the resistor. On the one hand, it serves as a contact point to short-circuit the resistor, enabling the metal contact point to be brought out in the complex IC circuit so that a voltage signal can be applied between the metal contact point and the first test point using a probe station or E-beam. On the other hand, it avoids the damage to the transistor caused by directly forming a metal contact point on the transistor and directly contacting the transistor with a probe.

[0061] In the above-described ion beam bombardment steps, those skilled in the art can select appropriate acceleration voltage process parameters according to actual process requirements.

[0062] S130. A conductive structure is formed between the first test point and the metal contact point to short-circuit the resistor.

[0063] To avoid the resistance affecting the accuracy of transistor failure point location results, after forming the metal contact point in step S120, a conductive material is connected between the metal contact point C and the first test point A, such as... Figure 3 As shown, the resistor is short-circuited based on a conductive material to ensure the accuracy of the positioning results.

[0064] In a specific implementation, the material of the conductive structure includes foil.

[0065] The conductive material includes foil. Since the foil material has a small resistance while ensuring good conductivity, it ensures the accuracy of the transistor failure point location result after applying voltage between the first test point and the second test point.

[0066] S140. Power on between the first test point and the second test point to locate the failure point.

[0067] In a specific implementation, powering on between the first test point and the second test point to locate the failure point includes:

[0068] Power is applied between the first and second test points, and the transistor is scanned with an electron beam based on the applied voltage to locate the failure point of the transistor.

[0069] Specifically, the FIB electronic signal is used to scan the transistor to obtain an electronic image of the transistor; the brightness and darkness in the electronic image of the transistor are used to determine the location of the failure point of the transistor.

[0070] Preferably, the voltage of the electronic signal of the FIB is 0.5 to 2 kV.

[0071] In this embodiment, an electronic image is obtained by using the secondary electronic signal generated in a FIB (Focused Ion Beam). Specifically, the FIB is used to apply pressure at the first and second test points to obtain an electronic image of the transistor. The structural defects of the transistor are then analyzed based on the obtained electronic image.

[0072] In this step, the process of obtaining the electronic image is based on the scanning function of FIB. The location of the failure point in the chip is determined by the brightness and darkness in the scanned electronic image of the transistor. During the pressure applied to the first and second test points, the generated electron beam strips the atoms on the surface of the transistor, thereby making the obtained electronic image of the transistor have obvious brightness and darkness. This enables the location of failure points over a wide range and quickly, and makes it easy to find the bright spots (i.e. failure points) in the electronic image of the transistor.

[0073] The chip failure point location method provided in this application, when the acquired failed chip is a transistor-resistor series chip, involves processing the failed chip to form metal contact points, and then using a conductive structure to connect the first test point and the metal contact points, effectively short-circuiting the resistor connected in series with the transistor. This allows for the location of the transistor failure point. Since the metal contact points formed by processing the failed chip are located between the transistor and the resistor, when the conductive structure connects the metal contact points and the first test point, the resistor connected in series with the transistor is short-circuited. Therefore, during power-on between the first and second test points, the applied voltage only includes the transistor, ensuring the accuracy of transistor failure point location. Furthermore, because the metal contact points are located between the transistor and the resistor, direct contact with the transistor via a probe avoids damage caused by directly forming metal contact points on the transistor.

[0074] As one possible implementation method, the method provided in this disclosure further includes:

[0075] A second insulating layer is formed on the side of the second metal layer away from the substrate layer.

[0076] By forming a second insulating layer on the side of the second metal layer away from the substrate, the second insulating layer is used to protect the second metal layer and prevent it from being directly exposed to the external environment, which would cause oxidation of the second metal layer. Oxidation of the second metal layer increases its resistance, which in turn affects the accuracy of the transistor failure point location.

[0077] This application also provides a chip failure point location device, which locates chip failure points based on the method described in the above embodiments.

[0078] In a specific implementation, when a failure point is detected in a chip during automated testing, an image information of the failed chip is acquired using a failure point location device. Specifically, the process of acquiring the image information of the failed chip is exemplified by scanning the failed chip using the electronic signal of a FIB (Focused Ion Beam) to obtain an electronic image of the failed chip. Based on the acquired electronic image of the failed chip, the positions of the first test point, the second test point, the transistor, and the resistor corresponding to the failed chip are determined. Then, based on the electronic image of the failed chip, the probe contact position between the transistor and the resistor in the failed chip can be determined. By processing the probe contact position of the failed chip, a metal contact point is formed. Then, the formed metal contact point is connected to the first test point through a conductive material to achieve short-circuiting of the resistor. Finally, power is applied between the first test point and the second test point to achieve accurate location of the transistor failure point.

[0079] The chip failure point location device provided in this embodiment, when the acquired failed chip is a transistor-resistor series chip, processes the failed chip to form metal contact points, and then uses a conductive structure to connect the first test point and the metal contact points, effectively short-circuiting the resistor connected in series with the transistor. This allows for the location of the transistor failure point. Since the metal contact points formed by processing the failed chip are located between the transistor and the resistor, when the conductive structure connects the metal contact points and the first test point, the resistor connected in series with the transistor is short-circuited. Therefore, during power-on between the first and second test points, the applied voltage only includes the transistor, ensuring the accuracy of transistor failure point location. Furthermore, because the metal contact points are located between the transistor and the resistor, direct metal contact points on the transistor are avoided, preventing damage to the transistor caused by direct contact with the transistor by a probe.

[0080] In specific embodiments, the failure point location device provided in this disclosure further includes a memory 410 and a processor 420, such as... Figure 4 As shown.

[0081] The failure point location device includes a memory 410 and a processor 420 that are interconnected via a system bus. It should be noted that only a failure point location device with components 410-420 is shown in the figure; however, it should be understood that it is not required to implement all the shown components, and more or fewer components can be implemented alternatively. Those skilled in the art will understand that the failure point location device described herein is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions. Its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0082] Failure point location devices can be computing devices such as desktop computers, laptops, handheld computers, and cloud servers. These devices can interact with users via keyboards, mice, remote controls, touchpads, or voice-activated devices.

[0083] The memory 410 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. RAM may include static RAM or dynamic RAM. In some embodiments, the memory 410 may be an internal storage unit of a failure point location device, such as the hard disk or RAM. In other embodiments, the memory 410 may also be an external storage device of the failure point location device, such as a plug-in hard drive, SmartMediaCard (SMC), SecureDigital (SD) card, or FlashCard equipped on the device. Of course, the memory 410 may include both internal storage units and external storage devices of the failure point location device. In this embodiment, the memory 410 is typically used to store the operating system and various application software installed on the failure point location device, such as the program code of the aforementioned method. Furthermore, the memory 410 may also be used to temporarily store various types of data that have been output or will be output.

[0084] The processor 420 is typically used to perform the overall operation of the failure point location device. In this embodiment, the memory 410 is used to store program code or instructions, including computer operation instructions. The processor 420 is used to execute the program code or instructions stored in the memory 410 or to process data, such as the program code for running the methods described above.

[0085] In this article, the bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus system can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0086] Another embodiment of this application also provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or combination of steps in the above method; and to generate means for implementing the functional actions specified in each block or combination of blocks in the block diagram.

[0087] Computer-readable media include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any suitable combination thereof, wherein the memory is used to store program code or instructions, the program code including computer operation instructions, and the processor is used to execute the program code or instructions of the above-described methods stored in the memory.

[0088] The definitions of memory and processor can be found in the description of the foregoing computer device embodiments, and will not be repeated here.

[0089] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0090] In the various embodiments of this application, the functional units or modules can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0091] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0092] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0093] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0094] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A method for locating chip failure points, characterized in that, include: Image information of a failed chip is acquired, wherein the failed chip includes a transistor and a resistor, the transistor and the resistor are connected in series, a first end of the resistor is electrically connected to a first test point, a second end of the resistor is electrically connected to a first end of the transistor, and a second end of the transistor is electrically connected to a second test point, the first test point and the second test point are determined based on the image information; Based on the image information, the failed chip is processed to form metal contact points, wherein the metal contact points are located between the transistor and the resistor; A conductive structure is formed between the first test point and the metal contact point to short-circuit the resistor; Power is applied between the first test point and the second test point to locate the failure point.

2. The method according to claim 1, characterized in that, The failed chip includes at least a substrate layer, a first metal layer, and a first insulating layer, and the resistor is electrically connected to the transistor through the first metal layer; The process of forming metal contact points by processing the failed chip based on the image information includes: Based on the image information, the probe contact position is determined; The first insulating layer is processed to remove the first insulating layer of the first metal layer at the probe contact position, forming a metal contact point.

3. The method according to claim 2, characterized in that, The process of treating the first insulating layer to remove the first insulating layer of the first metal layer at the probe contact position and form a metal contact point includes: The first insulating layer is bombarded with an ion beam, and the first insulating layer of the first metal layer at the probe contact position is removed by the ion beam to form a metal contact point.

4. The method according to claim 2, characterized in that, The step of forming a conductive structure between the first test point and the metal contact point to short-circuit the resistor includes: A second metal layer is formed on the side of the first insulating layer away from the substrate layer, so that the first test point and the metal contact point are electrically connected through the second metal layer.

5. The method according to claim 4, characterized in that, After forming a second metal layer on the side of the first insulating layer away from the substrate layer to electrically connect the first test point and the metal contact point through the second metal layer, the method further includes: A second insulating layer is formed on the side of the second metal layer opposite to the substrate layer.

6. The method according to claim 1, characterized in that, The material of the conductive structure includes foil.

7. The method according to claim 1, characterized in that, The step of powering on between the first test point and the second test point to locate the failure point includes: Power is applied between the first test point and the second test point, and the transistor is scanned with an electron beam based on the applied voltage to locate the failure point of the transistor.

8. The method according to claim 7, characterized in that, The step of performing electron beam scanning on the transistor based on the power-on voltage to locate the failure point of the transistor includes: The transistor is scanned using the electronic signal of the FIB to obtain an electronic image of the transistor; The location of the failure point of the transistor is determined by the brightness of the electronic image of the transistor.

9. The positioning method according to claim 8, characterized in that, The voltage of the electronic signal of the FIB is 0.5 to 2 kV.

10. A chip failure point location device, characterized in that, include: The method described in any one of claims 1-9 enables the location of chip failure points.

Images