Dual power priority selection circuit

Abstract

The application relates to a dual-power priority selection circuit, comprising: a dual-power power-on reset synthesis circuit for monitoring the condition of dual power and generating a power-on reset signal and a synthesis output signal according to the condition of the dual power, comprising two input ends and two output ends, the two input ends being connected with two power supply ends of the dual power respectively, and the two output ends being used for outputting the generated power-on reset signal; two-phase non-overlapping RS flip-flop circuits for generating corresponding level signals according to the power-on reset signal with the synthesis output signal as power supply; and a level converter for converting the level signals into power supply control signals. The application enables the system to automatically select between different input power sources to avoid power conflicts.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, and particularly to a dual power supply priority selection circuit. BACKGROUND

[0002] With the gradual increase of system functions of a system on chip (SoC), a multi-power supply system is adopted in a power supply module in the system, and a power supply priority selection circuit is needed when the system selects between different input power supplies. For example, when a charger is connected to two electronic products that need to be charged, the charger will preferentially charge the electronic product that is connected first, and shield the electronic product that is connected later, so as to avoid conflicts. SUMMARY

[0003] The present application provides a dual power supply priority selection circuit, which can automatically select between different input power supplies to avoid power supply conflicts.

[0004] The technical scheme adopted by the present application to solve the technical problem is as follows: a dual power supply priority selection circuit is provided, which comprises:

[0005] A dual power supply power-on reset synthesis circuit is used to monitor the status of the dual power supply, and generate a power-on reset signal and a synthesis output signal according to the status of the dual power supply, and comprises two input ends and two output ends, the two input ends are connected to two power supply ends of the dual power supply respectively, and the two output ends are used to output the generated power-on reset signal;

[0006] A two-phase non-overlapping RS flip-flop circuit is used to generate a corresponding level signal according to the power-on reset signal, with the synthesis output signal as a power supply;

[0007] A level converter is used to convert the level signal into a power control signal.

[0008] The dual power supply power-on reset synthesis circuit comprises a first power-on reset circuit and a second power-on reset circuit, the input end of the first power-on reset circuit is connected to one power supply end of the dual power supply, and the output end is connected to the input end of a first switching device; the input end of the second power-on reset circuit is connected to the other power supply end of the dual power supply, and the output end is connected to the input end of a second switching device; the output ends of the first switching device and the second switching device are connected to the power supply end of the two-phase non-overlapping RS flip-flop circuit.

[0009] The first switching device and the second switching device are both NMOS transistors.

[0010] The two-phase non-overlapping RS flip-flop circuit comprises a first RS flip-flop and a second RS flip-flop, a first input end of the first RS flip-flop is connected with one of two output ends of the dual-supply power-on reset synthetic circuit, and a second input end is connected with the other of the two output ends of the dual-supply power-on reset synthetic circuit; a first output end of the first RS flip-flop is connected with a first input end of the second RS flip-flop through a first inverter, and a second output end is connected with a second input end of the second RS flip-flop through a fourth inverter; a first output end of the second RS flip-flop is connected with a first input end of the level converter, and a second output end is connected with a second input end of the level converter.

[0011] The first input end and the second input end of the first RS flip-flop are connected with the ground through a resistance.

[0012] The first RS flip-flop comprises a first NAND gate and a third NAND gate, a first input end of the first NAND gate is connected with one of two output ends of the dual-supply power-on reset synthetic circuit, and a second input end is connected with an output end of the third NAND gate; a first input end of the third NAND gate is connected with the other of the two output ends of the dual-supply power-on reset synthetic circuit, and a second input end is connected with an output end of the first NAND gate; the output end of the first NAND gate is taken as a first output end of the first RS flip-flop, and the output end of the third NAND gate is taken as a second output end of the first RS flip-flop.

[0013] The second RS flip-flop comprises a second NAND gate, a fourth NAND gate, a second inverter, a third inverter, a fifth inverter and a sixth inverter, a first input end of the second NAND gate is connected with an output end of the first inverter, a second input end is connected with an output end of the sixth inverter, and an output end is connected with an input end of the second inverter; a first input end of the fourth NAND gate is connected with an output end of the fourth inverter, a second input end is connected with an output end of the third inverter, and an output end is connected with an input end of the fifth inverter; an output end of the second inverter is connected with an input end of the third inverter, and an output end of the fifth inverter is connected with an input end of the sixth inverter; the output end of the second inverter is taken as a first output end of the second RS flip-flop, and the output end of the fifth inverter is taken as a second output end of the second RS flip-flop.

[0014] Beneficial effects

[0015] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention enables the system to automatically select between different input power sources and avoid conflicts between power sources, which has certain industrial application value. Moreover, most of the circuit uses digital circuits, which can be miniaturized with the advancement of technology and have the advantage of easy integration. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a dual-power supply priority selection circuit according to an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of the waveform of the output signal of the power-on reset circuit changing over time in an embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of the truth table of a two-phase non-overlapping RS flip-flop circuit in an embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram of the output waveform of the level converter in an embodiment of the present invention. Detailed Implementation

[0020] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0021] Embodiments of the present invention relate to a dual-power supply priority selection circuit, such as... Figure 1 As shown, it includes: a dual-power-on reset synthesis circuit 100, used to monitor the status of the dual power supplies and generate a power-on reset signal and a synthesis output signal according to the status of the dual power supplies, including two input terminals and two output terminals, the two input terminals being connected to the two power supply terminals of the dual power supplies respectively, and the two output terminals being used to output the generated power-on reset signal; a two-phase non-overlapping RS flip-flop circuit 200, used to generate a corresponding level signal according to the power-on reset signal using the synthesis output signal as power supply; and a level converter 300, used to convert the level signal into a power control signal.

[0022] The dual-power supply power-on reset synthesis circuit 100 in the embodiment comprises a first power-on reset circuit and a second power-on reset circuit. The input end of the first power-on reset circuit is connected with one power supply end VDD1 in the dual-power supply, and the output end is connected with the input end of a first switching device NMOS1. The input end of the second power-on reset circuit is connected with the other power supply end VDD2 in the dual-power supply, and the output end is connected with the input end of a second switching device NMOS2. The output ends of the first switching device NMOS1 and the second switching device NMOS2 are connected with the power supply end of the two-phase non-overlapping RS flip-flop circuit. The first switching device NMOS1 and the second switching device NMOS2 are both NMOS transistors.

[0023] The dual-power supply power-on reset synthesis circuit in the embodiment is composed of two power-on reset circuits and two NMOS transistor switches. The input ends of the two power-on reset circuits are respectively connected with the power supply end VDD1 and the power supply end VDD2 to monitor the level of the dual-power supply. When the power supply end VDD1 or the power supply end VDD2 starts to power on, the corresponding power-on reset circuit generates a power-on reset signal POR1 or POR2. The generated power-on reset signal POR1 or POR2 is output to the two-phase non-overlapping RS flip-flop circuit through the two output ends of the dual-power supply power-on reset synthesis circuit. Meanwhile, the power-on reset signals POR1 and POR2 also control the on-off of the first switching device NMOS1 and the second switching device NMOS2, respectively. The power-on reset signals pass through the first switching device NMOS1 and the second switching device NMOS2 to be synthesized into a synthesized output signal, which is used as the power supply of the two-phase non-overlapping RS flip-flop. When neither the power supply end VDD1 nor the power supply end VDD2 is powered on, the power-on reset signals POR1 and POR2 are both in a low level state (Gnd), and the entire network is in a "zero" state, which has no synthesis effect on the power supply. Specifically:

[0024] When the power supply end VDD1 gradually rises to a high enough level, and the power supply end VDD2 remains at a low level, the signal passes through the power-on reset circuit to generate a power-on reset signal POR1, and the waveform is as follows: Figure 2As shown, the high level of the power-on reset signal POR1 input to the VDD1 / POR1 port of the two-phase non-overlapping RS flip-flop makes the first switch device NMOS1 conductive, while the low level of the second switch device NMOS2 is off, and the synthesized output signal is connected to the power supply of the two-phase non-overlapping RS flip-flop. When the power supply end VDD2 gradually rises to a high enough level, while the power supply end VDD1 remains at a low level, the signal passes through the power-on reset circuit to generate the power-on reset signal POR2, which is input to the VDD2 / POR2 port of the two-phase non-overlapping RS flip-flop. The high level of the power-on reset signal POR2 makes the second switch device NMOS2 conductive, while the low level of the first switch device NMOS1 is off, and the synthesized output signal is connected to the power supply of the two-phase non-overlapping RS flip-flop circuit.

[0025] The two-phase non-overlapping RS flip-flop circuit of the embodiment includes a first RS flip-flop and a second RS flip-flop. The first input end of the first RS flip-flop is connected to one of the two output ends of the dual-power supply power-on reset synthesis circuit, and the second input end is connected to the other of the two output ends of the dual-power supply power-on reset synthesis circuit. The first output end of the first RS flip-flop is connected to the first input end of the second RS flip-flop through a first inverter INV1, and the second output end is connected to the second input end of the second RS flip-flop through a fourth inverter INV4. The first output end of the second RS flip-flop is connected to the first input end of the level converter, and the second output end is connected to the second input end of the level converter. The first input end and the second input end of the first RS flip-flop are both connected to ground through a resistor.

[0026] The first RS flip-flop includes a first NAND gate NAND1 and a third NAND gate NAND3. The first input end of the first NAND gate NAND1 is connected to the power-on reset signal POR1 output by the dual-power supply power-on reset synthesis circuit, and the second input end is connected to the output end of the third NAND gate NAND3. The first input end of the third NAND gate NAND3 is connected to the power-on reset signal POR2 output by the dual-power supply power-on reset synthesis circuit, and the second input end is connected to the output end of the first NAND gate NAND1. The output end of the first NAND gate NAND1 serves as the first output end of the first RS flip-flop, and the output end of the third NAND gate serves as the second output end of the first RS flip-flop.

[0027] The second RS flip-flop comprises a second NAND gate NAND2, a fourth NAND gate NAND4, a second inverter INV2, a third inverter INV3, a fifth inverter INV5 and a sixth inverter INV6, the first input end of the second NAND gate NAND2 is connected with the output end of the first inverter INV1, the second input end is connected with the output end of the sixth inverter INV6, and the output end is connected with the input end of the second inverter INV2; the first input end of the fourth NAND gate NAND4 is connected with the output end of the fourth inverter INV4, the second input end is connected with the output end of the third inverter INV3, the output end is connected with the input end of the fifth inverter INV5, the output end of the second inverter INV2 is connected with the input end of the third inverter INV3, and the output end of the fifth inverter INV5 is connected with the input end of the sixth inverter INV6; the output end of the second inverter INV2 is the first output end of the second RS flip-flop, and the output end of the fifth inverter INV5 is the second output end of the second RS flip-flop.

[0028] The level shifter in the embodiment comprises a first level shifting part LevelShifter1 and a second level shifting part LevelShifter2 arranged in parallel, wherein the input end of the first level shifting part LevelShifter1 is connected with the output end of the second inverter INV2, and the input end of the second level shifting part LevelShifter2 is connected with the output end of the fifth inverter.

[0029] In the embodiment, the two input ports of the two-phase non-overlapping RS flip-flop circuit are connected with the ground through a resistance R1 and a resistance R2 respectively, and the logic values of the two ports are both low in the absence of power supply, so that the whole network is in a "zero" state, the second inverter INV2 and the fifth inverter INV5 both output low level "0", and the whole circuit has no selection effect on the power supply.

[0030] When the input port VDD1 / POR1 is high and the input port VDD2 / POR2 is low, the first NAND gate NAND1 outputs low level "0", the third NAND gate NAND3 outputs high level "1", the first inverter INV1 outputs high level "1", the second NAND gate NAND2 outputs low level "0", the second inverter INV2 outputs high level "1", the third inverter INV3 outputs low level "0", the fourth inverter INV4 outputs low level "0", the fourth NAND gate NAND4 outputs high level "1", the fifth inverter INV5 outputs low level "0", the sixth inverter INV6 outputs high level "1", and the truth table of the two-phase non-overlapping RS flip-flop circuit is as follows: Figure 3The high level output of the second inverter INV2 is level converted by the level converter, and becomes the control signal VDD1Control with high level of VDD1, and the VDD2Control with low level of "0", so that the VDD1 power supply is selected, and the waveform is as shown in Figure 4 as shown in the figure.

[0031] When the input port VDD2 / POR2 is high level and the VDD1 / POR1 is low level, the first NAND gate NAND1 outputs high level "1", the third NAND gate NAND3 outputs low level "0", the first inverter INV1 outputs low level "0", the second NAND gate NAND2 outputs high level "1", the second inverter INV2 outputs low level "0", the third inverter INV3 outputs high level "1", the fourth inverter INV4 outputs high level "1", the fifth inverter INV5 outputs high level "1", and the sixth inverter INV6 outputs low level "0". The high level output of the fifth inverter INV5 is level converted by the level converter, and becomes the control signal VDD2Control with high level of VDD2, and the VDD1Control with low level of "0", so that the VDD2 power supply is selected, and the circuit maintains the current level state by the outputs of the third inverter INV3 and the sixth inverter INV6.

[0032] When the input ports VDD1 / POR1 and VDD2 / POR2 are both high level, the whole circuit maintains the level state at the last time, if the port VDD1 / POR1 has high level input earlier than the VDD2 / POR2, the power supply is selected as POR1, and if the port VDD2 / POR2 has high level input earlier than the VDD1 / POR1, the power supply is selected as POR2.

[0033] It can be found that the present application has the advantages of automatically selecting the system between different input power supplies, avoiding the conflict between power supplies, having certain industrial utilization value, and most of the circuits being digital circuits, so that the circuits can be reduced with the progress of technology, and have the advantage of easy integration.

Claims

1. A dual-power supply priority selection circuit, characterized in that, The application relates to a dual-power supply power-on reset synthesis circuit. The dual-power supply power-on reset synthesis circuit comprises a two-phase non-overlapping RS flip-flop circuit, a level converter and a dual-power supply. The two-phase non-overlapping RS flip-flop circuit comprises a first RS flip-flop and a second RS flip-flop. The first RS flip-flop is connected with one of the two output terminals of the dual-power supply power-on reset synthesis circuit through a first input terminal and connected with the other output terminal of the dual-power supply power-on reset synthesis circuit through a second input terminal. The first output terminal of the first RS flip-flop is connected with the first input terminal of the second RS flip-flop through a first inverter, and the second output terminal of the first RS flip-flop is connected with the second input terminal of the second RS flip-flop through a fourth inverter. The first output terminal of the second RS flip-flop is connected with the first input terminal of the level converter, and the second output terminal of the second RS flip-flop is connected with the second input terminal of the level converter.

2. The dual power priority selection circuit of claim 1, wherein, The dual-power supply power-on reset synthesis circuit comprises a first power-on reset circuit and a second power-on reset circuit.

3. The dual power priority selection circuit of claim 2, wherein, The input terminal of the first power-on reset circuit is connected with one of the two power supply terminals of the dual-power supply, and the output terminal of the first power-on reset circuit is connected with the input terminal of a first switch device.

4. The dual power priority selection circuit of claim 1, wherein, The input terminal of the second power-on reset circuit is connected with the other power supply terminal of the dual-power supply, and the output terminal of the second power-on reset circuit is connected with the input terminal of a second switch device.

5. The dual power priority selection circuit of claim 1, wherein, The output terminals of the first switch device and the second switch device are connected with the power supply terminal of the two-phase non-overlapping RS flip-flop circuit. The first switch device and the second switch device are both NMOS transistors. The first input terminal and the second input terminal of the first RS flip-flop are both connected with the ground through a resistor. The first RS flip-flop comprises a first NAND gate and a third NAND gate. The first input terminal of the first NAND gate is connected with one of the two output terminals of the dual-power supply power-on reset synthesis circuit, and the second input terminal of the first NAND gate is connected with the output terminal of the third NAND gate. The first input terminal of the third NAND gate is connected with the other output terminal of the dual-power supply power-on reset synthesis circuit, and the second input terminal of the third NAND gate is connected with the output terminal of the first NAND gate. The output terminal of the first NAND gate is the first output terminal of the first RS flip-flop, and the output terminal of the third NAND gate is the second output terminal of the first RS flip-flop.

6. The dual power priority selection circuit of claim 1, wherein, The second RS flip-flop comprises a second NAND gate, a fourth NAND gate, a second inverter, a third inverter, a fifth inverter and a sixth inverter, the first input end of the second NAND gate is connected with the output end of the first inverter, the second input end is connected with the output end of the sixth inverter, and the output end is connected with the input end of the second inverter; the first input end of the fourth NAND gate is connected with the output end of the fourth inverter, the second input end is connected with the output end of the third inverter, the output end is connected with the input end of the fifth inverter, the output end of the second inverter is connected with the input end of the third inverter, and the output end of the fifth inverter is connected with the input end of the sixth inverter; the output end of the second inverter is used as the first output end of the second RS flip-flop, and the output end of the fifth inverter is used as the second output end of the second RS flip-flop.

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