Power-on reset circuit with under-voltage detection and method of operation thereof

Abstract

Disclosed herein are power-on reset circuits with under-voltage detection, including small and / or low power / low voltage power-on reset circuits. In one embodiment, a power-on reset circuit includes at least one current mirror and an inverter having an input coupled to the at least one current mirror. A voltage at the input of the inverter is generated based at least in part on a current generated by the at least one current mirror and a supply voltage. The power-on reset circuit is configured to generate a low-level active power-on reset signal based at least in part on an output of the inverter. In some embodiments, the power-on reset circuit can further include a Schmitt trigger buffer coupled to the output of the inverter to provide hysteresis to the low-level active power-on reset signal.

Description

Technical Field

[0001] This disclosure is generally related to power management circuits for integrated circuits. For example, several embodiments of the invention relate to power-on reset circuits with undervoltage detection, and also to related systems, apparatus, and methods. Background Technology

[0002] Power-on reset (POR) circuits are commonly used in integrated circuits and other electronic systems. These circuits ensure that internal registers and components are initialized to a known state before normal operation begins when power is initially applied to the system. This initialization is crucial for achieving correct functionality and preventing unpredictability.

[0003] In many electronic systems, especially those powered by batteries or subjected to fluctuating power supplies, maintaining proper operation is important not only during initial power-on but also during low-voltage states. These low-voltage states, often referred to as brown out, can occur when the supply voltage drops below a certain threshold but does not completely fail. Summary of the Invention

[0004] This disclosure generally relates to power-on reset circuits for integrated circuits and other electronic devices, and specifically to related systems, apparatus, and methods. The power-on reset circuits disclosed herein are configured to hold the corresponding integrated circuit and other electronic devices in a reset state until the power supply voltage ramps to a threshold voltage level, thereby ensuring proper initialization of the registers and / or other components of the integrated circuit / electronic device during power-on after the initial application / supply of power. The power-on reset circuits of this invention may also include undervoltage detection capability to indicate when the power supply voltage drops too low during operation. It is anticipated that the power-on reset circuits of this invention will consume very little power and occupy minimal space on the chip, making them particularly suitable for battery-powered devices where power saving and / or low-battery status detection are emphasized. Attached Figure Description

[0005] Many aspects of this disclosure can be better understood with reference to the following drawings. Elements in the drawings are not necessarily to scale. Rather, they are intended to clearly illustrate the principles of this disclosure. The drawings should not be construed as limiting this disclosure to the specific embodiments shown, but rather as a means of explaining and understanding the invention.

[0006] Figure 1 A circuit diagram illustrating various embodiments of a power-on reset circuit according to the present invention.

[0007] Figure 2 A graph illustrating the output voltage versus input voltage of an inverter in a power-on reset circuit according to various embodiments of the present invention.

[0008] Figure 3 A graph used to illustrate the voltage behavior of a power-on reset circuit over time according to various embodiments of the present invention.

[0009] [Explanation of Labels in the Attached Image]

[0010] 100: Power-on reset circuit; 110: First stage; 112: First current mirror; 114: Second current mirror; 120: Second stage; 122: Current mirror; 126: Inverter; 130: Third stage; 230: Curve; 340: Curve; I1: First current; I2: Second current; I3: Third current; I4: Fourth current; M1: Transistor; M2: Transistor; M3: Transistor; M4: Transistor; M5: Transistor; M6: Transistor; M7: Transistor; M8: Transistor; M9: Transistor; M10: Transistor; M11: Transistor; M12: Transistor; PORB: Active low power-on reset signal; R1: Resistor; t0: Time; t1: Time; t2: Time; t3: Time; t4: Time; V1: Node; V2: Node; V3: Node; V4: Node; V5: Node; V6: Node; V a Voltage level; V b Voltage level; V DD Power supply voltage; V IN Input voltage; V M Midpoint voltage / trigger voltage; V OH Output high voltage; V OL Output low voltage; V OUT Output voltage; V DD_FS Full voltage; V POR :Predetermined voltage level. Detailed Implementation

[0011] In the following description, specific details are set forth to provide a thorough understanding of the nature of the invention. However, those skilled in the art will recognize that the systems, apparatuses, and techniques described herein can be practiced without one or more of the specific details set forth herein or using other methods, elements, materials, etc.

[0012] Throughout this specification, the reference to "example" or "embodiment" is intended to include, in connection with that example or embodiment, a particular feature, structure, or characteristic described in connection with that example or embodiment, in at least one example or embodiment of the invention. Therefore, the use of the phrases "for example," "as an example," or "an embodiment" herein does not necessarily refer to the same example or embodiment, and is not necessarily limited to the specific example or embodiment described. Furthermore, the features, structures, or characteristics of the invention described herein can be combined in any suitable manner to provide other examples or embodiments of the invention.

[0013] For ease of description, spatial relative terms (e.g., “below,” “under,” “above,” “below,” “over,” “upper,” “top,” “top,” “bottom,” “left,” “right,” “center,” “middle,” and the like) are used herein to describe the relationship of an element or feature shown in the figures relative to one or more other elements or features. It should be understood that spatial relative terms are intended to cover different orientations of the device or system in use or operation other than those depicted in the figures. For example, if the device or system shown in the figures is rotated, turned, or flipped about a horizontal axis, an element or feature described as “below,” “under,” or “below” one or more other elements or features may be oriented “above” one or more other elements or features. Therefore, the illustrative terms “below” and “below” are non-limiting and may cover both above and below orientations. The device or system may additionally or alternatively be oriented in a manner different from that shown in the figures (e.g., rotated ninety degrees about a vertical axis, or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly. In addition, it should be understood that when an element is referred to as being "between" two other elements, the element may be the only element between the two other elements, or there may be one or more intermediate elements.

[0014] A. Overview

[0015] Power-on reset (POR) circuits are commonly used in integrated circuits and electronic systems to keep such integrated circuits and electronic systems in a reset state during power-on until the supply voltage V is reached. DDA predetermined voltage level VPOR is achieved to (a) ensure proper initialization of internal registers and components when the integrated circuit and electronic system are allowed to exit the reset state, and (b) increase the likelihood that the integrated circuit and electronic system will operate as intended. The predetermined voltage level VPOR (also referred to herein as the “reset voltage level” or “trigger voltage level”) is carefully selected to be higher than the minimum operating voltage of the system components (e.g., higher than the threshold voltage of an NMOS transistor), but lower than the full operating voltage (e.g., less than the difference between the nominal supply voltage and the threshold voltage of a PMOS transistor). In many cases, the predetermined voltage level VPOR is set to the nominal (or full-scale) voltage V. DD_FS About half of it.

[0016] Many power-on reset circuits utilize bandgap circuits. Although such power-on reset circuits can provide a stable trigger voltage V M However, these typically consume considerable power, require a large chip area, and are relatively complex to implement. Other power-on reset circuits utilize delay-generation-based circuits. However, such circuits may be sensitive to variations in temperature and power supply rise time, and may require large passive components to achieve suitable delay characteristics. For example, if the power supply voltage V DD If the rise time is longer than the RC delay in a delay-based circuit, it may prematurely allow the corresponding integrated circuit or other electronic system to exit the reset. Additionally, such circuits may require large RC components to achieve the supply voltage V. DD The appropriate time constant of the rise time means that such circuits typically occupy a large chip area.

[0017] As electronic devices continue to shrink in size, the demand for power-on reset circuits with smaller footprints is growing. Additionally, low-power power-on reset circuits are needed, especially for applications involving battery-powered devices (e.g., mobile or wearable devices). Furthermore, the ability to detect and respond to undervoltage states where the power supply voltage drops below a certain threshold but does not completely fail is becoming increasingly important, particularly in battery-powered, mobile phone, and / or wearable electronic devices.

[0018] The power-on reset circuits configured according to various embodiments of the present invention are expected to solve one or more of these requirements, while avoiding many of the problems described above with reference to other power-on reset circuit solutions. For example, the power-on reset circuits configured according to various embodiments of the present invention can utilize a multi-stage design including a current mirror and one or more inverters to generate a low-level active power-on reset bar signal (PORB). More specifically, the power-on reset circuits of the present invention may include: a first stage that uses a first current mirror and a second current mirror for generating a bias current; and a second stage that has a third current mirror and an inverter for generating a bias current once the power supply voltage V... DD Once the voltage has been ramped up to the predetermined voltage level VPOR, the low-level active power-on reset signal PORB is triggered. In some embodiments, the power-on reset circuit of the present invention may further include a third stage, which includes a Schmitt trigger buffer for providing hysteresis.

[0019] Compared to other power-on reset circuit solutions described above, such multi-stage designs have a smaller footprint and consume less power, making them particularly suitable for smaller and / or battery-powered devices. Furthermore, as described in more detail below, the trip point of these power-on reset circuits can be set by the ratio of the current in each stage, thereby providing stability against temperature variations and independence from power rise time. This allows these power-on reset circuits to be reliably used in a variety of applications, such as mobile phones, wearable electronics, industrial control systems, and automotive electronics, among others. In addition, many of these power-on reset circuits include integrated undervoltage detection capabilities, which allow the circuit to respond to low-voltage states during operation, thereby enhancing the reliability of battery-powered systems and / or systems with fluctuating power supplies. In other words, power-on reset circuits according to various embodiments of the present invention offer a variety of feature combinations that make them particularly suitable for use in mobile phones, wearable technologies, and other compact electronic devices where power efficiency and reliable operation are critical.

[0020] B. Examples of selected power-on reset circuits with undervoltage detection, and related systems, devices, and methods.

[0021] Figure 1A circuit diagram illustrating various embodiments of a power-on reset (POR) circuit 100 according to the present invention. As shown, the power-on reset circuit 100 includes a first stage 110, a second stage 120, and a third stage 130, optionally. The first stage 110 may be a current generating stage, the second stage 120 may be a trip (or trigger) voltage generating stage, and the third stage 130 may be an output stage, which includes a Schmitt-trigger buffer for providing hysteresis.

[0022] In the illustrated embodiment, the first stage 110 includes a first current mirror 112 formed by transistors M1 and M2, a second current mirror 114 formed by transistors M4 and M5, transistor M3, and resistor R1. The first current mirror 112 is a P-type field-effect transistor (PFET) current mirror, wherein transistors M1 and M2 are PMOS transistors. The gates of transistors M1 and M2 are coupled to each other, and the sources of transistors M1 and M2 are coupled to the power supply voltage V. DD The drain of transistor M2 is coupled to the second current mirror 114, and the drain of transistor M1 is coupled to the source of transistor M3. Transistor M3 is an example of a PMOS transistor. Both transistors M1 and M3 are diode-connected transistors, each having a gate coupled to its drain. Resistor R1 is coupled between transistor M3 and ground.

[0023] The second current mirror 114 is presented as an N-type field-effect transistor (NFET) current mirror, wherein transistors M4 and M5 are NMOS transistors. The gates of transistors M4 and M5 are coupled to each other, and the sources of transistors M4 and M5 are coupled to ground. Transistor M4 is presented as a diode-connected transistor, with its gate coupled to its drain. The drain of transistor M4 is further coupled to the drain of transistor M2, and the drain of transistor M5 is coupled to node V4 and the second stage 120.

[0024] In operation, the first stage 110 can be configured to be at least partially based on transistor M1, transistor M3, resistor R1, and power supply voltage V. DD A first current I1 is generated at the drain of transistor M1. More specifically, transistors M1 and M3, along with resistor R1, are based on the power supply voltage V. DD A bias voltage is generated at node V1, which is converted into a first current I1 by transistor M1. As shown in the figure, transistors M1 and M3 can be diode-connected PMOS transistors. Therefore, the first stage 110 can be configured to generate the first current I1 when the supply voltage V... DDThe voltage levels are sufficient to generate voltages at nodes V1 and V2, allowing current to flow through the channels of transistors M1 and M2 based on their threshold voltages. This ensures that the supply voltage V is within a certain range before the inverter 126 in the second stage 120 can be triggered, and before the low-level active power-on reset signal PORB output by the power-on reset circuit 100 can be asserted (e.g., activated, transitioned to an "on" state, or transitioned to a logic high state). DD Achieve a sufficient level.

[0025] The first current mirror 112 generates a second current I2 at the drain of transistor M2, at least in part, based on the first current I1. For example, the transistor M4 of the second current mirror 114 is a diode-connected NMOS transistor. Therefore, when the supply voltage V... DD When the voltage level is sufficient so that the voltage at node V3 allows current to be conducted through the channel of transistor M4 based on the threshold voltage of transistor M4, the first current mirror 112 can generate a second current I2; this occurs whenever the first stage 110 generates the first current I1 due to the configuration of transistors M1 and M3. The second current I2 is also referred to herein as the "intermediate current," "mirror current," and the like.

[0026] Assuming transistors M1 and M2 have the same size and process characteristics, the second current I2 generated at the drain of transistor M2 is equivalent to the first current I1 generated at the drain of transistor M1. Both transistors M1 and M2 in the first current mirror 112 operate in saturation. Therefore, the first current I1 and the second current I2 can be represented by the following Equation 1, where μP is the carrier mobility, Cox is the gate oxide capacitance per unit area, W1 is the channel width, L1 is the channel length, VGS1 is the gate-source voltage, and VT1 is the threshold voltage of the PMOS transistors M1 and M2 in the first current mirror 112:

[0027] Equation 1:

[0028]

[0029] Now referring to the second current mirror 114, the second current mirror 114 generates a third current I3 at the drain of transistor M5 based on the second current I2. The third current I3 is also referred to herein as the "mirror current" and similar terms. Assuming that transistors M4 and M5 have the same size and process characteristics, the third current I3 generated at the drain of transistor M5 is equivalent to the second current I2 generated at the drain of transistor M4. Both transistors M4 and M5 of the second current mirror 114 operate in saturation. Therefore, the second current I2 and the third current I3 can be represented by the following Equation 2, where μN is the carrier mobility, Cox is the gate oxide capacitance per unit area, W2 is the channel width, L2 is the channel length, VGS2 is the gate-source voltage, and VT2 is the threshold voltage of the NMOS transistors M4 and M5 of the second current mirror 114:

[0030] Equation 2:

[0031]

[0032] Equations 1 and 2 above illustrate that the first current I1, the second current I2, and the third current I3 each depend on the threshold voltages of transistors M1, M2, M4, and M5. Therefore, as described in more detail below, the first current mirror 112 and the second current mirror 114 are complementary to each other and are used to track changes in the threshold voltages of transistors M1, M2, M4, and M5 (e.g., due to temperature changes).

[0033] In some embodiments, the power-on reset circuit 100 may be configured as a low-voltage power-on reset circuit. For example, the characteristics of resistor R1 and / or transistors M1, M2, M3, M4 and / or M5 may be selected / designed such that the first stage 110 targets a first current I1 of approximately 100 nanoamps (nA), which is mirrored to the second current I2 and the third current I3. Such low current levels of the first current I1, the second current I2, and the third current I3 are expected to reduce direct current (DC) power and by lowering the gate-source voltage V of transistors M1, M2, M4 and / or M5. GS Maintaining a voltage less than or equal to their respective threshold voltages assists in operating the first current mirror 112 and the second current mirror 114 in the weak inversion region. Furthermore, it is anticipated that the operation of the first current mirror 112 and the second current mirror 114 in the weak inversion region will reduce static and dynamic power consumption, which is particularly beneficial for mobile applications and other battery-powered applications.

[0034] In some embodiments, the resistor R1 of the first stage 110 may be implemented as a variable resistor. For example, the resistor R1 may include multiple resistor segments having metal or register options to short-circuit one or more of these segments. Such a configuration may allow (a) adjustment of the bias voltage generated at node V1 and / or (b) adjustment of the first current I1 generated at the drain of transistor M1. In some embodiments, the ability to adjust the resistance of resistor R1 may provide a means of compensating for process variations or fine-tuning the trip point of the power-on reset circuit 100.

[0035] Referring now to the second stage 120 of the power-on reset circuit 100, the second stage 120 includes transistor M6 and an inverter 126 formed by transistors M7 and M8. Transistor M6 is presented as a diode-connected transistor, with its gate coupled to its drain. The source of transistor M6 is coupled to the power supply voltage V. DD The gate and drain of transistor M6 are coupled to the drain of transistor M5 and the gates of transistors M7 and M8 via node V4. Transistor M6 can act as an active load and forms a current mirror 122 with transistor M7.

[0036] Transistor M7 is a PMOS transistor, and transistor M8 is an NMOS transistor. The gates of transistors M7 and M8 are (i) coupled to each other, and (ii) coupled to the drains of transistors M5 and M6 via node V4. Transistor M7 further includes a connection to the power supply voltage V. DD The source of the transistor, and the drain of the transistor M8 and the input of the third stage 130, which are coupled via node V5. The transistor M8 further includes a source coupled to ground.

[0037] In operation, the second stage 120 is configured to generate a fourth current I4 at the drain of transistor M6. The voltage at node V4 depends on the difference between the fourth current I4 and the third current I3, and is used when (i) the supply voltage V DD The voltage rises and the voltage at node V4 rises to the trigger voltage level and (ii) the power supply voltage V DD When the voltage drops and the voltage at node V4 drops to the trigger voltage level, inverter 126 trips.

[0038] The trigger voltage level is a characteristic of inverter 126 and is set to be equal to or greater than the threshold voltage of transistor M8. In some embodiments, the trigger voltage level represents the voltage at node V4 (representing the input voltage V at the input of inverter 126). IN The equivalent voltage at node V5 (representing the output voltage V at the output of inverter 126) OUT The midpoint voltage V of inverter 126 that appears at time ) MIn these and other embodiments, the trigger voltage level may be or correspond to the full voltage V. DD_FS Approximately half (e.g., V) DD_FS / 2).

[0039] As a specific instance, refer to Figure 2 It showcases the presentation Figure 1 The voltage characteristic curve 230 shows the voltage characteristic of the inverter 126 in the second stage 120 of the power-on reset circuit 100. Curve 230 shows the input voltage V of the inverter 126. IN With output voltage V OUT The relationship between them. More specifically, the input voltage V IN Corresponding to Figure 1 The application at node V4 in the middle Figure 1 The gate voltages of transistors M7 and M8, and the output voltage V OUT Corresponding to the representation observed at node V5 Figure 1 The voltage of the output of inverter 126 and the output of the second stage 120.

[0040] As shown in curve 230, for voltages between 0 V and low input voltage (V... IL Input voltage between values, output voltage V OUT Maintained at a high level, approximately equal to the supply voltage V. DD More specifically, when the input voltage V IN Between 0 V and V IL During this period, the PMOS transistor M7 of inverter 126 is turned on (enabled), while the NMOS transistor M8 of inverter 126 is turned off (disabled). Therefore, the output voltage V OUT Approximately equivalent to power supply voltage V DD The voltage level or output high voltage V OH Input voltage V IN The range between 0V and V IL The voltage values ​​between these values ​​correspond to the logic level "0".

[0041] With input voltage V IN Increase more than V IL Output voltage V OUT It begins to decrease. As V... IN Near midpoint voltage V M The rate of decrease becomes steeper. When the input voltage V IN Equal to output voltage V OUT At that time, the midpoint voltage V appears. M This point represents the tripping point of inverter 126, at which inverter 126 changes state. As shown in the figure, the midpoint voltage V... M Approximately equal to the power supply voltage V DDHalf of (e.g., V) DD / 2).

[0042] For voltage input high (V) IH Value and power supply voltage V DD The input voltage and output voltage V between OUT It remains at a low level, approximately equal to 0 V. More specifically, when the input voltage V... IN Between V IH With power supply voltage V DD During this period, the PMOS transistor M7 of inverter 126 is turned off (disabled), while the NMOS transistor M8 of inverter 126 is turned on (enabled). Therefore, the output voltage V OUT Approximately equivalent to 0 V or low output voltage V OL Input voltage V IN Between V IH With power supply voltage V DD The voltage values ​​between them correspond to logic level "1".

[0043] At the trigger voltage level Figure 1 The transistors M7 and M8 of the inverter 126 operate in saturation, and it is assumed that the voltage at node V4 is equivalent to the midpoint voltage V. M At this time, the current through transistor M7 is equivalent to the current through transistor M8. Therefore, the midpoint voltage V can be mathematically determined. M (This indicates the tripping point of inverter 126). More specifically, at the midpoint voltage V... M The current flowing through transistors M7 and M8 can be represented by the following equation 3, where μ P and μ N C is the carrier mobility. OXP and C OXN W is the gate oxide capacitance per unit area. P and W N L is the channel width. P and L N V is the channel length. TP and V TN V is the threshold voltage of inverter 126, and V M Midpoint voltage:

[0044] Equation 3:

[0045]

[0046] Make the current I through transistor M7 M7 With the current I through transistor M8 M8 If they are equal, rearrange the equation and solve for the midpoint voltage V. M(As shown below), thus the midpoint voltage V is obtained. M Equation 4:

[0047] Make the currents through M7 and M8 equal:

[0048]

[0049] Rearrangement equations:

[0050]

[0051] Equation 4:

[0052]

[0053] Equation 4 above shows that the midpoint voltage V M (The trigger voltage or trip point of inverter 126) is set by the ratio of the current; and is related to the supply voltage V. DD The rise time is independent; and it is independent of the device size (channel width W and channel length L of transistors M7 and M8) and the threshold voltage V of transistors M7 and M8. TP and V TN and power supply voltage V DD The function of threshold voltage V of transistors M7 and M8. TP and V TN The channel length L is proportional to the channel width W. Therefore, assuming the channel width W remains constant, a longer transistor channel results in a higher threshold voltage. Thus, in some embodiments, the channel length of the transistors (e.g., one or more of transistors M1 to M8) in the power-on reset circuit 100 can be selected to be greater than the corresponding channel width (e.g., a multiple of three or more). Additionally, as described above, the midpoint voltage V... M Also the power supply voltage V DD The function of . Therefore, for a smaller supply voltage V DD Midpoint voltage V M (Indicating the break-off point of inverter 126) will be lower. Therefore, the characteristics of transistors M7 and M8 of inverter 126 (e.g., channel width W and / or channel length L) can be adjusted according to the supply voltage V. DD The threshold voltages of transistors M7 and M8 are used for selection.

[0054] The power-on reset circuit 100 is configured to ensure that the power supply voltage V remains constant until the power supply voltage V is reached. DD Only when a sufficient level is reached will the voltage at node V4 reach the midpoint (or trigger) voltage V. M More specifically, as described above, up to the power supply voltage V DDOnly when the PMOS transistors M1 and M2 of the first current mirror 112 and the NMOS transistors M4 and M5 of the second current mirror 114 are enabled and turned on can the first current I1, the second current I2 and the third current I3 be reliably generated.

[0055] In addition, as described above, Figure 1 The first current mirror 112 and the second current mirror 114 of the first stage 110 of the power-on reset circuit 100 are complementary to each other and operate to track the threshold voltage changes of transistors M1, M2, M4, and M5 (e.g., due to process differences and / or temperature changes over time). For example, as the threshold voltages of transistors M1 and M2 rise (e.g., due to temperature changes), the bias voltage generated at node V1 increases. Consequently, the first current I1 generated at the drain of transistor M1, the second current I2 generated at the drains of transistors M2 and M4, the third current I3 generated at the drain of transistor M5, and the fourth current I4 generated at the drain of transistor M6 each decrease. Therefore, compared to the scenario where the threshold voltages of transistors M1 and M2 do not increase, the power-on reset circuit 100 will require a power supply voltage V. DD To achieve a higher voltage level, the voltage at node V4 at the input of inverter 126 is charged to the trigger voltage V. M When the threshold voltages of transistors M4 and M5 increase, the power-on reset circuit 100 operates in a similar manner.

[0056] As another example, as the threshold voltages of transistors M1 and M2 decrease, the bias voltage generated at node V1 decreases. Consequently, the first current I1, the second current I2, the third current I3, and the fourth current I4 each increase. Therefore, compared to the scenario where the threshold voltages of transistors M1 and M2 do not decrease, the power-on reset circuit 100 will require a power supply voltage V. DD To achieve a lower voltage level, the voltage at node V4 at the input of inverter 126 is charged to the trigger voltage V. M When the threshold voltages of transistors M4 and M5 decrease, the power-on reset circuit 100 operates in a similar manner.

[0057] Referring now to the third stage 130 of the power-on reset circuit 100, the third stage 130 includes a Schmitt trigger buffer that provides hysteresis to the power-on reset circuit 100. In the illustrated embodiment, the Schmitt trigger buffer includes transistors M9, M10, M11, and M12. Transistor M9 is a PMOS transistor having a coupling to the supply voltage V. DDThe transistor M11 includes a source and a drain of transistor M12, a drain coupled to the drain of transistor M10 and the gate of transistor M12, and a gate coupled to transistors M10 and M11. Transistors M10, M11, and M12 are NMOS transistors. Transistor M11 further includes (i) a source coupled to ground and (ii) a drain coupled to the source of transistor M10 and the source of transistor M12 via node V6. The third stage 130 and the Schmitt trigger buffer are shown to have an input at node V5 coupled to the gates of transistors M9, M10, and M11. The third stage 130 and the Schmitt trigger buffer are further shown to have an output at the gate of transistor M12 between the drains of transistor M9 and M10. The output of the third stage 130 and the Schmitt trigger buffer corresponds to the output of the power-on reset circuit 100.

[0058] As described above, the Schmitt trigger buffer is configured to power on the power-on reset circuit 100 (e.g., to the trigger voltage V of the inverter 126). M Add hysteresis. This type of hysteresis is expected to reduce the impact of supply voltage V. DD Towards full voltage V DD_FS The possibility of the power-on reset circuit 100 being erroneously triggered in the event of noise or glitch during upslope transition. More specifically, the Schmitt trigger buffer can provide hysteresis by adding additional current to the buffer branch at node V6. For example, transistor M10 is connected in a feedback path that extends from the source of transistor M10 through transistor M12 to the supply voltage V. DD Therefore, when the power supply voltage V DD During the rise, the voltages at nodes V4 (corresponding to the input of inverter 126), node V5 (corresponding to the output of inverter 126 and the input of the Schmitt trigger buffer and the third stage 130), and the output of the power-on reset circuit 100 increase. Furthermore, due to the increased voltage at the gate of transistor M12, additional charge is injected through transistor M12 at node V6, causing the voltage at node V6 to rise. This increase in voltage at node V6 increases the threshold voltage of transistor M10, thereby delaying the tripping point of the power-on reset circuit 100 and ensuring that the voltage at node V5 sufficiently exceeds the threshold voltage of transistor M9 before triggering the power-on reset circuit 100 and causing it to exit reset (e.g., by enabling the low-level active power-on reset signal PORB). When the supply voltage V... DD When the slope is downward, the Schmitt trigger buffer similarly provides hysteresis, as described in more detail below.

[0059] Figure 3A graph 340 illustrates the behavior of the power-on reset circuit 100 over time according to various embodiments of the present invention. This graph shows the voltage on the vertical axis and time on the horizontal axis, with specific enabling time points marked as t0, t1, t2, t3, and t4. The hysteresis provided by the Schmitt trigger buffer is represented in curve 340 by the voltage difference Va-Vb. As described above, this hysteresis helps prevent damage due to the power supply voltage Vb. DD and / or node V4 (corresponding to Figure 1 The false triggering is caused by noise or fault in the voltage at the input of the inverter 126.

[0060] At time t0, the power supply voltage V DD The voltage starts to increase at an upward slope from 0 V. As shown in the figure, when the power supply voltage V... DD During the oblique transition between time t0 and time t1, node V4 (corresponding to...) Figure 1 The voltage at the input of inverter 126 also increases slowly. Although the supply voltage V... DD The voltage at node V4 increases, but the active low-level power-on reset signal PORB remains logic low (keeping the corresponding electronic system in a reset state). This is because the voltage at node V4 has not yet reached the trigger voltage V that would trip inverter 126 to enable transistor M8 and disable transistor M7. M .

[0061] Shortly before time t1, the voltage at node V4 reaches the trigger voltage V. M As shown in the figure, this occurs at power supply voltage V. DD It has risen to its full voltage V DD_FS At approximately halfway through. At this time, due to the hysteresis introduced by the Schmitt trigger buffer in the third stage 130 of the power-on reset circuit 100, the low-level active power-on reset signal PORB remains disabled.

[0062] At time t1, the power supply voltage V DD It has risen to voltage level V a This makes node V4 (corresponding to Figure 1 The voltage at the input of inverter 126 has risen to a level that accounts for the hysteresis introduced by the Schmitt trigger buffer. Therefore, at this time, the low-level active power-on reset signal PORB switches to logic high, and is related to the supply voltage V. DD The voltage level is matched, thereby enabling the corresponding electronic system to exit the reset.

[0063] Between time t1 and t2, as the power supply voltage V... DD The power-on reset signal PORB continues to rise, and is active low, following the power supply voltage V. DDDuring this period, the voltage at node V4 also continues to increase. At time t2, the supply voltage V... DD Reaching its full voltage V DD_FS .

[0064] Between time t2 and time t3, the power supply voltage V DD The display shows a downward slope towards 0 V. During this period, the low-level active power-on reset signal PORB remains enabled, but tracks the decreasing supply voltage V. DD During this period, the voltage at node V4 also decreases with the reduction of the supply voltage V. DD And it slopes downwards.

[0065] Shortly before time t3, node V4 (corresponding to Figure 1 The voltage at the input of inverter 126 reaches the trigger voltage V. M This trigger voltage causes inverter 126 to trip, disabling transistor M8 and enabling transistor M7. As shown in the figure, this occurs at supply voltage V. DD It has dropped to its full voltage V DD_FS At approximately halfway through. At this time, the low-level active power-on reset signal PORB remains enabled due to the hysteresis provided by the Schmitt trigger buffer in the third stage 130 of the power-on reset circuit 100.

[0066] At time t3, the power supply voltage V DD It has dropped to voltage level V b This makes node V4 (corresponding to Figure 1 The voltage at the input of inverter 126 has dropped to a level that must account for the hysteresis provided by the Schmitt trigger buffer. Therefore, at this point, the active-low power-on reset signal PORB switches to logic low to 0 V (or ground), causing the corresponding electronic system to return to reset. This transition indicates an undervoltage state, where the supply voltage has dropped below the safe operating level. The undervoltage detection functionality of the power-on reset circuit 100 is described in more detail below.

[0067] like Figure 3 As shown in curve 340, with the power supply voltage V DD The voltage continues to decrease between time t3 and time t4, with the active low power-on reset signal remaining logic low. During this period, the voltage at node V4 continues to follow the decreasing supply voltage V. DD .

[0068] If the power supply voltage V DD During the period following time t4, towards its full voltage V DD_FS If the voltage is tilted, the behavior of the voltage observed at node V4 and the low-level active power-on reset signal PORB will be similar to... Figure 3The behavior matching shown in curve 340 indicates the trigger voltage V M The corresponding tripping point of the power-on reset circuit 100 (including the hysteresis provided by the Schmitt trigger buffer) occurs throughout the power cycle and / or when the supply voltage V DD The trigger voltage V remains constant during multiple cycles from low to high and / or from high to low. M Such consistency in the tripping point of the power-on reset circuit 100 will ensure reliable operation of the power-on reset circuit 100 under varying power conditions.

[0069] Alternatively or alternatively, if the power supply voltage V DD As shown in curve 340, the voltage V tends to stabilize, decrease, and / or increase at different rates between time t0 and time t1. DD Reaching voltage level V a At this time, the low-level active power-on reset signal PORB will still be enabled. Similarly, if the power supply voltage V DD As shown in curve 340, the voltage V tends to stabilize, rise, and / or fall at different rates between time t2 and time t3. DD Drop to voltage level V b At this time, the low-level active power-on reset signal PORB will be deenabled. Therefore, Figure 1 The tripping point of the power-on reset circuit 100 is related to the power supply voltage V. DD The rise time or fall time is irrelevant.

[0070] As described above, the power-on reset circuit 100 provides undervoltage detection functionality. More specifically, when the power supply voltage V... DD The voltage at node V4 drops below the trigger voltage V of inverter 126. M When the voltage level drops, taking into account the hysteresis provided by the Schmitt trigger buffer of the third stage 130, the low-level active power-on reset signal PORB can be deenabled. Figure 3 The curve 340 shows the value at time t3, where the power supply voltage V DD It has dropped to voltage level V b The de-enabling of the active-low power-on reset signal PORB can be used to indicate an undervoltage state. For example, the de-enabling of the active-low power-on reset signal PORB (e.g., outside of power-off or reset operations of the corresponding electronic system) can be used as a warning signal to indicate an undervoltage condition when the supply voltage V... DD The data backup procedure is initiated before the level drops to a level where the register state might be lost. The hysteresis provided by the Schmitt trigger buffer helps prevent data loss due to power supply voltage V. DD Small fluctuations can cause false triggering, thus enhancing the reliability of undervoltage detection.

[0071] In some embodiments, in response to an undervoltage indication provided by the de-enabling of the low-level active power-on reset signal PORB, the corresponding electronic system may save critical data to non-volatile memory, complete one or more ongoing operations, prepare for orderly shutdown, and / or activate backup power (if available). In other words, the undervoltage detection capability of the power-on reset circuit 100 enables the corresponding electronic system to take proactive measures to maintain data integrity in an undervoltage state, thereby increasing the likelihood of a smooth recovery when power is restored. In some embodiments, the trigger voltage V M and / or the voltage level V that cancels the enable signal PORB (Power-On Reset Signal) when it is active low. b This can be selected to be sufficiently higher than the minimum operating voltage of the corresponding system component. This selection provides the system with a sufficient time interval to respond to undervoltage warnings before reaching a critical low voltage state where register contents or other volatile information may be impaired.

[0072] The undervoltage detection functionality of the power-on reset circuit 100 described above is particularly suitable for battery-powered devices, systems exposed to unreliable power sources, or applications where data integrity is critical. By providing early warning of reduced power supply voltage, the power-on reset circuit 100 enables more robust and reliable operation across a wide range of power conditions.

[0073] Despite Figure 1 The diagram shows the third stage 130 and its corresponding Schmitt trigger buffer, but in other embodiments of the invention, the power-on reset circuit 100 may omit the third stage 130 and its corresponding Schmitt trigger buffer. For example, instead of the third stage 130 and the Schmitt trigger buffer, the power-on reset circuit 100 may use a large capacitor on the power supply. In such embodiments, a low-level active power-on reset signal can (a) be applied when the power supply voltage V DD The voltage rises and reaches the trigger voltage V at node V4. M (a) When enabled, and (b) when the power supply voltage V DD The voltage at the falling node V4 drops to the trigger voltage V. M It is sometimes deactivated. Alternatively, although in Figure 1 The first current mirror 112 is presented as a P-type field-effect transistor current mirror and the second current mirror 114 is presented as an N-type field-effect transistor current mirror. However, in other embodiments of the present invention, the first current mirror 112 and the second current mirror 114 of the power-on reset circuit 100 may be an N-type field-effect transistor current mirror and a P-type field-effect transistor current mirror.

[0074] C. Conclusion

[0075] The detailed description of embodiments of the present invention above is not intended to be exhaustive or to limit the technology to the precise forms disclosed herein. Although specific embodiments and examples of the technology have been described above for illustrative purposes, those skilled in the art will understand that various equivalent modifications can be made within the scope of this technology. For example, although the steps are presented in the order given above, alternative embodiments may perform the steps in a different order. Furthermore, the various embodiments described herein may be combined to provide other embodiments.

[0076] Based on the foregoing, it should be understood that specific embodiments of the technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the technology.

[0077] Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, unless the word “or” is explicitly limited to meaning only a single item exclusive to other items in a list referring to two or more items, its use in this list may be interpreted as including: (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Additionally, as used herein, the phrase “and / or” in phrases such as “A and / or B” means only A, only B, and both A and B. Furthermore, the terms “comprising,” “including,” “having,” and “with” are used throughout to mean at least one or more of the described features, without excluding any larger number of identical features and / or other features of additional types. Moreover, as used herein, the phrases “based on,” “depending on,” “due to,” and “in response to” should not be construed as references to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrases "based at least inpart on" or "based at least partially on".

[0078] Based on the foregoing, it should also be understood that various modifications can be made without departing from this disclosure or the present technology. For example, those skilled in the art will understand that the various elements of the present technology can be further divided into sub-elements, or the various elements and functions of the present technology can be combined and integrated. Furthermore, in other embodiments, certain aspects of the technology described in the context of a particular embodiment can be combined or eliminated. Moreover, although advantages associated with other embodiments of the technology have been described in the context of some embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily need to exhibit such advantages to fall within the scope of the technology. Therefore, this disclosure and related technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A power-on reset circuit, characterized in that, Include: At least one current mirror; and An inverter having an input coupled to the at least one current mirror. in: The voltage at the input of the inverter is generated at least in part based on a current produced by the at least one current mirror and a supply voltage, and The power-on reset circuit is configured to generate a low-level active power-on reset signal based at least in part on one output of the inverter.

2. The power-on reset circuit as described in claim 1, characterized in that, The at least one current mirror includes a P-type field-effect transistor current mirror.

3. The power-on reset circuit as described in claim 2, characterized in that, The at least one current mirror further includes an N-type field-effect transistor current mirror coupled to the P-type field-effect transistor current mirror.

4. The power-on reset circuit as described in claim 1, characterized in that: The at least one current mirror includes a current mirror having a first transistor and a second transistor; The first transistor is a diode-connected transistor coupled between the power supply voltage and ground. The power-on reset circuit further includes a third transistor; and The third transistor is a diode-connected transistor coupled between the first transistor and ground.

5. The power-on reset circuit as described in claim 1, characterized in that: The at least one current mirror includes a current mirror having a first transistor and a second transistor; The first transistor is a diode-connected transistor coupled between the power supply voltage and ground. The power-on reset circuit further includes a resistor; and The resistor is coupled between the first transistor and ground.

6. The power-on reset circuit as described in claim 5, characterized in that, The resistor includes a variable resistor.

7. The power-on reset circuit as described in claim 1, characterized in that: The at least one current mirror includes a current mirror having a first transistor and a second transistor; The first transistor is a diode-connected transistor; The first transistor and the second transistor are each coupled between the power supply voltage and ground; The power-on reset circuit further includes a third transistor coupled between the power supply voltage and the second transistor; and The third transistor is a diode-connected transistor and is configured as an active load.

8. The power-on reset circuit as described in claim 1, characterized in that, It further includes a Schmitt trigger buffer coupled to the output of the inverter and configured to provide hysteresis to the low-level active power-on reset signal.

9. A power-on reset circuit, characterized in that, Include: A bias generation stage configured to generate a bias current based at least in part on a supply voltage; A breakpoint generation stage is coupled to the bias generation stage and configured to generate a voltage at a node based at least in part on the bias current. and An output stage coupled to the trip point generation stage and configured to generate a low-level active power-on reset signal based at least in part on the voltage at the node.

10. The power-on reset circuit as described in claim 9, characterized in that, This bias generation stage includes: A first current mirror, configured to generate the bias current; and A second current mirror is coupled to the first current mirror and configured to mirror the bias current to the trip point generation stage.

11. The power-on reset circuit as described in claim 9, characterized in that, The breakpoint generation stage includes an inverter, and the voltage at the node is applied to an input of the inverter.

12. The power-on reset circuit as described in claim 9, characterized in that, The output stage includes a Schmitt trigger buffer, wherein the Schmitt trigger buffer is configured to: When the power supply voltage rises above a first threshold, the low-level active power-on reset signal is enabled; and When the power supply voltage drops below a second threshold that is lower than the first threshold, the low-level active power-on reset signal is deactivated.

13. A method for operating a power-on reset circuit, characterized in that, The method includes: A current is generated, at least in part, based on a power supply voltage; The generated current is mirrored using one or more current mirrors; and An inverter trips at least in part based on the generated current and the power supply voltage.

14. The operating method as described in claim 13, characterized in that, The steps to trip the inverter include: As the power supply voltage rises, when the voltage at one input of the inverter reaches a trigger voltage of the inverter, the inverter trips; or As the power supply voltage drops, when the voltage at the input of the inverter drops to the trigger voltage of the inverter, the inverter trips.

15. The operating method as described in claim 14, characterized in that, It further includes enabling a low-level active power-on reset signal after taking hysteresis, based at least in part on the tripping of the inverter.

16. The operating method as described in claim 14, characterized in that, It further includes, at least in part, based on the inverter's tripping, canceling the enable of a low-level active power-on reset signal after taking hysteresis into account.

17. The operating method as described in claim 14, characterized in that, The step of tripping the inverter as the power supply voltage rises includes tripping the inverter when the power supply voltage reaches half of the full power supply voltage.

18. The operating method as described in claim 13, characterized in that, This current is generated by producing 100 nanoamps.

19. The operating method as described in claim 13, characterized in that, The step of mirroring the generated current includes operating at least one of the one or more current mirrors in a weakly inverted region.

20. The operating method as described in claim 13, characterized in that, The step of mirroring the generated current includes: mirroring the generated current through a first current mirror to generate an intermediate current, and mirroring the intermediate current through a second current mirror different from the first current mirror to generate a mirrored current, wherein the step of tripping the inverter at least in part based on the generated current includes tripping the inverter at least in part based on the mirrored current.

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